AD9483KS-100

a FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provided Low Power: 1.0 W Typical +5 V Converter Power Supply APPLICATIONS RGB Graphics Processing High Resolution Video LCD Monitors and Projectors Micromirror Projectors Plasma Display Panels Scan Converters R AIN R AIN G AIN G AIN B AIN B AIN ENCODE ENCODE DS DS Triple 8-Bit, 140 MSPS A/D Converter AD9483 FUNCTIONAL BLOCK DIAGRAM AD9483 T/H QUANTIZER 8 DRA7-0 DRB7-0 T/H QUANTIZER 8 DGA7-0 DGB7-0 T/H QUANTIZER 8 DBA7-0 DBB7-0 TIMING CLKOUT CLKOUT OMS I/P PD CONTROL +2.5V VREF RVREF GVREF BVREF VCC VDD GND OUT IN IN IN GENERAL DESCRIPTION The AD9483 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports display resolutions of up to 1280 × 1024 at 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. To minimize system cost and power dissipation, the AD9483 includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The digital outputs are threestate CMOS outputs. Separate output power supply pins support interfacing with 3.3 V or 5 V logic. The AD9483’s encode input interfaces directly to TTL, CMOS, or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual channel or single channel digital outputs. The Dual Channel (demultiplexed) mode interleaves ADC data through two 8-bit channels at onehalf the clock rate. Operation in Dual Channel mode reduces the speed and cost of external digital interfaces while allowing the ADCs to be clocked to the full 140 MSPS conversion rate. In the Single Channel mode, all data is piped at the full clock rate to the Channel A outputs and the ADCs conversion rate is limited to 100 MSPS. A data clock output is provided at the Channel A output data rate for both Dual-Channel or SingleChannel output modes. Fabricated in an advanced BiCMOS process, the AD9483 is provided in a space-saving 100-lead MQFP surface mount plastic package (S-100) and is specified over the 0° C to +85°C temperature range. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD9483–SPECIFICATIONS differential PECL) Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Compliance Range AIN or AIN Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) Data Sync Setup Time (tSDS) Data Sync Hold Time (tHDS) Data Sync Pulsewidth (tPWDS) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Clock Valid Time (tCV)3 Clock Propagation Delay (tCPD)3 Data to Clock Skew (tV–tCV) Data to Clock Skew (tPD–tCPD) DIGITAL INPUTS Input Capacitance DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) HIGH Input Voltage (VIHD) LOW Input Voltage (VILD) Common-Mode Input (VICM) HIGH Level Current (IIH) LOW Level Current (IIL) VREF IN Input Resistance +25°C Full +25°C Full Full +25°C Full I VI I VI VI I V Temperature Test Level (VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate AD9483KS-140 Typ Max 8 1.25/–1.0 1.50/–1.0 0.9 1.50/–1.50 1.75/–1.75 Guaranteed ±1 ±2 160 0.8 AD9483KS-100 Min Typ Max 8 1.25/–1.0 1.50/–1.0 0.9 1.50/–1.50 1.75/–1.75 Guaranteed ±1 ±2 160 0.8 Min Units Bits LSB LSB LSB LSB % FS ppm/°C Full Full +25°C Full +25°C Full +25°C +25°C Full +25°C Full Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C Full Full Full Full Full Full +25°C Full Full Full Full Full Full +25°C V V I VI I VI V I VI V VI V VI IV IV IV V V V IV IV IV VI VI VI VI VI VI V IV IV IV IV VI VI V ± 512 1.8 ±4 83 4 17 330 +2.4 +2.5 110 140 2.8 2.8 1.5 100 2.3 0 0.5 2.0 4.0 3.8 –1.0 –2.0 0 0.5 2.0 4.0 10 3.8 10 1.0 2.0 –1.0 –2.0 10 50 50 +2.6 +2.4 3.2 ± 16 ± 20 1.8 ± 512 ±4 83 4 17 330 +2.5 110 +2.6 3.2 ± 16 ± 20 35 25 35 25 36 50 36 50 mV p–p V mV mV kΩ kΩ pF µA µA MHz V ppm/°C MSPS MSPS ns ns ns ps ps rms ns ns ns ns ns ns ns ns ns pF mV V V V mA mA kΩ 100 4.0 4.0 1.5 100 2.3 10 50 50 6.3 8.0 6.2 8.0 0 0 3 6.3 8.0 6.2 8.0 0 0 3 10 10 1.0 2.0 400 0.4 0 1.5 VCC 1.2 1.2 2.5 400 0.4 0 1.5 VCC 1.2 1.2 2.5 – 2– REV. A AD9483 Parameter SINGLE-ENDED INPUTS HIGH Input Voltage (VIH) LOW Input Voltage (VIL) HIGH Level Current (IIH) LOW Level Current (IIL) DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY VCC Supply Current VDD Supply Current Total Power Dissipation4 Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE5 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Effective Number of Bits fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 2nd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 3rd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Crosstalk Temperature Full Full Full Full Full Full Test Level IV IV VI VI VI VI Min 2.0 0 AD9483KS-140 Typ Max VCC 0.8 1 1 AD9483KS-100 Min Typ Max 2.0 0 VCC 0.8 1 1 Units V V mA mA V V VDD – 0.05 0.05 Binary VDD – 0.05 0.05 Binary 215 60 1.3 20 100 215 60 1.3 20 100 Full Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C Full VI VI VI V V V V 1.0 4 20 1.5 1.5 1.0 4 20 1.5 1.5 mA mA W mA mW ns ns V I V 41 45 44 44 41 45 44 44 dB dB dB V I V V I V V I V V I V V 40 44 43 42 7.0 6.8 6.8 63 58 51 56 54 51 55 40 44 43 42 7.0 6.8 6.8 63 58 51 56 54 51 55 dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dB 6.4 6.4 50 50 46 46 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 tV and t PDF are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF. 3 tCV and tCPD are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF. 4 Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 5 SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Typical thermal impedance for the S-100 (MQFP) 100-lead package: θJC = 10°C/W, θCA = 17°C/W, θJA = 27°C/W. Specifications subject to change without notice. REV. A – 3– AD9483 ABSOLUTE MAXIMUM RATINGS* Table I. Output Coding VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . . . . 0°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. Step 255 254 253 • • • 129 128 127 126 • • • 2 1 0 AIN–AIN ≥ 0.512 V 0.508 V 0.504 V • • • 0.006 V 0.002 V –0.002 V –0.006 V • • • –0.504 V –0.508 V ≤ –0.512 V Code 255 254 253 • • • 129 128 127 126 • • • 2 1 0 Binary 1111 1111 1111 1110 1111 1101 • • • 1000 0001 1000 0000 0111 1111 0111 1110 • • • 0000 0010 0000 0001 0000 0000 EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25°C and sample tested at specified temperatures. III – Periodically sample tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – 100% production tested at +25°C; guaranteed by design and characterization testing. ORDERING GUIDE Model AD9483KS-100 AD9483KS-140 AD9483/PCB Temperature Range 0°C to +85°C 0°C to +85°C +25°C Package Description Plastic Thin Quad Flatpack Plastic Thin Quad Flatpack Evaluation Board Package Option S-100B S-100B CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9483 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. A AD9483 PIN FUNCTION DESCRIPTIONS Pin Number 1, 6, 7, 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 2 3 4 5 8 9 11, 21, 31, 41, 51, 61, 71 79, 82, 83, 93, 94, 98, 99 12–19 22–29 32–39 42–49 52–59 62–69 72 74 75 76 84 85 86 87 88 89 90 91 92 97 Name Function GND ENCODE ENCODE DS DS DCO DCO VDD VCC DBB7–DBB0 DBA7–DBA0 DGB7–DGB0 DGA7–DGA0 DRB7–DRB0 DRA7–DRA0 NC OMS I/P PD R AIN R AIN R REF IN G AIN G AIN G REF IN B AIN B AIN B REF IN REF OUT Ground Encode clock for ADC (ADC samples on rising edge of ENCODE). Encode clock complement (ADC samples on falling edge of ENCODE). Data Sync Aligns output channels in Dual-Channel mode. Data Sync complement. Data Clock Output. Clock output at Channel A data rate. Data Clock Output complement. Output Power Supply. Nominally 3.3 V. Converter Power Supply. Nominally 5.0 V. Digital Outputs of Converter “B,” Channel B. DBB7 is the MSB. Digital Outputs of Converter “B,” Channel A. DBA7 is the MSB. Digital Outputs of Converter “G,” Channel B. DGB7 is the MSB. Digital Outputs of Converter “G,” Channel A. DGA7 is the MSB. Digital Outputs of Converter “R,” Channel B. DRB7 is the MSB. Digital Outputs of Converter “R,” Channel A. DRA7 is the MSB. No Connect. Selects Single Channel or Dual Channel output mode, (HIGH = single, LOW = demuxed). Selects interleaved or parallel output mode, (HIGH = interleaved, LOW = parallel). Power-Down and Three-State Select (HIGH = power-down). Analog Input Complement for Converter “R.” Analog Input True for Converter “R.” Reference Input for Converter “R” (+2.5 V Typical, ± 10%). Analog Input Complement for Converter “G.” Analog Input True for Converter “G.” Reference Input for Converter “G” (+2.5 V Typical, ± 10%). Analog Input Complement for Converter “B.” Analog Input True for Converter “B.” Reference Input for Converter “B” (+2.5 V Typical, ± 10%). Internal Reference Output (+2.5 V Typical); Bypass with 0.01 µF to Ground. REV. A –5– AD9483 PIN CONFIGURATION Plastic Thin Quad Flatpack (S-100B) 97 REF OUT 89 G REF IN 92 B REF IN 88 G AIN 87 G AIN 90 B AIN 86 R REF IN 91 B AIN 100 GND 84 R AIN 85 R AIN 98 VCC 95 GND 99 VCC 96 GND GND ENCODE ENCODE DS DS GND GND DCO DCO 82 VCC 83 VCC 93 VCC 94 VCC 81 GND 1 2 3 4 5 6 7 8 9 PIN 1 IDENTIFIER 80 GND 79 VCC 78 GND 77 GND 76 PD 75 I/P 74 OMS 73 GND 72 NC 71 VDD 70 GND 69 DRA 0 68 DRA 1 67 DRA 2 66 DRA 3 65 DRA 4 64 DRA 5 63 DRA 6 62 DRA 7 61 VDD 60 GND 59 DRB 0 58 DRB 1 57 DRB 2 56 DRB 3 55 DRB 4 54 DRB 5 53 DRB 6 52 DRB 7 51 VDD VDD 31 DGB7 32 DGB6 33 DGB2 37 DGB0 39 DGA4 45 DGA3 46 DGA0 49 DGB5 34 DGB4 35 DGA2 47 DGA1 48 DGB1 38 DGB3 36 DGA6 43 DGA5 44 DGA7 42 GND 50 GND 40 VDD 41 GND 10 VDD 11 D BB7 12 D BB6 13 D BB5 14 D BB4 15 D BB3 16 D BB2 17 D BB1 18 D BB0 19 GND 20 VDD 21 D BA 7 22 D BA 6 23 D BA 5 24 D BA 4 25 D BA 3 26 D BA 2 27 D BA 1 28 D BA 0 29 GND 30 AD9483 TOP VIEW (PINS DOWN) NC = NO CONNECT –6– REV. A AD9483 TIMING SAMPLE N–1 AIN SAMPLE N SAMPLE N+3 SAMPLE N+4 tA ENCODE ENCODE SAMPLE N+1 SAMPLE N+2 t EH t EL 1 /f S t PD D7–D0 DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 tV DATA N t CPD CLOCK OUT CLOCK OUT t CV Figure 1. Timing—Single Channel Mode SAMPLE N–1 AIN SAMPLE N–2 SAMPLE N SAMPLE N+3 SAMPLE N+4 SAMPLE N+5 t EH ENCODE ENCODE t EL tA 1 /f S SAMPLE N+1 SAMPLE N+2 SAMPLE N+6 t HDS DS DS t SDS t PD INTERLEAVED DATA OUT tV PORT A D7–D0 DATA N–7 OR N–8 DATA N–7 OR N–6 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC DATA N–2 DATA N PORT B D7–D0 DATA N–8 OR N–7 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC PARALLEL DATA OUT DATA N–3 DATA N–1 DATA N+1 PORT A D7–D0 DATA N–9 OR N–8 DATA N–7 OR N–8 DATA N–7 OR N–6 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC DATA N–2 DATA N PORT B D7–D0 DATA N–8 OR N–7 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC DATA N–3 DATA N–1 DATA N+1 t CPD CLKOUT CLKOUT t CV Figure 2. Timing—Dual Channel Mode REV. A –7– AD9483 EQUIVALENT CIRCUITS VCC VDD AD9483 AIN AIN DIGITAL OUTPUTS AD9483 Figure 3. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit VCC VCC VREF IN 500 VREF OUT AD9483 2k AD9483 Figure 4. Equivalent Reference Input Circuit Figure 8. Equivalent Reference Output Circuit VCC 17.5k ENCODE DS 300 VCC AD9483 ENCODE DS AD9483 300 7.5k DIGITAL INPUTS Figure 5. Equivalent Encode and Data Select Input Circuit Figure 9. Equivalent Digital Input Circuit VCC AD9483 DEMUX Figure 6. Equivalent DEMUX Input Circuit –8– REV. A Typical Performance Characteristics–AD9483 0 –0.5 –1 –1.5 –2 –2.5 –3 –3.5 –4 –4.5 –5 0 50 100 150 200 250 300 350 400 450 2.4 –40 –20 0 20 40 60 TEMPERATURE – C 80 100 2.42 2.48 2.5 NYQUIST FREQUENCY (70MHz) –3dB (333MHz) 2.46 VOLTS 2.44 dB fIN – MHz Figure 10. Frequency Response: fS = 140 MSPS Figure 13. Reference Voltage vs. Temperature –70 –60 –50 2.6 2.5 2.4 VREF 0 2.5 5 7.5 10 25 50 fIN – MHz 75 100 150 200 250 –40 dB 2.3 –30 2.2 –20 –10 0 2.1 2 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 VCC – V Figure 11. Crosstalk vs. fIN: fS = 140 MSPS Figure 14. Reference Voltage vs. Power Supply Voltage –80 2.6 2.5 –75 2.4 2.3 2.2 –70 VOLTS 10 20 30 40 50 60 70 TEMPERATURE – C 80 90 100 dB –65 2.1 2 –60 1.9 1.8 1.7 –55 –50 0 1.6 0 1 2 3 4 5 6 789 IREF – mA 10 11 12 13 14 15 Figure 12. Crosstalk vs. Temperature: fIN = 70 MHz Figure 15. Reference Voltage vs. Reference Load REV. A –9– AD9483–Typical Performance Characteristics 9 8.5 8 7.5 7 ns 5 TPD 3.3V 4.5 4 VDD = +5V TPD 5V VOLTS 3.5 3 2.5 2 VDD = +3.3V TV 5V 6.5 6 5.5 5 4.5 4 5 10 15 20 LOAD CAPACITANCE – pF 25 30 TV 3.3V 1.5 1 0.5 0 0 2 4 6 8 12 10 IOH – mA 14 16 18 20 Figure 16. Clock Output Delay vs. Capacitance Figure 19. Output Voltage HIGH vs. Output Current 9 8 7 6 TPD 2 1.8 1.6 1.4 TV 1.2 VOLTS 5 ns 1 0.8 4 3 2 1 0 3 0.6 0.4 VDD = +3.3V 0.2 0 3.3 3.6 3.9 4.2 4.5 VDD – V 4.75 5 5.25 5.5 VDD = +5V 0 5 10 IOL 15 20 Figure 17. Output Delay vs. VDD Figure 20. Output Voltage LOW vs. Output Current 9 8.5 8 7.5 7 ns 6.5 6 TV 3.3V 5.5 5 4.5 4 –40 TV 5V TPD 5V TPD 3.3V 600 500 400 mW 300 200 100 0 0 50 TEMPERATURE – C 100 3 3.5 4 VDD – V 4.5 5 5.5 Figure 18. Output Delay vs Temperature Figure 21. Output Power vs. VDD, CLOAD = 10 pF –10– REV. A AD9483 50 48 46 SNR 44 42 dB 40 38 36 34 32 30 0 30 60 100 fS – MSPS 140 180 SINAD dB 50 48 46 44 42 40 38 36 34 32 30 0 20 40 60 80 100 120 fS – MSPS 140 160 180 200 SINAD SNR Figure 22. SNR vs. fS: fIN = 19.7 MHz Figure 25. SNR vs fS: fIN = 71.7 MHz –75 –56 –54 2ND HARMONIC –70 3RD HARMONIC –65 dB dB –52 –50 –48 3RD HARMONIC –46 –44 –60 2ND HARMONIC –55 –42 –40 –38 –50 0 25 50 90 fS – MSPS 130 170 –36 0 40 80 120 fS – MSPS 155 175 Figure 23. Harmonic Distortion vs. fS: fIN = 19.7 MHz Figure 26. Harmonic Distortion vs fS: fIN = 71.7 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 10 20 30 40 50 MHz 60 70 80 90 100 FUNDAMENTAL = –0.5dBFS SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 10 20 30 40 50 MHz 60 70 80 90 100 FUNDAMENTAL = –0.5dBFS SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = 63.1dB 3RD HARMONIC = 39.1dB dB Figure 24. Spectrum: fS = 140 MSPS, fIN = 19.57 MHz Figure 27. Spectrum: fS = 140 MSPS, fIN = 70.3 MHz REV. A –11– dB AD9483 46 44 42 40 fS = 140 MSPS fIN = 19.3MHz SNR 46 SNR 45 SINAD 44 SINAD dB dB 38 36 43 42 34 32 30 25% 28% 2 1.8 31% 2.2 38% 45% 52% 59% 66% 73% 76% 2.7 3.2 3.7 4.2 4.7 5.2 5.4 ENCODE DUTY CYCLE – % ENCODE PULSEWIDTH – ns 41 40 –25 0 40 60 TEMPERATURE – C 80 100 Figure 28. SNR vs. Clock Pulsewidth (tPWH): fS = 140 MSPS Figure 31. SNR vs. Temperature, fS = 140 MSPS 55 –70 50 NYQUIST FREQUENCY (70.0MHz) 45 dB dB –65 –60 –55 SNR 40 –50 35 SINAD –45 30 0 50 100 150 fIN – MHz 200 250 –40 –25 0 40 60 TEMPERATURE – C 80 100 Figure 29. SNR vs. fIN: fS = 140 MSPS Figure 32. 2nd Harmonic vs. Temperature, fS = 140 MSPS –60 0 –10 F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = –7.0dBFS –56 –20 –30 –52 –40 dB dB –48 –44 –40 –25 –50 –60 –70 –80 –90 –100 0 40 60 TEMPERATURE – C 80 100 0 10 20 30 40 50 MHz 60 70 80 90 100 Figure 30. 3rd Harmonic vs. Temperature, fS = 140 MSPS Figure 33. Two Tone Intermodulation Distortion –12– REV. A AD9483 APPLICATION NOTES Theory of Operation The AD9483 combines Analog Devices’ patented MagAmp bitper-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input logic that accepts TTL, CMOS or PECL levels. Each of the three analog input signals is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and combined into the 8-bit result. If the user has selected Single Channel mode (OMS = HIGH) the 8-bit data word is directed to an A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel mode (OMS = LOW) the data are alternately directed between the A and B output banks and the data has five pipeline delays. At power-up, the N sample data can appear at either the A or B Port. To align the data in a known state, the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section. Graphics Applications needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VCC pins to a quiet analog power supply system and tying all GND pins to a quiet analog system ground. Minimum Encode Rate The minimum sampling rate for the AD9483 is 10 MHz for the 140 MSPS and 100 MSPS versions. To achieve this sampling rate, the Track/Hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by operating the converter in Dual Port output mode and using only one output channel. A majority of the power dissipated by the AD9483 is static (not related to conversion rate), so the penalty for clocking at twice the desired rate is not high. Digital Inputs SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies and wide bandwidths. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 µF decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic. When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a total differential swing ≥800 mV (VID ≥400 mV). Note the 6-diode clock input protection circuitry in Figure 5. This limits the differential input voltage to ± 2.1 V. When the diodes turn on, current is limited by the 300 Ω series resistor. Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter. DRIVING DIFFERENTIAL INPUTS DIFFERENTIALLY CLOCK ENC VIH D VIC M CLOCK ENC VIL D VID The high bandwidth and low power of the AD9483 makes it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another, then is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems, and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architecture of the AD9483 is vastly superior to older flash architectures, which not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rapidly slewing signal. The AD9483’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. Using the AD9483 Good high speed design practices must be followed when using the AD9483. Decoupling capacitors should be physically as close as possible to the chip to obtain maximum benefit. We recommend placing a 0.1 µF capacitor at each power ground pin pair (14 total) for high frequency decoupling and including one 10 µF capacitor for local low frequency decoupling. Each of the three VREF IN pins should also be decoupled by a 0.1 µF capacitor. The part should be located on a solid ground plane and output trace lengths should be short (