AD9551BCPZ

Multiservice Clock Generator AD9551 FEATURES Translation between any two standard network rates Dual reference inputs and dual clock outputs Pin programmable for standard network rate translation SPI programmable for arbitrary rational rate translation Output frequencies from 10 MHz to 900 MHz Input frequencies from 19.44 MHz to 806 MHz On-chip VCO Meets OC-192 high band jitter generation requirement Supports standard forward error correction (FEC) rates Supports holdover operation Supports hitless switchover and phase build-out (even with unequal reference frequencies) SPI-compatible 3-wire programming interface Single supply (3.3 V) Reference conditioning and switchover circuitry internally synchronizes the two references so that if one reference fails, there is virtually no phase perturbation at the output. The AD9551 uses an external crystal and an internal DCXO to provide for holdover operation. If both references fail, the device maintains a steady output signal. The AD9551 provides pin-selectable, preset divider values for standard (and FEC adjusted) network frequencies. The pinselectable frequencies include any combination of 15 possible input frequencies and 16 possible output frequencies. A SPI interface provides further flexibility by making it possible to program almost any rational input/output frequency ratio. The AD9551 is a clock generator that employs fractional-N-based phase-locked loops (PLL) using sigma-delta (Σ-Δ) modulators (SDMs). The fractional frequency synthesis capability enables the device to meet the frequency and feature requirements for multiservice switch applications. The AD9551 precisely generates a wide range of standard frequencies when using any one of those same standard frequencies as a timing base (reference). The primary challenge of this function is the precise generation of the desired output frequency because even a slight output frequency error can cause problems for downstream clocking circuits in the form of bit or cycle slips. The requirement for exact frequency translation in such applications necessitates the use of a fractional-N-based PLL architecture with variable modulus. APPLICATIONS Multiservice switches Multiservice routers Exact network clock frequency translation General-purpose frequency translation GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation. BASIC BLOCK DIAGRAM CRYSTAL (26MHz) REFA REFB REFERENCE CONDITIONING AND SWITCHOVER HOLDOVER LOOP PLL OUTPUT CIRCUITRY OUT1 OUT2 PIN-DEFINED AND SERIAL PROGRAMMING AD9551 07805-001 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9551 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Basic Block Diagram ........................................................................ 1  Revision History ............................................................................... 2  Functional Block Diagram .............................................................. 3  Specifications..................................................................................... 4  Reference Clock Input Characteristics ...................................... 4  Output Characteristics ................................................................. 4  Jitter Characteristics (180 Hz Loop Bandwidth) ...................... 5  Crystal Oscillator Characteristics............................................... 5  Power Consumption .................................................................... 5  Logic Input Pins ............................................................................ 6  RESET Pin ..................................................................................... 6  Logic Output Pins......................................................................... 6  Serial Control Port ....................................................................... 6  Serial Control Port Timing ......................................................... 7  Absolute Maximum Ratings............................................................ 8  ESD Caution .................................................................................. 8  Pin Configuration and Function Descriptions ............................. 9  Typical Performance Characteristics ........................................... 11  Preset Frequency Ratios................................................................. 14  Theory of Operation ...................................................................... 16  Operating Modes ........................................................................ 16  Component Blocks ..................................................................... 16  Holdover Mode ........................................................................... 21  Jitter Tolerance ............................................................................ 21  External Loop Filter Capacitor ................................................. 21  Output/Input Frequency Relationship .................................... 21  Calculating Divider Values ....................................................... 22  Low Dropout (LDO) Regulators .............................................. 24  Applications Information .............................................................. 25  Thermal Performance ................................................................ 25  Serial Control Port ......................................................................... 26  Serial Control Port Pin Descriptions ....................................... 26  Operation of the Serial Control Port ....................................... 26  Instruction Word (16 Bits) ........................................................ 27  MSB/LSB First Transfers ........................................................... 27  Register Map ................................................................................... 29  Register Map Descriptions ........................................................ 32  Outline Dimensions ....................................................................... 40  Ordering Guide .......................................................................... 40  REVISION HISTORY 9/09—Rev. A to Rev. B Changes to Table 25 ........................................................................ 33 6/09—Rev. 0 to Rev. A Changes to Figure 23 ...................................................................... 23 4/09—Revision 0: Initial Version Rev. B | Page 2 of 40 AD9551 The AD9551 is easily configured using the external control pins (A[3:0], B[3:0], and Y[3:0]). The logic state of these pins sets predefined divider values that establish a specific input-to-output frequency ratio. For applications requiring other frequency ratios, the user can override any of the preconfigured divider settings via the serial port, which enables a very wide range of applications. The AD9551 architecture consists of two cascaded PLL stages. The first stage consists of fractional division (via SDM), followed by a digital PLL that uses a crystal resonator-based DCXO. The DCXO relies on an external crystal with a resonant frequency in the range of 19.44 MHz to 52 MHz. The DCXO constitutes the first PLL, which operates within a narrow frequency range (±50 ppm) around the crystal resonant frequency. This PLL has a loop bandwidth of approximately 180 Hz, providing initial jitter cleanup of the input reference signal. The second stage is a frequency multiplying PLL that translates the first stage output frequency (in the range of 19.44 MHz to 104 MHz) up to ~3.7 GHz. This PLL incorporates an SDM-based fractional feedback divider that enables fractional frequency multiplication. Programmable integer dividers at the output of this second PLL establish a final output frequency of up to 900 MHz. It is important to understand that the architecture of the AD9551 produces an output frequency that is most likely not coherent with the input reference frequency. The reason is that the input and crystal frequencies typically are not harmonically related and neither are the output and crystal frequencies. As a result, there is generally no relationship between the phase of the input and output signals. INPUT PLL LOCKED XTAL1 XTAL0 The AD9551 includes reference signal processing blocks that enable a smooth switching transition between two reference inputs. This circuitry automatically detects the presence of the reference input signals. If only one input is present, the device uses it as the active reference. If both inputs are present, one becomes the active reference and the other becomes the alternate reference. The circuitry edge-aligns the backup reference with the active reference. If the active reference fails, the circuitry automatically switches to the backup reference (if available), making it the new active reference. Meanwhile, if the failed reference is once again available, it becomes the new backup reference and is edge-aligned with the new active reference (a precaution against failure of the new active reference). If neither reference can be used, the AD9551 supports a holdover mode. Note that the external crystal is necessary to provide the switchover and holdover functionality. It is also the clock source for the reference synchronization and monitoring functions. The AD9551 relies on a single external capacitor for the output PLL loop filter. With proper termination, the output is compatible with LVPECL, LVDS, or CMOS logic levels, although the AD9551 is implemented in a strictly CMOS process. The AD9551 operates over the extended industrial temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM OUTPUT PLL LOCKED LF TEST MUX REFA, REFA 2 fREFA AD9551 LOCK DETECT NA SDMA SYNCHRONIZATION AND SWITCH OVER CONTROL 19.44MHz MODE P DIG. F LOOP D FILTER fIF DCXO LOOP CONFIGURATION P F D CHARGE PUMP 3350MHz TO 4050MHz VCO 4 TO 11 P0 1 TO 63 P1 fOUT1 2 OUT1, OUT1 REFB, REFB 2 fREFB NB SDMB N = 4N1 + N0 REFERENCE MONITOR N1 4/5 1 TO 63 P2 N fOUT2 2 OUT2, OUT2 SAMPLE RATE CONTROL SCLK, SDIO, CS 3 SDM REGISTER BANK NB, MODB, FRACB A[3:0] B[3:0] Y[3:0] 4 4 4 PRECONFIGURED DIVIDER VALUES 19.44MHz MODE N, MOD, FRAC, P0, P1, P2 FRAC, MOD NA, MODA, FRACA P2, P1, P0 07805-002 Figure 2. Rev. B | Page 3 of 40 AD9551 SPECIFICATIONS Minimum and maximum values apply for full range of supply voltage and operating temperature variation. Typical values apply for VDD = 3.3 V, TA = 25°C, unless otherwise noted. REFERENCE CLOCK INPUT CHARACTERISTICS Table 1. Parameter FREQUENCY RANGE INPUT CAPACITANCE INPUT RESISTANCE DUTY CYCLE REFERENCE CLOCK INPUT VOLTAGE SWING Differential Single-Ended 1 Min 19 1 Typ 3 6 Max 806 40 60 Unit MHz pF kΩ % Test Conditions/Comments Measured single-ended Measured with a differential probe across the input pins Maximum magnitude across pin pair Peak-to-peak 250 250 mV mV The 19 MHz lower limit applies only to the 19.44 MHz operating mode. OUTPUT CHARACTERISTICS Table 2. Parameter LVPECL MODE Differential Output Voltage Swing Common-Mode Output Voltage Frequency Range Duty Cycle Rise/Fall Time 1 (20% to 80%) LVDS MODE Differential Output Voltage Swing Balanced, VOD Unbalanced, ΔVOD Min 690 VDD − 1.77 0 40 Typ 765 VDD − 1.66 Max 889 VDD − 1.20 900 60 305 Unit mV V MHz % ps Test Conditions/Comments Output driver static Output driver static Up to 805 MHz output frequency 100 Ω termination between both pins of the output driver 255 247 454 25 mV mV Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static Output driver static Voltage difference between output pins; output driver static Offset Voltage Common Mode, VOS Common-Mode Difference, ΔVOS Short-Circuit Output Current Frequency Range Duty Cycle Rise/Fall Time1 (20% to 80%) CMOS MODE Output Voltage High, VOH IOH = 10 mA IOH = 1 mA Output Voltage Low, VOL IOL = 10 mA IOL = 1 mA Frequency Range 1.125 1.375 25 17 24 900 60 355 V mV mA MHz % ps 0 40 285 Up to 805 MHz output frequency 100 Ω termination between both pins of the output driver Output driver static; standard drive strength setting 2.8 2.8 V V Output driver static; standard drive strength setting 0.5 0.3 200 Rev. B | Page 4 of 40 0 V V MHz 3.3 V CMOS; standard drive strength setting AD9551 Parameter Duty Cycle Rise/Fall Time1 (20% to 80%) 1 Min 45 Typ 500 Max 55 745 Unit % ps Test Conditions/Comments At maximum output frequency 3.3 V CMOS; standard drive strength setting; 10 pF load The listed values are for the slower edge (rise or fall). JITTER CHARACTERISTICS (180 HZ LOOP BANDWIDTH) Table 3. Parameter JITTER GENERATION 12 kHz to 20 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz JITTER TRANSFER BANDWIDTH JITTER TRANSFER PEAKING Min Typ 1.3 0.8 0.5 0.6 0.1 180 0.1 Max Unit ps rms ps rms ps rms ps rms ps rms Hz dB Test Conditions/Comments fIN = 19.44 MHz, fOUT = 622.08 MHz fIN = 622.08 MHz, fOUT = 622.08 MHz fIN = 19.44 MHz, fOUT = 622.08 MHz fIN = 622.08 MHz, fOUT = 622.08 MHz fIN = 622.08 MHz, fOUT = 622.08 MHz See the Typical Performance Characteristics section See the Typical Performance Characteristics section CRYSTAL OSCILLATOR CHARACTERISTICS Table 4. Parameter CRYSTAL FREQUENCY Range Tolerance CRYSTAL MOTIONAL RESISTANCE DCXO LOAD CAPACITANCE CONTROL RANGE Min 19 Typ 26 Max 52 20 100 Unit MHz ppm Ω pF Test Conditions/Comments 3 to 21 Requires a crystal with a 10 pF load specification POWER CONSUMPTION Table 5. Parameter TOTAL CURRENT VDD CURRENT BY PIN Pin 9 Pin 23 Pin 27 Pin 34 LVPECL OUTPUT DRIVER Min Typ 169 Max 195 Unit mA Test Conditions/Comments At maximum output frequency with both output channels active 24 78 36 36 38 27 84 42 42 mA mA mA mA mA 900 MHz with 100 Ω termination between both pins of the output driver Rev. B | Page 5 of 40 AD9551 LOGIC INPUT PINS Table 6. Parameter INPUT CHARACTERISTICS 1 Logic 1 Voltage, VIH Logic 0 Voltage, VIL Logic 1 Current, IIH Logic 0 Current, IIL 1 Min 1.0 Typ Max Unit V Test Conditions/Comments For the CMOS inputs, a static Logic 1 results from either a pull-up resistor or no connection 0.8 3 17 V μA μA The A[3:0], B[3:0], Y[3:0], and OUTSEL pins have 100 kΩ internal pull-up resistors. RESET PIN Table 7. Parameter INPUT CHARACTERISTICS 1 Input Voltage High, VIH Input Voltage Low, VIL Input Current High, IINH Input Current Low, IINL MINIMUM PULSE WIDTH HIGH 1 Min 1.8 Typ Max Unit V V μA μA ns 0.3 31 2 1.3 12.5 43 The RESET pin has a 100 kΩ internal pull-up resistor, so the default state of the device is reset. LOGIC OUTPUT PINS Table 8. Parameter OUTPUT CHARACTERISTICS Output Voltage High, VOH Output Voltage Low, VOL Min 2.7 0.4 Typ Max Unit V V SERIAL CONTROL PORT Table 9. Parameter CS Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO Input Input Logic 1 Voltage Input Logic 0 Voltage Min 1.6 0.5 0.03 2 2 1.6 0.5 2 0.03 2 Typ Max Unit V V μA μA pF V V μA μA pF Test Conditions/Comments 1.6 0.5 Rev. B | Page 6 of 40 V V AD9551 Parameter Input Logic 1 Current Input Logic 0 Current Input Capacitance Output Output Logic 1 Voltage Output Logic 0 Voltage Min Typ 1 1 2 Max Unit μA μA pF V V Test Conditions/Comments 2.8 0.3 1 mA load current 1 mA load current SERIAL CONTROL PORT TIMING Table 10. Parameter SCLK Clock Rate, 1/tCLK Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO, tDV CS to SCLK Setup (tS) and Hold (tH) CS Minimum Pulse Width High Limit 50 3 3 4 0 13 0 6.4 Unit MHz max ns min ns min ns min ns min ns max ns min ns min Rev. B | Page 7 of 40 AD9551 ABSOLUTE MAXIMUM RATINGS Table 11. Parameter Supply Voltage (VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 3.6 V −0.5 V to VDD + 0.5 V −65°C to +150°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 8 of 40 AD9551 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 39 38 37 36 35 34 33 32 31 B2 1 B3 2 REFA 3 REFA 4 REFB 5 REFB 6 RESET 7 LDO_IPDIG 8 VDD 9 LDO_XTAL 10 B1 B0 A3 A2 A1 A0 VDD OUT1 OUT1 GND PIN 1 INDICATOR AD9551 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 GND OUT2 OUT2 VDD OUTPUT PLL LOCKED INPUT PLL LOCKED LDO_1.8 VDD LDO_VCO Y0 XTAL0 XTAL1 CS SCLK SDIO OUTSEL LF Y3 Y2 Y1 11 12 13 14 15 16 17 18 19 20 NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND. Figure 3. Pin Configuration Table 12. Pin Function Descriptions Pin No. 9, 23, 27, 34 30, 31 4 3 5 6 13 14 15 7 11 12 33 32 29 28 17 26 25 16 8 10 22 24 35 36 37 38 Mnemonic VDD GND REFA REFA REFB REFB CS SCLK SDIO RESET XTL0 XTL1 OUT1 OUT1 OUT2 OUT2 LF OUTPUT PLL LOCKED INPUT PLL LOCKED OUTSEL LDO_IPDIG LDO_XTAL LDO_VCO LDO_1.8 A0 A1 A2 A3 Type 1 P P I I I I I I I/O I I I O O O O I/O O O I P/O P/O P/O P/O I I I I Description Power Supply Connection (3.3 V Analog Supply). Analog Ground. Analog Input (Active High)—Reference Clock Input A. Analog Input (Active High)—Complementary Reference Clock Input A. Analog Input (Active High)—Reference Clock Input B. Analog Input (Active High)—Complementary Reference Clock Input B. Digital Input Chip Select (Active Low). Serial Data Clock. Digital Serial Data Input/Output. Digital Input (Active High). Resets internal logic to default states. This pin has an internal 100 kΩ pull-up resistor, so the default state of the device is reset. Pin for Connecting an External Crystal (20 MHz to 30 MHz). Pin for Connecting an External Crystal (20 MHz to 30 MHz). Square Wave Clocking Output 1. Complementary Square Wave Clocking Output 1. Square Wave Clocking Output 2. Complementary Square Wave Clocking Output 2. Loop Filter Node for the Output PLL. Connect an external 12 nF capacitor (100 nF in 19.44 MHz mode) from this pin to Pin 22 ( LDO_VCO). Active High Locked Status Indicator for the Output PLL. Active High Locked Status Indicator for the Input PLL. Logic 0 selects LVDS, and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2 when the outputs are not under SPI port control. Can be overridden via the programming registers. LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground. LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground. LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground. LDO Decoupling Pin. Connect a 0.47 μF decoupling capacitor from this pin to ground. Control Pin. Selects preset values for the REFA dividers. Control Pin. Selects preset values for the REFA dividers. Control Pin. Selects preset values for the REFA dividers. Control Pin. Selects preset values for the REFA dividers. Rev. B | Page 9 of 40 07805-003 AD9551 Pin No. 39 40 1 2 21 20 19 18 EP 1 Mnemonic B0 B1 B2 B3 Y0 Y1 Y2 Y3 Exposed Die Pad Type 1 I I I I I I I I Description Control Pin. Selects preset values for the REFB dividers. Control Pin. Selects preset values for the REFB dividers. Control Pin. Selects preset values for the REFB dividers. Control Pin. Selects preset values for the REFB dividers. Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. Control Pin. Selects preset values for the output PLL feedback dividers and OUT1 dividers. The exposed die pad must be connected to GND. P = power, I = input, O = output, I/O = input/output, P/O = power/output. Rev. B | Page 10 of 40 AD9551 TYPICAL PERFORMANCE CHARACTERISTICS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 100 CARRIER 622.080005MHz 0.8813dBm RMS JITTER: 0.827ps (12kHz TO 20MHz) 0.618ps (50kHz TO 80MHz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 100 CARRIER 619.666689MHz 0.8705dBm RMS JITTER: 0.773ps (12kHz TO 20MHz) 0.559ps (50kHz TO 80MHz) 07805-004 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz) 100M 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz) 100M Figure 4. Phase Noise, Fractional-N (fIN = 622.08 MHz, fOUT1 = 622.08 MHz, fXTAL = 26 MHz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 100 CARRIER 622.080027MHz 0.5414dBm RMS JITTER: 1.336ps (12kHz TO 20MHz) 0.463ps (50kHz TO 80MHz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 Figure 7. Phase Noise, Integer-N (fIN = 622.08 MHz, fOUT1 = 619.67 MHz, fXTAL = 26 MHz) CARRIER 619.666712MHz 0.6233dBm RMS JITTER: 1.327ps (12kHz TO 20MHz) 0.438ps (50kHz TO 80MHz) PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) 07805-006 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz) 100M 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER (Hz) 100M Figure 5. Phase Noise, 19.44 MHz Mode, Fractional-N (fIN = 19.44 MHz, fOUT1 = 622.08 MHz, fXTAL = 52 MHz) 5 0 –5 5 0 –5 Figure 8. Phase Noise, 19.44 MHz Mode, Integer-N (fIN = 19.44 MHz, fOUT1 = 619.67 MHz, fXTAL = 52 MHz) JITTER TRANSFER (dB) –10 –15 –20 –25 –30 –35 –40 10 1.0 0.5 0 –0.5 –1.0 10 100 07805-008 JITTER TRANSFER (dB) –10 –15 –20 –25 –30 –35 –40 10 1.0 0.5 0 –0.5 –1.0 10 100 100 1k 10k FREQUENCY OFFSET (Hz) 100k 100 1k 10k FREQUENCY OFFSET (Hz) 100k Figure 6. Jitter Transfer (Minimal Peaking) (Register 0x33[7] = 0) Figure 9. Jitter Transfer (Nominal Peaking) (Register 0x33[7] = 1) Rev. B | Page 11 of 40 07805-009 07805-007 –160 –170 –180 100 07805-005 AD9551 35 25 30 SUPPLY CURRENT (mA) LVPECL SUPPLY CURRENT (mA) 20 25 15 20 LVDS (STRONG) 15 10 10 5 LVDS (WEAK) 07805-024 1k FREQUENCY (MHz) 0 50 100 150 FREQUENCY (MHz) 200 250 Figure 10. Supply Current vs. Output Frequency— LVPECL and LVDS (10 pF Load) 1.6 LVPECL Figure 13 Supply Current vs. Output Frequency—CMOS (10 pF Load) 4.0 3.5 3.0 1.4 5pF AMPLITUDE (V p-p) AMPLITUDE (V p-p) 1.2 LVDS (STRONG) 1.0 2.5 2.0 1.5 1.0 0.5 10pF 20pF 0.8 LVDS (WEAK) 0.6 07805-028 0 200 400 600 FREQUENCY (MHz) 800 1000 0 100 200 300 FREQUENCY (MHz) 400 500 Figure 11. Peak-to-Peak Output Voltage vs. Frequency—LVPECL and LVDS (10 pF Load) 60 Figure 14. Peak-to-Peak Output Voltage vs. Frequency—CMOS 55 54 5pF 10pF 20pF 53 DUTY CYCLE (%) 55 DUTY CYCLE (%) 52 LVDS (WEAK) LVDS (STRONG) LVPECL 07805-026 51 200 300 400 500 600 700 FREQUENCY (MHz) 800 900 1000 0 100 200 FREQUENCY (MHz) 300 Figure 12. Duty Cycle vs. Output Frequency—LVPECL and LVDS (10 pF Load) Figure 15. Duty Cycle vs. Output Frequency—CMOS Rev. B | Page 12 of 40 07805-027 50 100 50 07805-029 0.4 0 07805-025 5 100 0 AD9551 200mV/DIV 07805-010 100mV/DIV 500ps/DIV 500ps/DIV Figure 16. Typical Output Waveform—LVPECL (805 MHz) Figure 18. Typical Output Waveform—LVDS (805 MHz, 3.5 mA Drive Current) 500mV/DIV 1.25ns/DIV Figure 17. Typical Output Waveform—CMOS (250 MHz, 10 pF Load) 07805-023 Rev. B | Page 13 of 40 07805-022 AD9551 PRESET FREQUENCY RATIOS The frequency selection pins (A[3:0], B[3:0], and Y[3:0]) allow the user to hardwire the device for preset input and output divider values based on the pin logic states. The A[3:0] pins control the REFA dividers, the B[3:0] pins control the REFB dividers, and the Y[3:0] pins control the feedback and output dividers. The pins decode ground or open connections as Logic 0 or Logic 1, respectively. To override the preset divider settings, use the serial I/O port to program the desired divider values. Table 13 lists the input divider values based on the logic state of the frequency selection pins. The table headings are as follows: • • A[3:0], B[3:0]. The logic state of the A[3:0] or B[3:0] pins. NA, NB. The integer part of the REFA input divider (NA) or the REFB input divider (NB). • • MODA, MODB. The modulus of the REFA input divider SDM (MODA) or the REFB input divider SDM (MODB). FRACA, FRACB. The fractional part of the REFA input divider SDM (FRACA) or the REFB input divider SDM (FRACB). fREFA, fREFB. The frequency of the REFA input (fREFA) or the REFB input (fREFB). • The divider settings shown in Table 13 cause the frequency at the reference input of the output PLL’s PFD (fIF) to operate at exactly 26 MHz when using the indicated input reference frequency, fREFA or fREFB, assuming the use of a 26 MHz external crystal. Table 13. Preset Input Settings A[3:0], B[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 NA, NB 23 24 24 24 24 25 25 25 25 25 25 MODA, MODB 130,000 130,000 154,050 130,000 166,400 104,000 198,016 154,700 154,050 182,000 153,400 FRACA, FRACB 110,800 −120,000 −114,594 45,200 96,400 −44,625 −42,891 41,820 74,970 93,000 108,120 fREFA, fREFB (MHz) 1 622.08 625 622 .08 622.08 ( ) ≈ 627.33 239 237 66 64 625 ( ) ≡ 644.53125 66 64 ( ) ≡ 641.52 ( ) ≈ 660.18 255 622.08(238 ) ≈ 666.51 622.08( ) ≈ 669.33 10518 .75 239 16 238 10518.75 16 ≡ 657.421875 622.08 1011 1100 1101 1110 1111 2 1 2 26 26 27 27 197,184 146,900 198,016 197,184 67,998 83,612 −161,755 −115,995 19.44 MHz mode ( ) ≈ 672.16 625( 255 )× ( 66 ) ≈ 693.48 237 64 253 622.08( 226 ) ≈ 696.40 255 236 15 625(14 ) ≈ 669.64 255 237 10518.75 255 16 238 10518.75 255 16 237 ( ) ≈ 704.38 ( ) ≈ 707.35 Assumes the use of a 26 MHz external crystal. If all four A[3:0] pins or all four B[3:0] pins are Logic 1, the 19.44 MHz mode is in effect. Rev. B | Page 14 of 40 AD9551 The Y[3:0] pins select the divider values for the feedback path of the output PLL, as well as for the OUT1 dividers, P0 and P1. The OUT2 divider, P2, defaults to unity unless otherwise programmed using the serial port. Table 14 lists the feedback and output divider values based on the logic state of the Y[3:0] frequency selection pins. The table headings are as follows: The divider settings shown in Table 14 produce the indicated frequency at OUT1 when the frequency at the reference input of the output PLL’s PFD (fIF) is exactly 26 MHz. When operating in the 19.44 MHz mode, the N, MOD, and FRAC values may be different from those shown in Table 14, but the fOUT1 values remain the same. The reason is that the 19.44 MHz mode relies on a crystal with a resonant frequency other than 26 MHz (see the 19.44 MHz Mode section in the Operating Modes portion of the Theory of Operation section). • • • • • • Y[3:0]. The logic state of the Y[3:0] pins. N. The integer part of the feedback divider. MOD. The modulus of the feedback SDM. FRAC. The fractional part of the feedback SDM. P0, P1. The P0 and P1 divider values. fOUT1. The frequency of the OUT1 output. Table 14. Preset Output Settings Y[3:0] 0000 N 143 MOD 520,000 FRAC 289,600 P0, P1 6/1 fOUT1 (MHz) 622.08 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 144 144 148 148 151 152 153 154 154 155 133 133 135 136 149 520,000 308,100 520,000 465,920 520,000 465,920 465,920 328,640 460,096 490,880 328,640 470,080 349,440 394,368 520,000 120,000 236,736 22,400 343,840 370,625 163,160 377,856 151,168 245,216 56,192 119,005 433,856 159,975 11,577 280,000 6/1 6/1 6/1 6/1 6/1 6/1 6/1 6/1 6/1 6/1 5/1 5/1 5/1 5/1 5/1 625 ( ) ≈ 627.33 622.08 ( ) ≡ 641.52 625 ( 66 ) ≡ 644 .53125 64 622 .08 239 237 66 64 ( ) ≈ 660.18 255 622 .08 ( 238 ) ≈ 666 .51 255 622.08 ( 237 ) ≈ 669.33 10518 .75 239 16 238 255 622.08( 236 ) ≈ 672.16 10518.75 16 ≡ 657.421875 15 625(14 ) ≈ 669.64 625( 255 )( 66 ) ≈ 693.48 237 64 253 622.08( 226 ) ≈ 696.40 10518.75 255 16 238 ( ) ≈ 704.38 622.08 (10 ) ≡ 777.6 8 10518 .75 255 16 237 ( ) ≈ 707.35 Rev. B | Page 15 of 40 AD9551 THEORY OF OPERATION OPERATING MODES The AD9551 provides the following fundamental operating modes: Although the 19.44 MHz mode limits the input divide ratio to 1, 2, or 4, the user has full control of the dividers in the output section. This includes the integer and fractional components of the output PLL feedback divider and the final output dividers (P0, P1, and P2), enabling the synthesis of a wide range of output frequencies. Note that the 19.44 MHz mode alters the configuration of the input PLL (see the Input PLL section). When using the 19.44 MHz mode, the loop filter in the output PLL requires a 100 nF capacitor. Furthermore, the user must program the output PLL charge pump current to 25 μA (via Register 0x0A). Note that SPI port programming capability is necessary when using 19.44 MHz mode because it requires a charge pump current that is different from the default value. • • Normal mode 19.44 MHz mode Mode selection depends on the state of the frequency selection pins (A[3:0] and B[3:0]). If all four of the A[3:0] pins or all four of the B[3:0] pins are Logic 1s, the 19.44 MHz mode is in effect. Otherwise, normal mode is in effect. Normal Mode Normal mode offers two methods of operation. The first method relies on the frequency selection pins to configure the device. The second method involves the use of the serial port for device configuration. The first method is for applications that use one of the input/output frequency sets defined in Table 13 and Table 14 (excluding the 19.44 MHz mode selection). The advantage of this method is that the serial port is not required. Connect the pins to the appropriate logic levels, and the device operates with the defined input and output frequencies. The pin settings establish all the necessary internal divider values. Note, however, that this method requires an external crystal with a resonant frequency of 26 MHz. The second method, which relies on the serial port, enables the user to program custom divider settings to achieve input/output frequency ratios not available via the frequency selection pins. Furthermore, the 26 MHz constraint on the external crystal no longer applies. Note, however, that the external pin settings still establish the default values of the dividers. The serial port simply enables the user to override the default settings. COMPONENT BLOCKS Input Dividers Each reference input feeds a dedicated reference divider block. The input dividers provide division of the reference frequency in integer steps from 1 to 63. They provide the bulk of the frequency prescaling necessary to reduce the reference frequency to accommodate the bandwidth limitations of both the input and output PLLs. Input Sigma-Delta Modulators (SDM) Each of the two input dividers is coupled with an optional, secondorder SDM, enabling fractional division of the input reference frequency. With both integer and fractional divide capability, the AD9551 can accept two different reference frequencies that span a wide range of possible input frequency ratios. A typical SDM offers fractional division in the form N + F/M, where N is the integer part, M is the modulus, and F is the fractional part (F < M). All three parameters are positive integers. The input SDMs of the AD9551 are atypical in that they implement fractional division in the form, N + 1/2 + F/(2M), with F being a signed integer, and |F| < M. Note that when the SDM is in use, the minimum integer divide value is 4. Both SDMs have an integrated pseudorandom binary sequence (PRBS) generator. The PRBS generator serves to suppress spurious artifacts by adding a random component to the SDM output. By default, the PRBS generator is active in both input SDMs, but the user can disable the PRBS using Register 0x1E[2]. Note that in 19.44 MHz mode, the input SDMs are inactive and unavailable. 19.44 MHz Mode This special operating mode allows for input references that operate specifically at 19.44 MHz, 38.88 MHz, or 77.76 MHz. The 19.44 MHz mode is invoked by the frequency selection pins and occurs when either A[3:0] = 1111b or B[3:0] = 1111b. Furthermore, this mode requires an external crystal with one of the following four possible resonant frequencies, based on the contents of Register 0x33[5:4]. • • • • 49.152 MHz 49.860 MHz 50.000 MHz 52.000 MHz In the 19.44 MHz mode, the reference input dividers allow for integer divide ratios of 1, 2, or 4 only, set via Register 0x1E[1:0]. Therefore, if fIN = 19.44 MHz, the divide ratio must be set to 1; if fIN = 38.88 MHz, the divide ratio must be set to 2; and if fIN = 77.76 MHz, the divide ration must be set to 4. Note that for applications using both REFA and REFB in the 19.44 MHz mode, the input frequencies must match. Reference Monitor The reference monitor verifies the presence or absence of the prescaled REFA and REFB signals (that is, after division by the input dividers). The status of the reference monitor guides the activity of the synchronization and switchover control logic. Note that the DCXO must be operational for the reference monitor to function. Rev. B | Page 16 of 40 AD9551 DLL A REFA, REFA ÷ DELAY HOLD A OUT ENABLE 1 0 A/B ACC P F D HOLD B HOLD A A/B A/B 1 OUT ENABLE A/B 1 REF. DLL DQ N/2 INPUT PLL DCXO TO OUTPUT PLL REFERENCE MONITOR ÷2 0 0 DCXO HOLD LOCKED ACC 0 1 A/B REFB, REFB ÷ DELAY HOLD B DLL B 07805-011 Figure 19. Synchronization Block Diagram Synchronization/Switchover Control Figure 19, which is a block diagram of the hitless reference switchover circuit, shows that reference synchronization occurs after the input reference dividers. The synchronization and switchover functionality relies on the reference monitor logic to control the operation of the three delay-locked loops (DLLs). The delay blocks of the three DLLs are identical, so that they exhibit the same time delay for a given delay value setting. Note that the DCXO must be operational for the synchronization and switchover control to operate. Both the REFA and REFB paths have a dedicated DLL (DLL A and DLL B, respectively). DLL A and DLL B are each capable of operating in either an open-loop or closed-loop mode under the direction of the reference monitor status signals. When the reference monitor selects one of the references as the active reference, the DLL associated with the active reference operates in open-loop mode. While in open-loop mode, the DLL delays the active reference by a constant time interval based on a fixed delay value. As long as one of the references is the active reference, the other reference is, by default, the alternate reference. The DLL associated with the alternate reference operates in closedloop mode. While in closed-loop mode, the DLL automatically adjusts its delay so that the rising edge of the delayed alternate reference is edge-aligned with the rising edge of the delayed active reference. When the reference monitor selects one of the references as the active reference, it switches the output mux to select the output of the DLL associated with the active reference and, simultaneously, routes the active reference to the reference DLL. The reference DLL automatically measures the period of the active reference (with approximately 250 ps accuracy). When the reference DLL locks, the value of its delay setting (N) represents one period of the active reference. Upon acquiring lock, the reference DLL captures N and divides it by two (N/2 corresponds to a delay value that represents a half-cycle of the active reference). Both DLL A and DLL B have access to the N/2 value generated by the reference DLL. The following paragraphs describe the typical sequence of events resulting from a device reset, power-up, or return from holdover mode. Active Reference and Alternate Reference The reference monitor continuously checks for the presence of the divided REFA and/or REFB signals. If both signals are avail-able, the device arbitrarily selects one of them as the active reference, making the other the alternate reference. If only one of the references is available, it becomes the active reference, making the other the alternate reference (if it ever becomes available). In either case, the following two events occur: • • The output mux selects the output of the active DLL as the source to the input PLL. The input mux selects the active reference as the source to the reference DLL. Rev. B | Page 17 of 40 OUT ENABLE P F D DCXO HOLD LOCKED AD9551 The reference DLL measures the period of the active reference and produces the required N/2 delay value. When the reference DLL locks, the following three events occur: The absence of a REFB signal causes the device to perform a hitless switchover to REFA. If REFA is already the active reference, the absence of REFB results in no action, and REFA remains the active reference. In this way, the user can ensure that REFA is the active reference. Likewise, by using the same procedure but reversing the roles of the two references, the user can force the device to select REFB as the active reference. • • • Both DLL A and DLL B are enabled. The DLL associated with the active reference enters openloop mode. The DLL associated with the alternate reference enters closed-loop mode. Digitally Controlled Crystal Oscillator (DCXO) The DCXO is the fundamental building block of the input PLL (see the Input PLL section). The DCXO relies on an external crystal (19.44 MHz to 52 MHz) as its frequency source. The resonant frequency of the external crystal varies as a function of the applied load capacitance. The AD9551 has two internal capacitor banks (static and dynamic) that provide the required load capacitance. In operation, the control loop of the input PLL automatically adjusts the value of the capacitive load to push or pull the crystal resonant frequency over a small range of approximately ±50 ppm. The tuning capacitor bank sets the static load capacitance, which defaults to ~2 pF. The varactor bank is a dynamic capacitance controlled by the DCXO to push or pull the crystal resonant frequency. The nominal varactor capacitance is ~6 pF, and when combined with the 2 pF static capacitance and 2 pF of typical parasitic capacitance, the total crystal load capacitance is ~10 pF (default). The user can alter the default load capacitance by changing the static load capacitance of the tuning capacitor bank via Register 0x1B[5:0]. These six bits set the static load capacitance in 0.25 pF increments up to a maximum of ~16 pF. The control loop of the input PLL locks the DCXO to the active reference signal by dynamically controlling the varactor capacitance. Note that the narrow frequency control range (±50 ppm) of the varactor bank, combined with the default operating parameters of the AD9551, dictate the use of a crystal with specified load capacitance of 10 pF and a frequency tolerance of 20 ppm (see the NDK NX3225SA, for example). The narrow tuning range of the DCXO has two implications. First, the user must properly choose the divide ratio of the input reference divider to establish a frequency that is within the DCXO tuning range. Second, the user must ensure that the jitter/wander of the input reference is low enough to ensure the stability of the input PLL control loop for applications where the DCXO is the reference source for the output PLL (the default configuration). Normally, the input SDMs help to mitigate the input jitter because of the way they interact with the behavior of the input PLL. Input jitter becomes an issue, however, when the input dividers operate in integer-only mode or the input PLL is bypassed. This implies that the signal driving the input PLL is the active reference (after division by its input divider) with a half-cycle delay. Because the alternate DLL is in closed-loop mode, and assuming that the alternate reference is available, the output of the alternate DLL is edge-aligned with the delayed output of the active DLL. Furthermore, the closed-loop operation of the alternate DLL causes its delay value to be adjusted dynamically so that it maintains nominal edge alignment with the output of the active DLL. Edge alignment of the active and alternate references is the key to the hitless switchover capability of the AD9551. Reference Switchover and Holdover Mode If the reference monitor detects the loss of the active reference, it initiates the following three simultaneous operations: • • • The output mux selects the output of the alternate DLL. The alternate DLL holds its most recent delay setting (that is, the delay setting that edge-aligned the output of the alternate DLL with the output of the active DLL). Note that this operation ensures hitless switching between references. The new active reference is connected to the reference DLL to measure its period (that is, a new N/2 value). Because the failed alternate reference is assigned to the alternate DLL, upon its return the alternate DLL (which is in closed-loop mode) automatically edge-aligns the delayed alternate reference with the delayed active reference. Thus, if the new active reference fails, switchover to the alternate reference occurs in a hitless manner. This method of swapping the functionality of DLL A and DLL B as either active (open-loop) or alternate (closed-loop) allows for continuous hitless switching from one reference to the other, as needed (assuming the availability of an alternate reference upon failure of the active reference). Note that if both references fail, the device enters holdover mode. In this case, the reference monitor holds the DCXO at its last setting prior to the holdover condition, and the DCXO free runs at this setting until the holdover condition expires. Forcing Selection of the Active Reference Because the synchronization mechanism autonomously switches between references, the user has no way of knowing which reference is currently the active reference. However, the device can be forced to select a specific input reference as the active reference. For example, to force REFA to be the active reference, power down the REFB input receiver by programming the appropriate registers (or disconnect the REFB signal source). Rev. B | Page 18 of 40 AD9551 Input PLL The input PLL consists of a phase/frequency detector (PFD), a digital loop filter, and a digitally controlled crystal oscillator (DCXO) that operates in a closed loop. The loop contains a 2× frequency multiplier, a 2× frequency divider, a 5× divider that has a dedicated SDM, and switching logic, as shown in Figure 20. XTAL 19.44MHz MODE REG. 0x33[6] In all cases mentioned previously, the user must ensure that fREF meets the required relationship relative to the crystal resonant frequency. This is important because the narrow control range of the DCXO requires close adherence to the required frequency ratio (1/2, 1, or 2, depending on the selected option). Note, also, that the frequency delivered to the output PLL is always the same as fREF in normal mode. When the device is in 19.44 MHz mode, the user must ensure that fREF = 19.44 MHz. In 19.44 MHz mode, the configuration of the input PLL is different from that of normal mode. Specifically, the feed-back signal and the signal delivered to the output PLL are no longer the same. Instead, the device automatically configures the feedback path to include the 2× frequency multiplier along with a 5× divider coupled to a dedicated third-order SDM. The device automatically sets the modulus of this SDM based on the crystal frequency configured by Register 0x33[5:4]. This SDM also has a built-in PRBS generator to randomize its output sequence. Even though the device automatically configures the feedback path in 19.44 MHz mode, the user can select the 2× multiplied or 2× divided output of the DCXO as the signal to the output PLL. The 2× divider is in effect when Register 0x1D[2] = 0 (default). The 2× multiplier is in effect when Register 0x1D[2] = 1. Note that, unlike normal mode, the 19.44 MHz mode does not have a unity option. Using Register 0x1D[1] allows the user to bypass the entire input PLL section. With the input PLL bypassed, the prescaled active input reference signal (after synchronization) routes directly to the PFD of the output PLL. However, even when the input PLL is bypassed, the user must provide an external crystal so that the DCXO is functional because the reference monitor and reference synchronization blocks use the DCXO output as a clock source. fREF ÷2 P DIG. F LOOP D FILTER DCXO 2x SDM 1 0 19.44MHz MODE 1 0 0 1 REG. 0x1D[2] TO OUTPUT PLL ÷5 07805-012 Figure 20. Input PLL The input PLL has a digital loop filter with a loop bandwidth of approximately 180 Hz. This relatively narrow loop bandwidth gives the AD9551 the ability to suppress jitter appearing on the input references (REFA and REFB). By default, the sample rate of the digital loop filter is fREF/8 (fREF is the frequency of the active input reference after it is scaled down by the input divider). This yields a loop response with peaking of typically