14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) AD9642
FEATURES
SNR = 71.0 dBFS at 185 MHz AIN and 250 MSPS SFDR = 83 dBc at 185 MHz AIN and 250 MSPS −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS AIN, 250 MSPS Total power consumption: 390 mW at 250 MSPS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS IF sampling frequencies of up to 350 MHz Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer Serial port control Energy saving power-down modes User-configurable, built-in self-test (BIST) capability
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD
VIN+ VIN– VCM
PIPELINE 14-BIT ADC
14 PARALLEL DDR LVDS AND DRIVERS
D0±/D1±
AD9642
D12±/D13±
DCO± REFERENCE
SERIAL PORT
1-TO-8 CLOCK DIVIDER
09995-001
SCLK
SDIO
CSB
CLK+
CLK–
Figure 1.
APPLICATIONS
Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications
GENERAL DESCRIPTION
The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The ADC output data is routed directly to the external 14-bit LVDS output port. Flexible power-down options allow significant power savings, when desired.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz. 3-pin, 1.8 V SPI port for register programming and readback. Pin compatibility with the AD9634, allowing a simple migration from 14 bits to 12 bits, and with the AD6672.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD9642 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 Thermal Characteristics .............................................................. 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Equivalent Circuits ......................................................................... 16 Theory of Operation ...................................................................... 17 ADC Architecture ...................................................................... 17 Analog Input Considerations ................................................... 17 Voltage Reference ....................................................................... 19 Clock Input Considerations...................................................... 19 Power Dissipation and Standby Mode .................................... 20 Digital Outputs ........................................................................... 20 Serial Port Interface (SPI).............................................................. 22 Configuration Using the SPI..................................................... 22 Hardware Interface..................................................................... 22 SPI Accessible Features.............................................................. 23 Memory Map .................................................................................. 24 Reading the Memory Map Register Table............................... 24 Memory Map Register Table..................................................... 25 Applications Information .............................................................. 27 Design Guidelines ...................................................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9642 SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) 1 TEMPERATURE DRIFT Offset Error Gain Error INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span Input Capacitance 2 Input Resistance 3 Input Common-Mode Voltage POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 POWER CONSUMPTION Sine Wave Input (DRVDD = 1.8 V) Standby Power 4 Power-Down Power
1 2 3
Temperature Full Full Full Full Full 25°C Full 25°C Full Full 25°C
Min 14
AD9642-170 Typ Max
Min 14
AD9642-210 Typ Max
Min 14
AD9642-250 Typ Max
Unit Bits
Guaranteed ±11 +2/−11 ±0.5 ±0.3 ±1.3 ±0.6 ±7 ±52 0.83
Guaranteed ±11 +3.5/−8 ±0.55 ±0.3 ±2.0 ±0.75 ±7 ±105 0.85
Guaranteed ±10 +3/−7 ±0.6 ±0.32 ±2.5 ±1.0 ±7 ±75 0.85 mV %FSR LSB LSB LSB LSB ppm/°C ppm/°C LSB rms V p-p pF kΩ V
Full Full Full Full
1.75 2.5 20 0.9
1.75 2.5 20 0.9
1.75 2.5 20 0.9
Full Full Full Full Full Full Full
1.7 1.7
1.8 1.8 123 50 311 50 5
1.9 1.9 136 64 360
1.7 1.7
1.8 1.8 129 56 333 50 5
1.9 1.9 139 67 371
1.7 1.7
1.8 1.8 136 64 360 50 5
1.9 1.9 146 69 387
V V mA mA mW mW mW
Measured with a low input frequency, full-scale sine wave. Input capacitance refers to the effective capacitance between one differential input pin and its complement. Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).
Rev. 0 | Page 3 of 28
AD9642
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted. Table 2.
Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz TWO-TONE SFDR fIN = 184.1 MHz, 187.1 MHz (−7 dBFS) Temperature 25°C 25°C Full 25°C 25°C Full 25°C Min AD9642-170 Typ Max 72.5 72.2 70.7 71.8 71.2 70.7 70.0 71.6 71.5 68.6 71.0 70.9 71.8 71.4 Min AD9642-210 Typ Max 72.4 72.2 Min AD9642-250 Typ Max 72.2 72.0 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS
25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C Full 25°C
71.5 71.3 69.6 70.8 70.3 69.7 11.6 11.6 11.5 11.4 11.3 −96 −95 −82 −97 −86 −84 68.7
71.5 71.3 70.6 70.5 67.5 70.1 11.6 11.6 11.4 11.4 11.3 −96 −92 −79 −94 −95 −84
71.2 71.0 70.9 70.4 70.0 11.5 11.5 11.5 11.4 11.3 −90 −89 −90 −86 −80 −86
dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc
25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C Full 25°C 25°C Full 25°C 25°C
96 95 82 97 86 84 −99 −95 −87 −98 −96 −97 87
Rev. 0 | Page 4 of 28
96 92 79 94 95 80 84 −98 −97 −81 −96 −97 −94 88
90 89 90 86 86 −95 −98 −97 −96 −81 −95 88
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
AD9642
Parameter 1 FULL POWER BANDWIDTH 2 NOISE BANDWIDTH 3
1 2
Temperature 25°C 25°C
Min
AD9642-170 Typ Max 350 1000
Min
AD9642-210 Typ Max 350 1000
Min
AD9642-250 Typ Max 350 1000
Unit MHz MHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved. 3 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise may enter the ADC and is not attenuated internally.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3.
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS LVDS Data and OR Outputs (OR+, OR−) Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode
1 2
Temperature
Min
Typ
Max
Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
0.3 AGND 0.9 10 −22 12 1.22 0 50 −5
CMOS/LVDS/LVPECL 0.9 3.6 AVDD 1.4 22 −10 4 15 18 2.1 0.6 71 +5 26 2
V V p-p V V μA μA pF kΩ V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF
1.22 0 45 −5 26 2 1.22 0 45 −5 26 5
2.1 0.6 70 +5
2.1 0.6 70 +5
Full Full Full Full
250 1.15 150 1.15
350 1.25 200 1.25
450 1.35 280 1.35
mV V mV V
Pull-up. Pull-down.
Rev. 0 | Page 5 of 28
AD9642
SWITCHING SPECIFICATIONS
Table 4.
Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 Mode Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO-to-Data Skew (tSKEW) Pipeline Delay (Latency) Wake-Up Time (from Standby) Wake-Up Time (from Power-Down) Out-of-Range Recovery Time
1
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Min
AD9642-170 Typ Max 625 170
Min
AD9642-210 Typ Max 625 210
Min
AD9642-250 Typ Max 625 250
Unit MHz MSPS ns ns ns ns ns ps rms
40 5.8 2.61 2.76 0.8 2.9 2.9
40 4.8 2.16 2.28 0.8 2.4 2.4
40 4 1.8 1.9 0.8 2.0 2.0
3.19 3.05
2.64 2.52
2.2 2.1
1.0 0.1
4.1 4.7 4.7 5.3
1.0 0.1 5.2
5.8 4.1 4.7 4.7 5.3
1.0 0.1 5.2
5.8 4.1 4.7 4.7 5.3
5.2
5.8
0.3
0.5 10 10 100 3
0.7
0.3
0.5 10 10 100 3
0.7
0.3
0.5 10 10 100 3
0.7
ns ns ns Cycles μs μs Cycles
Conversion rate is the clock rate after the divider.
Timing Diagram
tA
N–1 N VIN N+1 N+2 N+4 N+5 N+3
tCH
CLK+ CLK–
tCLK
tDCO
DCO– DCO+
tSKEW tPD
D0 N – 10 D1 N – 10 D0 N–9 D1 N–9 D0 N–8 D1 N–8 D0 N–7 D1 N–7 D0 N–6
EVEN/ODD
D0±/D1± (LSB)
D12±/D13± (MSB)
D12 N – 10
D13 N – 10
D12 N–9
D13 N–9
D12 N–8
D13 N–8
D12 N–7
D12 N–7
D12 N–6
Figure 2. LVDS Data Output Timing
Rev. 0 | Page 6 of 28
09995-002
AD9642
TIMING SPECIFICATIONS
Table 5.
Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments See Figure 58 for SPI timing diagram Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) Min 2 2 40 2 2 10 10 10 10 Typ Max Unit ns ns ns ns ns ns ns ns ns
Rev. 0 | Page 7 of 28
AD9642 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Electrical AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND D0−/D1−, D0+/D1+ Through D12−/D13−, D12+/D13+ to AGND DCO+, DCO− to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V
1
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 7. Thermal Resistance
Airflow Velocity (m/sec) 0 1.0 2.0
Package Type 32-Lead LFCSP 5 mm × 5 mm (CP-32-12)
θJA1, 2 37.1 32.4 29.1
θJC1, 3 3.1
θJB1, 4 20.7
Unit °C/W °C/W °C/W
−40°C to +85°C 150°C −65°C to +125°C
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air).
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces—through holes, ground, and power planes—reduces the θJA.
ESD CAUTION
Rev. 0 | Page 8 of 28
AD9642 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
AVDD AVDD VIN+ VIN– AVDD AVDD VCM DNC
CLK+ CLK– AVDD D0–/D1– (LSB) D0+/D1+ (LSB) D2–/D3– D2+/D3+ DRVDD
1 2 3 4 5 6 7 8
AD9642
INTERLEAVED LVDS TOP VIEW (Not to Scale)
CSB SCLK SDIO DCO+ DCO– D12+/D13+ (MSB) D12–/D13– (MSB) DRVDD
NOTES 1. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 2. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
D4–/D5– D4+/D5+ D6–/D7– D6+/D7+ D8–/D9– D8+/D9+ D10–/D11– D10+/D11+
9 10 11 12 13 14 15 16
Figure 3. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No. ADC Power Supplies 8, 17 3, 27, 28, 31, 32 0 Mnemonic DRVDD AVDD AGND, Exposed Paddle DNC VIN+ VIN− VCM CLK+ CLK− D0+/D1+ (LSB) D0−/D1− (LSB) D2+/D3+ D2−/D3− D4+/D5+ D4−/D5− D6+/D7+ D6−/D7− D8+/D9+ D8−/D9− D10+/D11+ D10−/D11− D12+/D13+ (MSB) D12−/D13− (MSB) DCO+ DCO− SCLK SDIO CSB Input Input Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input/output Input Type Supply Supply Ground Description Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Analog Ground. The exposed thermal paddle on the bottom of the package provides the analog ground for the part. This exposed paddle must be connected to ground for proper operation. Do Not Connect. Do not connect to this pin. Differential Analog Input Pin (+). Differential Analog Input Pin (−). Common-Mode Level Bias Output for Analog Inputs. This pin should be decoupled
25 ADC Analog 30 29 26 1 2 Digital Outputs 5 4 7 6 10 9 12 11 14 13 16 15 19 18 21 20 SPI Control 23 22 24
to ground using a 0.1 μF capacitor.
ADC Clock Input—True. ADC Clock Input—Complement. DDR LVDS Output Data 0/1—True. DDR LVDS Output Data 0/1—Complement. DDR LVDS Output Data 2/3—True. DDR LVDS Output Data 2/3—Complement. DDR LVDS Output Data 4/5—True. DDR LVDS Output Data 4/5—Complement. DDR LVDS Output Data 6/7—True. DDR LVDS Output Data 6/7—Complement. DDR LVDS Output Data 8/9—True. DDR LVDS Output Data 8/9—Complement. DDR LVDS Output Data 10/11—True. DDR LVDS Output Data 10/11—Complement. DDR LVDS Output Data 12/13—True. DDR LVDS Output Data 12/13—Complement. LVDS Data Clock Output—True. LVDS Data Clock Output—Complement. SPI Serial Clock. SPI Serial Data I/O. SPI Chip Select (Active Low).
Rev. 0 | Page 9 of 28
09995-003
AD9642 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample, TA = 25°C, unless otherwise noted.
0 –20 –40
AMPLITUDE (dBFS)
0 170MSPS 90.1MHz @ –1dBFS SNR = 71.82dB (72.2dBFS) SFDR = 93dBc –20 –40 170MSPS 305.1MHz @ –1dBFS SNR = 68.0dB (69.0dBFS) SFDR = 86dBc
–60 –80 –100 –120 –140 SECOND HARMONIC THIRD HARMONIC
AMPLITUDE (dBFS)
–60 –80 –100 –120 –140
SECOND HARMONIC THIRD HARMONIC
09995-004
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
Figure 4. AD9642-170 Single-Tone FFT with fIN = 90.1 MHz
Figure 7. AD9642-170 Single-Tone FFT with fIN = 305.1 MHz
0 –20 –40 170MSPS 185.1MHz @ –1dBFS SNR = 70.2dB (71.2dBFS) SFDR = 86dBc
120 SFDR (dBFS) 100
SNR/SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
80
SNR (dBFS)
–60 –80 –100 –120 –140 THIRD HARMONIC SECOND HARMONIC
60 SFDR (dBc) 40 SNR (dBc) 20
09995-005
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
–90
–80
–70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS)
–20
–10
0
Figure 5. AD9642-170 Single-Tone FFT with fIN = 185.1 MHz
Figure 8. AD9642-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 90.1 MHz, fS = 170 MSPS
100
0 –20 –40 170MSPS 220.1MHz @ –1dBFS SNR = 69.7dB (70.7dBFS) SFDR = 84dBc
95 90
SFDR (dBc)
SUPPLY CURRENT (A)
AMPLITUDE (dBFS)
85 80 75 70 65
–60 –80 –100 –120 –140
THIRD HARMONIC SECOND HARMONIC
SNR (dBFS)
09995-006
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
75
105
Figure 6. AD9642-170 Single-Tone FFT with fIN = 220.1 MHz
Figure 9. AD9642-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN), fS = 170 MSPS
Rev. 0 | Page 10 of 28
09995-058
60 60
90
120 150 180 210 240 270 300 330 135 165 195 225 255 285 315 345 FREQUENCY (MHz)
09995-007
0 –100
09995-106
AD9642
0 0 –20 SFDR (dBc) –40 IMD3 (dBc) –60 –40 170MSPS 184.12MHz @ –7dBFS 187.12MHz @ –7dBFS SFDR = 87dBc (94dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
AMPLITUDE (dBFS)
09995-009
–60 –80 –100 –120
–80 SFDR (dBFS) –100 IMD3 (dBFS)
0
10
20
INPUT AMPLITUDE (dBFS)
30 40 50 60 FREQUENCY (MHz)
70
80
Figure 10. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS
Figure 13. AD9642-170 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
0
100 SFDR (dBFS)
–20
95
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBc and dBFS)
SFDR (dBc) –40 IMD3 (dBc) –60
90
85
–80 SFDR (dBFS) –100 IMD3 (dBFS) –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS)
09995-010
80
75 SNR (dBc)
09995-013
09995-014
70 40
50
60
70
80
90 100 110 120 130 140 150 160 170
SAMPLE RATE (MSPS)
Figure 11. AD9642-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS
Figure 14. AD9642-170 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90 MHz
0 –20 –40 170MSPS 89.12MHz @ –7dBFS 92.12MHz @ –7dBFS SFDR = 88dBc (95dBFS)
6000 0.830 LSB rms 16,384 TOTAL HITS 5000
AMPLITUDE (dBFS)
–60 –80 –100 –120 –140
NUMBER OF HITS
4000
3000
2000
1000
N+1
N+2
N+3
N+4
N+5
OUTPUT CODE
Figure 12. AD9642-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
Figure 15. AD9642-170 Grounded Input Histogram, fS = 170 MSPS
Rev. 0 | Page 11 of 28
N+6
N–5
N–4
N–3
N–2
N–1
0
10
20
30 40 50 60 FREQUENCY (MHz)
70
80
09995-011
0
N
09995-012
–120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
–140
AD9642
0 –20 –40 –60 –80 –100 –120 –140 THIRD HARMONIC SECOND HARMONIC 210MSPS 90.1MHz @ –1dBFS SNR = 71.2dB (72.2dBFS) SFDR = 92dBc
0 –20 –40
AMPLITUDE (dBFS)
210MSPS 305.1MHz @ –1dBFS SNR = 68.7dB (69.7dBFS) SFDR = 83dBc
AMPLITUDE (dBFS)
–60 –80 –100 –120 –140
SECOND HARMONIC
THIRD HARMONIC
09995-015
0
15
30
45
60
75
90
105
0
15
30
45
60
75
90
105
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. AD9642-210 Single-Tone FFT with fIN = 90.1 MHz
Figure 19. AD9642-210 Single-Tone FFT with fIN = 305.1 MHz
0 –20 –40 –60 –80 –100 –120 –140 SECOND HARMONIC THIRD HARMONIC 210MSPS 185.1MHz @ –1dBFS SNR = 70.5dB (71.5dBFS) SFDR = 93dBc
120 SFDR (dBFS) 100
SNR/SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
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SNR (dBFS)
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FREQUENCY (MHz)
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–20
–10
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Figure 17. AD9642-210 Single-Tone FFT with fIN = 185.1 MHz
Figure 20. AD9642-210 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 90.1 MHz, fS = 210 MSPS
100
0 –20 –40 –60 –80 –100 –120 –140 SECOND HARMONIC THIRD HARMONIC 210MSPS 220.1MHz @ –1dBFS SNR = 70dB (71dBFS) SFDR = 84dBc
95 SFDR (dBc)
SNR/SFDR (dBc and dBFS)
90 85 80 75 SNR (dBFS) 70 65
AMPLITUDE (dBFS)
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FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 18. AD9642-210 Single-Tone FFT with fIN = 220.1 MHz
Figure 21. AD9642-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN), fS = 210 MSPS
Rev. 0 | Page 12 of 28
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AD9642
0
0 –20
210MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS SFDR = 88dBc (95dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
SFDR (dBc)
AMPLITUDE (dBFS)
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–40 IMD3 (dBc) –60
–40 –60 –80 –100 –120
–80 SFDR (dBFS) –100 IMD3 (dBFS)
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90
105
FREQUENCY (MHz)
Figure 22. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 210 MSPS
Figure 25. AD9642-210 Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
0
100 SFDR (dBc)
–20
95
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBc and dBFS)
SFDR (dBc)
–40
IMD3 (dBc)
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–60
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–80
SFDR (dBFS)
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–100
IMD3 (dBFS)
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75 SNR (dBFS) 70
INPUT AMPLITUDE (dBFS)
SAMPLE RATE (MSPS)
Figure 23. AD9642-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 210 MSPS
Figure 26. AD9642-210 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90 MHz
0 –20 –40 –60 –80 –100 –120 –140 210MSPS 89.12MHz @ –7dBFS 92.12MHz @ –7dBFS SFDR = 89dBc (96dBFS)
6000 0.852 LSB rms 16,384 TOTAL HITS 5000
AMPLITUDE (dBFS)
NUMBER OF HITS
4000
3000
2000
1000
N+1
N+2
N+3
N+4
N+5
N+6
N–5
N–4
N–3
N–2
N–1
FREQUENCY (MHz)
OUTPUT CODE
Figure 24. AD9642-210 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
Figure 27. AD9642-210 Grounded Input Histogram, fS = 210 MSPS
Rev. 0 | Page 13 of 28
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–120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0
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–120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 INPUT AMPLITUDE (dBFS)
–140
AD9642
0 –20 –40 –60 –80 –100 –120 –140 THIRD HARMONIC SECOND HARMONIC 250MSPS 90.1MHz @ –1dBFS SNR = 71dB (72dBFS) SFDR = 89dBc 0 –20 –40 –60 –80 –100 –120 –140 250MSPS 305.1MHz @ –1dBFS SNR = 68.5dB (69.5dBFS) SFDR = 82dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
SECOND HARMONIC THIRD HARMONIC
0
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125
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FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. AD9642-250 Single-Tone FFT with fIN = 90.1 MHz
Figure 31. AD9642-250 Single-Tone FFT with fIN = 305.1 MHz
0 –20 –40 –60 –80 –100 –120 –140 THIRD HARMONIC SECOND HARMONIC 250MSPS 185.1MHz @ –1dBFS SNR = 70.4dB (71.4dBFS) SFDR = 86dBc
120 SFDR (dBFS) 100
SNR/SFDR (dBc AND dBFS)
AMPLITUDE (dBFS)
80
SNR (dBFS)
60 SFDR (dBc) 40 SNR (dBc) 20
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–90
–80
FREQUENCY (MHz)
–70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS)
–20
–10
0
Figure 29. AD9642-250 Single-Tone FFT with fIN = 185.1 MHz
Figure 32. AD9642-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 90.1 MHz, fS = 250 MSPS
100
0 –20 –40
250MSPS 220.1MHz @ 1.0dBFS SNR = 69.9dB (70.9dBFS) SFDR = 91dBc
SNR/SFDR (dBc and dBFS)
95 SFDR (dBFS) 90 85 80 75 70 SNR (dBc) 65 60
AMPLITUDE (dBFS)
–60 –80 –100 –120 –140
THIRD HARMONIC SECOND HARMONIC
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0
25
50
75
100
125
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. AD9642-250 Single-Tone FFT with fIN = 220.1 MHz
Figure 33. AD9642-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN), fS = 250 MSPS
Rev. 0 | Page 14 of 28
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AD9642
0
0 –20
250MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS SFDR = 87dBc (94dBFS)
–20
SFDR/IMD3 (dBc and dBFS)
SFDR (dBc) –40 IMD3 (dBc) –60
–40
AMPLITUDE (dBFS)
09995-031
–60 –80 –100 –120
–80 SFDR (dBFS) –100 IMD3 (dBFS)
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125
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 34. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
Figure 37. AD9642-250 Two Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz
0
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–20
95
SNR/SFDR (dBFS/dBc)
SFDR/IMD3 (dBc and dBFS)
SFDR (dBc) –40 IMD3 (dBc) –60
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–80 SFDR (dBFS) –100 IMD3 (dBFS)
80
75 SNR
09995-032
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250
INPUT AMPLITUDE (dBFS)
SAMPLE RATE (MSPS)
Figure 35. AD9642-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
Figure 38. AD9642-250 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90 MHz
0 –20 –40
NUMBER OF HITS
5000
250MSPS 89.12MHz @ –7.0dBFS 92.12MHz @ –7.0dBFS SFDR = 88dBc (95dBFS)
4500 4000 3500 3000 2500 2000 1500 1000
0.847LSB rms 16,384 TOTAL HITS
AMPLITUDE (dBFS)
–60 –80 –100 –120 –140
500
09995-033
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25
50 75 FREQUENCY (MHz)
100
125
N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 OUTPUT CODE
Figure 36. AD9642-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz
Figure 39. AD9642-250 Grounded Input Histogram, fS = 250 MSPS
Rev. 0 | Page 15 of 28
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–140
AD9642 EQUIVALENT CIRCUITS
DRVDD
AVDD VIN
SDIO
09995-037
350Ω 26kΩ
Figure 40. Equivalent Analog Input Circuit
Figure 43. Equivalent SDIO Circuit
AVDD
AVDD 0.9V CLK+ 15kΩ 15kΩ
AVDD
SCLK 350 Ω 26kΩ
CLK–
09995-038
Figure 41. Equivalent Clock Input Circuit
Figure 44. Equivalent SCLK Input Circuit
DRVDD
AVDD 26kΩ 350 Ω
V+ DATAOUT– V–
V– DATAOUT+ V+
CSB
09995-039
Figure 42. Equivalent LVDS Output Circuit
Figure 45. Equivalent CSB Input Circuit
Rev. 0 | Page 16 of 28
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09995-041
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AD9642 THEORY OF OPERATION
The AD9642 can sample any fS/2 frequency segment from dc to 250 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Programming and control of the AD9642 are accomplished using a 3-pin, SPI-compatible serial interface. “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject.
BIAS S CS VIN+ CPAR1 CPAR2 H CS VIN– S
09995-043
S CFB
ADC ARCHITECTURE
The AD9642 architecture consists of a front-end sample-andhold circuit, followed by a pipelined switched-capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of the AD9642 contains a differential sampling circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state.
S
S
CPAR1
CPAR2 BIAS
S
CFB
Figure 46. Switched-Capacitor Input
For best dynamic performance, match the source impedances driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9642 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. An onboard common-mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Place this decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9642 is a differential switchedcapacitor circuit that has been designed to attain optimum performance when processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in Figure 46). When the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, the shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article,
Differential Input Configurations
Optimum performance can be achieved when driving the AD9642 in a differential input configuration. For baseband applications, the AD8138, ADA4937-1, and ADA4930-1 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4930-1 is easily set with the VCM pin of the AD9642 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal.
15pF 200Ω VIN 76.8Ω 90Ω 33Ω 5pF 15Ω VIN– AVDD ADC 15Ω VIN+ VCM
ADA4930-1
0.1µF 120Ω 200Ω 15pF 33Ω
0.1µF
Figure 47. Differential Input Configuration Using the ADA4930-1
Rev. 0 | Page 17 of 28
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AD9642
For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 48. To bias the analog input, connect the VCM voltage to the center tap of the secondary winding of the transformer.
C2 R3 R1 2V p-p 49.9Ω C1 R1 0.1µF C2 R2 VIN– ADC VCM R2 VIN+
adjusted or some components may need to be removed. Table 9 displays recommended values to set the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. Note that the values given in Table 9 are for each R1, R2, C2, and R3 component shown in Figure 48 and Figure 50. Table 9. Example RC Network
Frequency Range (MHz) 0 to 100 100 to 300 R1 Series (Ω) 33 15 C1 Differential (pF) 8.2 3.9 R2 Series (Ω) 0 0 C2 Shunt (pF) 15 8.2 R3 Shunt (Ω) 49.9 49.9
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R3
0.1µF
Figure 48. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz. Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9642. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 50). In this configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω resistor. This resistor compensates for losses in the input baluns to provide a 50 Ω impedance to the driver. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters, the value of the input resistors and capacitors may need to be
An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use an amplifier with variable gain. The AD8375 digital variable gain amplifier (DVGA) provides good performance for driving the AD9642. Figure 49 shows an example of the AD8375 driving the AD9642 through a band-pass antialiasing filter.
1000pF 180nH 220nH
1µH VPOS
165Ω 5.1pF 1nF 301Ω 3.9pF 165Ω
15pF VCM 1nF 68nH
AD8375
1µH
AD9642
2.5kΩ║2pF
1000pF 180nH 220nH NOTES 1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz.
Figure 49. Differential Input Configuration Using the AD8375
C2 0.1µF 2V p-p PA S S P 0.1µF 33Ω 0.1µF 33Ω 0.1µF C1 R1 R2 VIN– ADC VCM R3 R1 R2
VIN+
R3 C2
0.1µF
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Figure 50. Differential Double Balun Input Configuration
Rev. 0 | Page 18 of 28
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AD9642
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9642. The full-scale input range can be adjusted by varying the reference voltage via SPI. The input span of the ADC tracks reference voltage changes linearly.
CLOCK INPUT 390pF 25Ω 390pF
ADC
CLK+
390pF 1nF 25Ω SCHOTTKY DIODES: HSMS2822 CLK–
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CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9642 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or via capacitors. These pins are biased internally (see Figure 51) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking.
AVDD
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 54. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/ ADCLK925 clock drivers offer excellent jitter performance.
0.1µF 0.1µF CLK+
0.9V CLK+ 4pF 4pF
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CLK–
CLOCK INPUT
50kΩ
50kΩ
240Ω
240Ω
Figure 51. Simplified Equivalent Clock Input Circuit
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
Clock Input Options
The AD9642 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 52 and Figure 53 show two preferable methods for clocking the AD9642 (at clock rates of up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the secondary winding of the transformer limit clock excursions into the AD9642 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9642 while preserving the fast rise and fall times of the signal, which are critical for low jitter performance.
Mini-Circuits® ADT1-1WT, 1:1Z 390pF XFMR 100Ω 390pF CLK– SCHOTTKY DIODES: HSMS2822
09995-056
A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 55. The AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers offer excellent jitter performance.
0.1µF CLOCK INPUT 0.1µF CLK+
AD95xx
0.1µF CLOCK INPUT 50kΩ 50kΩ LVDS DRIVER
100Ω 0.1µF
ADC
AD9642
CLK–
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Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9642 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The duty cycle stabilizer (DCS) is enabled by default on power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9642 contains a DCS that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9642. Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer. The duty
CLOCK INPUT
390pF 50Ω
ADC
CLK+
Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)
Rev. 0 | Page 19 of 28
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CLOCK INPUT
0.1µF
AD95xx, ADCLK9xx
100Ω 0.1µF
ADC
PECL DRIVER
AD9642
CLK–
AD9642
cycle control loop does not function for clock rates less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate may change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. using the same operating conditions as those used for the Typical Performance Characteristics section.
0.4
0.25
0.20
TOTAL POWER (W)
TOTAL POWER
0.15
IAVDD 0.2
0.10
0.1 IDRVDD
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 (−SNRLF /10) ] In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 56.
80
0.05
40
55
70
ENCODE FREQUENCY (MSPS)
Figure 57. AD9642-250 Power and Current vs. Sample Rate
By setting the internal power-down mode bits (Bits[1:0]) in the power modes register (Address 0x08) to 01, the AD9642 is placed in power-down mode. In this state, the ADC typically dissipates 2.5 mW. During power-down, the output drivers are placed in a high impedance state. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. To put the part into standby mode, set the internal power-down mode bits (Bits[1:0]) in the power modes register (Address 0x08) to 10. See the Memory Map section and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional details.
75
70
SNR (dBFS)
65
60
0.05ps 0.2ps 0.5ps 1ps 1.5ps MEASURED
55
1
10
100
1000
INPUT FREQUENCY (MHz)
Figure 56. AD9642-250 SNR vs. Input Frequency and Jitter
In cases where aperture jitter may affect the dynamic range of the AD9642, treat the clock input as an analog signal. In addition, use separate power supplies for the clock drivers and the ADC output driver to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators provide the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step. Refer to the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs.
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50
DIGITAL OUTPUTS
The AD9642 output drivers can be configured for either ANSI LVDS or reduced swing LVDS using a 1.8 V DRVDD supply. As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control.
Digital Output Enable Function (OEB)
The AD9642 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SPI interface. The data outputs can be three-stated by using the output enable bar bit (Bit 4) in Register 0x14. This OEB function is not intended for rapid access to the data bus.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the power dissipated by the AD9642 is proportional to its sample rate. The data in Figure 57 was taken
Rev. 0 | Page 20 of 28
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0
0 85 100 115 130 145 160 175 190 205 220 235 250
SNR/SFDR (dBc and dBFS)
0.3
AD9642
Timing
The AD9642 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length of the output data lines as well as the loads placed on these lines to reduce transients within the AD9642. These transients may degrade converter dynamic performance. The lowest typical conversion rate of the AD9642 is 40 MSPS. At clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9642 also provides the data clock output (DCO) intended for capturing the data in an external register. Figure 2 shows a timing diagram of the AD9642 output modes.
Table 10. Output Data Format
Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN−, Input Span = 1.75 V p-p (V) +0.875 Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Twos Complement Mode (Default) 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111
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AD9642 SERIAL PORT INTERFACE (SPI)
The AD9642 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 11). The SCLK (serial clock) pin is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) pin is a dualpurpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 11. Serial Port Interface Pins
Pin SCLK SDIO Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles.
HARDWARE INTERFACE
The pins described in Table 11 comprise the physical interface between the user programming device and the serial port of the AD9642. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9642 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
CSB
The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 58 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits.
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AD9642
SPI ACCESSIBLE FEATURES
Table 12 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Table 12. Features Accessible Using the SPI
Feature Name Mode Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Digital Processing Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage Allows the user to enable the synchronization features
tDS tS
CSB
tHIGH tDH tLOW
tCLK
tH
SCLK
DON’T CARE
DON’T CARE
SDIO
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 58. Serial Port Interface Timing Diagram
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09995-055
AD9642 MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the transfer register (Address 0xFF); and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x25). The memory map register table (Table 13) documents the default hexadecimal value for each hexadecimal address shown. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1 and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0x25. Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written.
Default Values
After the AD9642 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (Table 13).
Logic Levels
An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x20 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears.
Open Locations
All address and bit locations that are not included in Table 13 are not currently supported for this device. Write 0s to unused bits of a valid address location. Writing to these locations is required only when part of an address location is open (for example,
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AD9642
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device. Table 13. Memory Map Registers
Addr Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI port configuration Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments Nibbles are mirrored so that LSB first mode or MSB first mode is set correctly, regardless of shift mode. Read only.
0x01
Chip ID
0x02
Chip grade
Open
Open
8-bit chip ID[7:0] (AD9642 = 0x86) (default) Speed grade ID Open 00 = 250 MSPS 01 = 210 MSPS 11 = 170 MSPS
0x86
Open
Open
Open
Speed grade ID used to differentiate devices; read only. 0x00 Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation.
Transfer Register 0xFF Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
ADC Functions Registers 0x08 Power modes
Open
Open
Open
Open
Open
Open
Internal power-down mode 00 = normal operation 01 = full power-down 10 = standby 11 = reserved Duty cycle stabilizer (default) Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Open
0x00
0x09
Global clock
Open
Open
Open
Open
Open
Open
0x01
0x0B
Clock divide
Open
Open
Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles
0x00
0x0D
Test mode
User test mode control 0 = continuous/ repeat pattern 1 = single pattern, then 0s
Open
Reset PN long gen
Reset PN short gen
Output test mode 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN long sequence 0110 = PN short sequence 0111 = one/zero word toggle 1000 = user test mode 1001 to 1110 = unused 1111 = ramp output
0x00
Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active. When this register is set, the test data is placed on the output pins in place of normal data.
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AD9642
Addr (Hex) 0x0E 0x10 0x14 Register Name BIST enable Offset adjust Output mode Bit 7 (MSB) Open Open Open Bit 6 Open Open Open Open Bit 5 Open Bit 4 Open Bit 2 Bit 1 Open Reset BIST sequence Offset adjust in LSBs from +31 to −32 (twos complement format) Open Output format Output Output enable bar invert 00 = offset binary 0 = normal 01 = twos complement 0 = on (default) (default) (default) 1 = inverted 10 = gray code 1 = off 11 = reserved Bit 3 Open Bit 0 (LSB) BIST enable Default Value (Hex) 0x00 0x00 0x01 Configures the outputs and the format of the data. Default Notes/ Comments
0x15
Output adjust
Open
Open
Open
Open
0x16
Clock phase control DCO output delay
Invert DCO clock Enable DCO clock delay
Open
Open
Open
LVDS output drive current adjust 0000 = 3.72 mA output drive current 0001 = 3.5 mA output drive current (default) 0010 = 3.30 mA output drive current 0011 = 2.96 mA output drive current 0100 = 2.82 mA output drive current 0101 = 2.57 mA output drive current 0110 = 2.27 mA output drive current 0111 = 2.0 mA output drive current (reduced range) 1000 to 1111 = reserved Open Open Open Open
0x01
0x00
0x17
Open
Open
0x18
Input span select
Open
Open
Open
0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x24 0x25
User Test Pattern 1 LSB User Test Pattern 1 MSB User Test Pattern 2 LSB User Test Pattern 2 MSB User Test Pattern 3 LSB User Test Pattern 3 MSB User Test Pattern 4 LSB User Test Pattern 4 MSB BIST signature LSB BIST signature MSB
DCO clock delay [delay = (3100 ps × register value/31 + 100)] 00000 = 100 ps 00001 = 200 ps 00010 = 300 ps … 11110 = 3100 ps 11111 = 3200 ps Full-scale input voltage selection 01111 = 2.087 V p-p … 00001 = 1.772 V p-p 00000 = 1.75 V p-p (default) 11111 = 1.727 V p-p … 10000 = 1.383 V p-p User Test Pattern 1[7:0] User Test Pattern 1[15:8] User Test Pattern 2[7:0] User Test Pattern 2[15:8] User Test Pattern 3[7:0] User Test Pattern 3[15:8] User Test Pattern 4[7:0] User Test Pattern 4[15:8] BIST signature[7:0] BIST signature[15:8]
0x00
0x00
Full-scale input adjustment in 0.022 V steps.
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Read only. Read only.
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AD9642 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD9642, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins.
VCM
Decouple the VCM pin to ground with a 0.1 μF capacitor, as shown in Figure 48.
SPI Port
The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9642 to keep these signals from transitioning at the converter input pins during critical sampling periods.
Power and Ground Recommendations
When connecting power to the AD9642, it is recommended that two separate 1.8 V supplies be used: use one supply for analog (AVDD) and a separate supply for the digital outputs (DRVDD). The designer can employ several different decoupling capacitors to cover both high and low frequencies. Locate these capacitors close to the point of entry at the PC board level and close to the pins of the part with minimal trace length. A single PCB ground plane should be sufficient when using the AD9642. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9642 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged with nonconductive epoxy. To maximize the coverage and adhesion between the ADC and the PCB, overlay a silkscreen to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. See the evaluation board for a PCB layout example. For detailed information about the packaging and PCB layout of chip scale packages, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
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AD9642 OUTLINE DIMENSIONS
PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18
25 24 32 1
PIN 1 INDICATOR
*3.75 3.60 SQ 3.55
0.50 BSC
EXPOSED PAD
17
8 16 9
TOP VIEW 0.80 0.75 0.70
0.50 0.40 0.30
BOTTOM VIEW
0.25 MIN
SEATING PLANE
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 59. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-12) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD9642BCPZ-170 AD9642BCPZ-210 AD9642BCPZ-250 AD9642BCPZRL7-170 AD9642BCPZRL7-210 AD9642BCPZRL7-250 AD9642-170EBZ AD9642-210EBZ AD9642-250EBZ
1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board with AD9642 and Software Evaluation Board with AD9642 and Software Evaluation Board with AD9642 and Software
08-16-2010-B
Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12
Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09995-0-7/11(0)
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