AD9737ABBCZ

11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters AD9737A/AD9739A FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION (DIV-BY-4) IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics 4-TO-1 DATA ASSEMBLER DCI LVDS DDR RECEIVER APPLICATIONS LVDS DDR RECEIVER I120 DB0[13:0] Direct RF synthesis at 2.5 GSPS update rate DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix-mode Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface Up to 1.25 GSPS operation Source synchronous DDR clocking Pin compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS DATA CONTROLLER Data Sheet Figure 1. GENERAL DESCRIPTION The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A. The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. Rev. D The AD9737A/AD9739A are manufactured on a 0.18 µm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mixmode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. Programmable differential current output with an 8.66 mA to 31.66 mA range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9737A/AD9739A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Register Map Description .................................................. 40 Applications ....................................................................................... 1 SPI Operation ............................................................................. 40 Functional Block Diagram .............................................................. 1 SPI Register Map ............................................................................ 42 General Description ......................................................................... 1 SPI Port Configuration and Software Reset ........................... 43 Product Highlights ........................................................................... 1 Power-Down LVDS Interface and TxDAC®............................ 43 Revision History ............................................................................... 3 Controller Clock Disable ........................................................... 43 Specifications..................................................................................... 4 Interrupt Request (IRQ) Enable/Status ................................... 44 DC Specifications ......................................................................... 4 TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 44 LVDS Digital Specifications ........................................................ 5 TxDAC Quad-Switch Mode of Operation .............................. 44 Serial Port Specifications ............................................................. 6 DCI Phase Alignment Status .................................................... 44 AC Specifications.......................................................................... 7 Data Receiver Controller Configuration ................................. 44 Absolute Maximum Ratings ............................................................ 8 Data Receiver Controller_Data Sample Delay Value ............ 45 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Data Receiver Controller_DCI Delay Value/Window and Phase Rotation ............................................................................ 45 Pin Configurations and Function Descriptions ........................... 9 Data Receiver Controller_Delay Line Status .......................... 45 Typical Performance Characteristics—AD9737A...................... 14 Data Receiver Controller Lock/Tracking Status..................... 45 Static Linearity ............................................................................ 14 CLK Input Common Mode ...................................................... 46 AC (Normal Mode) .................................................................... 15 Mu Controller Configuration and Status ................................ 46 AC (Mix-Mode) .......................................................................... 17 Part ID.......................................................................................... 47 One-Carrier DOCSIS Performance (Normal Mode) ............ 20 Theory of Operation ...................................................................... 48 Four-Carrier DOCSIS Performance (Normal Mode) ........... 21 LVDS Data Port Interface .......................................................... 49 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22 Mu Controller ............................................................................. 52 16-Carrier DOCSIS Performance (Normal Mode) ............... 23 Interrupt Requests ...................................................................... 54 32-Carrier DOCSIS Performance (Normal Mode) ............... 24 Analog Interface Considerations.................................................. 55 64- and 128-Carrier DOCSIS Performance (Normal Mode)25 Analog Modes of Operation ..................................................... 55 Typical Performance Characteristics—AD9739A...................... 26 Clock Input Considerations ...................................................... 56 Static Linearity ............................................................................ 26 Voltage Reference ....................................................................... 57 AC (Normal Mode) .................................................................... 28 Analog Outputs .......................................................................... 57 AC (Mix-Mode) .......................................................................... 31 Output Stage Configuration ..................................................... 59 One-Carrier DOCSIS Performance (Normal Mode) ............ 33 Nonideal Spectral Artifacts ....................................................... 60 Four-Carrier DOCSIS Performance (Normal Mode) ........... 34 Lab Evaluation of the AD9737A/AD9739A ........................... 61 Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35 Recommended Start-Up Sequence .......................................... 61 16-Carrier DOCSIS Performance (Normal Mode) ............... 36 Outline Dimensions ....................................................................... 63 32-Carrier DOCSIS Performance (Normal Mode) ............... 37 Ordering Guide .......................................................................... 63 64- and 128-Carrier DOCSIS Performance (Normal Mode)38 Terminology .................................................................................... 39 Serial Port Interface (SPI) Register............................................... 40 Rev. D | Page 2 of 64 Data Sheet AD9737A/AD9739A REVISION HISTORY 6/2017—Rev. C to Rev. D Changes to Table 24 ........................................................................46 Changes to Table 25 ........................................................................47 Changes to Theory of Operation Section ....................................48 Changes to Table 27 ........................................................................53 Changes to Clock Input Considerations Section ........................56 2/2012—Rev. B to Rev. C Changes to Figure 5........................................................................... 9 Changes to Table 7 ..........................................................................11 Changes to Ordering Guide ...........................................................63 2/2012—Rev. A to Rev. B Added AD9737A ................................................................ Universal Reorganized Layout ........................................................... Universal Moved Revision History Section ..................................................... 3 Deleted ±6% from Table Summary Statement; Changes to Table 1 ............................................................................................ 4 Deleted ±6% from Table Summary Statement, Table 2................ 5 Deleted ±6% from Table Summary Statement, Table 3................ 6 Changes to AC Specifications Section and Table 4 ....................... 7 Added Figure 5, Renumbered Sequentially ................................... 9 Added Figure 7 and Table 7, Renumbered Sequentially ............10 Deleted Figure 24 ............................................................................13 Added Typical Performance Characteristics—AD9737A Section and Figure 9 to Figure 77 .................................................14 Deleted Table 9 ................................................................................25 Added Static Linearity Section and Figure 78 to Figure 88 ............26 Added Figure 106 ............................................................................30 Changes to Figure 116, Figure 117, Figure 118, Figure 119, Figure 120, and Figure 121 .............................................................33 Changes to Figure 122, Figure 123, Figure 124, Figure 125, Figure 126, and Figure 127 .............................................................34 Changes to Figure 128, Figure 129, Figure 130, Figure 131, Figure 132, and Figure 133 .............................................................35 Changes to Figure 134, Figure 135, Figure 136, Figure 137, Figure 138, and Figure 139 .............................................................36 Changes to Figure 140, Figure 141, Figure 142, Figure 143, Figure 144, and Figure 145 .............................................................37 Changes to Figure 146, Figure 147, Figure 148, Figure 149, and Figure 150; Added Figure 151 ................................................ 38 Added Table 10 ................................................................................ 42 Added SPI Port Configuration and Software Reset Section, Power-Down LVDS Interface and TxDAC Section, Controller Clock Disable Section, and Table 11 to Table 13 ........................ 43 Added Interrupt Request (IRQ) Enable/Status Section, TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC Quad-Switch Mode of Operation Section, DCI Phase Alignment Status Section, Data Receiver Controller Configuration Section, and Table 14 to Table 18 ........................ 44 Added Data Receiver Controller_Data Sample Delay Value Section, Data Receiver Controller_DCI Delay Value/Window and Phase Rotation Section, Data Receiver Controller_Delay Line Status Section, Data Receiver Controller Lock/Tracking Status Section, and Table 19 to Table 22 ...................................... 45 Added CLK Input Common Mode Section, and Mu Controller Configuration and Status Section, and Table 23 and Table 24 ..................................................................................... 46 Added Part ID Section, and Table 25 ........................................... 47 Changes to LVDS Data Port Interface Section ............................ 49 Changes to Data Receiver Controller Initialization Description Section ........................................................................ 51 Changes to Mu Controller Section ............................................... 52 Added Figure 167 and Table 27, Changes to Mu Controller Initialization Description Section ................................................. 53 Changes to Analog Modes of Operation Section, Figure 171, and Figure 172 ................................................................................. 55 Updated Outline Dimensions........................................................ 63 Changes to Ordering Guide ........................................................... 63 7/2011—Rev. 0 to Rev. A Changed Maximum Update Rate (DACCLK Input) Parameter to DAC Clock Rate Parameter in Table 4....................................... 6 Added Adjusted DAC Update Rate Parameter and Endnote 1 in Table 4 ................................................................................................. 6 Updated Outline Dimensions........................................................ 43 1/2011—Revision 0: Initial Version Rev. D | Page 3 of 64 AD9737A/AD9739A Data Sheet SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current Output Compliance Range Common-Mode Output Resistance Differential Output Resistance Output Capacitance DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage Common-Mode Voltage Clock Rate TEMPERATURE DRIFT Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES VDDA VDDC DIGITAL SUPPLY VOLTAGES VDD33 VDD SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS IVDDA IVDDC IVDD33 IVDD Power Dissipation Sleep Mode, IVDDA Power-Down Mode (All Power-Down Bits Set in Register 0x01 and Register 0x02) IVDDA IVDDC IVDD33 IVDD SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS IVDDC IVDD33 IVDD Power Dissipation Min AD9737A Typ Max 11 Min ±0.5 ±0.5 8.66 −1.0 5.5 20.2 ±2.5 ±2.0 31.66 +1.0 8.66 −1.0 10 70 1 1.2 1.6 900 1.6 AD9739A Typ Max 14 5.5 20.2 LSB LSB 31.66 +1.0 10 70 1 2.0 1.2 2.5 1.6 60 20 1.6 900 Unit Bits 2.0 2.5 60 20 % mA V MΩ Ω pF V mV GHz ppm/°C ppm/°C 1.15 1.2 5 1.25 1.15 1.2 5 1.25 V kΩ 3.1 1.70 3.3 1.8 3.5 1.90 3.1 1.70 3.3 1.8 3.5 1.90 V V 3.10 1.70 3.3 1.8 3.5 1.90 3.10 1.70 3.3 1.8 3.5 1.90 V V 37 158 14.5 173 0.770 2.5 38 167 16 183 37 158 14.5 173 0.770 2.5 38 167 16 183 mA mA mA mA W mA Rev. D | Page 4 of 64 2.75 2.75 0.02 6 0.6 0.1 0.02 6 0.6 0.1 mA mA mA mA 223 14.5 215 0.960 223 14.5 215 0.960 mA mA mA mW Data Sheet AD9737A/AD9739A LVDS DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.31996 reduced range link, unless otherwise noted. Table 2. Parameter LVDS DATA INPUTS (DB0[13:0], DB1[13:0]) 1 Input Common-Mode Voltage Range, VCOM Logic High Differential Input Threshold, VIH_DTH Logic Low Differential Input Threshold, VIL_DTH Receiver Differential Input Impedance, RIN Input Capacitance LVDS Input Rate LVDS Minimum Data Valid Period (tMDE) (See Figure 159) LVDS CLOCK INPUT (DCI) 2 Input Common-Mode Voltage Range, VCOM Logic High Differential Input Threshold, VIH_DTH Logic Low Differential Input Threshold, VIL_DTH Receiver Differential Input Impedance, RIN Input Capacitance Maximum Clock Rate LVDS CLOCK OUTPUT (DCO) 3 Output Voltage High (DCO_P or DCO_N) Output Voltage Low (DCO_P or DCO_N) Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, Single-Ended, RO RO Single-Ended Mismatch Maximum Clock Rate Min Typ 825 175 −175 80 400 −400 Max Unit 1575 mV mV mV Ω pF MSPS ps 120 1.2 1250 344 825 175 −175 80 1575 400 −400 120 1.2 625 1375 1025 150 1150 80 625 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins. DCI_P and DCI_N pins. 3 DCO_P and DCO_N pins with 100 Ω differential termination. 1 2 Rev. D | Page 5 of 64 200 100 250 1250 120 10 mV mV mV Ω pF MHz mV mV mV mV Ω % MHz AD9737A/AD9739A Data Sheet SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3. Parameter WRITE OPERATION (See Figure 154) SCLK Clock Rate, fSCLK, 1/tSCLK SCLK Clock High, tHIGH SCLK Clock Low, tLOW SDIO to SCLK Setup Time, tDS SCLK to SDIO Hold Time, tDH CS to SCLK Setup Time, tS SCLK to CS Hold Time, tH Min Typ Max Unit 20 MHz ns ns ns ns ns ns 20 MHz ns ns ns ns ns ns ns 18 18 2 1 3 2 READ OPERATION (See Figure 155 and Figure 156) SCLK Clock Rate, fSCLK, 1/tSCLK SCLK Clock High, tHIGH SCLK Clock Low, tLOW SDIO to SCLK Setup Time, tDS SCLK to SDIO Hold Time, tDH CS to SCLK Setup Time, tS SCLK to SDIO (or SDO) Data Valid Time, tDV CS to SDIO (or SDO) Output Valid to High-Z, tEZ 18 18 2 1 3 15 2 INPUTS (SDI, SDIO, SCLK, CS) Voltage in High, VIH Voltage in Low, VIL Current in High, IIH Current in Low, IIL OUTPUT (SDIO) Voltage Out High, VOH Voltage Out Low, VOL Current Out High, IOH Current Out Low, IOL 2.0 3.3 0 −10 −10 0.8 +10 +10 2.4 0 3.5 0.4 4 4 Rev. D | Page 6 of 64 V V µA µA V V mA mA Data Sheet AD9737A/AD9739A AC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE DAC Clock Rate Adjusted DAC Update Rate 1 Output Settling Time to 0.1% SPURIOUS-FREE DYNAMIC RANGE (SFDR) fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), fOUT2 = fOUT1 + 1.25 MHz fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 850 MHz WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL fDAC = 2457.6 MSPS, fOUT = 350 MHz fDAC = 2457.6 MSPS, fOUT = 950 MHz fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix-Mode) fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix-Mode) 1 Min AD9737A Typ Max 1600 1600 2500 2500 Min AD9739A Typ Max 1600 1600 2500 2500 Unit 13 13 MSPS MSPS ns 70 65 58 55 70 65 58 55 dBc dBc dBc dBc 94 78 72 68 94 78 72 68 dBc dBc dBc dBc −162 −162 −161 −161 −167 −166 −164 −163 dBm/Hz dBm/Hz dBm/Hz dBm/Hz 80/81 75/75 69/71 66/67 80/80 78/79 74/74 69/72 dBc dBc dBc dBc Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor is 1. Thus, with fDAC = 2500 MSPS, fDAC, adjusted, = 2500 MSPS. Rev. D | Page 7 of 64 AD9737A/AD9739A Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VDDA to VSSA VDD33 to VSS VDD to VSS VDDC to VSSC VSSA to VSS VSSA to VSSC VSS to VSSC DACCLK_P, DACCLK_N to VSSC DCI, DCO to VSS LVDS Data Inputs to VSS IOUTP, IOUTN to VSSA I120, VREF to VSSA IRQ, CS, SCLK, SDO, SDIO, RESET to VSS Junction Temperature Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to VDDC + 0.18 V −0.3 V to VDD33 + 0.3 V −0.3 V to VDD33 + 0.3 V −1.0 V to VDDA + 0.3 V −0.3 V to VDDA + 0.3 V −0.3 V to VDD33 + 0.3 V 150°C −65°C to +150°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 160-Ball CSP_BGA 1 With no airflow movement. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 8 of 64 θJA 31.2 θJC 7.0 Unit °C/W1 Data Sheet AD9737A/AD9739A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 1 14 A A B B C C D D E E F F G G AD9737A/AD9739A H 2 3 4 5 6 7 8 9 10 11 12 13 14 AD9737A/AD9739A J J K K L L M M N N P P VDDC, 1.8V, CLOCK SUPPLY VSSA, ANALOG SUPPLY GROUND VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD 09616-002 VDDA, 3.3V, ANALOG SUPPLY VSSC, CLOCK SUPPLY GROUND Figure 4. Digital LVDS Clock Supply Pins (Top View) Figure 2. Analog Supply Pins (Top View) 1 2 3 4 5 6 09616-004 H 7 8 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 10 11 12 13 14 A B A B DACCLK_N C DACCLK_P D C E D F E G F H AD9737A/AD9739A H DCO_P/_N DCI_P/_N L DB1[0:10]P J J K DB1[0:10]N M K L DB0[0:10]P N DB0[0:10]N P 09616-036 G AD9737A M N DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA) P Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View) VDD, 1.8V, DIGITAL SUPPLY 2 3 4 5 6 7 8 9 10 11 12 13 14 A Figure 3. Digital Supply Pins (Top View) B DACCLK_N C DACCLK_P D E F G AD9739A H J DCO_P/_N K DCI_P/_N DB1[0:13]P L DB1[0:13]N M DB0[0:13]P N DB0[0:13]N P DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA) Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View) Rev. D | Page 9 of 64 09616-005 VDD33, 3.3V DIGITAL SUPPLY 1 09616-003 VSS DIGITAL SUPPLY GROUND 1 2 3 4 5 6 IOUTP Data Sheet IOUTN AD9737A/AD9739A 7 8 9 10 11 12 13 14 A B I120 C VREF D E F IRQ G AD9737A H RESET CS SDIO SCLK SDO J K L M 09616-006 N P Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View) Table 7. AD9737A Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, A6, A9, B6, B9, C6, C9, D6, D9, E11, E12, E13, E14, F1, F2, F3, F4, F11, F12 A14 A7, B7, C7, D7 A8, B8, C8, D8 B14 Mnemonic VDDC VSSC Description 1.8 V Clock Supply Input. Clock Supply Ground. VDDA VSSA VSSA Shield 3.3 V Analog Supply Input. Analog Supply Ground. Analog Supply Ground Shield. Tie to VSSA at the DAC. NC IOUTN IOUTP I120 Do not connect to this pin. DAC Negative Current Output Source. DAC Positive Current Output Source. Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current. Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. Factory Test Pin. Do not connect to this pin. Negative/Positive DAC Clock Input (DACCLK). Interrupt Request Open Drain Output. Active high. Pull up to VDD33 with a 10 kΩ resistor. Reset Input. Active high. Tie to VSS if unused. Serial Port Enable Input. Serial Port Data Input/Output. Serial Port Clock Input. Serial Port Data Output. 3.3 V Digital Supply Input. 1.8 V Digital Supply Input. Digital Supply Ground. Differential resistor of 200 Ω exists between J1 and J2. Do not connect to this pin. Differential resistor of 100 Ω exists between K1 and K2. Do not connect to this pin. Positive/Negative Data Clock Output (DCO). Positive/Negative Data Clock Input (DCI). C14 VREF D14 C3, D3 F13 NC DACCLK_N/DACCLK_P IRQ F14 G13 G14 H13 H14 J3, J4, J11, J12 G1, G2, G3, G4, G11, G12 H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 J1, J2 RESET CS SDIO SCLK SDO VDD33 VDD VSS NC K1, K2 NC J13, J14 K13, K14 DCO_P/DCO_N DCI_P/DCI_N Rev. D | Page 10 of 64 Data Sheet Pin No. L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12, M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 AD9737A/AD9739A Mnemonic NC, NC NC, NC NC, NC DB1[0]P/DB1[0]N DB1[1]P/DB1[1]N DB1[2]P/DB1[2]N DB1[3]P/DB1[3]N DB1[4]P/DB1[4]N DB1[5]P/DB1[5]N DB1[6]P/DB1[6]N DB1[7]P/DB1[7]N DB1[8]P/DB1[8]N DB1[9]P/DB1[9]N DB1[10]P/DB1[10]N NC, NC NC, NC NC, NC DB0[0]P/DB0[0]N DB0[1]P/DB0[1]N DB0[2]P/DB0[2]N DB0[3]P/DB0[3]N DB0[4]P/DB0[4]N DB0[5]P/DB0[5]N DB0[6]P/DB0[6]N DB0[7]P/DB0[7]N DB0[8]P/DB0[8]N DB0[9]P/DB0[9]N DB0[10]P/DB0[10]N Description Do not connect to this pin. Do not connect to this pin. Do not connect to this pin. Port 1 Positive/Negative Data Input Bit 0. Port 1 Positive/Negative Data Input Bit 1. Port 1 Positive/Negative Data Input Bit 2. Port 1 Positive/Negative Data Input Bit 3. Port 1 Positive/Negative Data Input Bit 4. Port 1 Positive/Negative Data Input Bit 5. Port 1 Positive/Negative Data Input Bit 6. Port 1 Positive/Negative Data Input Bit 7. Port 1 Positive/Negative Data Input Bit 8. Port 1 Positive/Negative Data Input Bit 9. Port 1 Positive/Negative Data Input Bit 10. Do not connect to this pin. Do not connect to this pin. Do not connect to this pin. Port 0 Positive/Negative Data Input Bit 0. Port 0 Positive/Negative Data Input Bit 1. Port 0 Positive/Negative Data Input Bit 2. Port 0 Positive/Negative Data Input Bit 3. Port 0 Positive/Negative Data Input Bit 4. Port 0 Positive/Negative Data Input Bit 5. Port 0 Positive/Negative Data Input Bit 6. Port 0 Positive/Negative Data Input Bit 7. Port 0 Positive/Negative Data Input Bit 8. Port 0 Positive/Negative Data Input Bit 9. Port 0 Positive/Negative Data Input Bit 10. Rev. D | Page 11 of 64 1 2 3 4 5 6 IOUTP Data Sheet IOUTN AD9737A/AD9739A 7 8 9 10 11 12 13 14 A B I120 C VREF D E F IRQ G AD9739A H RESET CS SDIO SCLK SDO J K L M 09616-037 N P Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View) Table 8. AD9739A Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, A6, A9, B6, B9, C6, C9, D6, D9, E11, E12, E13, E14, F1, F2, F3, F4, F11, F12 A14 A7, B7, C7, D7 A8, B8, C8, D8 B14 Mnemonic VDDC VSSC Description 1.8 V Clock Supply Input. Clock Supply Ground. VDDA VSSA VSSA Shield 3.3 V Analog Supply Input. Analog Supply Ground. Analog Supply Ground Shield. Tie to VSSA at the DAC. NC IOUTN IOUTP I120 C14 VREF D14 C3, D3 F13 NC DACCLK_N/DACCLK_P IRQ F14 G13 G14 H13 H14 J3, J4, J11, J12 G1, G2, G3, G4, G11, G12 H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 J1, J2 RESET CS SDIO SCLK SDO VDD33 VDD VSS NC K1, K2 NC J13, J14 K13, K14 DCO_P/DCO_N DCI_P/DCI_N Do not connect to this pin. DAC Negative Current Output Source. DAC Positive Current Output Source. Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current. Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. Factory Test Pin. Do not connect to this pin. Negative/Positive DAC Clock Input (DACCLK). Interrupt Request Open Drain Output. Active high. Pull up to VDD33 with a 10 kΩ resistor. Reset Input. Active high. Tie to VSS if unused. Serial Port Enable Input. Serial Port Data Input/Output. Serial Port Clock Input. Serial Port Data Output. 3.3 V Digital Supply Input. 1.8 V Digital Supply Input. Digital Supply Ground. Differential resistor of 200 Ω exists between J1 and J2. Do not connect to this pin. Differential resistor of 100 Ω exists between K1 and K2. Do not connect to this pin. Positive/Negative Data Clock Output (DCO). Positive/Negative Data Clock Input (DCI). Rev. D | Page 12 of 64 Data Sheet Pin No. L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12, M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 AD9737A/AD9739A Mnemonic DB1[0]P/DB1[0]N DB1[1]P/DB1[1]N DB1[2]P/DB1[2]N DB1[3]P/DB1[3]N DB1[4]P/DB1[4]N DB1[5]P/DB1[5]N DB1[6]P/DB1[6]N DB1[7]P/DB1[7]N DB1[8]P/DB1[8]N DB1[9]P/DB1[9]N DB1[10]P/DB1[10]N DB1[11]P/DB1[11]N DB1[12]P/DB1[12]N DB1[13]P/DB1[13]N DB0[0]P/DB0[0]N DB0[1]P/DB0[1]N DB0[2]P/DB0[2]N DB0[3]P/DB0[3]N DB0[4]P/DB0[4]N DB0[5]P/DB0[5]N DB0[6]P/DB0[6]N DB0[7]P/DB0[7]N DB0[8]P/DB0[8]N DB0[9]P/DB0[9]N DB0[10]P/DB0[10]N DB0[11]P/DB0[11]N DB0[12]P/DB0[12]N DB0[13]P/DB0[13]N Description Port 1 Positive/Negative Data Input Bit 0. Port 1 Positive/Negative Data Input Bit 1. Port 1 Positive/Negative Data Input Bit 2. Port 1 Positive/Negative Data Input Bit 3. Port 1 Positive/Negative Data Input Bit 4. Port 1 Positive/Negative Data Input Bit 5. Port 1 Positive/Negative Data Input Bit 6. Port 1 Positive/Negative Data Input Bit 7. Port 1 Positive/Negative Data Input Bit 8. Port 1 Positive/Negative Data Input Bit 9. Port 1 Positive/Negative Data Input Bit 10. Port 1 Positive/Negative Data Input Bit 11. Port 1 Positive/Negative Data Input Bit 12. Port 1 Positive/Negative Data Input Bit 13. Port 0 Positive/Negative Data Input Bit 0. Port 0 Positive/Negative Data Input Bit 1. Port 0 Positive/Negative Data Input Bit 2. Port 0 Positive/Negative Data Input Bit 3. Port 0 Positive/Negative Data Input Bit 4. Port 0 Positive/Negative Data Input Bit 5. Port 0 Positive/Negative Data Input Bit 6. Port 0 Positive/Negative Data Input Bit 7. Port 0 Positive/Negative Data Input Bit 8. Port 0 Positive/Negative Data Input Bit 9. Port 0 Positive/Negative Data Input Bit 10. Port 0 Positive/Negative Data Input Bit 11. Port 0 Positive/Negative Data Input Bit 12. Port 0 Positive/Negative Data Input Bit 13. Rev. D | Page 13 of 64 AD9737A/AD9739A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A STATIC LINEARITY IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 0.25 0.3 0.20 0.2 0.15 0.10 ERROR (LSB) ERROR (LSB) 0.1 0 –0.1 0.05 0 –0.05 –0.10 –0.2 –0.15 –0.3 0 256 512 768 1024 1280 1536 1792 2048 CODE –0.25 09616-109 –0.4 0 256 512 768 1024 1280 1536 1792 2048 1792 2048 1792 2048 CODE Figure 9. Typical INL, 20 mA at 25°C 09616-112 –0.20 Figure 12. Typical DNL, 10 mA at 25°C 0.4 0.6 0.5 0.3 0.4 0.3 0.2 ERROR (LSB) ERROR (LSB) 0.2 0.1 0 0.1 0 –0.1 –0.2 –0.1 –0.3 –0.4 –0.2 512 768 1024 1280 1536 1792 CODE 2048 –0.6 0 256 0.1 0 0.10 –0.1 ERROR (LSB) 0.15 0.05 0 –0.05 –0.4 –0.5 –0.6 –0.20 –0.7 –0.25 1024 1280 1536 CODE 1536 –0.2 –0.15 768 1280 –0.3 –0.10 1792 2048 09616-111 ERROR (LSB) 0.2 0.20 512 1024 Figure 13. Typical INL, 30 mA at 25°C 0.25 256 768 CODE Figure 10. Typical DNL, 20 mA at 25°C 0 512 –0.8 0 256 512 768 1024 1280 1536 CODE Figure 14. Typical DNL, 30 mA at 25°C Figure 11. Typical INL, 10 mA at 25°C Rev. D | Page 14 of 64 09616-114 256 09616-110 0 09616-113 –0.5 –0.3 Data Sheet AD9737A/AD9739A AC (NORMAL MODE) IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 120 1.2GSPS 100 1.6GSPS 10dB/DIV IIMD (dBc) 80 2.0GSPS 2.4GSPS 60 40 STOP 2.4GHz VBW 20kHz 09616-115 0 START 20MHz 0 200 400 600 800 1200 1000 1400 fOUT (MHz) Figure 15. Single Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS 09616-118 20 Figure 18. IMD vs. fOUT over fDAC –150 –152 –154 10dB/DIV NSD (dBm/Hz) –156 –158 1.2GSPS –160 –162 –164 2.4GSPS –166 –168 0 400 600 800 1000 1200 1200 fOUT (MHz) Figure 19. Single-Tone NSD over fOUT Figure 16. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS –150 90 –152 80 –154 1.2GSPS 70 2.4GSPS –156 50 1.6GSPS NSD (dBm/Hz) 60 2.0GSPS 40 –158 1.2GSPS –160 –162 30 –164 20 –166 10 –168 2.4GSPS –170 0 0 200 400 600 800 fOUT (MHz) 1000 1200 09616-117 SFDR (dBc) 200 09616-119 VBW 20kHz –170 09616-120 STOP 2.4GHz 09616-116 START 20MHz 0 200 400 600 800 fOUT (MHz) Figure 20. Eight-Tone NSD over fOUT Figure 17. SFDR vs. fOUT over fDAC Rev. D | Page 15 of 64 1000 AD9737A/AD9739A Data Sheet fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 90 100 85 95 –6dBFS 80 75 70 80 65 75 60 0dBFS 55 –6dBFS 85 –3dBFS IMD (dBc) 50 –3dBFS 70 65 50 45 40 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 09616-121 35 30 0 100 200 300 400 500 600 700 800 900 1000 09616-124 55 40 900 1000 09616-125 60 45 900 1000 09616-126 SFDR (dBc) 0dBFS 90 fOUT (MHz) Figure 21. SFDR vs. fOUT over Digital Full Scale Figure 24. IMD vs. fOUT over Digital Full Scale 90 90 85 –6dBFS 80 80 70 SFDR (dBc) SFDR (dBc) 30mA FS 75 –3dBFS 70 60 0dBFS 50 65 20mA FS 60 10mA FS 55 50 45 40 40 35 0 200 400 600 800 1000 fOUT (MHz) 30 09616-122 30 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 22. SFDR for Second Harmonic vs. fOUT over Digital Full Scale Figure 25. SFDR vs. fOUT over DAC IOUTFS 90 100 95 –6dBFS 80 90 20mA FS 85 30mA FS 80 60 IMD (dBc) –3dBFS 0dBFS 50 75 70 10mA FS 65 60 55 40 50 30 40 45 0 200 400 600 800 1000 fOUT (MHz) 09616-123 SFDR (dBc) 70 Figure 23. SFDR for Third Harmonic vs. fOUT over Digital Full Scale 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 26. IMD vs. fOUT over DAC IOUTFS Rev. D | Page 16 of 64 Data Sheet AD9737A/AD9739A AC (MIX-MODE) fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 90 –150 85 –152 80 –154 +85°C 75 –156 NSD (dBm/Hz) +25°C 65 60 –40°C 55 50 –158 +85°C –160 –162 –164 +25°C 45 –166 40 –168 35 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) –170 09616-127 30 0 200 100 300 400 500 600 700 800 900 09616-130 SFDR (dBc) 70 1000 fOUT (MHz) Figure 30. Eight-Tone NSD vs. fOUT over Temperature Figure 27. SFDR vs. fOUT over Temperature 100 –82.2dBc –81.6dBc 95 –81.7dBc –81.1dBc –80.5dBc –13.2dBm –79.7dBc –80.2dBc –80.8dBc –81.4dBc –81.5dBc –35 90 +85°C 85 –45 +25°C –55 –40°C 75 10dB/DIV IMD (dBc) 80 70 65 60 –65 –75 –85 –95 55 –105 50 –115 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) CENTER 350MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz VBW 3kHz –13.167dBm/3.84MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –80.51 –93.67 –81.11 –94.27 –81.67 –94.84 –81.61 –94.77 –82.19 –95.35 SPAN 54.68MHz SWEEP 1.509s ACP-IBW UPPER dBc dBm –79.73 –92.90 –80.21 –93.38 –80.85 –94.01 –81.41 –94.58 –81.46 –94.63 FILTER ON ON ON ON ON 09616-131 40 09616-128 45 Figure 31. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Figure 28. IMD vs. fOUT over Temperature –150 –50 –152 –55 –154 –60 ACLR (dBc) –158 +85°C –160 –162 +25°C –65 –70 FIRST ADJ CH –75 –164 –80 SECOND ADJ CH –166 –170 0 100 200 300 400 500 600 700 800 900 fOUT (MHz) 1000 –90 0 200 400 600 800 1000 1200 1400 fOUT (MHz) Figure 32. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS Figure 29. Single-Tone NSD vs. fOUT over Temperature Rev. D | Page 17 of 64 09616-226 FIFTH ADJ CH –85 –168 09616-129 NSD (dBm/Hz) –156 AD9737A/AD9739A Data Sheet fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 100 90 10dB/DIV IMD (dBc) 80 70 60 50 30 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 09616-132 START 20MHz #RES BW 20kHz STOP 2.4GHz SWEEP 7.174s (601pts) VBW 20kHz fOUT (MHz) 09616-135 40 Figure 36. IMD in Mix-Mode vs. fOUT at 2.4 GSPS Figure 33. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS –71.9dBc –72.3dBc –71.8dBc –69.9dBc –68.8dBc –19.5dBm –69.8dBc –71.1dBc –71.8dBc –72.2dBc –72.7dBc –35 –45 10dB/DIV 10dB/DIV –55 –65 –75 –85 –95 –105 –115 VBW 20kHz CENTER 2.108MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz VBW 3kHz –19.526dBm/3.84MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz LOWER dBm dBc –69.82 –88.34 –69.93 –89.46 –71.77 –91.29 –72.26 –91.79 –71.90 –91.42 SPAN 54.68MHz SWEEP 1.509s ACP-IBW UPPER dBm dBc –69.84 –89.36 –71.15 –90.67 –71.75 –91.28 –72.19 –91.71 –72.70 –92.22 FILTER ON ON ON ON ON 09616-136 STOP 2.4GHz SWEEP 7.174s (601pts) 09616-133 START 20MHz #RES BW 20kHz Figure 37. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Figure 34. Single-Tone Spectrum at fOUT = 1.31 GHz, fDAC = 2.4 GSPS 80 –50 75 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –55 70 65 –60 60 FIRST ADJ CH ACLR (dBc) 50 45 40 35 –65 –70 SECOND ADJ CH THIRD ADJ CH –75 30 –80 25 20 –85 fOUT (MHz) Figure 38. Single-Carrier WCDMA ACLR vs. fOUT, fDAC = 2457.6 MSPS Figure 35. SFDR in Mix-mode vs. fOUT at 2.4 GSPS Rev. D | Page 18 of 64 09616-137 3557.6 3307.6 3057.6 2807.6 2557.6 2307.6 2057.6 –90 1807.6 fOUT (MHz) 1557.6 10 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 1307.6 15 09616-134 SFDR (dBc) 55 Data Sheet AD9737A/AD9739A fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. –65.8dBc –65.8dBc –65.8dBc –65.7dBc –65.6dBc –29.2dBm –65.6dBc –65.8dBc –66.0dBc –66.1dBc –66.1dBc –58.0dBc –58.0dBc –58.0dBc –37.4dBm –37.1dBm –58.2dBc –58.3dBc –58.2dBc –57.9dBc –37.1dBm –36.9dBm –58.1dBc –58.3dBc –58.0dBc –45 –60 –55 –70 –80 –75 10dB/DIV 10dB/DIV –65 –85 –95 –105 –90 –100 –110 –120 –115 –130 –125 –140 OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz –26.161dBm/3.84MHz SPAN 54.68MHz SWEEP 1.509s CENTER 2.808MHz #RES BW 30kHz ACP-IBW LOWER INTEG BW dBc dBm 3.840MHz –65.65 –94.81 3.840MHz –65.70 –94.86 3.840MHz –65.81 –94.97 3.840MHz –65.84 –95.00 3.840MHz –65.84 –95.00 UPPER dBc dBm –65.56 –94.72 –65.82 –94.98 –65.98 –95.14 –66.06 –95.22 –66.14 –95.31 FILTER ON ON ON ON ON CARRIER POWER Figure 39. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) –65.6dBc OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz –50 –60 10dB/DIV –70 –80 –90 –100 –110 –120 –130 OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz –21.446dBm/15.36MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –65.42 –92.72 –64.93 –92.23 –65.12 –92.42 –65.24 –92.53 –65.61 –92.91 SPAN 69.68MHz SWEEP 1.922s ACP-IBW UPPER dBc dBm –64.93 –92.23 –64.26 –91.56 –65.21 –92.50 –65.74 –93.04 –66.13 –93.42 FILTER ON ON ON ON ON 09616-139 CARRIER POWER VBW 3kHz –31.097dBm/15.36MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –58.05 –95.11 –57.95 –95.02 –57.95 –95.01 –57.97 –95.04 –58.05 –95.11 SPAN 69.68MHz SWEEP 1.922s ACP-IBW UPPER dBc dBm –58.20 –95.26 –58.15 –95.21 –58.26 –95.32 –58.33 –95.39 –58.21 –95.27 FILTER ON ON ON ON ON Figure 41. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) –65.2dBc –64.9dBc –27.6dBm –27.3dBm –64.9dBc –65.2dBc –66.1dBc –65.4dBc –65.1dBc –27.6dBm –27.4dBm –64.3dBc –65.7dBc CENTER 2.108MHz #RES BW 30kHz VBW 3kHz 09616-140 CARRIER POWER VBW 3kHz 09616-138 CENTER 2.808MHz #RES BW 30kHz Figure 40. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Rev. D | Page 19 of 64 AD9737A/AD9739A Data Sheet ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –78.4dBc –78.6dBc –78.4dBc –79.3dBc –10.2dBm –79.9dBc –79.0dBc –78.7dBc –78.7dBc –30 1 –40 –40 –50 –50 –60 –60 10dB/DIV –70 –80 –70 –80 –90 –90 5∆1 –100 –100 –110 START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 3∆1 X 200.10MHz 199.50MHz 399.95MHz 599.45MHz 413.25MHz (∆) (∆) (∆) (∆) Y –10.238dBm –74.467dB –77.224dB –78.437dB –67.413dB CENTER 200MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) VBW 2kHz MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) –110 4∆1 FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz CARRIER POWER FUNCTION VALUE –10.238dBm (∆) –74.467dB (∆) –77.224dB (∆) –78.437dB (∆) –67.413dB OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz 09616-141 2∆1 Figure 42. Low Band Wideband ACLR –10.226dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBm dBc –58.34 –68.57 –79.27 –89.50 –78.44 –88.66 –78.59 –88.82 –78.41 –88.63 UPPER dBm dBc –57.47 –67.70 –79.87 –90.10 –78.96 –89.19 –78.69 –88.92 –78.68 –88.90 FILTER OFF OFF OFF OFF OFF 09616-144 10dB/DIV –30 Figure 45. Low Band Narrow-Band ACLR –76.0dBc –75.0dBc –74.5dBc –74.0dBc –12.1dBm –74.1dBc –74.7dBc –78.9dBc –75.3dBc –30 –30 –40 –50 –50 –60 –60 10dB/DIV –70 –80 –70 –80 –90 –90 –100 5∆1 –110 MKR 1 2 3 4 5 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) X 550.65MHz –487.35MHz (∆) 125.40MHz (∆) 253.65MHz (∆) 62.70MHz (∆) Y –11.538dBm –74.421dB –76.294dB –68.472dB –66.156dB CENTER 550MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) VBW 2kHz FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz CARRIER POWER FUNCTION VALUE –11.538dBm (∆) –74.399dB (∆) –74.344dB (∆) –68.472dB (∆) –66.197dB OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz ACP-IBW LOWER dBm dBc –59.37 –71.48 –74.02 –86.12 –74.53 –86.63 –75.00 –87.11 –75.97 –88.08 UPPER dBm dBc –60.92 –73.03 –74.14 –86.25 –74.68 –86.79 –74.91 –87.01 –75.34 –87.44 FILTER OFF OFF OFF OFF OFF Figure 46. Mid Band Narrow-Band ACLR Figure 43. Mid Band Wideband ACLR –71.9dBc –70.9dBc –70.0dBc –69.0dBc –13.6dBm –69.4dBc –70.5dBc –71.0dBc –71.7dBc –30 –30 1 –40 –40 –50 –60 –60 10dB/DIV –50 –70 –80 –70 –80 –90 –90 2∆1 –100 4∆1 –100 5∆1 3∆1 6∆1 –110 –110 START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 6 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 VBW 2kHz X 948.70MHz –393.30MHz –553.85MHz –612.75MHz –335.35MHz –57.95MHz (∆) (∆) (∆) (∆) (∆) Y –14.418dBm –60.856dB –66.000dB –68.751dB –63.533dB –66.162dB CENTER 950MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –14.446dBm (∆) –60.856dB (∆) –66.013dB (∆) –68.697dB (∆) –63.533dB (∆) –68.162dB CARRIER POWER 09616-143 10dB/DIV –12.104dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz 09616-145 START 50MHz #RES BW 20kHz 09616-142 –110 –100 4∆1 3∆1 2∆1 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –13.589dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBm dBc –57.84 –71.43 –69.02 –82.61 –70.01 –83.60 –70.89 –84.48 –71.94 –85.53 UPPER dBm dBc –61.30 –74.89 –69.39 –82.98 –70.50 –84.09 –71.02 –84.61 –71.75 –85.34 FILTER OFF OFF OFF OFF OFF Figure 47. High Band Narrow-Band ACLR Figure 44. High Band Wideband ACLR Rev. D | Page 20 of 64 09616-146 10dB/DIV 1 –40 Data Sheet AD9737A/AD9739A FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –30 –40 –50 –50 –60 –60 –70 10dB/DIV –70 –80 –90 –53.2dBc 0dBc 0.1dBc –73.3dBc –0.6dBc –72.9dBc –73.5dBc –73.7dBc –80 –90 –100 5∆1 –100 –110 2∆1 3∆1 START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 VBW 2kHz X 200.10MHz 221.35MHz 431.30MHz 651.70MHz 413.25MHz (∆) (∆) (∆) (∆) Y –18.419dBm –69.252dB –71.282dB –72.100dB –59.520dB –120 4∆1 STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –18.419dBm (∆) –69.277dB (∆) –71.485dB (∆) –72.343dB (∆) –59.518dB CENTER 218MHz #RES BW 30kHz CARRIER POWER 09616-147 –110 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz VBW 3kHz –17.892dBm/6MHz INTEG BW 750kHz 5.25kHz 6MHz 6MHz 6MHz SPAN 54MHz SWEEP 1.49s ACP-IBW LOWER dBm dBc –10.82 –28.71 –0.566 –18.46 –0.123 –17.77 –0.028 –17.86 –53.18 –71.07 UPPER dBc dBm –58.82 –76.71 –73.28 –91.17 –72.92 –90.81 –73.50 –91.39 –73.74 –91.63 FILTER OFF OFF OFF OFF OFF 09616-150 10dB/DIV –17.9dBc 1 –40 Figure 51. Low Band Narrow-Band ACLR (Worse Side) Figure 48. Low Band Wideband ACLR –40 –30 –19.5dBc –50 –60 –60 –70 10dB/DIV –70 –80 –90 –68.5dBc –68.3dBc –0.5dBc –0.2dBc 0dBc –54.2dBc –80 –90 –110 3∆1 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) X 549.70MHz –486.40MHz (∆) 126.35MHz (∆) 228.00MHz (∆) 63.65MHz (∆) Y –19.885dBm –70.252dB –69.535dB –67.793dB –58.085dB –120 CENTER 550MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –19.885dBm (∆) –70.252dB (∆) –69.581dB (∆) –67.793dB (∆) –58.085dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz 09616-148 MKR 1 2 3 4 5 VBW 2kHz 4∆1 Figure 49. Mid Band Wideband ACLR –17.892dBm/6MHz INTEG BW 750kHz 5.25kHz 6MHz 6MHz 6MHz SPAN 54MHz SWEEP 1.49s ACP-IBW LOWER dBm dBc –58.29 –77.82 –68.28 –87.81 –68.47 –88.00 –69.72 –89.25 –70.64 –90.17 UPPER dBc dBm –10.49 –30.02 –0.526 –20.06 –0.160 –19.69 –0.024 –19.56 –54.18 –73.72 FILTER OFF OFF OFF OFF OFF Figure 52. Mid Band Narrow-Band ACLR (Worse Side) –40 –40 1 –50 –60 –60 –70 –70 10dB/DIV –50 –80 –90 VBW 3kHz 09616-151 2∆1 START 50MHz #RES BW 20kHz 5∆1 –100 –21.5dBm –66.6dBc –65.4dBc –64.3dBc –0.4dBc –63.9dBc –0.2dBc 0.1dBc –53.1dBc –80 –90 –100 2∆1 4∆1 –110 6∆1 3∆1 –110 –120 –120 START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 6 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X 950.60MHz –415.15MHz (∆) –529.15MHz (∆) –610.85MHz (∆) –337.25MHz (∆) –59.85MHz (∆) Y –21.631dBm –62.206dB –65.730dB –67.064dB –56.405dB –65.729dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –21.676dBm (∆) –62.206dB (∆) –65.730dB (∆) –67.064dB (∆) –56.405dB (∆) –65.729dB CENTER 950MHz #RES BW 30kHz CARRIER POWER 09616-149 10dB/DIV –69.7dBc –100 5∆1 –100 –110 –70.6dBc Figure 50. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz VBW 3kHz –21.510dBm/6MHz INTEG BW 750kHz 5.25kHz 6MHz 6MHz 6MHz SPAN 54MHz SWEEP 1.49s ACP-IBW LOWER dBm dBc –59.52 –81.03 –63.90 –85.41 –64.29 –85.80 –65.41 –86.92 –66.57 –88.08 UPPER dBm dBc –11.04 –32.55 –0.437 –21.95 –0.172 –21.68 –0.098 –21.41 –53.11 –74.62 FILTER OFF OFF OFF OFF OFF Figure 53. High Band Narrow-Band ACLR (Worse Side) Rev. D | Page 21 of 64 09616-152 10dB/DIV –50 1 –40 AD9737A/AD9739A Data Sheet EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –69.1dBc –69.2dBc –50 –50 –60 –60 –70 –70 –80 –90 3∆1 –100 –0.6dBc –0.3dBc –0.2dBc –80 –90 –110 –120 VBW 2kHz FUNCTION MKR MODE TRC SCL X Y FUNCTION WIDTH 1 N 1 f 200.10MHz –22.253dBm BAND POWER 6MHz 2 ∆1 1 f (∆) 235.60MHz (∆) –66.457dB BAND POWER 6MHz 3 ∆1 1 f (∆) 431.25MHz (∆) –55.791dB BAND POWER 6MHz FUNCTION VALUE –22.253dBm (∆) –66.457dB (∆) –55.791dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz Figure 54. Low Band Wideband ACLR –40 VBW 3kHz CENTER 200MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) 09616-153 START 50MHz #RES BW 20kHz –23.288dBm/6MHz LOWER INTEG BW dBc dBm 750kHz –55.24 –78.53 5.25MHz –70.28 –93.56 6MHz –69.23 –92.52 6MHz –69.11 –92.40 UPPER dBc dBm –10.96 –34.25 –0.572 –23.86 –0.250 –23.54 –0.186 –23.47 –40 1 –23.7dBc –50 –66.8dBc 0.1dBc –60 –70 –70 10dB/DIV –60 –80 –90 0.3dBc –66.4dBc –66.8dBc –0.1dBc –80 –90 –100 2∆1 –110 FILTER OFF OFF OFF OFF Figure 57. Low Band Narrow-Band ACLR (Worse Side) –50 –100 SPAN 42MHz SWEEP 1.159s ACP-IBW 09616-156 –120 –110 3∆1 –120 –120 STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION MKR MODE TRC SCL X Y FUNCTION WIDTH 1 N 1 f 550.65MHz –23.586dBm BAND POWER 6MHz 2 ∆1 1 f (∆) 62.70MHz (∆) –54.209dB BAND POWER 6MHz 3 ∆1 1 f (∆) 167.20MHz (∆) –66.696dB BAND POWER 6MHz FUNCTION VALUE –23.585dBm (∆) –54.206dB (∆) –66.628dB CENTER 592MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz –23.676dBm/6MHz INTEG BW 750kHz 5.25kHz 6MHz 6MHz SPAN 42MHz SWEEP 1.159s VBW 3kHz ACP-IBW LOWER dBc dBm –10.79 –34.47 –0.089 –23.76 –0.289 –23.39 –0.145 –23.53 UPPER dBc dBm –56.23 –79.91 –66.75 –90.43 –66.45 –90.12 –66.78 –90.46 09616-157 VBW 2kHz 09616-154 START 50MHz #RES BW 20kHz FILTER OFF OFF OFF OFF Figure 58. Mid Band Narrow-Band ACLR (Worse Side) Figure 55. Mid Band Wideband ACLR –40 –40 –26.4dBm 1 –50 –60 –60 –70 –70 10dB/DIV –50 –80 –90 5∆1 –100 –110 –62.7dBc –62.2dBc –62.7dBc –0.4dBc 0.1dBc 0.1dBc 0.2dBc –80 –90 –100 2∆1 3∆1 –63.5dBc 4∆1 –110 –120 –120 MKR 1 2 3 4 5 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X 950.60MHz –448.40MHz (∆) –582.35MHz (∆) –80.75MHz (∆) –338.20MHz (∆) Y –26.330dBm –61.549dB –63.183dB –62.616dB –51.728dB FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –26.330dBm (∆) –61.574dB (∆) –63.268dB (∆) –62.616dB (∆) –51.728dB VBW 3kHz CENTER 950MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) CARRIER POWER 09616-155 START 50MHz #RES BW 20kHz Figure 56. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –26.388dBm/6MHz INTEG BW 750kHz 5.25kHz 6MHz 6MHz 6MHz SPAN 54MHz SWEEP 1.49s ACP-IBW LOWER dBc dBm –60.71 –87.10 –62.67 –89.06 –62.21 –88.60 –62.68 –89.07 –63.49 –89.88 UPPER dBc dBm –10.99 –37.38 –0.366 –26.75 –0.073 –26.31 –0.053 –26.33 –0.225 –26.16 FILTER OFF OFF OFF OFF OFF Figure 59. High Band Narrow-Band ACLR Rev. D | Page 22 of 64 09616-158 10dB/DIV –23.3dBc –100 2∆1 –110 10dB/DIV –70.3dBc –40 1 10dB/DIV 10dB/DIV –40 Data Sheet AD9737A/AD9739A 16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc 1 –60 –70 –70 –80 –80 10dB/DIV –60 –90 –100 4∆1 –0.3dBc –26.3dBm –65.2dBc –63.9dBc –64.1dBc –64.1dBc –110 3∆1 2∆1 –90 –100 –120 –120 –130 –130 START 50MHz #RES BW 20kHz MKR 1 2 3 4 –0.2dBc MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X Y 160.20MHz –26.390dBm 80.75MHz (∆) –64.811dB 232.75MHz (∆) –65.150dB 452.20MHz (∆) –51.688dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –26.391dBm (∆) –64.927dB (∆) –65.369dB (∆) –51.688dB CENTER 160MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 60. Low Band Wideband ACLR –25.250dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBc dBm –10.95 –37.20 –0.314 –26.56 –0.166 –26.42 –0.125 –26.38 –0.034 –26.28 UPPER dBc dBm –61.30 –87.55 –65.24 –91.49 –63.93 –90.18 –64.07 –90.32 –64.08 –90.33 FILTER OFF OFF OFF OFF OFF 09616-162 –110 –0.1dBc –50 09616-159 10dB/DIV –50 Figure 63. Low Band Narrow-Band ACLR 1 –50 0.3dBc –60 –0.2dBc –27.4dBm –63.9dBc –62.8dBc –63.1dBc –63.3dBc –65 –80 –90 10dB/DIV 10dB/DIV 0.2dBc –55 –70 –100 –110 0.3dBc –45 3∆1 2∆1 –75 –85 –95 4∆1 –105 –120 –115 –130 –125 MODE TRC SCL 1 f N 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 X 549.70MHz –486.40MHz (∆) 126.35MHz (∆) 254.60MHz (∆) Y –27.503dBm –63.639dB –62.748dB –63.408dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –27.503dBm (∆) –63.639dB (∆) –62.631dB (∆) –63.408dB CENTER 640MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 61. Mid Band Wideband ACLR ACP-IBW LOWER dBc dBm INTEG BW –11.65 –39.04 750.0kHz 5.250MHz –0.239 –27.63 6.000MHz –0.199 –27.19 6.000MHz –0.282 –27.10 6.000MHz –0.288 –27.10 UPPER dBc dBm –60.24 –87.62 –63.87 –91.26 –62.76 –90.15 –63.08 –90.46 –63.33 –90.72 FILTER OFF OFF OFF OFF OFF Figure 64. Mid Band Narrow-Band ACLR (Worse Side) –62.7dBc 1 –50 SPAN 54MHz SWEEP 1.49s VBW 3kHz –27.386dBm/6MHz 09616-163 MKR 1 2 3 4 VBW 2kHz 09616-160 START 50MHz #RES BW 20kHz –62.1dBc –61.3dBc 61.8dBc –28.1dBm ––0.4dBc –0.3dBc –0.3dBc –0.1dBc –45 –60 –55 –70 10dB/DIV –90 5∆1 –100 –110 4∆1 3∆1 –75 –85 –95 2∆1 –105 –120 –115 –130 –125 MKR 1 2 3 4 5 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X 899.30MHz –343.90MHz (∆) –504.45MHz (∆) –563.35MHz (∆) –285.95MHz (∆) Y –28.493dBm –60.066dB –61.070dB –61.014dB –49.417dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –28.493dBm (∆) –60.066dB (∆) –61.070dB (∆) –61.014dB (∆) –49.417dB CENTER 900MHz #RES BW 30kHz CARRIER POWER Figure 62. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –28.112dBm/6MHz ACP-IBW LOWER dBc dBm –58.27 –86.38 –61.84 –89.95 –61.30 –89.42 –62.11 –90.22 –62.66 –90.77 UPPER dBc dBm –11.14 –39.25 –0.446 –28.56 –0.271 –28.38 –0.318 –28.43 –0.147 –28.26 FILTER OFF OFF OFF OFF OFF Figure 65. High Band Narrow-Band ACLR Rev. D | Page 23 of 64 09616-164 START 50MHz #RES BW 20kHz 09616-161 10dB/DIV –65 –80 AD9737A/AD9739A Data Sheet 32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.1dBc 0.1dBc –60 –60 –70 –70 –80 –80 –90 –100 4∆1 –28.2dBm –65.6dBc –64.1dBc –64.2dBc –64.1dBc –90 –100 3∆1 2∆1 –120 –120 –130 Y X –29.852dBm 256.15MHz 94.05MHz (∆) –61.581dB 243.20MHz (∆) –61.313dB 356.25MHz (∆) –48.122dB FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –29.853dBm (∆) –61.410dB (∆) –61.639dB (∆) –48.122dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 66. Low Band Wideband ACLR 1 –70 –80 –80 10dB/DIV –60 –70 –90 –100 –120 –130 X 550MHz –462.65MHz (∆) 314.45MHz (∆) Y –29.461dbm –61.621dB –61.831dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –29.461dBm (∆) –61.621dB (∆) –61.831dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 67. Mid Band Wideband ACLR –60 –60 –70 –70 10dB/DIV –80 4∆1 –100 2∆1 3∆1 Y –32.396dBm –57.463dB –58.079dB –45.705dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –32.396dBm (∆) –57.463dB (∆) –58.079dB (∆) –45.705dB –29.512dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBc dBm –58.70 –88.21 –62.34 –91.85 –61.36 –90.87 –61.70 –91.21 –61.84 –91.36 –59.6dBc –59.9dBc –61.4dBc CENTER 800MHz #RES BW 30kHz CARRIER POWER 09616-167 X 799.55MHz –138.70MHz (∆) –601.35MHz (∆) –187.15MHz (∆) –0.1dBc UPPER dBc dBm –10.88 –40.39 –0.576 –30.09 –0.222 –29.73 –0.423 –29.93 –0.133 –29.63 FILTER OFF OFF OFF OFF OFF –32.2dBm ––0.2dBc 0.3dBc 0.3dBc 0.2dBc –110 –130 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) –0.4dBc –100 –120 MKR 1 2 3 4 –0.2dBc –90 –130 VBW 2kHz ––0.6dBc –80 –120 START 50MHz #RES BW 20kHz –29.5dBm –50 1 –110 –62.3dBc Figure 70. Mid Band Narrow-Band ACLR (Worse Side) –60.0dBc –50 –90 –61.4dBc CENTER 550MHz #RES BW 30kHz 09616-166 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) –61.7dBc –100 –130 MKR 1 2 3 FILTER OFF OFF OFF OFF OFF –90 –120 VBW 2kHz UPPER dBc dBm –60.27 –88.50 –65.64 –93.87 –64.12 –92.35 –64.24 –92.47 –64.12 –92.35 –110 3∆1 2∆1 START 50MHz #RES BW 20kHz LOWER INTEG BW dBc dBm 750.0kHz –10.80 –39.03 5.250MHz –0.336 –28.56 6.000MHz 0.060 –28.17 6.000MHz 0.081 –28.15 6.000MHz 0.080 –28.15 –50 –60 –110 ACP-IBW Figure 69. Low Band Narrow-Band ACLR –61.8dBc –50 SPAN 54MHz SWEEP 1.49s VBW 3kHz –28.229dBm/6MHz 09616-169 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 CENTER 256MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) Figure 68. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –32.154dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER UPPER dBm dBc dBm dBc –59.39 –91.54 –10.73 –42.89 –61.40 –93.55 –0.201 –32.35 –59.86 –92.01 0.300 –31.85 –59.61 –91.77 0.296 –31.86 –60.04 –92.20 0.230 –31.92 FILTER OFF OFF OFF OFF OFF Figure 71. High Band Narrow-Band ACLR Rev. D | Page 24 of 64 09616-170 MKR 1 2 3 4 VBW 2kHz 09616-165 START 50MHz #RES BW 20kHz 09616-168 –130 10dB/DIV –0.3dBc –110 –110 10dB/DIV 0.1dBc –50 1 10dB/DIV 10dB/DIV –50 Data Sheet AD9737A/AD9739A 64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.1dBc 1 –60 –70 –70 –80 –80 10dB/DIV –60 –90 2∆1 –110 –120 –130 –130 CENTER 448MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) VBW 2kHz X Y 448.05MHz –33.679dBm 165.30MHz (∆) –46.452dB 372.40MHz (∆) –56.577dB FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –33.680dBm (∆) –46.450dB (∆) –56.577dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –58.7dBc –59.0dBc –58.9dBc SPAN 54MHz SWEEP 1.49s VBW 3kHz –33.368dBm/6MHz ACP-IBW LOWER INTEG BW dBm dBc 750.0kHz –11.02 –44.39 5.250MHz –0.337 –33.74 6.000MHz 0.050 –33.32 6.000MHz 0.064 –33.30 6.000MHz 0.099 –33.27 UPPER dBm dBc –59.56 –92.93 –60.04 –93.41 –58.69 –92.06 –59.04 –92.40 –58.86 –92.23 FILTER OFF OFF OFF OFF OFF Figure 75. 64-Carrier Low Band Narrow-Band ACLR –58.0dBc –57.8dBc –58.4dBc –59.3dBc –33.8dBm ––0.4dBc 0.0dBc 0.0dBc 0.0dBc –50 –50 1 3 –60 –60 –70 –70 –80 10dB/DIV –90 –100 –80 –90 –100 –110 –110 2∆1 –120 –120 –130 MKR 1 2 3 MODE TRC SCL N 1 f ∆1 1 f (∆) N 1 f VBW 2kHz X 599.10MHz –292.60MHz (∆) 978.15MHz Y –34.413dBm –56.033dB –36.289dBm CENTER 600MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE 6MHz –34.413dBm (∆) –56.033dB 6MHz 6MHz –36.289dBm CARRIER POWER 09616-172 START 50MHz #RES BW 20kHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 73. High Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –33.849dBm/6MHz ACP-IBW LOWER dBm dBc –58.63 –92.48 –59.29 –93.14 –58.37 –92.22 –57.84 –91.69 –58.04 –91.89 UPPER dBm dBc –11.06 –44.91 –0.380 –34.23 –0.004 –33.85 –0.012 –33.86 0.043 –33.81 FILTER OFF OFF OFF OFF OFF 09616-175 –130 Figure 76. 64-Carrier High Band Narrow-Band ACLR 0.3dBc 0.3dBc 0.4dBc –0.2dBc –38.5dBm –54.3dBc –53.4dBc –53.3dBc –53.1dBc –50 –50 1 –60 –60 3 –70 –70 10dB/DIV –80 –90 –100 –110 –80 –90 –100 –110 2∆1 –120 –120 –130 –130 MKR 1 2 3 MODE TRC SCL f 1 N f (∆) 1 ∆1 f 1 N VBW 2kHz Y X –34.909dBm 69.95MHz 855.00MHz (∆) –53.920dB –38.646dBm 831.85MHz CENTER 832MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE –35.909dBm 6MHz 6MHz (∆) –53.920dB –38.646dBm 6MHz CARRIER POWER 09616-173 START 50MHz #RES BW 20kHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –38.456dBm/6MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBc dBm INTEG BW –11.07 –49.53 750.0kHz 5.250MHz –0.210 –38.67 0.353 –38.10 6.000MHz 0.253 –38.20 6.000MHz 0.292 –38.16 6.000MHz UPPER dBc dBm –59.28 –97.73 –54.33 –92.79 –53.36 –91.82 –53.35 –91.81 –53.07 –91.53 FILTER OFF OFF OFF OFF OFF Figure 77. 128-Carrier Narrow-Band ACLR Figure 74. 128-Carrier Low Band Wideband ACLR Rev. D | Page 25 of 64 09616-218 10dB/DIV –60.0dBc –90 Figure 72. Low Band Wideband ACLR 10dB/DIV –33.4dBm –100 –120 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) –0.4dBc –110 3∆1 MKR 1 2 3 0.0dBc 09616-174 –100 START 50MHz #RES BW 20kHz 0.1dBc –50 09616-171 10dB/DIV –50 AD9737A/AD9739A Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS—AD9739A STATIC LINEARITY 1.0 3.0 2.5 0.5 2.0 0 1.5 ERROR (LSB) ERROR (LSB) 1.0 0.5 0 –0.5 –0.5 –1.0 –1.5 –1.0 –2.0 –1.5 –2.0 –2.5 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –3.0 0 2048 1.5 0 1.0 –0.5 0.5 ERROR (LSB) 0.5 –1.0 –1.5 0 –0.5 –2.0 –1.0 –2.5 –1.5 –3.0 6144 8192 10,240 12,288 14,336 16,384 CODE –2.0 09616-210 ERROR (LSB) 2.0 4096 8192 10,240 12,288 14,336 16,384 Figure 81. Typical DNL, 20 mA at −40°C 1.0 2048 6144 CODE Figure 78. Typical INL, 20 mA at 25°C 0 4096 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 79. Typical DNL, 20 mA at 25°C 09616-209 0 09616-207 –3.0 09616-211 –2.5 Figure 82. Typical INL, 20 mA at 85°C 3.0 1.0 2.5 2.0 0.5 1.5 ERROR (LSB) 0 0.5 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE –2.0 Figure 80. Typical INL, 20 mA at −40°C 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 83. Typical DNL, 20 mA at 85°C Rev. D | Page 26 of 64 09616-212 –2.5 09616-208 ERROR (LSB) 1.0 Data Sheet AD9737A/AD9739A 2.0 1.0 1.5 0.5 1.0 0 ERROR (LSB) ERROR (LSB) 0.5 0 –0.5 –1.0 –0.5 –1.0 –1.5 –1.5 –2.0 –2.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 09616-213 –3.0 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 84. Typical INL, 10 mA at 25°C 09616-217 –2.5 –2.5 Figure 87. Typical DNL, 30 mA at 25°C 1.0 1.2 1.1 0.5 1.0 TOTAL 0.9 0 POWER (W) ERROR (LSB) 0.8 –0.5 –1.0 –1.5 0.7 0.6 0.5 DVDD18 0.4 CLKVDD 0.3 –2.0 0.2 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 09616-216 –3.0 Figure 85. Typical DNL, 10 mA at 25°C 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –3.0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE 09616-214 –2.5 0 0 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 fDAC (MHz) Figure 88. Power Consumption vs. fDAC at 25°C 3.0 ERROR (LSB) AVDD DVDD33 0.1 Figure 86. Typical INL, 30 mA at 25°C Rev. D | Page 27 of 64 09616-215 –2.5 AD9737A/AD9739A Data Sheet AC (NORMAL MODE) STOP 2.4GHz VBW 10kHz START 20MHz STOP 2.4GHz VBW 10kHz Figure 89. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS 09616-010 START 20MHz 09616-007 10dB/DIV 10dB/DIV IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. Figure 92. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS 80 100 1.2GSPS 95 1.6GSPS 75 1.2GSPS 70 85 65 80 2.0GSPS 75 60 IMD (dBc) SFDR (dBc) 90 2.4GSPS 55 2.0GSPS 50 1.6GSPS 70 65 2.4GSPS 60 55 45 50 40 45 40 35 35 30 0 fOUT (MHz) Figure 93. IMD vs. fOUT over fDAC –160 –152 –161 –154 –162 –156 –163 NSD (dBm/Hz) –150 –158 2.4GSPS –160 –162 –164 –165 2.4GSPS –166 –167 1.2GSPS –166 1.2GSPS –168 –168 –169 –170 –170 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 fOUT (MHz) 09616-009 NSD (dBm/Hz) Figure 90. SFDR vs. fOUT over fDAC –164 100 200 300 400 500 600 700 800 900 1000 1100 1200 09616-011 fOUT (MHz) Figure 91. Single-Tone NSD vs. fOUT 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 fOUT (MHz) Figure 94. Eight-Tone NSD vs. fOUT Rev. D | Page 28 of 64 09616-012 100 200 300 400 500 600 700 800 900 1000 1100 1200 09616-008 0 30 Data Sheet AD9737A/AD9739A fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 110 90 100 80 –6dBFS 90 –6dBFS –3dBFS 80 IMD (dBc) SFDR (dBc) 70 60 70 –3dBFS 0dBFS 60 0dBFS 50 50 40 40 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 0 100 200 300 400 500 600 700 800 900 1000 09616-016 100 09616-013 0 1000 09616-017 30 30 fOUT (MHz) Figure 95. SFDR vs. fOUT over Digital Full Scale Figure 98. IMD vs. fOUT over Digital Full Scale 90 90 –6dBFS –6dBFS 80 80 –3dBFS 70 SFDR (dB) 60 0dBFS –3dBFS 60 0dBFS 50 50 40 40 30 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 30 0 09616-014 0 200 300 400 500 600 700 800 900 fOUT (MHz) Figure 96. SFDR for Second Harmonic over fOUT vs. Digital Full Scale Figure 99. SFDR for Third Harmonic over fOUT vs. Digital Full Scale 90 110 100 80 20mA FS 90 30mA FS 10mA FS 70 IMD (dBc) 80 60 20mA FS 70 10mA FS 60 50 30mA FS 50 40 40 30 0 100 200 300 400 500 600 700 800 fOUT (MHz) 900 1000 30 0 09616-015 SFDR (dBc) 100 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 97. SFDR vs. fOUT over DAC IOUTFS Figure 100. IMD vs. fOUT over DAC IOUTFS Rev. D | Page 29 of 64 900 1000 09616-018 SFDR (dB) 70 AD9737A/AD9739A Data Sheet fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. 110 90 100 80 90 +85°C –40°C 60 70 +25°C 60 +25°C 50 +85°C 80 IMD (dBc) SFDR (dBc) 70 –40°C 50 40 40 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 0 200 300 400 500 600 700 800 900 1000 900 1000 fOUT (MHz) Figure 101. SFDR vs. fOUT over Temperature Figure 104. IMD vs. fOUT over Temperature –150 –150 –152 –152 –154 –154 –156 –156 –158 NSD (dBm/Hz) –40°C –160 –162 +85°C –164 –158 –160 –162 –40°C –164 –166 –166 +25°C –168 +85°C –168 +25°C –170 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 09616-020 –170 0 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 102. Single-Tone NSD vs. fOUT over Temperature Figure 105. Eight-Tone NSD vs. fOUT over Temperature –50 –55 –65 –70 FIRST ADJ CH –75 –80 SECOND ADJ CH FIFTH ADJ CH –85 FREQ VBW 300kHz –90 0 REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –14.54dBm/ 10 3.84MHz 15 20 25 SPAN 53.84MHz SWEEP 174.6ms (601pts) (MHz) 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) –79.90 –94.44 –80.60 –95.14 –80.90 –95.45 –80.62 –95.16 –80.76 –95.30 UPPER (dBc) (dBm) –79.03 –93.57 –79.36 –94.40 –80.73 –95.27 –80.97 –95.51 –80.95 –95.49 200 400 600 800 1000 1200 1400 fOUT (MHz) 09616-021 CENTER 350.27MHz #RES BW 30kHz Figure 103. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Figure 106. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS Rev. D | Page 30 of 64 09616-225 ACLR (dBc) –60 10dB/DIV NSD (dBm/Hz) 100 09616-022 100 09616-019 0 09616-023 30 30 Data Sheet AD9737A/AD9739A AC (MIX-MODE) STOP 2.4GHz SWEEP 28.7s (601pts) VBW 10kHz START 20MHz #RES BW 10kHz VBW 10kHz STOP 2.4GHz SWEEP 28.7s (601pts) 09616-030 START 20MHz #RES BW 10kHz 09616-026 10dB/DIV 10dB/DIV fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. Figure 110. Single-Tone Spectrum in Mix-Mode at fOUT = 1.31 GHz, fDAC = 2.4 GSPS Figure 107. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS 80 75 90 70 85 65 80 60 75 70 50 65 IMD (dBc) 45 40 35 60 55 30 50 25 45 20 40 15 fOUT (MHz) 35 09616-027 10 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 30 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 fOUT (MHz) Figure 108. SFDR in Mix-Mode vs. fOUT at 2.4 GSPS 09616-031 SFDR (dBc) 55 Figure 111. IMD in Mix-Mode vs. fOUT at 2.4 GSPS –40 –45 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –50 ACLR (dBc) 10dB/DIV –55 –60 –65 FIRST ADJ CH –70 SECOND ADJ CH –75 –80 FIFTH ADJ CH fOUT (MHz) REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –21.43dBm/ 10 3.84MHz 15 20 25 –90 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 (MHz) 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) –68.99 –90.43 –72.09 –93.52 –72.86 –94.30 –74.34 –95.77 –74.77 –96.20 UPPER (dBc) (dBm) –63.94 –90.37 –71.07 –92.50 –71.34 –92.77 –72.60 –94.03 –73.26 –94.70 09616-032 FREQ VBW 300kHz SPAN 53.84MHz SWEEP 174.6ms (601pts) Figure 109. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Figure 112. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS Rev. D | Page 31 of 64 09616-025 –85 CENTER 2.10706MHz #RES VW 30kHz AD9737A/AD9739A Data Sheet 10dB/DIV 10dB/DIV fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted. CENTER 2.81271GHz #RES BW 30kHz FREQ REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –24.4dBm/ 10 3.84MHz 15 20 25 SPAN 53.84MHz SWEEP 174.6ms (601pts) (MHz) 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) –64.90 –89.30 –66.27 –90.67 –68.44 –92.84 –70.20 –94.60 –70.85 –95.25 UPPER (dBc) (dBm) –63.82 –88.22 –65.70 –90.10 –66.55 –90.95 –68.95 –93.35 –70.45 –94.85 CARRIER POWER (MHz) 5 –27.98dBm/ 10 3.84MHz 15 20 25 30 (MHz) 3.84 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) 0.22 –25.31 –66.68 –92.21 –68.01 –93.53 –68.61 –94.14 –68.87 –94.40 –69.21 –94.74 UPPER (dBc) (dBm) 0.24 –25.29 0.14 –25.38 –66.82 –92.35 –67.83 –93.36 –67.64 –93.17 –68.50 –94.03 09616-034 CARRIER POWER (MHz) 5 –25.53dBm/ 10 3.84MHz 15 20 25 30 SPAN 63.84MHz SWEEP 207ms (601pts) REF RMS RESULTS OFFSET BW (MHz) 3.84 3.84 3.84 3.84 3.84 3.84 LOWER (dBc) (dBm) –0.42 –28.40 –64.32 –92.30 –66.03 –94.01 –66.27 –94.24 –66.82 –94.79 –67.16 –95.13 UPPER (dBc) (dBm) –0.10 –28.07 –0.08 –28.06 –65.37 –93.34 –66.06 –94.03 –63.36 –93.34 –66.54 –94.51 Figure 115. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) 10dB/DIV FREQ VBW 300kHz SPAN 63.84MHz SWEEP 207ms (601pts) REF RMS RESULTS OFFSET BW Figure 113. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) CENTER 2.09758GHz #RES BW 30kHz VBW 300kHz 09616-035 FREQ VBW 300kHz 09616-033 CENTER 2.807GHz #RES BW 30kHz Figure 114. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Rev. D | Page 32 of 64 Data Sheet AD9737A/AD9739A ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) fOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –80.7dBc –42 –45 –53 –55 –64 –65 –75 –86 –97 –10.2dBm –81.3Bc –80.7dBc –80.7dBc –80.8dBc –75 –85 –115 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) X 200.00MHz 199.60MHz 400.05MHz 597.65MHz 413.35MHz (∆) (∆) (∆) (∆) Y –11.476dBm –77.042dB –76.238dB –74.526dB –75.919dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –11.475dBm (∆) –77.042dB (∆) –76.238dB (∆) –74.526dB (∆) –75.919dB CENTER 200MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 116. Low Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –10.190dBm/6MHz ACP-IBW LOWER dBm dBc –59.38 –69.57 –81.23 –91.42 –80.71 –90.90 –80.72 –90.91 –80.73 –90.92 UPPER dBm dBc –60.16 –70.35 –81.26 –91.45 –80.72 –90.91 –80.76 –90.95 –80.78 –90.97 FILTER OFF OFF OFF OFF OFF 09616-179 MKR 1 2 3 4 5 VBW 2kHz 09616-176 START 50MHz #RES BW 20kHz Figure 119. Low Band Narrow-Band ACLR 1 –78.5dBc –31 –77.6dBc –76.3dBc –75.1Bc –10.4dBm –74.4Bc –75.6dBc –76.7dBc –77.7dBc –35 –42 –45 –53 –55 –64 10dB/DIV –75 –86 –97 5∆1 3∆1 –75 –85 –95 4∆1 2∆1 –65 6∆1 –105 –119 –115 MODE TRC SCL X f 1 N 549.60MHz f (∆) –485.35MHz (∆) 1 ∆1 f (∆) 127.40MHz (∆) 1 ∆1 f (∆) 254.70MHz (∆) 1 ∆1 f (∆) 1 ∆1 63.75MHz (∆) f (∆) 293.65MHz (∆) 1 ∆1 Y –10.231dBm –76.444dB –75.649dB –70.658dB –75.836dB –78.054dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –10.231dBm (∆) –76.425dB (∆) –75.626dB (∆) –70.658dB (∆) –75.824dB (∆) –78.118dB CENTER 550MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 117. Mid Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –10.368dBm/6MHz ACP-IBW LOWER dBm dBc –57.91 –68.28 –75.09 –85.46 –76.29 –86.65 –77.63 –88.00 –78.51 –88.88 UPPER dBm dBc –58.53 –68.90 –74.41 –84.78 –75.55 –85.92 –76.69 –87.06 –77.67 –88.03 FILTER OFF OFF OFF OFF OFF 09616-180 MKR 1 2 3 4 5 6 VBW 2kHz 09616-177 START 50MHz #RES BW 20kHz Figure 120. Mid Band Narrow-Band ACLR –76.7dBc –31 1 –75.9dBc –75.3dBc –72.2Bc –13.8dBm –72.1Bc –73.4dBc –75.0dBc –76.3dBc –30 –42 –40 –53 –50 10dB/DIV –64 –75 –86 –97 2∆1 –70 –80 –90 3∆1 5∆1 4∆1 –108 –60 –100 –119 –110 MKR 1 2 3 4 5 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X 979.00MHz –484.40MHz –118.65MHz –613.60MHz –365.65MHz (∆) (∆) (∆) (∆) Y –13.703dBm –65.548dB –66.990dB –69.044dB –72.789dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –13.658dBm (∆) –66.548dB (∆) –66.990dB (∆) –69.049dB (∆) –72.789dB CENTER 980MHz #RES BW 30kHz CARRIER POWER 09616-178 START 50MHz #RES BW 20kHz Figure 118. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –13.798dBm/6MHz ACP-IBW LOWER dBm dBc –57.81 –71.61 –72.17 –85.97 –75.28 –89.08 –75.91 –89.71 –76.71 –90.50 UPPER dBm dBc –61.44 –75.24 –72.10 –85.90 –73.42 –87.22 –75.03 –88.83 –76.31 –90.11 FILTER OFF OFF OFF OFF OFF Figure 121. High Band Narrow-Band ACLR Rev. D | Page 33 of 64 09616-181 10dB/DIV –81.2dBc –105 4∆1 3∆1 2∆1 –119 10dB/DIV –80.7dBc –95 5∆1 –108 –108 –80.7dBc –35 1 10dB/DIV 10dB/DIV –31 AD9737A/AD9739A Data Sheet FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. –53.4dBc 1 –50 –47 –60 –57 –70 –67 –80 –90 –110 5∆1 3∆1 2∆1 –17.6dBm –73.6dBc –75.4dBc –78.1dBc –79.1dBc –77 –87 –117 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) X 200MHz 216.60MHz 400MHz 621.30MHz 413.25MHz (∆) (∆) (∆) (∆) Y –18.593dBm –73.198dB –73.654dB –71.306dB –68.955dB FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –18.594dBm (∆) –73.170dB (∆) –73.621dB (∆) –71.289dB (∆) –68.946dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 122. Low Band Wideband ACLR ACP-IBW LOWER dBc dBm –11.15 –28.70 –0.454 –18.01 –0.065 –17.62 –0.091 –17.65 –53.44 –70.99 UPPER dBc dBm –58.78 –76.34 –73.56 –91.12 –75.42 –92.98 –78.08 –95.64 –79.06 –96.62 FILTER OFF OFF OFF OFF OFF Figure 125. Low Band Narrow-Band ACLR (Worse Side) –76.6dBc –38 –17.556dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz 09616-186 MKR 1 2 3 4 5 CENTER 210MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) VBW 2kHz 09616-183 START 50MHz #RES BW 20kHz –76.4dBc –75.0dBc –72.9dBc –19.5dBm –0.3dBc –0.1dBc –0.1dBc –50.2dBc –37 1 –48 –47 –58 –57 –68 –67 10dB/DIV –78 –88 –98 –77 –87 –97 2∆1 4∆1 3∆1 –107 6∆1 5∆1 –117 MKR 1 2 3 4 5 6 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) 1 f (∆) ∆1 1 f (∆) ∆1 VBW 2kHz X 667.80MHz –192.20MHz (∆) –98.15MHz (∆) –614.00MHz (∆) –567.45MHz (∆) –55.40MHz (∆) Y –18.760dBm –69.536dB –71.601dB –72.824dB –75.786dB –71.997dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –18.760dBm (∆) –69.536dB (∆) –71.601dB (∆) –72.833dB (∆) –75.320dB (∆) –71.997dB CENTER 650MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 123. Mid Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –19.503dBm/6MHz ACP-IBW LOWER dBc dBm –61.84 –81.35 –72.95 –92.45 –74.99 –94.49 –76.38 –95.89 –76.59 –96.10 UPPER dBc dBm –11.18 –30.68 –0.294 –19.80 –0.075 –19.58 –0.145 –19.65 –50.21 –69.71 FILTER OFF OFF OFF OFF OFF 09616-187 START 50MHz #RES BW 20kHz 09616-184 –118 Figure 126. Mid Band Narrow-Band ACLR (Worse Side) –74.2dBc –38 –73.0dBc –70.7dBc –68.7Bc –20.7dBm –0.5dBc –0.1dBc –0.5dBc –52.3dBc –37 1 –47 –58 –57 –68 –67 10dB/DIV –48 –78 –88 –98 –77 –87 –97 2∆1 –108 4∆1 –107 5∆1 3∆1 6∆1 –118 –117 MKR 1 2 3 4 5 6 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) 1 f (∆) ∆1 1 f (∆) ∆1 VBW 2kHz X 987.95MHz –490.50MHz (∆) –624.45MHz (∆) –738.45MHz (∆) –130.45MHz (∆) –374.60MHz (∆) Y –20.040dBm –60.683dB –69.390dB –71.954dB –66.954dB –68.889dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –21.029dBm (∆) –60.683dB (∆) –69.390dB (∆) –71.847dB (∆) –66.954dB (∆) –68.889dB CENTER 970MHz #RES BW 30kHz CARRIER POWER 09616-185 START 50MHz #RES BW 20kHz Figure 124. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –20.666dBm/6MHz ACP-IBW LOWER dBc dBm –60.65 –81.32 –68.68 –89.34 –70.67 –91.33 –72.96 –93.63 –74.22 –94.89 UPPER dBc dBm –10.77 –31.44 –0.522 –21.19 –0.140 –20.81 –0.511 –21.18 –52.31 –72.98 FILTER OFF OFF OFF OFF OFF Figure 127. High Band Narrow-Band ACLR Rev. D | Page 34 of 64 09616-188 10dB/DIV –0.5dBc –107 4∆1 –120 10dB/DIV –0.1dBc –97 –100 –108 –0.1dBc –37 10dB/DIV 10dB/DIV –40 Data Sheet AD9737A/AD9739A EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc 1 –50 –47 –60 –57 –70 –67 –80 –90 –100 –110 4∆1 3∆1 2∆1 –0.3dBc –21.9dBm –70.0Bc –69.9dBc –69.7dBc –70.1dBc –77 –87 –107 –120 –117 Y MODE TRC SCL X N 1 f 200MHz –22.043dBm ∆1 1 f (∆) 216.60MHz (∆) –71.545dB ∆1 1 f (∆) 400MHz (∆) –70.510dB ∆1 1 f (∆) 621.30MHz (∆) –68.566dB ∆1 1 f (∆) 413.25MHz (∆) –65.219dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE 6MHz –22.044dBm 6MHz (∆) –71.492dB 6MHz (∆) –70.555dB 6MHz (∆) –68.566dB 6MHz (∆) –65.237dB CENTER 222MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 128. Low Band Wideband ACLR ACP-IBW LOWER INTEG BW dBm dBc 750.0kHz –10.98 –32.85 5.250MHz –0.334 –22.21 6.000MHz 0.087 –21.79 6.000MHz –0.034 –21.91 6.000MHz 0.031 –21.84 UPPER dBm dBc –59.41 –81.28 –69.96 –91.83 –69.91 –91.78 –69.74 –91.62 –70.08 –91.95 FILTER OFF OFF OFF OFF OFF Figure 131. Low Band Narrow-Band ACLR (Worse Side) –71.6dBc –38 SPAN 54MHz SWEEP 1.49s VBW 3kHz –21.874dBm/6MHz 09616-192 MKR 1 2 3 4 5 VBW 2kHz 09616-189 START 50MHz #RES BW 20kHz 1 –71.5dBc –71.2dBc –71.3dBc –22.6dBm –0.5Bc –0.1dBc –0.2dBc –0.2dBc –37 –48 –47 –58 –57 –68 10dB/DIV –78 –88 –98 –67 –77 –87 –97 6∆1 –108 4∆1 –118 2∆1 3∆1 –107 5∆1 –117 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 X 667.80MHz –171.30MHz –98.15MHz –614.00MHz –567.45MHz –55.40MHz (∆) (∆) (∆) (∆) (∆) Y –23.977dBm –69.185dB –68.551dB –69.923dB –72.145dB –65.009dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE –23.977dBm 6MHz 6MHz (∆) –69.185dB 6MHz (∆) –68.551dB 6MHz (∆) –69.938dB 6MHz (∆) –72.083dB 6MHz (∆) –65.009dB CENTER 580MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 129. Mid Band Wideband ACLR –22.556dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBm dBc –60.21 –82.77 –71.35 –93.90 –71.20 –93.75 –71.51 –94.06 –71.60 –94.16 UPPER dBm dBc –11.25 –33.80 –0.459 –23.01 –0.137 –22.69 –0.181 –22.74 –0.221 –22.78 FILTER OFF OFF OFF OFF OFF 09616-193 MKR 1 2 3 4 5 6 VBW 2kHz 09616-190 START 50MHz #RES BW 20kHz Figure 132. Mid Band Narrow-Band ACLR (Worse Side) –67.7dBc –38 –67.7dBc –67.3dBc –67.4dBc –25.3dBm –0.5Bc –0.2dBc 0.0dBc 0.0dBc –37 1 –48 –47 –58 –57 10dB/DIV –68 –78 –88 –98 –67 –77 –87 –97 2∆1 –108 4∆1 6∆1 5∆1 3∆1 –107 –118 –117 MKR 1 2 3 4 5 6 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 VBW 2kHz X 990.80MHz –481.00MHz –633.95MHz –734.65MHz –128.55MHz –378.40MHz (∆) (∆) (∆) (∆) (∆) Y –25.435dBm –61.947dB –67.517dB –69.583dB –65.237dB –64.615dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE –25.435dBm 6MHz 6MHz (∆) –61.947dB 6MHz (∆) –67.532dB 6MHz (∆) –69.602dB 6MHz (∆) –65.237dB 6MHz (∆) –64.615dB CENTER 950MHz #RES BW 30kHz CARRIER POWER 09616-191 START 50MHz #RES BW 20kHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –25.344dBm/6MHz ACP-IBW LOWER dBm dBc –60.39 –85.73 –67.44 –92.78 –67.29 –92.63 –67.65 –93.00 –67.65 –93.00 UPPER dBm dBc –10.93 –36.27 –0.487 –25.83 –0.205 –25.55 –0.047 –25.39 –0.016 –25.33 FILTER OFF OFF OFF OFF OFF Figure 133. High Band Narrow-Band ACLR Figure 130. High Band Wideband ACLR Rev. D | Page 35 of 64 09616-194 10dB/DIV 0.1dBc –97 5∆1 10dB/DIV 0.0dBc –37 10dB/DIV 10dB/DIV –40 AD9737A/AD9739A Data Sheet 16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.0dBc –38 1 –64 –68 –74 –78 –88 –98 6∆1 –24.8dBm –70.4dBc –69.7dBc –69.7dBc –69.8dBc –84 –94 –124 X 289.70MHz 202.05MHz (∆) –183.65MHz (∆) 697.95MHz (∆) 18.70MHz (∆) 322.70MHz (∆) Y –25.335dBm –66.838dB –70.421dB –65.880dB –67.033dB –64.481dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –25.335dBm (∆) –66.838dB (∆) –70.312dB (∆) –65.928dB (∆) –66.973dB (∆) –64.451dB CENTER 290MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 134. Low Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –24.824dBm/6MHz ACP-IBW LOWER dBc dBm –10.83 –35.76 –0.545 –25.37 –0.099 –24.92 –0.155 –24.98 –0.041 –24.87 UPPER dBc dBm –59.93 –84.76 –70.37 –95.20 –69.75 –94.57 –69.75 –94.57 –69.79 –94.62 FILTER OFF OFF OFF OFF OFF 09616-198 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz 09616-195 START 50MHz #RES BW 20kHz MKR 1 2 3 4 5 6 –114 4∆1 2∆1 5∆1 3∆1 –118 Figure 137. Low Band Narrow-Band ACLR 0.4dBc –38 0.2dBc 0.0dBc –0.5dBc –26.8dBm –67.5dBc –66.8dBc –66.8Bc –66.8dBc –44 –48 1 –54 –58 –64 –68 –74 10dB/DIV –78 –88 –98 –84 –94 –104 –108 –114 4∆1 2∆1 3∆1 –124 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) X 690.60MHz –141.85MHz (∆) –623.50MHz (∆) 152.65MHz (∆) Y –28.317dBm –64.672dB –65.202dB –64.574dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –28.317dBm (∆) –64.672dB (∆) –65.207dB (∆) –64.574dB CENTER 690MHz #RES BW 30kHz CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 135. Mid Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –26.792dBm/6MHz ACP-IBW LOWER dBm dBc –11.17 –37.97 –0.460 –27.25 –0.049 –26.74 –0.196 –26.60 –0.366 –26.43 UPPER dBm dBc –58.12 –84.92 –67.47 –94.26 –66.83 –93.62 –66.80 –93.59 –66.79 –93.58 FILTER OFF OFF OFF OFF OFF 09616-199 MKR 1 2 3 4 VBW 2kHz 09616-196 START 50MHz #RES BW 20kHz Figure 138. Mid Band Narrow-Band ACLR (Worse Side) –64.9dBc –38 –64.8dBc –64.6dBc –65.0dBc –28.4dBm –0.5dBc –0.1dBc 0.0dBc 0.2dBc –44 –48 –54 1 –64 –68 –74 10dB/DIV –58 –78 –88 –84 –94 –104 –98 –108 3∆1 2∆1 4∆1 –114 6∆1 5∆1 –124 –118 MKR 1 2 3 4 5 6 MODE TRC SCL f 1 N f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 f (∆) 1 ∆1 VBW 2kHz X 989.85MHz –422.10MHz (∆) –922.75MHz (∆) –668.15MHz (∆) –137.10MHz (∆) –377.45MHz (∆) Y –27.971dBm –61.110dB –63.327dB –65.509dB –62.779dB –59.858dB CENTER 900MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –27.960dBm (∆) –61.110dB (∆) –63.332dB (∆) –65.483dB (∆) –62.779dB (∆) –59.828dB CARRIER POWER 09616-197 START 50MHz #RES BW 20kHz Figure 136. High Band Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –28.435dBm/6MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER dBc dBm –57.24 –85.68 –65.03 –93.46 –64.64 –93.08 –64.80 –93.24 –64.86 –93.29 UPPER dBc dBm –11.30 –39.73 –0.490 –28.92 –0.119 –28.55 –0.016 –28.45 0.153 –28.28 FILTER OFF OFF OFF OFF OFF Figure 139. High Band Narrow-Band ACLR Rev. D | Page 36 of 64 09616-200 10dB/DIV –0.5dBc –104 –108 10dB/DIV –0.1dBc –54 –58 10dB/DIV 10dB/DIV –48 –118 –0.2dBc –44 Data Sheet AD9737A/AD9739A 0.1dBc 1 –54 –72 –64 –82 –74 10dB/DIV –62 –92 –102 –114 –124 VBW 2kHz X 384.70MHz –283.40MHz (∆) 227.70MHz (∆) 325.55MHz (∆) Y –29.646dBm –64.175dB –59.429dB –62.750dB CENTER 386MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –29.645dBm (∆) –64.167dB (∆) –59.423dB (∆) –62.750dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 140. Low Band Wideband ACLR 1 –64.5dBc –64.4dBc SPAN 54MHz SWEEP 1.49s VBW 3kHz –29.920dBm/6MHz ACP-IBW LOWER dBc dBm INTEG BW –10.67 –40.59 750.0kHz 5.250MHz –0.431 –30.35 6.000MHz –0.070 –29.99 6.000MHz –0.011 –29.93 0.116 –29.80 6.000MHz UPPER dBc dBm –61.86 –91.78 –65.40 –95.32 –64.76 –94.68 –64.50 –94.42 –64.40 –94.32 FILTER OFF OFF OFF OFF OFF –63.2dBc –63.1dBc –63.3dBc –29.3dBm –0.5dBc –0.2dBc –0.2dBc –0.1dBc –44 –62 –54 –72 –64 –82 10dB/DIV –92 –102 4∆1 3∆1 2∆1 –74 –84 –94 –104 –122 –114 –132 –124 MKR 1 2 3 4 MODE TRC SCL 1 f N 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 VBW 2kHz X 685.5MHz –611.15MHz (∆) –243.50MHz (∆) 162.15MHz (∆) Y –30.335dBm –63.136dB –63.860dB –62.151dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –30.335dBm (∆) –63.112dB (∆) –63.860dB (∆) –62.151dB CENTER 200MHz #RES BW 30kHz CARRIER POWER 09616-202 START 50MHz #RES BW 20kHz OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 141. Mid Band Wideband ACLR INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –29.311dBm/6MHz ACP-IBW LOWER dBm dBc –58.76 –88.07 –63.30 –92.61 –63.05 –92.36 –63.21 –92.52 –64.46 –92.78 UPPER dBm dBc –10.78 –40.09 –0.487 –29.80 –0.175 –29.49 –0.151 –29.46 –0.061 –29.37 FILTER OFF OFF OFF OFF OFF 09616-205 10dB/DIV –64.8dBc Figure 143. Low Band Narrow-Band ACLR –63.5dBc –52 –112 –65.4dBc –94 –132 MODE TRC SCL 1 f N 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 –29.9dBm –104 4∆1 2∆1 MKR 1 2 3 4 –0.4dBc –84 –122 START 50MHz #RES BW 20kHz –0.1dBc 09616-204 3∆1 –112 0.0dBc –44 09616-201 10dB/DIV –52 Figure 144. Mid Band Narrow-Band ACLR (Worse Side) –52 –62.8dBc 1 –62 –63.2dBc –30.7dBm –0.4dBc –0.4dBc –0.5dBc –0.4dBc –64 10dB/DIV –82 –92 –102 4∆1 3∆1 2∆1 –74 –84 –94 –104 –122 –114 –132 –124 MKR 1 2 3 4 MODE TRC SCL 1 f N 1 f (∆) ∆1 1 f (∆) ∆1 1 f (∆) ∆1 VBW 2kHz X 985.10MHz –334.70MHz (∆) –909.45MHz (∆) –373.65MHz (∆) Y –31.516dBm –59.997dB –60.458dB –57.761dB STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz 6MHz FUNCTION VALUE –31.516dBm (∆) –59.997dB (∆) –60.535dB (∆) –57.763dB CENTER 800MHz #RES BW 30kHz Figure 142. High Band Wideband ACLR CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –30.746dBm/6MHz ACP-IBW LOWER dBc dBm –60.75 –91.49 –63.18 –93.92 –62.76 –93.50 –62.74 –93.48 –62.84 –93.59 UPPER dBc dBm –10.84 –41.59 –0.437 –31.18 –0.354 –31.10 –0.455 –31.20 –0.410 –31.16 FILTER OFF OFF OFF OFF OFF Figure 145. High Band Narrow-Band ACLR Rev. D | Page 37 of 64 09616-206 START 50MHz #RES BW 20kHz 09616-203 10dB/DIV –62.8dBc –54 –72 –112 –62.7dBc –44 AD9737A/AD9739A Data Sheet 64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE) IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted. 0.3dBc 1 –61 –72 –71 –82 –81 10dB/DIV –62 –92 –102 –131 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) X Y 478.75MHz –33.210dBm 372.10MHz (∆) –58.746dB 132.70MHz (∆) –55.165dB –62.3dBc –61.5dBc –61.5dBc –61.4dBc –101 –121 MKR 1 2 3 –32.4dBm –111 2∆1 –132 VBW 2kHz –0.3dBc –91 –122 START 50MHz #RES BW 20kHz 0.1dBc CENTER 478MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –33.209dBm (∆) –58.804dB (∆) –55.165dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 146. 64-Carrier Low Band Wideband ACLR SPAN 54MHz SWEEP 1.49s VBW 3kHz –32.409dBm/6MHz ACP-IBW LOWER INTEG BW dBc dBm 750.0kHz –10.83 –43.24 5.250MHz –0.267 –32.68 6.000MHz 0.139 –32.27 6.000MHz 0.201 –32.21 6.000MHz 0.308 –32.10 UPPER dBc dBm –60.80 –93.21 –62.25 –94.66 –61.47 –93.88 –61.54 –93.95 –61.40 –93.81 FILTER OFF OFF OFF OFF OFF 09616-222 3∆1 –112 0.2dBc –51 09616-219 10dB/DIV –52 Figure 149. 64-Carrier Low Band Narrow-Band ACLR –60.6dBc –60.6dBc –60.6dBc –61.1dBc –33.6dBm –0.3dBc –0.1dBc 0.2dBc 0.1dBc –51 –52 –72 –71 –82 –81 10dB/DIV –61 –92 –102 –111 2∆1 3∆1 –121 –132 –131 START 50MHz #RES BW 20kHz MKR 1 2 3 MODE TRC SCL N 1 f ∆1 1 f (∆) ∆1 1 f (∆) VBW 2kHz X 978.45MHz –901.85MHz (∆) –561.75MHz (∆) Y –35.872dBm –58.5816dB –59.214dB CENTER 600MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION WIDTH 6MHz 6MHz 6MHz FUNCTION VALUE –35.873dBm (∆) –58.625dB (∆) –59.286dB CARRIER POWER OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz Figure 147. 64-Carrier High Band Wideband ACLR ACP-IBW LOWER UPPER dBc dBm dBc dBm –60.02 –93.58 –11.48 –45.04 –61.11 –94.66 –0.284 –33.84 –60.57 –94.13 0.099 –33.46 –60.64 –94.20 0.221 –33.34 –60.58 –94.14 0.060 –33.50 FILTER OFF OFF OFF OFF OFF Figure 150. 64-Carrier High Band Narrow-Band ACLR 0.3dBc 0.3dBc 0.3dBc –0.3dBc –37.3dBm –57.7dBc –56.6dBc –56.5dBc –56.4dBc –50 –50 1 3 –60 –60 –70 –80 –80 10dB/DIV –70 –90 –100 –110 –90 –100 –110 2∆1 –120 –120 –130 –130 START 50MHz #RES BW 20kHz MKR 1 2 3 MODE TRC SCL N 1 f ∆1 1 f (∆) 1 1 f VBW 2kHz X Y 69.00MHz –35.495dBm 855.95MHz (∆) –55.328dB 831.85MHz –37.544dBm CENTER 832MHz #RES BW 30kHz STOP 1GHz SWEEP 24.1s (1001pts) FUNCTION BAND POWER BAND POWER BAND POWER FUNCTION FUNCTION WIDTH VALUE 6MHz –35.495dBm 6MHz (∆) –55.328dB 6MHz –37.545dBm CARRIER POWER 09616-221 10dB/DIV INTEG BW 750.0kHz 5.250MHz 6.000MHz 6.000MHz 6.000MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz –33.558dBm/6MHz 09616-223 –122 Figure 148. 128-Carrier Wideband ACLR OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz –37.33dBm/6MHz SPAN 54MHz SWEEP 1.49s VBW 3kHz ACP-IBW LOWER INTEG BW dBc dBm 750.0kHz –10.77 –48.10 5.250MHz –0.277 –37.61 6.000MHz 0.318 –37.01 6.000MHz 0.328 –37.00 6.000MHz 0.337 –37.00 UPPER dBc dBm –59.34 –96.67 –57.70 –95.03 –56.56 –93.89 –56.49 –93.82 –56.35 –93.69 FILTER OFF OFF OFF OFF OFF Figure 151. 128-Carrier Narrow-Band ACLR Rev. D | Page 38 of 64 09616-224 –112 –91 –101 09616-220 10dB/DIV 1 –62 Data Sheet AD9737A/AD9739A TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of 0 is called the offset error. For IOUTP, 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Noise Spectral Density (NSD) NSD is the converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal. Adjacent Channel Leakage Ratio (ACLR) The adjacent channel leakage (power) ratio is a ratio, in dBc, of the measured power within a channel relative to its adjacent channels. Modulation Error Ratio (MER) Modulated signals create a discrete set of output values referred to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. Intermodulation Distortion (IMD) IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values. Rev. D | Page 39 of 64 AD9737A/AD9739A Data Sheet SERIAL PORT INTERFACE (SPI) REGISTER SPI REGISTER MAP DESCRIPTION SPI OPERATION The AD9737A/AD9739A contain a set of programmable registers, described in Table 10, that are used to configure and monitor various internal parameters. Note the following points when programming the AD9737A/AD9739A SPI registers: The serial port of the AD9737A/AD9739A, shown in Figure 152, has a 3- or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. It provides a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The 3.3 V serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols.     Registers pertaining to similar functions are grouped together and assigned adjacent addresses. Bits that are undefined within a register should be assigned a 0 when writing to that register. Registers that are undefined should not be written to. A hardware or software reset is recommended on powerup to place SPI registers in a known state. A SPI initialization routine is required as part of the boot process. See Table 29 for an example procedure. SDO (PIN H14) SDIO (PIN G14) AD9737A/AD9739A SCLK (PIN H13) SPI PORT CS (PIN G13) Figure 152. AD9737A/AD9739A SPI Port Reset Issuing a hardware or software reset places the AD9737A/ AD9739A SPI registers in a known state. All SPI registers (excluding 0x00) are set to their default states, as described in Table 10, upon issuing a reset. After issuing a reset, the SPI initialization process needs only to write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application. Although the AD9737A/AD9739A do feature an internal power-on reset (POR), it is still recommended that a software or hardware reset be implemented shortly after power-up. The internal reset signal is derived from a logical OR operation from the internal POR signal, the RESET pin, and the software reset state. A software reset can be issued via the reset bit (Register 0x00, Bit 5) by toggling the bit high, then low. Note that, because the MSB/LSB format may still be unknown upon initial power-up (that is, internal POR is unsuccessful), it is also recommended that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the instruction cycle that issues a software reset. A hardware reset can be issued from a host or external supervisory IC by applying a high pulse with a minimum width of 40 ns to the RESET pin (that is, Pin F14). RESET should be tied to VSS if unused. Table 9. SPI Registers Pertaining to SPI Options Address (Hex) 0x00 09616-072  Bit 7 6 5 Description Enable 3-wire SPI Enable SPI LSB first Software reset The default 4-wire SPI interface consists of a clock (SCLK), serial port enable (CS), serial data input (SDIO), and serial data output (SDO). The inputs to SCLK, CS, and SDIO contain a Schmitt trigger with a nominal hysteresis of 0.4 V centered about VDD33/2. The maximum frequency for SCLK is 20 MHz. The SDO pin is active only during the transmission of data and remains three-stated at any other time. A 3-wire SPI interface can be enabled by setting the SDIO_DIR bit (Register 0x00, Bit 7). This causes the SDIO pin to become bidirectional such that output data appears on only the SDIO pin during a read operation. The SDO pin remains three-stated in a 3-wire SPI interface. Instruction Header Information MSB 17 R/W 16 A6 15 A5 14 A4 13 A3 12 A2 LSB 11 A1 10 A0 An 8-bit instruction header must accompany each read and write operation. The MSB is a R/W indicator bit with logic high indicating a read operation. The remaining seven bits specify the address bits to be accessed during the data transfer portion. The eight data bits immediately follow the instruction header for both read and write operations. For write operations, registers change immediately upon writing to the last bit of each transfer byte. CS can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the SPI. Rev. D | Page 40 of 64 Data Sheet AD9737A/AD9739A The AD9737A/AD9739A serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 153 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the LSB/MSB bit (Register 0x00, Bit 6). The default value of Bit 6 is 0, MSB first. When the LSB/MSB bit is set high, the serial port interprets both instruction and data bytes LSB first. INSTRUCTION CYCLE Figure 155 illustrates the timing for a 3-wire read operation to the SPI port. After CS goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. DATA TRANSFER CYCLE SCLK N2 A4 A3 A2 A1 INSTRUCTION CYCLE CS D1N D0N A0 D71 D61 DATA TRANSFER CYCLE Figure 156 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, whereas the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times. SCLK A0 A1 A2 A3 A4 N2 D6N D7N N1 R/W D01 D11 09616-073 SDATA Figure 153. SPI Timing, MSB First (Upper) and LSB First (Lower) tS 1/fSCLK tH CS tLOW tHI SCLK tDS tDH SDIO R/W N1 N0 A0 D6 D1 D7 D0 09616-074 R/W N1 Figure 154. SPI Write Operation Timing tS 1/fSCLK CS tLOW tHI SCLK tDV tDS tEZ tDH SDIO R/W N1 A2 A1 A0 D7 D6 D1 D0 09616-075 SDATA Figure 155. SPI 3-Wire Read Operation Timing tS 1/fSCLK CS tLOW tHI SCLK tDS SDIO tEZ tDH R/W N1 A2 A1 A0 tEZ tDV D7 SDO D6 D1 Figure 156. SPI 4-Wire Read Operation Timing Rev. D | Page 41 of 64 D0 09616-076 CS Figure 154 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable (CS) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles. AD9737A/AD9739A Data Sheet SPI REGISTER MAP Table 10. Full Register Map (N/A = Not Applicable) Name Mode PowerDown CNT_CLK_ DIS IRQ_EN IRQ_REQ Address 0x00 0x01 Bit 7 SDIO_DIR N/A Bit 6 LSB/MSB N/A Bit 4 N/A LVDS_ RCVR_PD N/A Bit 3 N/A N/A Bit 2 N/A N/A N/A Bit 5 Reset LVDS_ DRVR_PD N/A Bit 0 N/A DAC_BIAS_ PD MU_CNT_ CLK RCV_LCK_EN RCV_LCK_ IRQ N/A FSC[0] FSC[8] DAC_DEC[0] N/A N/A N/A DCI_PST_ PH0 N/A N/A N/A RCVR_CNT_ ENA Default 0x00 0x00 N/A FSC[2] N/A N/A N/A N/A N/A DCI_PRE_ PH0 N/A N/A N/A RCVR_FLG_ RST Bit 1 N/A CLK_RCVR_ PD REC_CNT_ CLK RCV_LST_EN RCV_LST_ IRQ N/A FSC[1] FSC[9] DAC_DEC[1] N/A N/A N/A DCI_PST_ PH2 N/A N/A N/A RCVR_ LOOP_ON 0x02 N/A CLKGEN_PD N/A 0x03 0x04 N/A N/A N/A N/A N/A N/A N/A N/A MU_LST_EN MU_LST_IRQ MU_LCK_EN MU_LCK_IRQ RSVD FSC_1 FSC_2 DEC_CNT RSVD LVDS_CNT DIG_STAT LVDS_STAT1 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C N/A FSC[6] N/A N/A N/A N/A N/A N/A N/A FSC[5] N/A N/A N/A N/A N/A DCI_PHS3 N/A FSC[4] N/A N/A N/A N/A N/A DCI_PHS1 0x0D 0x0E 0x0F 0x10 N/A FSC[7] Sleep N/A N/A N/A N/A SUP/HLD_ Edge1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A FSC[3] N/A N/A N/A N/A N/A DCI_PRE_ PH2 N/A N/A N/A N/A LVDS_STAT2 RSVD RSVD LVDS_ REC_CNT1 LVDS_ REC_CNT2 LVDS_ REC_CNT3 LVDS_ REC_CNT4 LVDS_ REC_CNT5 LVDS_ REC_CNT6 LVDS_ REC_CNT7 LVDS_ REC_CNT8 LVDS_ REC_CNT9 LVDS_ REC_STAT1 LVDS_ REC_STAT2 LVDS_ REC_STAT3 LVDS_ REC_STAT4 LVDS_ REC_STAT5 LVDS_ REC_STAT6 LVDS_ REC_STAT7 LVDS_ REC_STAT8 LVDS_ REC_STAT9 CROSS_ CNT1 0x11 SMP_DEL[1] SMP_DEL[0] N/A N/A N/A N/A N/A N/A 0xDD 0x12 SMP_DEL[9] SMP_DEL[8] SMP_DEL[7] SMP_DEL[6] SMP_DEL[5] SMP_DEL[4] SMP_DEL[3] SMP_DEL[2] 0x29 0x13 DCI_DEL[3] DCI_DEL[2] DCI_DEL[1] DCI_DEL[0] FINE_DEL_ SKW[3] FINE_DEL_ SKW[2] FINE_DEL_ SKW[1] FINE_DEL_ SKW[0] 0x71 0x14 N/A N/A DCI_DEL[9] DCI_DEL[8] DCI_DEL[7] DCI_DEL[6] DCI_DEL[5] DCI_DEL[4] 0x0A 0x15 N/A N/A N/A N/A N/A N/A N/A N/A 0x42 0x16 N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x17 N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x18 N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x19 SMP_DEL[1] SMP_DEL[0] N/A N/A N/A N/A N/A N/A 0xC7 0x1A SMP_DEL[9] SMP_DEL[8] SMP_DEL[7] SMP_DEL[6] SMP_DEL[5] SMP_DEL[4] SMP_DEL[3] SMP_DEL[2] 0x29 0x1B DCI_DEL[1] DCI_DEL[0] N/A N/A N/A N/A N/A N/A 0xC0 0x1C DCI_DEL[9] DCI_DEL[8] DCI_DEL[7] DCI_DEL[6] DCI_DEL[5] DCI_DEL[4] DCI_DEL[3] DCI_DEL[2] 0x29 0x1D N/A N/A N/A N/A N/A N/A N/A N/A 0x86 0x1E N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x1F N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x20 N/A N/A N/A N/A N/A N/A N/A N/A 0x00 0x21 N/A N/A N/A N/A RCVR_TRK_ ON RCVR_FE_ ON RCVR_LST RCVR_LCK 0x00 0x22 N/A N/A N/A DIR_P CLKP_ OFFSET[3] CLKP_ OFFSET[2] CLKP_ OFFSET[1] CLKP_ OFFSET[0] 0x00 Rev. D | Page 42 of 64 0x03 0x00 0x00 N/A 0x00 0x02 0x00 N/A 0x00 RNDM RNDM RNDM/0 N/A N/A 0x42 Data Sheet AD9737A/AD9739A Name CROSS_ CNT2 PHS_DET Address 0x23 Bit 7 N/A Bit 6 N/A Bit 5 N/A Bit 4 DIR_N Bit 3 CLKN_ OFFSET[3] Bit 2 CLKN_ OFFSET[2] Bit 1 CLKN_ OFFSET[1] Bit 0 CLKN_ OFFSET[0] Default 0x00 0x24 N/A N/A CMP_BST N/A N/A N/A N/A 0x00 MU_DUTY 0x25 POS/NEG ADJ[5] N/A N/A N/A N/A 0x00 MU_CNT1 MU_CNT2 0x26 0x27 MU_ DUTYAUTO_ EN N/A MUDEL[0] PHS_DET AUTO_EN ADJ[4] Read SET_PHS[3] Gain[1] SET_PHS[2] Gain[0] SET_PHS[1] Enable SET_PHS[0] 0x42 0x40 0x28 0x29 0x2A 0x2B 0x2C 0x32 0x33 0x34 0x35 MUDEL[8] SEARCH_TOL N/A N/A N/A N/A N/A N/A ID[7] Mode[1] SRCH_ MODE[0] MUDEL[6] CONTRST N/A N/A N/A N/A N/A N/A ID[5] Mode[0] SET_PHS[4] MU_CNT3 MU_CNT4 MU_STAT1 RSVD RSVD ANA_CNT1 ANA_CNT2 RSVD PART_ID Slope SRCH_ MODE[1] MUDEL[7] Retry N/A N/A N/A N/A N/A N/A ID[6] MUDEL[5] Guard[4] N/A N/A N/A N/A N/A N/A ID[4] MUDEL[4] Guard[3] N/A N/A N/A N/A N/A N/A ID[3] MUDEL[3] Guard[2] N/A N/A N/A N/A N/A N/A ID[2] MUDEL[2] Guard[1] MU_LOST N/A N/A N/A N/A N/A ID[1] MUDEL[1] Guard[0] MU_LKD N/A N/A N/A N/A N/A ID[0] 0x00 0x0B 0x00 N/A N/A 0xCA 0x03 N/A 0x40 SPI PORT CONFIGURATION AND SOFTWARE RESET Table 11. SPI Port Configuration and Software Reset Register (Mode) Address (Hex) 0x00 Bit Name SDIO_DIR LSB/MSB Reset Bits 7 6 5 R/W R/W R/W R/W Default Setting 0x0 0x0 0x0 Description 0 = 4-wire SPI, 1 = 3-wire SPI. 0 = MSB first, 1 = LSB first. Software reset is recommended before modification of other SPI registers from the default setting. 0 = inactive state; allows the user to modify registers from the default setting. 1 = causes all registers (except 0x00) to be set to the default setting. POWER-DOWN LVDS INTERFACE AND TxDAC® Table 12. Power-Down LVDS Interface and TxDAC Register (Power-Down) Address (Hex) 0x01 Bit Name LVDS_DRVR_PD LVDS_RCVR_PD CLK_RCVR_PD DAC_BIAS_PD Bits 5 4 1 0 R/W R/W R/W R/W R/W Default Setting 0x0 0x0 0x0 0x0 Description Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable. CONTROLLER CLOCK DISABLE Table 13. Controller Clock Disable Register (CNT_CLK_DIS) Address (Hex) 0x02 Bit Name CLKGEN_PD REC_CNT_CLK Bits 3 1 R/W R/W R/W Default Setting 0x0 0x1 MU_CNT_CLK 0 R/W 0x1 Description Internal CLK distribution enable: 0 = enable, 1 = disable. LVDS receiver and Mu controller clock disable. 0 = disable, 1 = enable. Rev. D | Page 43 of 64 AD9737A/AD9739A Data Sheet INTERRUPT REQUEST (IRQ) ENABLE/STATUS Table 14. Interrupt Request (IRQ) Enable (IRQ_EN)/Status (IRQ_REQ) Register Address (Hex) 0x03 0x04 Bit Name MU_LST_EN MU_LCK_EN RCV_LST_EN RCV_LCK_EN MU_LST_IRQ Bits 3 2 1 0 3 R/W W W W W R Default Setting 0x0 0x0 0x0 0x0 0x0 MU_LCK_IRQ RCV_LST_IRQ RCV_LCK_IRQ 2 1 0 R R R 0x0 0x0 0x0 Description This register enables the Mu and LVDS Rx controllers to update their corresponding IRQ status bits in Register 0x04, which defines whether the controller is locked (LCK) or unlocked (LST). 0 = disable (resets the status bit), 1 = enable. This register indicates the status of the controllers. For LCK_IRQ bits: 0 = lock lost, 1 = locked. For LST_IRQ bits: 0 = lock not lost, 1 = unlocked. Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing 0, followed by another write of 1 to enable. TxDAC FULL-SCALE CURRENT SETTING (IOUTFS) AND SLEEP Table 15. TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Register (FSC_1 and FSC_2) Address (Hex) 0x06 0x07 Bit Name FSC[7:0] FSC[9:8] Sleep Bits [7:0] [1:0] 7 R/W R/W R/W R/W Default Setting 0x00 0x02 Description Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA). IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023. 0 = enable DAC output, 1 = disable DAC output (sleep). TxDAC QUAD-SWITCH MODE OF OPERATION Table 16. TxDAC Quad-Switch Mode of Operation Register (DEC_CNT) Address (Hex) 0x08 Bit Name DAC_DEC Bits [1:0] R/W R/W Default Setting 0x00 Description 0x00 = normal baseband mode. 0x02 = mix-mode. DCI PHASE ALIGNMENT STATUS Table 17. DCI Phase Alignment Status Register (LVDS_STAT1) Address (Hex) 0x0C Bit Name DCI_PRE_PH0 Bits 2 R/W R Default Setting 0x0 DCI_PST_PH0 0 R 0x0 Description 0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling edge. 0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling edge. DATA RECEIVER CONTROLLER CONFIGURATION Table 18. Data Receiver Controller Configuration Register (LVDS_REC_CNT1) Address (Hex) 0x10 Bit Name RCVR_FLG_RST RCVR_LOOP_ON Bits 2 1 R/W W R/W Default Setting 0x0 0x1 RCVR_CNT_ENA 0 R/W 0x0 Description Data receiver controller flag reset. Write 1 followed by 0 to reset flags. 0 = disable, 1 = enable. When this bit is enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine. Data receiver controller enable. 0 = disable, 1 = enable. Rev. D | Page 44 of 64 Data Sheet AD9737A/AD9739A DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE Table 19. Data Receiver Controller_Data Sample Delay Value Register (LVDS_REC_CNT2 and LVDS_REC_CNT3) Address (Hex) 0x11 Bit Name SMP_DEL[1:0] Bits [7:6] R/W R/W Default Setting 0x11 0x12 SMP_DEL[9:2] [7:0] R/W 0x25 Description Controller enabled: the 10-bit value (with a maximum of 384) represents the start value for the delay line used by the state machine to sample data. Leave at the default setting of 167, which is near the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. DATA RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION Table 20. Data Receiver Controller_DCI Delay Value (LVDS_REC_CNT4)/Window and Phase Rotation Register (LVDS_REC_CNT5) Address (Hex) 0x13 Bit Name DCI_DEL[3:0] Bits [7:4] R/W R/W Default Setting 0x0111 [3:0] R/W 0x0001 0x14 FINE_DEL_ SKW[3:0] DCI_DEL[9:4] [5:0] R/W 0x001010 Description Refer to the DCI_DEL description in Register 0x14. A 4-bit value sets the difference (that is, window) for the DCI PRE and POST sampling clocks. Leave at the default value of 1 for a narrow window. Controller enabled: the 10-bit value (with a maximum of 384) represents the start value for the delay line used by the state machine to sample the DCI input. Leave at the default setting of 167, which is near the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. DATA RECEIVER CONTROLLER_DELAY LINE STATUS Table 21. Data Receiver Controller_Delay Line Status Register (LVDS_REC_STAT[1:4]) Address (Hex) 0x19 0x1A 0x1B 0x1C Bit Name SMP_DEL[1:0] SMP_DEL[9:2] DCI_DEL[1:0] DCI_DEL[9:2] Bits [7:6] [7:0] [7:6] [7:0] R/W R R R R Default Setting 0x00 0x00 0x00 0x00 Description The actual value of the DCI and data delay lines are determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. Note that these values should be equal. DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS Table 22. Data Receiver Controller Lock/Tracking Status Register (LVDS_REC_STAT9) Address (Hex) 0x21 Bit Name RCVR_TRK_ON RCVR_FE_ON Bits 3 2 R/W R R Default Setting 0x0 0x0 RCVR_LST RCVR_LCK 1 0 R R 0x0 0x0 Description 0 = tracking not established, 1 = tracking established. 0 = find edge state machine is not active, 1 = find edge state machine is active. 0 = controller has not lost lock, 1 = controller has lost lock. 0 = controller is not locked, 1 = controller is locked. Rev. D | Page 45 of 64 AD9737A/AD9739A Data Sheet CLK INPUT COMMON MODE Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2) Address (Hex) 0x22 0x23 Bit Name DIR_P CLKP_OFFSET[3:0] Bits 4 [3:0] R/W R/W R/W Default Setting 0x0 0x0000 DIR_N CLKN_OFFSET[3:0] 4 [3:0] R/W R/W 0x0 0x0000 Description DIR_P and DIR_N. 0 = VCM at the DACCLK_P input decreases with the offset value. 1 = VCM at the DACCLK_P input increases with the offset value. CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N inputs. For optimum performance, set to 1111. MU CONTROLLER CONFIGURATION AND STATUS Table 24. Mu Controller Configuration and Status Register (PHS_DET, MU_DUTY, MU_CNT[1:4], and MU_STAT1) Address (Hex) 0x24 0x25 0x26 0x27 0x28 Bit Name CMP_BST PHS_DET AUTO_EN MU_ DUTYAUTO_EN Bits 5 4 R/W R/W R/W Default Setting 0x0 0x0 7 R/W 0x0 Slope 6 R/W 0x1 Mode[1:0] [5:4] R/W 0x00 Read Gain[1:0] 3 [2:1] R/W R/W 0x0 0x01 Enable 0 R/W 0x0 MUDEL[0] SRCH_MODE[1:0] 7 [6:5] R/W R/W 0x0 0x0 SET_PHS[4:0] [4:0] R/W 0x0 MUDEL[8:1] [7:0] W 0x00 R 0x00 Description Phase detector enable and boost bias bits. Note that both bits should always be set to 1 to enable these functions. Mu controller duty cycle enable. Note that this bit should always be set to 1 to enable. Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note that a setting of 0 is recommended for best ac performance. Sets the Mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track. Set to 1 to read the current value of the Mu delay line in. Sets the Mu controller tracking gain. Recommended to leave at the default 01 setting. 0 = disable the Mu controller. 1 = enable the Mu controller. The LSB of the 9-bit MUDEL setting. Sets the direction in which the Mu controller searches (from its initial MUDEL setting) for the optimum Mu delay line setting that corresponds to the desired phase/slope setting (that is, SET_PHS and slope ). 00 = down. 01 = up. 10 = down/up (recommended). Sets the target phase that the Mu controller locks to with a maximum setting of 16. A setting of 4 (that is, 00100) is recommended for optimum ac performance. With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value that the Mu delay is set to. Note that the maximum value is 432. With enable set to 1, this value represents the Mu delay value at which the controller begins its search. Setting this value to the delay line midpoint of 216 is recommended. When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the Mu controller locks to when enable = 1. Rev. D | Page 46 of 64 Data Sheet Address (Hex) 0x29 0x2A AD9737A/AD9739A Bit Name SEARCH_TOL Bits 7 R/W R/W Default Setting 0x0 Retry 6 R/W 0x0 CONTRST 5 R/W 0x0 Guard[4:0] [4:0] R/W 0x01011 MU_LOST 1 R 0x0 MU_LKD 0 R 0x0 R/W R Default Setting 0x24 0x27 Description 0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting). 0 = stop the search if the correct value is not found, 1 = retry the search if the correct value is not found. Controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting), 1 = reset. Sets a guard band from the beginning and end of the Mu delay line, which the Mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is Decimal 11 or 0x0B). 0 = Mu controller has not lost lock. 1 = Mu controller has lost lock. 0 = Mu controller is not locked. 1= Mu controller is locked. PART ID Table 25. Part ID Register (PART_ID) Address (Hex) 0x35 Bit Name ID[7:0] Bits [7:0] Description 0x24—AD9739A 0x2C—AD9737A Rev. D | Page 47 of 64 AD9737A/AD9739A Data Sheet THEORY OF OPERATION RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF CLK DISTRIBUTION (DIV-BY-4) DATA LATCH IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK Figure 157. Functional Block Diagram of the AD9737A/AD9739A Rev. D | Page 48 of 64 09616-077 DCO 4-TO-1 DATA ASSEMBLER DCI LVDS DDR RECEIVER I120 LVDS DDR RECEIVER As mentioned, the host processor provides the AD9737A/ AD9739A with a deinterleaved data stream such that the DB0 and DB1 data ports receive alternating samples (that is, odd/even data streams). The AD9737A/AD9739A data assembler is used to reassemble (that is, multiplex) the odd/even data streams into their original order before delivery into the TxDAC for signal reconstruction. The pipeline delay from a sample being latched into the data port to when it appears at the DAC output is on the order of 78 (±) 2DACCLK cycles. The following sections discuss the various functional blocks in more detail as well as their implications when interfacing to external ICs and circuitry. Although a detailed description of the various controllers (and associated SPI registers used to configure and monitor) is also included for completeness, the recommended SPI boot procedure can be used to ensure reliable operation. DATA CONTROLLER The AD9737A/AD9739A data receiver controller generates an internal sampling clock for the DDR receiver such that the data instance sampling is optimized. When enabled and configured properly for track mode, it ensures proper data recovery between the host and the AD9737A/AD9739A clock domains. The data receiver controller has the ability to track several hundreds of picoseconds of drift between these clock domains, typically caused by supply and temperature variation. A SPI interface is used to configure the various functional blocks as well as monitor their status for debug purposes. Proper operation of the AD9737A/AD9739A requires that controller blocks be initialized upon power-up. A simple SPI initialization routine is used to configure the controller blocks (see Table 28). An IRQ output signal is available to alert the host should any of the controllers fall out of lock during normal operation. DB0[13:0] The AD9737A/AD9739A include two LVDS data ports (DB0 and DB1) to reduce the data interface rate to ½ the TxDAC update rate. The host processor drives deinterleaved data with offset binary format onto the DB0 and DB1 ports, along with an embedded DCI clock that is synchronous with the data. Because the interface is double data rate (DDR), the DCI clock is essentially an alternating 0-1 bit pattern with a frequency that is equal to ¼ the TxDAC update rate (fDAC). To simplify synchronization with the host processor, the AD9737A/AD9739A passes an LVDS clock output (DCO) that is also equal to the DCI frequency. The AD9737A/AD9739A includes a delay lock loop (DLL) circuit controlled via a Mu controller to optimize the timing hand-off between the AD9737A/AD9739A digital clock domain and TxDAC core. Besides ensuring proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing alignment over temperature, time, and power supply variation. DB1[13:0] The AD9739A and the AD9737A are 14- and 11-bit TxDACs with a specified update rate of 1.6 GSPS to 2.5 GSPS. Figure 157 shows a top-level functional diagram of the AD9737A/AD9739A. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA) to a balanced load referenced to ground. The frequency of the clock signal appearing at the AD9737A/AD9739A differential clock receiver, DACCLK, sets the TxDAC’s update rate. This clock signal, which serves as the master clock, is routed directly to the TxDAC as well as to a clock distribution block that generates all critical internal and external clocks. Data Sheet AD9737A/AD9739A LVDS DATA PORT INTERFACE The AD9737A/AD9739A supports input data rates from 1.6 GSPS to 2.5 GSPS using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded data clock input (DCI) at fDAC/4 with its rising and falling edges aligned with the data transitions. The data format is offset binary; however, twos complement format can be realized by reversing the polarity of the MSB differential trace. As shown in Figure 158, the host feeds the AD9737A/ AD9739A with deinterleaved input data into two 11-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock rate (that is, fDAC/2). The AD9737A/AD9739A internal data receiver controller then generates a phase shifted version of DCI to register the input data on both the rising and falling edges. HOST PROCESSOR 14 × 2 LVDS DDR RECEIVER ODD DATA SAMPLES 1×2 DATA CONTROLLER fDATA = fDAC /2 DB1[13:0] LVDS DDR DRIVER DATA DEINTERLEAVER 14 × 2 DB0[13:0] EVEN DATA SAMPLES LVDS DDR RECEIVER AD9737A/AD9739A DCI DCO 1×2 DIV-BY-4 fDAC fDCO = fDAC /4 09616-078 fDCI = fDAC /4 Figure 158. Recommended Digital Interface Between the AD9737A/AD9739A and Host Processor As shown in Figure 159, the DCI clock edges must be coincident with the data bit transitions with minimum skew, jitter, and intersymbol interference. To ensure coincident transitions with the data bits, the DCI signal should be implemented as an additional data line with an alternating (010101…) bit sequence from the same output drivers used for the data. Maximizing the opening of the eye in both the DCI and data signals improves the reliability of the data port interface. Differential controlled impedance traces of equal length (that is, delay) should also be used between the host processor and AD9737A/AD9739A input to limit bit-to-bit skew. The maximum allowable skew and jitter out of the host processor with respect to the DCI clock edge on each LVDS port is calculated as follows: MaxSkew + Jitter = Period(ps) − ValidWindow(ps) − Guard = 800 ps − 344 ps − 100 ps = 356 ps where ValidWindow(ps) is represented by tVALID and Guard is represented by tGUARD in Figure 159. The minimum specified LVDS valid window is 344 ps, and a guard band of 100 ps is recommended. Therefore, at the maximum operating frequency of 2.5 GSPS, the maximum allowable FPGA and PCB bit skew plus jitter is equal to 356 ps. For synchronous operation, the AD9737A/AD9739A provides a data clock output, DCO, to the host at the same rate as DCI (that is, fDAC/4) to maintain the lowest skew variation between these clock domains. The host processor has a worst case skew between DCO and DCI that is both implementation and process dependent. This worst case skew can also vary an additional 30% over temperature and supply corners. The delay line within the data receiver controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that generates a synchronous fDAC/4 from which the DCI signal is derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation. The data receiver controller is used to ensure proper data handoff between the host and AD9737A/AD9739A internal digital clock domains. The circuit shown in Figure 160 functions as a delay lock loop in which a 90° phase shifted version of the DCI clock input is used to sample the input data into the DDR receiver registers. This ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched DCI and DBx[13:0] delays). Note that, because the DCI delay and sample delay clocks are derived from the DIV-BY-4 circuitry, this 90° phase relationship holds as long as the delay settings (that is, DCI_DEL in Register 0x13 and Register 0x14, and SMP_DEL in Register 0x11 and Register 0x12) are also matched. 2 × 1/fDAC DCI max skew + jitter 09616-079 tVALID + tGUARD tVALID DB0[13:0] AND DB1[13:0] Figure 159. LVDS Data Port Timing Requirements Rev. D | Page 49 of 64 AD9737A/AD9739A Data Sheet DATA RECEIVER CONTROLLER DCI DDR FF DCI WINDOW PRE FINE DELAY PRE DDR FF DELAY DELAY DCI DELAY PATH DCI DELAY DCI WINDOW POST DDR FF 0 90 DIV-BY-4 180 270 STATE MACHINE/ TRACKING LOOP FINE DELAY POST FDAC SAMPLE DELAY DCI WINDOW SAMPLE SAMPLE DELAY PATH FINE DELAY DELAY DELAY SAMPLE DBx[13:1] DDR FF DDR FF DDR FF DDR FF DATA TO CORE 09616-080 ELASTIC FIFO DCO Figure 160. Top Level Diagram of the Data Receiver Controller The DIV-BY-4 circuit generates four clock phases that serve as inputs to the data receiver controller. All DDR registers in the data and DCI paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0° and 90°) corresponding to the positive edge of each path are shown. One of the DIV-BY4 phases is used to generate the DCO signal; therefore, the phase relationship between DCO and clocks fed into the controller remains fixed. Note that it is this attribute that allows possible factory calibration of images and clock spurs that are attributed to fDAC/4 modulation of the critical DAC clock. After this data has been successively sampled into the first set of registers, an elastic FIFO is used to transfer the data into the AD9737A/AD9739A clock domain. To track any phase variation continuously between the two clock domains, the data receiver controller should always be enabled and placed into track mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates continuously in the background to track delay variations between the host and AD9737A/AD9739A clock domains. It does so by ensuring that the DCI signal is sampled within a very narrow window defined by two internally generated clocks (that is, PRE and PST), as shown in Figure 161. Note that proper sampling of the DCI signal can also be confirmed by monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings are correct, the state of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0 should be 1. The skew or window width (FINE_DEL_SKEW) is set via Register 0x13, Bits[3:0], with a maximum skew of approximately 300 ps and resolution of 12 ps. It is recommended that the skew be set to 36 ps (that is, Register 0x13 = 0x72) during initialization. Note that the skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time. Data Receiver Controller Initialization Description The data controller should be initialized and placed into track mode as the second step in the SPI boot sequence. The following steps are recommended for the initialization of the data receiver controller: 1. 2. 3. 4. 5. 6. DCI FINE DELAY PRE FINE_DEL_SKEW 09616-081 FINE DELAY PST Figure 161. Pre- and Post-Delay Sampling Diagram Rev. D | Page 50 of 64 Set FINE_DEL_SKEW to 2 for a larger DCI sampling window (Register 0x13 = 0x72). Note that the default DCI_DEL and SMP_DEL settings of 167 are optimum. Disable the controller before enabling (that is, Register 0x10 = 0x00). Enable the Rx controller in two steps: Register 0x10 = 0x02 followed by Register 0x10 = 0x03. Wait 135 k clock cycles. Read back Register 0x21 and confirm that it is equal to 0x05 to ensure that the DLL loop is locked and tracking. Read back the DCI_DEL value to determine whether the value falls within a user defined tracking guard band. If it does not, go back to Step 2. Data Sheet AD9737A/AD9739A LVDS Driver and Receiver Input The AD9737A/AD9739A feature an LVDS-compatible driver and receivers. The LVDS driver output used for the DCO signal includes an equivalent 200 Ω source resistor that limits its nominal output voltage swing to ±200 mV when driving a 100 Ω load. The DCO output driver can be powered down via Register 0x01, Bit 5. An equivalent circuit is shown in Figure 162. On initialization of the AD9737A/AD9739A, a certain period of time is required for the data receiver controller to establish a lock of the DCI clock signal. Note that, due to its dependency on the Mu controller, the data receiver controller should be enabled only after the Mu controllers have been enabled and established lock. All of the internal controllers operate at a submultiple of the DAC update rate. The number of fDAC clock cycles required to lock onto the DCI clock is typically 70 k clock cycles but can be up to 135 k clock cycles. During the SPI initialization process, the user has the option of polling Register 0x21 (Bit 0, Bit 1, and Bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into track mode before completing the boot sequence. Alternatively, the appropriate IRQ bit (Register 0x03 and Register 0x04) can be enabled such that an IRQ output signal is generated upon the controller establishing lock. Rev. D | Page 51 of 64 VDD33 V+ V– 100Ω 100Ω DCO_N ESD V– ESD VCM DCO_P V+ 09616-082 The adjustable delay span for these internal clocks (that is, DCI and sample delay) is nominally 4 ns. The 10-bit delay value is user programmable from the decimal equivalent code (0 to 384) with approximately 12 ps/LSB resolution via the DCI_DEL (Register 0x13 and Register 0x14)and SMP_DEL registers (Register 0x11 and Register 0x12). When the controller is enabled, it overwrites these registers with the delay value it converges upon. The minimum difference between this delay value and the minimum/maximum values (that is, 0 and 384) represents the guard band for tracking. Therefore, if the controller initially converges upon a DCI_DEL and SMP_DEL value between 80 and 3044, the controller has a guard band of at least 80 code (approximately 1 ns) to track phase variations between the clock domains. The data receiver controller can also be configured to generate an interrupt request (IRQ) upon losing lock. Losing lock can be caused by disruption of the main DAC clock input or loss of a power supply rail. To service the interrupt, the host can poll the RCVR_LCK bit (Bit 0, Recister 0x21) to determine the current state of the controller. If this bit is cleared, the search/track procedure can be restarted by setting the RCVR_LOOP_ON bit (Bit 1) in Register 0x10. After waiting the required lock time, the host can poll the RCVR_LCK bit to see if it has been set. Before leaving the interrupt routine, the RCVR_FLG_RST bit (Bit 2, Register 0x10) should be reset by writing a high followed by a low. VSS Figure 162. Equivalent LVDS Output VDD33 100Ω DCI_P DBx[13:0]P ESD ESD DCI_N DBx[13:0]N VSS Figure 163. AD9739A Equivalent LVDS Input 09616-083 After the controller is enabled during the initial SPI boot process (see Table 29), the controller enters a search mode where it seeks to find the closest rising edge of the DCI clock (relative to a delayed version of an internal fDAC/4 clock) by simultaneously adjusting the delays in the clocks used to register the DCI and data inputs. A state machine searches above and below the initial DCI_DEL value. The state machine first searches for the first rising edge above the DCI_DEL and then searches for the first rising edge below the DCI_DEL value. The state machine selects the closest rising edge and then enters track mode. It is recommended that the default midpoint delay setting (that is, Decimal 167) for the DCI_DEL and SMP_DEL bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for tracking timing variations and preventing the controller from falling out of lock. AD9737A/AD9739A Data Sheet LVDS INPUTS (NO FAIL-SAFE) VCOM = (V + V )/2 P N VP,N VP LVDS RECEIVER 100Ω V N GND Example 14-BIT DATA 16 0V 14 –0.4V LOGIC 1 12 MU PHASE 18 0.4V 09616-084 1.0V Figure 164. LVDS Data Input Levels IOUTN PHASE DETECTOR The Mu controller adjusts the timing relationship between the digital and analog domains via a tapped digital delay line having a nominal total delay of 864 ps. The delay value is programmable to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL bits (Register 0x27 and 0x28), resulting in a nominal resolution of 2 ps/LSB. Because a time delay maps to a phase offset for a fixed clock frequency, the control loop essentially compares the phase relationship between the two clock domains and adjusts the phase (that is, via a tapped delay line) of the digital clock such that it is at the desired fixed phase offset (SET_PHS) from the critical analog clock. VP LOGIC 0 IOUTP Figure 165. AD97339A Mu Delay Controller Block Diagram VN LOGIC BIT EQUIVALENT ANALOG CIRCUITRY MU DELAY CONTROLLER DAC CLOCK 1.4V N 14-BIT DATA MU DELAY V P V DIGITAL CIRCUITRY 09616-085 The LVDS receivers include 100 Ω termination resistors, as shown in Figure 163. These receivers meet the IEEE-1596.3-1996 reduced swing specification (with the exception of input hysteresis, which cannot be guaranteed over all process corners). Figure 164 and Table 26 show an example of nominal LVDS voltage levels seen at the input of the differential receiver with resulting common-mode voltage and equivalent logic level. Note that the AD9737A/AD9739A LVDS inputs do not include fail-safe capability; hence, any unused input should be biased with an external circuit or static driver. The LVDS receivers can be powered-down via Register 0x01, Bit 4. GUARD BAND GUARD BAND 10 DESIRED PHASE 8 6 Table 26. Example of LVDS Input Levels 4 SEARCH STARTING LOCATION 2 Logic Bit Binary Equivalent 1 0 1 0 MU CONTROLLER A delay lock loop (DLL) is used to optimize the timing between the internal digital and analog domains of the AD9737A/AD9739A such that data is successfully transferred into the TxDAC core at rates of up to 2.5 GSPS. As shown in Figure 165, the DAC clock is split into an analog and a digital path with the critical analog path leading to the DAC core (for minimum jitter degradation) and the digital path leading to a programmable delay line. Note that the output of this delay line serves as the master internal digital clock from which all other internal and external digital clocks are derived. The amount of delay added to this path is under the control of the Mu controller, which optimizes the timing between these two clock domains and continuously tracks any variation (once in track mode) to ensure proper data hand-off. 0 0 40 80 120 160 200 240 280 320 360 400 440 MU DELAY 09616-086 Applied Voltages VP VN 1.4 V 1.0 V 1.0 V 1.4 V 1.0 V 0.8 V 0.8 V 1.0 V Resulting Differential Voltage VP,N +0.4 V −0.4 V +200 mV −200 mV Resulting CommonMode Voltage VCOM 1.2 V 1.2 V 900 mV 900 mV Figure 166. Typical Mu Phase Characteristic Plot at 2.4 GSPS Figure 166 maps the typical Mu phase characteristic at 2.4 GSPS vs. the 9-bit digital delay setting (MUDEL). The Mu phase scaling is such that a value of 16 corresponds to 180 degrees. The critical keep-out window between the digital and analog domains occurs at a value of 0 (but can extend out to 2 depending on the clock rate). The target Mu phase (and slope) is selected to provide optimum ac performance while ensuring that the Mu controller for any device can establish and maintain lock. For example, although a slope and phase setting of −6 is considered optimum for operation between 1.6 GSPS and 2.5 GSPS, other values are required below 1.6 GSPS. Rev. D | Page 52 of 64 Data Sheet 18 AD9737A/AD9739A Mu Controller Initialization Description NOM_P1 SLOW_P1 FAST_P1 16 The Mu controller must be initialized and placed into track mode as a first step in the SPI boot sequence. The following steps are required for initialization of the Mu controller. Note that the AD9737A/AD9739A data sheet specifications and characterization data are based on the following Mu controller settings: 14 MU PHASE 12 10 8 1. 2. 6 4 2 3. 0 40 80 120 160 200 240 280 320 360 400 440 DELAY LINE TAP 09616-050 0 Figure 167. Mu Phase Characteristics of Three Devices from Different Process Lots at 1.2 GSPS The Mu phase characteristics can vary significantly among devices due to gm variations in the digital delay line that are sensitive to process skews, along with temperature and supply. As a result, careful selection of the target phase location is required such that the Mu controller can converge upon this phase location for all devices. Figure 167 shows the Mu phase characteristics of three devices at 25°C from slow, nominal, and fast skew lots at 1.2 GSPS. Note that a −6 Mu phase setting does not map to any delay line tap setting for the fast process skew case; therefore, another target Mu phase is recommended at this clock rate. Table 27 provides a list of recommended Mu phase/slope settings over the specified clock range of the AD9737A/AD9739A based on the considerations previously described. These values should be used to ensure robust operation of the Mu controller. Table 27. Recommended Target Mu Phase Settings vs. Clock Rate Clock Rate (GSPS) 1.6 to 2.5 Slope − Mu Phase 6 After the Mu controller completes its search and establishes lock on the target Mu phase, it attempts to maintain a constant timing relationship between the two clock domains over the specified temperature and supply range. If the Mu controller requests a Mu delay setting that exceeds the tapped delay line range (that is, 432), the Mu controller can lose lock, causing possible system disruption (that is, can generate an IRQ or restart the search). To avoid this scenario, symmetrical guard bands are recommended at each end of the Mu delay range. The guard band scaling is such that one LSB of Guard[4:0] (Register 0x29) corresponds to eight LSBs of MUDEL[8:0] (Register 0x28). The recommended guard band setting of 11 (that is, Register 0x29 = 0xCB) corresponds to 88 LSBs, thus providing sufficient margin. 4. 5. Turn on the phase detector with boost (Register 0x24 = 0x30). Enable the Mu delay controller duty-cycle correction circuitry and specify the recommended slope for phase. (that is, Register 0x25 = 0x80 corresponds to a negative slope). Specify search/track mode with a recommended target phase, SET_PHS, of 6 (for example) and an initial MUDEL[8:0] setting of 216 (Register 0x27 = 0x46 and Register 0x28 = 0x6C). Set search tolerance to exact, and retry if the search fails its initial attempt. Also, set the guard band to the recommended setting of 11 (Register 0x29 = 0xCB). Set the Mu controller tracking gain to the recommended setting and enable the Mu controller state machine (Register 0x26 = 0x03). On completion of the last step, the Mu controller begins a search algorithm that starts with an initial delay setting specified by the MUDEL bits (that is, 216, which corresponds to the midpoint of the delay line). The initial search algorithm works by sweeping through different Mu delay values in an alternating manner until the desired phase (that is, a SET_PHS of 4) is exactly measured. When the desired phase is measured, the slope of the phase measurement is then calculated and compared against the specified slope (slope = negative). If everything matches, the search algorithm is finished. If not, the search continues in both directions until an exact match is found or a programmable guard band is reached in one of the directions. When the guard band is reached, the search still continues but only in the opposite direction. If the desired phase is not found before the guard band is reached in the second direction, the search changes back to the alternating mode and continues looking within the guard band. The typical locking time for the Mu controller is approximately 180 k DAC cycles (at 2 GSPS ~ 75 µs). The search fails if the Mu delay controller reaches the endpoints. The Mu controller can be configured to retry (Register 0x29, Bit 6) the search or stop. For applications that have a microcontroller, the preferred approach is to poll the MU_LKD status bit (Register 0x2A, Bit 0) after the typical locking time has expired. This method lets the system controller check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to Register 0x26). Rev. D | Page 53 of 64 AD9737A/AD9739A Data Sheet After the Mu delay value is found that exactly matches the desired Mu phase setting and slope (for example, 6 with a negative slope), the Mu controller goes into track mode. In this mode, the Mu controller makes slight adjustments to the delay value to track any variations between the two clock paths due to temperature, time, and supply variations. Two status bits, MU_LKD (Register 0x2A, Bit 0) and MU_LST (Register 0x2A, Bit 1) are available to the user to signal the existing status control loop. If the current phase is more than four steps away from the desired phase, the MU_LKD bit is cleared, and if the lock acquired was previously set, the MU_LST bit is set. Should the phase deviation return to within three steps, the MU_LKD bit is set again while the MU_LST is cleared. Note that this sort of event may occur if the main clock input (that is, DACCLK) is disrupted or the Mu controller exceeds the tapped delay line range (that is, 432). If lock is lost, the Mu controller has the option of remaining in the tracking loop or resetting and starting the search again via the CONTRST bit (Register 0x29, Bit 5). Continued tracking is the preferred state because it is the least disruptive to a system in which the AD9737A/AD9739A temporarily loses lock. The user can poll the Mu delay and phase value by first setting the read bit high (Register 0x26, Bit 3). After the read bit is set, the MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27 and Register 0x28) that the controller is currently using can be read. INTERRUPT REQUESTS The AD9737A/AD9739A can provide the host processor with an interrupt request output signal (IRQ) that indicates that one or more of the AD9737A/AD9739A internal controllers have achieved lock or lost lock. These controllers include the Mu, data receiver, and synchronization controllers. The host can then poll the IRQ status register (Register 0x04) to determine which controller has lost lock. The IRQ output signal is an active high output signal available on Pin F13. If used, its output should be connected via a 10 kΩ pull-up resistor to VDD33. Each IRQ is enabled by setting the enable bits in Register 0x03, which purposely has the same bit mapping as the IRQ status bits in Register 0x04. Note that these IRQ status bits are set only when the controller transitions from a false to true state. Hence, it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to be set when a controller temporarily loses lock but is able to reestablish lock before the IRQ is serviced by the host. In this case, the host should validate the present status of the suspect controller by reading back its current status bits, which are available in Register 0x21 and/or Register 0x2A. Based on the status of these bits, the host can take appropriate action, if required, to reestablish lock. To clear an IRQ after servicing, it is necessary to reset relevant bits in Register 0x03 by writing 0 followed by another write of 1 to reenable. A detailed diagram of the interrupt circuitry is shown in Figure 168. D SPI DATA Q INT(n) (PIN F13) INT SOURCE SPI ISR READ DATA INT SOURCE SCLK SPI WRITE SPI ADDRESS IMR DATA = 1 09616-087 For applications that do not have polling capabilities, the Mu controller state machine should be reconfigured to restart the search, such that lock can be re-attempted with system conditions that may have changed and be different, and thus may enable the controller to lock. Figure 168. Interrupt Request Circuitry It is also possible to use the IRQ during the AD9737A/AD9739A initialization phase after power-up to determine when the Mu and data receiver controllers have achieved lock. For example, before enabling the Mu controller, the MU_LCK_EN bit can be set and the IRQ output signal monitored to determine when lock has been established before continuing in a similar manner with the data receiver controllers. Note that the relevant LCK bit should be cleared before continuing to the next controller. After all controllers are locked, the lost lock enable bits (that is, x_LST_EN) should be set. Table 28. Interrupt Request Registers Address (Hex) 0x03 0x04 0x21 0x2A Rev. D | Page 54 of 64 Bit 3 2 1 0 3 2 1 0 3 1 0 1 0 Description MU_LST_EN MU_LCK_EN RCV_LST_EN RCV_LCK_EN MU_LST_IRQ MU_LCK_IRQ RCV_LST_IRQ RCV_LCK_IRQ RCVR_TRK_ON RCVR_LST RCVR_LCK MU_LST MU_LKD Data Sheet AD9737A/AD9739A ANALOG INTERFACE CONSIDERATIONS The AD9737A/AD9739A use the quad-switch architecture shown in Figure 169. The quad-switch architecture masks the code-dependent glitches that occur in a conventional two-switch DAC. Figure 170 compares the waveforms for a conventional DAC and the quad-switch DAC. In the two-switch architecture, a code-dependent glitch occurs each time the DAC switches to a different state (that is, D1 to D2). This code-dependent glitching causes an increased amount of distortion in the DAC. In quadswitch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the code-dependent glitches. However, a constant glitch occurs at 2 × DACCLK_x because half the internal switches change state on the rising DACCLK_x edge whereas the other half change state on the falling DACCLK_x edge. VDD DACCLK_x CLK VG1 VG2 VG1 LATCHES V 3 G DBx[13:0] VG4 VG2 VG3 IOUTP 09616-088 VG4 IOUTN Figure 169. AD9739A Quad-Switch Architecture centered around the DAC sample rate, thus improving the output power of these images. INPUT DATA D1 D2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D4 D5 D6 D7 D8 D9 D10 DACCLK_x –D8 D3 D2 FOUR-SWITCH DAC OUTPUT (fS MIX MODE) –D7 D4 D1 D5 –D9 –D6 –D10 t –D5 D6 –D1 –D2 D10 D9 D7 –D4 D8 –D3 Figure 171. Mix-Mode DAC Waveforms Figure 171 shows the DAC waveforms for mix-mode. This ability to change modes provides the user the flexibility to place a carrier anywhere in the first two Nyquist zones, depending on the operating mode selected. Switching between the analog modes reshapes the sinc roll-off that is inherent at the DAC output. The maximum amplitude in both Nyquist zones is impacted by this sinc roll-off, depending on where the carrier is placed (see Figure 172). As a practical matter, the usable bandwidth in the third Nyquist zone becomes limited at higher DAC clock rates (that is, >2 GSPS) when the output bandwidth of the DAC core and the interface network (that is, balun) contributes to additional roll-off. FIRST NYQUIST ZONE INPUT DATA D3 09616-090 ANALOG MODES OF OPERATION D10 SECOND NYQUIST ZONE 0 THIRD NYQUIST ZONE MIX MODE DACCLK_x –5 D1 D2 D3 D4 D5 t D6 D7 D8 D9 –10 D10 –15 D6 D2 D3 D4 D7 D8 D9 D10 –20 t D5 09616-089 FOUR-SWITCH DAC OUTPUT (NORMAL MODE) D1 NORMAL MODE –25 Figure 170. Two-Switch and Quad-Switch DAC Waveforms –30 Another attribute of the quad-switch architecture is that it also enables the DAC core to operate in one of the following two modes: normal mode and mix-mode. The mode is selected via SPI Register 0x08, Bits[1:0], with normal mode being the default value. In the mix-mode, the output is effectively chopped at the DAC sample rate. This has the effect of reducing the power of the fundamental signal while increasing the power of the images –35 0FS Rev. D | Page 55 of 64 0.25FS 0.50FS 0.75FS 1.00FS 1.25FS 1.50FS FREQUENCY (Hz) Figure 172. Sinc Roll-Off for Each Analog Operating Mode 09616-091 TWO-SWITCH DAC OUTPUT AD9737A/AD9739A Data Sheet CLOCK INPUT CONSIDERATIONS AD9737A/AD9739A VCC VREF VT 50Ω 50Ω 50Ω 50Ω D Q D Q 50Ω 10nF DACCLK_P 100Ω DACCLK_N 10nF 10nF 09616-092 10nF 50Ω ADCLK914 VEE Figure 173. ADCLK914 Interface to the AD9737A/AD9739A CLK Input AD9737A/AD9739A 3.9nH VVCO ADF4350 1nF RFOUTA+ PLL FREF VCO DIV-BY-2N DACCLK_P 100Ω N=0–4 1nF DACCLK_N RFOUTA– 1.8V p-p RFOUTA+ 09616-093 RFOUTA– Figure 174. ADF4350 Interface to the AD9737A/AD9739A CLK Input Figure 174 shows a clock source based on the ADF4350 low phase noise/jitter PLL. The ADF4350 can provide output frequencies from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms. Each single-ended output can provide a squared-up output level that can be varied from −4 dBm to +5 dBm, allowing for >2 V p-p output differential swings. The ADF4350 also includes an additional CML buffer that can be used to drive another AD9737A/AD9739A device. The AD9737A/AD9739A clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or CML output drivers. For a low jitter sinusoidal clock source, the ADCLK914 can be used to square-up the signal and provide a CML input signal for the AD9737A/AD9739A clock receiver. Note that all specifications and characterization presented in the data sheet are with the ADCLK914 driven by a high quality RF signal generator with the clock receiver biased at an 800 mV level. Rev. D | Page 56 of 64 VDDC 4-BIT PMOS IOUT ARRAY DACCLK_P DACCLK_N CLKx_OFFSET DIR_x = 0 ESD CLKx_OFFSET DIR_x = 0 4-BIT NMOS IOUT ARRAY VSSC Figure 175. Clock Input and Common-Mode Control 09616-094 The quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. The phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. For optimal ac performance of the AD9737A/AD9739A, the recommended minimum differential peak-to-peak voltage is approximately 1.4 VPP. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10(fOUT/fCLK) when the DAC clock path contribution, along with thermal and quantization effects, are negligible. Data Sheet AD9737A/AD9739A The AD9737A/AD9739A clock receiver features the ability to independently adjust the common-mode level of its inputs over a span of ±100 mV centered about its mid-supply point (that is, VDDC/2), as well as an offset for hysteresis purposes. Figure 175 shows the equivalent input circuit of one of the inputs. ESD diodes are not shown for clarity purposes. It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V. This can be achieved by writing a 0x0F (corresponding to a −15) setting to both cross controller registers (that is, Register 0x22 and Register 0x23). 1.10 CLKP CLKN 1.05 IOUTFS can be adjusted digitally over 8.7 mA to 31.7 mA by using FSC[9:0] (Register 0x06 and Register 0x07). The following equation relates IOUTFS to the FSC[9:0] bits, which can be set from 0 to 1023. IOUTFS = 22.6 × FSC[9:0]/1000 + 8.7 Note that a default value of 0x200 generates 20 mA full scale, which is used for most of the characterization presented in this data sheet (unless noted otherwise). Equivalent DAC Output and Transfer Function 0.90 0.85 0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 OFFSET CODE 09616-095 0.75 The AD9737A/AD9739A provide complementary current outputs, IOUTP and IOUTN, that source current into an external ground reference load. Figure 178 shows an equivalent output circuit for the DAC. Note that, compared to most current output DACs of this type, the AD9737A/AD9739A outputs exhibit a slight offset current (that is, IOUTFS/16), and the peak differential ac current is slightly below IOUTFS/2 (that is, 15/32 × IOUTFS). IOUTFS = 8.6 – 31.2mA Figure 176. Common-Mode Voltage with Respect to CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N 17/32 × IOUTFS VOLTAGE REFERENCE IPEAK = 15/32 × IOUTFS The AD9737A/AD9739A output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 177. FSC[9:0] VREF 10kΩ VSSA CURRENT SCALING IFULL-SCALE I120 09616-097 Figure 177. Voltage Reference Circuit The reference current is obtained by forcing the band gap voltage across an external 10 kΩ resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 μA reference current in the 10 kΩ resistor. Note the following constraints when configuring the voltage reference circuit:   2.2pF As shown in Figure 178, the DAC output can be modeled as a pair of dc current sources that source a current of 17/32 × IOUTFS to each output. A differential ac current source, IPEAK, is used to model the signal-dependent nature of the DAC output. The polarity and signal dependency of this ac current source are related to the digital code by the following equation: 09616-096 + 70Ω Figure 178. Equivalent DAC Output Circuit DAC – I120 1nF AC 17/32 × IOUTFS AD9737A/AD9739A VBG 1.2V  (1) 0.95 0.80  An external reference can be used to overdrive the internal reference by connecting it to the VREF pin. ANALOG OUTPUTS 1.00 COMMON MODE (V)  Both the 10 kΩ resistor and 1 nF bypass capacitor are required for proper operation. Digitally adjust the DAC’s output full-scale current, IOUTFS, from its default setting of 20 mA. The AD9737A/AD9739A are not a multiplying DAC. Modulating the reference current, I120, with an ac signal is not supported. The band gap voltage appearing at the VREF pin (Pin C14) must be buffered for use with an external circuitry because its output impedance is approximately 5 kΩ. F(Code) = (DACCODE − 8192)/8192 (2) −1 < F(Code) < 1 (3) where DACCODE = 0 to 16,383 (decimal). Because IPEAK can swing ±(15/32) × IOUTFS, the output currents measured at IOUTP and IOUTN can span from IOUTFS/16 to IOUTFS. However, because the ac signal-dependent current component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (34/32) × IOUTFS). Rev. D | Page 57 of 64 AD9737A/AD9739A Data Sheet If the AD9737A/AD9739A are programmed for IOUTFS = 20 mA, the peak ac current is 9.375 mA and the peak power delivered to the equivalent load is 2.2 mW (that is, P = I2R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mW or 0.4 dBm. The code-dependent current measured at the IOUTP and IOUTN outputs is as follows: IOUTP = 17/32 × IOUTFS + 15/32 × IOUTFS × F(Code) (4) IOUTN = 17/32 × IOUTFS − 15/32 × IOUTFS × F(Code) (5) Figure 179 shows the IOUTP vs. DACCODE transfer function when IOUTFS is set to 19.65 mA. To calculate the rms power delivered to the load, the following must be considered: 20 18 • • • OUTPUT CURRENT (mA) 16 14 12 10 For example, a reconstructed sine wave with no digital backoff ideally measures −2.6 dBm because it has a peak-to-rms ratio of 3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of actual power can be expected in the region where the sinc response of the DAC has negligible influence. Increasing the output power is best accomplished by increasing IOUTFS, although any degradation in linearity performance must be considered acceptable for the target application. 8 6 4 0 4096 8192 16,384 12,288 DAC CODE 09616-098 2 0 Peak-to-rms of the digital waveform Any digital backoff from digital full scale The DAC’s sinc response and nonideal losses in external network Figure 179. Gain Curve for FSC[9:0] = 512, DAC OFFSET = 1.228 mA Peak DAC Output Power Capability The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, IPEAK, and the equivalent load resistance it sees. Because the AD9737A/ AD9739A include a differential 70 Ω resistance, it is best to use a doubly terminated external output network similar to what is shown in Figure 181. In this case, the equivalent load seen by the ac current source of the DAC is 25 Ω. RSOURCE = 50Ω IOUTFS = 8.6 – 31.2mA AC 70Ω 180Ω LOSSLESS BALUN 1:1 RLOAD = 50Ω 09616-099 IPEAK = 15/32 × IOUTFS Figure 180. Equivalent Circuit for Determining Maximum Peak Power to a 50 Ω Load Rev. D | Page 58 of 64 Data Sheet AD9737A/AD9739A The AD9737A/AD9739A are intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac performance can be realized only if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. The output network used to interface to the DAC should provide a near 0 Ω dc bias path to analog ground. Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9737A/AD9739A. Figure 183 shows an interface that can be considered when interfacing the DAC output to a self-biased differential gain block. The inductors shown serve as RF chokes (L) that provide the dc bias path to analog ground. The value of the inductor, along with the dc blocking capacitors (C), determines the lower cutoff frequency of the composite pass-band response. An RF balun should also be considered before the RF differential gain stage and any filtering to ensure symmetrical common-mode impedance seen by the DAC output while suppressing any common mode noise, harmonics, and clock spurs prior to amplification. OPTIONAL BALUN AND FILTER IOUTP C 90Ω L 70Ω 90Ω LPF C RF DIFF AMP L 09616-102 OUTPUT STAGE CONFIGURATION IOUTN MINI-CIRCUITS® TC1-33-75G+ IOUTP Figure 183. Interfacing the DAC Output to the Self-Biased Differential Gain Stage 90Ω 70Ω 90Ω Figure 181. Recommended Balun for Wideband Applications with Upper Bandwidths of up to 2.2 GHz Most applications requiring balanced-to-unbalanced conversion can take advantage of the Ruthroff 1:1 balun configuration shown in Figure 181. This configuration provides excellent amplitude/phase balance over a wide frequency range while providing a 0 Ω dc bias path to each DAC output. Also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction of up to 2.2 GHz. The characterization plots shown in this data sheet are based on the AD9737A/AD9739A evaluation board, which uses this configuration. Figure 182 compares the measured frequency response for normal and mix-mode using the AD9737A/AD9739A evaluation board vs. the ideal frequency response. 0 IDEAL BASEBAND MODE –3 C IOUTP 90Ω L 90Ω L 70Ω IOUTN C Figure 184. Recommended Mix-Mode Configuration Offering Extended RF Bandwidth Using a TC1-1-43A+ Balun MURATA JOHANSON TECHNOLOGY CHIP BALUNS BASEBAND –6 TC1-33-75G IOUTP MIX MODE TC1-33-75G –9 MINI-CIRCUITS TC1-1-462M 09616-103 09616-100 IOUTN For applications operating the AD9737A/AD9739A in mix-mode with output frequencies extending beyond 2.2 GHz, the circuits shown in Figure 184 should be considered. The circuit in Figure 184 uses a wideband balun with a configuration similar to the one shown in Figure 183 to provide a dc bias path for the DAC outputs. The circuit in Figure 185 takes advantage of ceramic chip baluns to provide a dc bias path for the DAC outputs while providing excellent amplitude/phase balance over a narrower RF band. These low cost, low insertion loss baluns are available for different popular RF bands and provide excellent amplitude/ phase balance over their specified frequency range. 70Ω IDEAL MIX MODE –15 –18 IOUTN –21 –24 Figure 185. Lowest Cost and Size Configuration for Narrow RF Band Operation –27 –30 0 500 1000 1500 2000 2500 FREQUENCY (MHz) 3000 3500 09616-101 –33 –36 180Ω 09616-104 POWER (dBc) –12 Figure 182. Measured vs. Ideal Frequency Response for Normal (Baseband) and Mix-Mode Operation Using a TC1-33-75G Transformer on the AD9737A/AD9739A EVB Rev. D | Page 59 of 64 AD9737A/AD9739A Data Sheet NONIDEAL SPECTRAL ARTIFACTS 3. The AD9737A/AD9739A output spectrum contains spectral artifacts that are not part of the original digital input waveform. These nonideal artifacts include harmonics (including alias harmonics), images, and clock spurs. Figure 186 shows a spectral plot of the AD9737A/AD9739A within the first Nyquist zone (that is, dc to fDAC/2) reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides the desired fundamental tone at the −7.8 dBm level, the spectrum also reveals these nonideal artifacts that also appear as spurs above the measurement noise floor. Because these nonideal artifacts are also evident in the second and third Nyquist zones during mix-mode operation, the effects of these artifacts should also be considered when selecting the DAC clock rate for a target RF band. 4. 0 FUND AT –7.6dBm –10 –20 POWER (dBc) –30 –40 fDAC /2 – fDAC /4 fOUT –50 fDAC /4 – fOUT –60 –70 3/4 × fDAC /4 – fOUT HD3 HD2 HD5 HD6 HD4 5. HD9 –80 –100 0 200 400 600 800 FREQUENCY (MHz) 1000 1200 09616-105 –90 Figure 186. Spectral Plot Note the following important observations pertaining to these nonideal spectral artifacts: 1. 2. A full-scale sine wave (that is, single-tone) typically represents the worst case condition because it is has a peak-to-rms ratio of 3 dB and is unmodulated. Harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs. Significant characterization of a high speed DAC is performed using single (or multitone) signals for this reason. Modulated signals (that is, AM, PM, or FM) do not appear as spurs but rather as signals whose power spectral density is spread over a defined bandwidth determined by the modulation parameters of the signals. Any harmonics from the DAC spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. For this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern. 6. Rev. D | Page 60 of 64 Images appear as replicas of the original signal, hence, can be easier to identify. In the case of the AD9737A/AD9739A, internal modulation of the sampling clock at intervals related to fDAC/4 generate image pairs at ¼ × fDAC, ½ × fDAC, and ¾ × fDAC. Both upper and lower sideband images associated with ¼ × fDAC fall within the first Nyquist zone, whereas only the lower image of ½ × fDAC and ¾ × fDAC fall back. Note that the lower images appear frequency inverted. The ratio between the fundamental and various images (that is, dBc) remains mostly signal independent because the mechanism causing these images is related to corruption of the sampling clock. The magnitude of these images for a given device depends on several factors, including DAC clock rate, output frequency, and Mu controller phase setting. Because the image magnitude is repeatable between power-up cycles (assuming the same conditions), a one-time factory calibration procedure can be used to improve suppression. Calibration consists of additional dedicated DSP resources in the host that can generate a replica of the image with proper amplitude, phase, and frequency scaling to cancel the image from the DAC. Because the image magnitude can vary among devices, each device must be calibrated. A clock spur appears at fDAC/4 and integer multiples of it. Similar to images, the spur magnitude also depends on the same factors that cause variations in image levels. However, unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. The calibration method is similar to image calibration; however, only a digital tone of equal amplitude and opposite phase at fDAC/4 need be generated. A large clock spur also appears at 2 × fDAC in either normal or mix-mode operation. This clock spur is due to the quad switch DAC architecture causing switching events to occur on both edges of fDAC. Data Sheet AD9737A/AD9739A LAB EVALUATION OF THE AD9737A/AD9739A RECOMMENDED START-UP SEQUENCE Figure 187 shows a recommended lab setup that was used to characterize the performance of the AD9737A/AD9739A. The DPG2 is a dual port LVDS/CMOS data pattern generator that is available from Analog Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9737A/AD9739A evaluation board via Tyco Z-PACK HM-Zd connectors. A low phase noise/jitter RF source such as an R&S SMA100A signal generator is used for the DAC clock. A +5 V power supply is used to power up the AD9737A/AD9739A evaluation board, and SMA cabling is used to interface to the supply, clock source, and spectrum analyzer. A USB 2.0 interface to a host PC is used to communicate to both the AD9737A/AD9739A evaluation board and the DPG2. On power-up of the AD9737A/AD9739A, a host processor is required to initialize and configure the AD9737A/AD9739A via its SPI port. Figure 188 shows a flowchart of the sequential steps required. Table 29 provides more detail on the SPI register write/read operations required to implement the flowchart steps. Note the following: ADI PATTERN GENERATOR DPG2 DCO USB 2.0     CONFIGURE SPI PORT SET CLK INPUT CMV LAB PC LVDS DATA AND DCI AD9739 EVAL. BOARD POWER SUPPLY +5V 10 MHz REFIN 10 MHz REOUT AGILENT PSA E4440A NO CONFIGURE RX DATA CONT. NO RECONFIGURE TXDAC FROM DEFAULT SETTING WAIT A FEW 100µs WAIT A FEW 100µs OPTIONAL MU CONT. LOCKED? RX DATA CONT. LOCKED? YES YES Figure 188. Flowchart for Initialization and Configuration of the AD9737A/AD9739A 09616-106 1.6GHz TO 2.5GHz 3dBm CONFIGURE MU CONT. SOFTWARE RESET GPIB RHODE AND SCHWARTZ SMA 100A A software reset is optional because the AD9737A/AD9739A have both an internal POR circuit and a RESET pin. The Mu controller must be first enabled (and in track mode) before the data receiver controller is enabled because the DCO output signal is derived from this circuitry. A wait period is related to fDATA periods. Limit the number of attempts to lock the controllers to three; locks typically occur on the first attempt. Hardware or software interrupts can be used to monitor the status of the controllers. Figure 187. Lab Test Setup Used to Characterize the AD9737A/AD9739A Rev. D | Page 61 of 64 09616-107 A high dynamic range spectrum analyzer is required to evaluate the ac performance of the AD9737A/AD9739A reconstructed waveform. This is especially the case when measuring ACLR performance for high dynamic range applications such as multicarrier DOCSIS CMTS applications. Harmonic, SFDR, and IMD measurements pertaining to unmodulated carriers can benefit by using a sufficiently high RF attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. However, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range RF amplifier and/or passive filters to measure close-in and wideband ACLR performance when using spectrum analyzers of limited dynamic range.  AD9737A/AD9739A Data Sheet Table 29. Recommended SPI Initialization Step 1 Address (Hex) 0x00 Write Value 0x00 2 3 4 5 6 7 8 9 10 11 12 13 14 0x00 0x00 0x22 0x23 0x24 0x25 0x27 0x28 0x29 0x26 0x26 0x20 0x00 0x0F 0x0F 0x30 0x80 0x44 0x6C 0xCB 0x02 0x03 15 16 17 18 19 20 21 22 23 0x2A 0x13 0x10 0x10 0x10 0x72 0x00 0x02 0x03 0x21 0x06 0x07 0x08 0x00 0x02 0x00 Comments Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up. Software reset to default SPI values. Clear the reset bit. Set the common-mode voltage of DACCLK_P and DACCLK_N inputs Configure the Mu controller. Enable the Mu controller search and track mode. Wait for 160 k × 1/fDATA cycles. Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, return to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a Mu lock failure. Ensure that the AD9737A/AD9739A are fed with DCI clock input from the data source. Set FINE_DEL_SKEW to 2. Disable the data Rx controller before enabling it. Enable the data Rx controller for loop and IRQ. Enable the data Rx controller for search and track mode. Wait for 135 k × 1/fDATA cycles. Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, return to Step 16 and repeat. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure. Optional: modify the TxDAC IOUTFS setting (the default is 20 mA). Optional: modify the TxDAC operation mode (the default is normal mode). Rev. D | Page 62 of 64 Data Sheet AD9737A/AD9739A OUTLINE DIMENSIONS 14 13 12 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A DETAIL A 0.43 MAX 0.25 MIN 1.40 MAX A1 BALL CORNER 1 SEATING PLANE 1.00 MAX 0.85 MIN 0.55 0.50 0.45 BALL DIAMETER COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. COPLANARITY 0.12 11-18-2011-A A1 BALL CORNER 12.10 12.00 SQ 11.90 Figure 189. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9737ABBCZ AD9737ABBCZRL AD9737A-EBZ AD9739ABBCZ AD9739ABBCZRL AD9739A-EBZ AD9739A-FMC-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board for Normal, CMTS, and Mix-Mode Evaluation 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board for Normal, CMTS, and Mix-Mode Evaluation Evaluation Board with FMC Connector for Xilinx Based FPGA Development Platforms Z = RoHS Compliant Part. Rev. D | Page 63 of 64 Package Option BC-160-1 BC-160-1 BC-160-1 BC-160-1 AD9737A/AD9739A Data Sheet NOTES ©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09616-0-6/17(D) Rev. D | Page 64 of 64