AD9772AST

a 14-Bit, 150 MSPS TxDAC+™ with 2ⴛ Interpolation Filter AD9772 FEATURES Single 2.7 V to 3.6 V Supply 14-Bit DAC Resolution and Input Data Width 150 MSPS Input Data Rate 63.3 MHz Reconstruction Passband @ 150 MSPS 75 dBc SFDR @ 25 MHz 2ⴛ Interpolation Filter with High or Low Pass Response 73 dB Image Rejection with 0.005 dB Passband Ripple “Zero-Stuffing” Option for Enhanced Direct IF Performance Internal 2ⴛ/4ⴛ Clock Multiplier 205 mW Power Dissipation; 13 mW with Power-Down Mode 48-Lead LQFP Package OBS CLKCOM CLKVDD MOD0 MOD1 The AD9772 is a single supply, oversampling, 14-bit digital-toanalog converter (DAC) optimized for baseband or IF waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2× digital interpolation filter and clock multiplier. The on-chip PLL clock multiplier provides all the necessary clocks for the digital filter and the 14-bit DAC. A flexible differential clock input allows for a singleended or differential clock driver for optimum jitter performance. For baseband applications, the 2× digital interpolation filter provides a low pass response, hence providing up to a three-fold reduction in the complexity of the analog reconstruction filter. It does so by multiplying the input data rate by a factor of two while simultaneously suppressing the original upper inband image by more than 73 dB. For direct IF applications, the 2× digital interpolation filter response can be reconfigured to select the upper inband image (i.e., high pass response) while suppressing the original baseband image. To increase the signal level of the higher IF images and their passband flatness in direct IF applications, the AD9772 also features a “zero stuffing” option in which the data following the 2× interpolation filter is upsampled by a factor of two by inserting midscale data samples. The AD9772 can reconstruct full-scale waveforms with bandwidths as high as 63.3 MHz while operating at an input data rate of 150 MSPS. The 14-bit DAC provides differential current outputs to support differential or single-ended applications. A TxDAC+ is a trademark of Analog Devices, Inc. RESET PLLLOCK DIV0 DIV1 AD9772 PLLCOM CLK+ CLOCK DISTRIBUTION AND MODE SELECT CLK– 13 DATA INPUTS (DB13...DB0) 13/23 EDGETRIGGERED LATCHES FILTER CONTROL MUX CONTROL 23 FIR INTERPOLATION FILTER PLL CLOCK MULTIPLIER 23/43 ZERO STUFF MUX DCOM DVDD ACOM AVDD LPF PLLVDD IOUTA 14-BIT DAC IOUTB +1.2V REFERENCE AND CONTROL AMP SLEEP OLE APPLICATIONS Communication Transmit Channel WCDMA Base Stations, Multicarrier Base Stations, Direct IF Synthesis Instrumentation PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REFIO FSADJ REFLO segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The differential current outputs may be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an appropriate resistive load. TE The on-chip bandgap reference and control amplifier are configured for maximum accuracy and flexibility. The AD9772 can be driven by the on-chip reference or by a variety of external reference voltages. The full-scale current of the AD9772 can be adjusted over a 2 mA to 20 mA range, thus providing additional gain ranging capabilities. The AD9772 is available in a 48-lead LQFP package and specified for operation over the industrial temperature range of –40°C to +85°C. PRODUCT HIGHLIGHTS 1. A flexible, low power 2× interpolation filter supporting reconstruction bandwidths of up to 63.3 MHz can be configured for a low or high pass response with 73 dB of image rejection for traditional baseband or direct IF applications. 2. A “zero-stuffing” option enhances direct IF applications. 3. A low glitch, fast settling 14-bit DAC provides exceptional dynamic range for both baseband and direct IF waveform reconstruction applications. 4. The AD9772 digital interface, consisting of edge-triggered latches and a flexible differential or single-ended clock input, can support input data rates up to 150 MSPS. 5. On-chip PLL clock multiplier generates all of the internal high speed clocks required by the interpolation filter and DAC. REV. 0 6. The current output(s) of the AD9772 can easily be configured for various single-ended or differential circuit topologies. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9772–SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, IOUTFS = 20 mA, unless otherwise DC SPECIFICATIONS noted) Parameter Min RESOLUTION 14 Bits DC ACCURACY1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) Monotonicity (12-Bit) ± 3.5 ± 2.0 Guaranteed Over Specified Temperature Range LSB LSB –0.025 –2 –5 % of FSR % of FSR % of FSR mA V kΩ pF ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance OBS REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (REFLO = 3 V) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift Typ ± 0.5 ± 1.5 20 –1.0 Max Units +0.025 +2 +5 +1.25 200 3 OLE POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD ) Analog Supply Current in SLEEP Mode (IAVDD ) PLLVDD4 Voltage Range PLL Clock Multiplier Supply Current (IPLLVDD) CLKVDD Voltage Range Clock Supply Current (ICLKVDD) DVDD5 Voltage Range Digital Supply Current (IDVDD) Nominal Power Dissipation5 Power Supply Rejection Ratio (PSRR)6 – AVDD Power Supply Rejection Ratio (PSRR)6 – DVDD OPERATING RANGE 1.14 1.20 1 0.1 1.26 V µA 1.25 V MΩ MHz TE 10 0.5 0 ± 50 ± 100 ± 50 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C 2.7 3.0 34 4.3 3.6 37 6 V mA mA 2.7 3.0 4.5 3.6 6 V mA 2.7 3.0 5.5 3.6 7 V mA 2.7 3.0 29 205 –0.6 –0.025 3.6 33 231 +0.6 +0.025 V mA mW % of FSR/V % of FSR/V –40 +85 °C NOTES 1 Measured at IOUTA driving a virtual ground. 2 Nominal full-scale current, I OUTFS , is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 Measured at fDATA = 100 MSPS and f OUT = 1 MHz, PLLVDD = 3.0 V. 5 Measured at fDATA = 50 MSPS and f OUT = 1 MHz. 6 Measured over a 2.7 V to 3.6 V range. Specifications subject to change without notice. –2– REV. 0 AD9772 (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, DVDD = +3 V, PLLVDD = 0 V, IOUTFS = 20 mA, DYNAMIC SPECIFICATIONS Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted) Parameter Min DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.025%) Output Propagation Delay1 (t PD) Output Rise Time (10% to 90%)2 Output Fall Time (10% to 90%)2 Output Noise (IOUTFS = 20 mA) Typ 400 AC LINEARITY–BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 65 MSPS; fOUT = 1.01 MHz fDATA = 65 MSPS; fOUT = 10.01 MHz fDATA = 65 MSPS; fOUT = 26.01 MHz fDATA = 150 MSPS; fOUT = 2.02 MHz fDATA = 150 MSPS; fOUT = 20.02 MHz fDATA = 150 MSPS; fOUT = 52.02 MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS) fDATA = 65 MSPS; fOUT1 = 5.01 MHz; fOUT2 = 6.01 MHz fDATA = 65 MSPS; fOUT1 = 15.01 MHz; fOUT2 = 17.51 MHz fDATA = 65 MSPS; fOUT1 = 24.1 MHz; fOUT2 = 26.2 MHz fDATA = 150 MSPS; fOUT1 = 10.02 MHz; fOUT2 = 12.02 MHz fDATA = 150 MSPS; fOUT1 = 30.02 MHz; fOUT2 = 35.02 MHz fDATA = 150 MSPS; fOUT1 = 48.2 MHz; fOUT2 = 52.4 MHz Total Harmonic Distortion (THD) fDATA = 50 MSPS; fOUT = 1.0 MHz; 0 dBFS fDATA = 65 MSPS; fOUT = 10.01 MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fDATA = 65 MSPS; fOUT = 16.26 MHz; 0 dBFS fDATA = 100 MSPS; fOUT = 25.1 MHz; 0 dBFS Adjacent Channel Power Ratio (ACPR) WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing IF = 16 MHz, fDATA = 65.536 MSPS IF = 32 MHz, fDATA = 131.072 MSPS Four-Tone Intermodulation 15.6 MHz, 15.8 MHz, 16.2 MHz and 16.4 MHz at –12 dBFS fDATA = 65 MSPS, Missing Center OBS OLE AC LINEARITY–IF MODE Four-Tone Intermodulation at IF = 70 MHz 68.1 MHz, 69.3 MHz, 71.2 MHz and 72.0 MHz at –20 dBFS fDATA = 52 MSPS, fDAC = 208 MHz NOTES 1 Propagation delay is delay from CLK input to DAC update. 2 Measured single-ended into 50 Ω load. Specifications subject to change without notice. REV. 0 –3– Max Units 11 17 0.8 0.8 50 MSPS ns ns ns ns pA/√Hz 82 79 74 82 81 73 dBc dBc dBc dBc dBc dBc 82 72 66 80 78 71 dBc dBc dBc dBc dBc dBc –78 –77 dB dB 74 69 dB dB 78 68 dBc dBc 88 dBFS 77 dBFS TE AD9772–SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, IOUTFS = 20 mA, unless otherwise noted) DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current1 Logic “0” Current Input Capacitance Min Typ 2.1 3 0 –10 –10 Max Units 0.9 +10 +10 V V µA µA pF 5 CLOCK INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage 0 0.75 0.5 PLL CLOCK ENABLED—FIGURE 1a Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) 1.0 2.5 1.5 OBS PLL CLOCK DISABLED—FIGURE 1b Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) CLK/PLLLOCK Delay (tOD) 3 2.25 1.5 1.5 ns ns ns OLE 1.0 2.5 1.5 5 NOTES 1 MOD1 and MOD0 have typical input currents of 120 µA while SLEEP has a typical input current of 15 µA. Specifications subject to change without notice. DB0–DB13 tH tS PLLLOCK DB0–DB13 tS CLK+ – CLK– tOD ns ns ns ns TE tH CLK+ – CLK– tLPW tPD IOUTA OR IOUTB V V V tST tLPW tPD 0.025% tST 0.025% IOUTA OR IOUTB 0.025% 0.025% Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled –4– REV. 0 AD9772 DIGITAL FILTER SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted) Parameter Min MAXIMUM INPUT DATA RATE (fDATA ) 150 DIGITAL FILTER CHARACTERISTICS Passband Width1: 0.005 dB Passband Width: 0.01 dB Passband Width: 0.1 dB Passband Width: –3 dB Typ Max Units MSPS 0.401 0.404 0.422 0.479 fOUT/fDATA fOUT/fDATA fOUT/fDATA fOUT/fDATA 73 dB GROUP DELAY 21 Input Clocks IMPULSE RESPONSE DURATION –40 dB –60 dB 36 42 Input Clocks Input Clocks LINEAR PHASE (FIR IMPLEMENTATION) STOPBAND REJECTION 0.606 fCLOCK to 1.394 fCLOCK OBS 2 OLE NOTES 1 Excludes sin(x)/x characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. Specifications subject to change without notice. 0 –20 OUTPUT – dB –40 –60 –80 –100 –120 –140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FREQUENCY – DC TO fDATA 0.8 0.9 1 Figure 2a. FIR Filter Frequency Response—Baseband Mode 1 NORMALIZED OUTPUT 0.8 0.6 0.4 0.2 0 –0.2 –0.4 0 5 10 15 20 25 30 TIME – Samples 35 40 45 Figure 2b. FIR Filter Impulse Response—Baseband Mode REV. 0 TE Table I. Integer Filter Coefficients for Interpolation Filter (43-Tap Half-Band FIR Filter) –5– Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) 10 0 –31 0 69 0 –138 0 248 0 –419 0 678 0 –1083 0 1776 0 –3282 0 10364 16384 AD9772 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Units AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM REFIO, REFLO, FSADJ, SLEEP IOUTA, IOUTB DB0–DB13, MOD0, MOD1 CLK+, CLK–, PLLLOCK DIV0, DIV1, RESET LPF Junction Temperature Storage Temperature Lead Temperature (10 sec) ACOM, DCOM, CLKCOM, PLLCOM AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM ACOM ACOM DCOM CLKCOM CLKCOM PLLCOM –0.3 –4.0 –0.3 –0.3 –1.0 –0.3 –0.3 –0.3 –0.3 +4.0 +4.0 +0.3 AVDD + 0.3 AVDD + 0.3 DVDD + 0.3 CLKVDD + 0.3 CLKVDD + 0.3 PLLVDD + 0.3 +150 +150 +300 V V V V V V V V V °C °C °C –65 OBS *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. OLE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9772 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD9772AST AD9772EB Temperature Range Package Description Package Option* –40°C to +85°C 48-Lead LQFP ST-48 Evaluation Board WARNING! TE ESD SENSITIVE DEVICE *ST = Thin Plastic Quad Flatpack. THERMAL CHARACTERISTIC Thermal Resistance 48-Lead LQFP θJA = 91°C/W θJC = 28°C/W –6– REV. 0 AD9772 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1, 2, 19, 20 3 4–15 16 17 18 DCOM DB13 DB12–DB1 DB0 MOD0 MOD1 23, 24 21, 22, 47, 48 25 NC DVDD PLLLOCK 26 RESET 27, 28 29 30 31 32 33 34 DIV1, DIV0 CLK+ CLK– CLKCOM CLKVDD PLLCOM PLLVDD 35 36 37, 41, 44 38 LPF SLEEP ACOM REFLO 39 REFIO 40 42 43 45, 46 FSADJ IOUTB IOUTA AVDD Digital Common. Most Significant Data Bit (MSB). Data Bits 1–12. Least Significant Data Bit (LSB). Invokes digital high-pass filter response (i.e., “half-wave” digital mixing mode). Active High. Invokes “zero-stuffing” mode. Active High. Note, “quarter-wave” digital mixing occurs with MOD0 also set HIGH. No Connect, Leave Open. Digital Supply Voltage (+2.7 V to +3.6 V). Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is locked to input clock. Provides 1× clock output when PLL clock multiplier is disabled. Maximum fanout is one (i.e.,