AD9988BBPZ-4D4AC

Data Sheet AD9988 4T4R Direct RF Receiver and Transmitter FEATURES APPLICATIONS Flexible, reconfigurable radio common platform design ► Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) ► RF DAC/RF ADC RF frequency range up to 7.5 GHz ► On-chip PLL with multichip synchronization ► External RF clock input option ► Versatile digital features ► Selectable interpolation and decimation filters ► Configurable DDCs and DUCs ► 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) ► 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) ► FDUCs and FDDCs are fully bypassable ► 2 independent 48-bit NCOs per DUC or DDC ► Programmable 192-tap PFIR filter for receive equalization ► Supports 4 different profile settings loaded via GPIO ► Receive AGC support ► Fast detect with low latency for fast AGC control ► Signal monitor for slow AGC control ► Dedicated AGC support pins ► Transmit DPD support ► Programmable delay and gain per transmit data path ► Coarse DDC delay adjust for DPD observation path ► Supports real or complex digital data (8-, 12-, or 16-bit) ► ► ► ► ► ► ► ► Wireless communications infrastructure W-CDMA, LTE, LTE-A, massive multiple input multiple output (MIMO) Point to point microwave, E-band, and 5G mmWave Broadband communications systems DOCSIS 3.0+ cable modem termination system (CMTS) Communication test and measurement systems GENERAL DESCRIPTION The AD9988 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The device supports four transmitter channels and four receiver channels with a 4T4R configuration. This product is well suited for four-antenna TDD transmitter applications, where the receiver path can be shared between receiver and observation modes. The GPIO pins can be configured and toggled to support different user modes, while phase coherency is maintained. The maximum radio channel bandwidth supported is 1.2 GHz in a 4T4R configuration and a sample resolution of 16 bits. The AD9988 features a 16-lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port that allows up to eight lanes per transmit/receive link, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct to RF radio applications. Auxiliary features ► ADC clock driver with selectable divide ratios ► Power amplifier downstream protection circuitry ► On-chip temperature monitoring unit ► Programmable GPIO pins support toggling between modes ► TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps ► 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) ► Supports Subclass 1 ► Supports multidevice synchronization ► 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch ► Rev. A DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD9988 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 General Description...............................................1 Functional Block Diagram......................................3 Specifications........................................................ 4 Recommended Operating Conditions................ 4 Power Consumption........................................... 4 DAC DC Specifications...................................... 5 ADC DC Specifications...................................... 6 Clock Inputs and Outputs................................... 7 Clock Input and Phase-Locked Loop (PLL) Frequency Specifications................................. 7 DAC Sample Rate Specifications.......................7 ADC Sample Rate Specifications.......................9 Input Data Rates Specifications....................... 10 NCO Frequency Specifications........................ 11 JESD204B and JESD204C Interface Electrical and Speed Specifications............... 11 CMOS Pin Specifications................................. 14 DAC AC Specifications.....................................14 ADC AC Specifications.....................................16 Timing Specifications....................................... 18 Absolute Maximum Ratings.................................20 Thermal Resistance......................................... 20 ESD Caution.....................................................20 Pin Configuration and Function Descriptions...... 21 Typical Performance Characteristics................... 26 DAC..................................................................26 ADC..................................................................31 Theory of Operation.............................................38 Applications Information...................................... 39 Outline Dimensions............................................. 40 Ordering Guide.................................................40 Evaluation Boards............................................ 40 REVISION HISTORY 7/2021—Rev. 0 to Rev. A Changes to Table 20 ..................................................................................................................................... 20 3/2021—Revision 0: Initial Version analog.com Rev. A | 2 of 40 Data Sheet AD9988 FUNCTIONAL BLOCK DIAGRAM Figure 1. analog.com Rev. A | 3 of 40 Data Sheet AD9988 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Successful DAC calibration is required during the device initialization phase that occurs shortly after power-up to ensure long-term reliability of the DAC core circuitry. Refer to UG-1578, the device user guide, for more information on device initialization. Table 1. Parameter Min OPERATING JUNCTION TEMPERATURE (TJ) ANALOG SUPPLY VOLTAGE RANGE AVDD2, BVDD2, RVDD2 AVDD1, AVDD1_ADC, CLKVDD1, FVDD1, VDD1_NVG1 DIGITAL SUPPLY VOLTAGE RANGE DVDD1, DVDD1_RT, DCLKVDD1, DAVDD1 DVDD1P8 SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGE RANGE SVDD2_PLL SVDD1, SVDD1_PLL −40 Typ Max Unit +120 °C 1.9 0.95 2.0 1.0 2.1 1.05 V V 0.95 1.7 1.0 1.8 1.05 2.1 V V 1.9 0.95 2.0 1.0 2.1 1.05 V V POWER CONSUMPTION Typical at nominal supplies and maximum at 5% supplies. For the minimum and maximum values, TJ varies between −40°C and +120°C. For the typical values, TA = 25°C, which corresponds to TJ = 80°C, unless otherwise noted. DAC datapath with a complex I/Q data rate frequency (fIQ_DATA) = 1500 MSPS, interpolation of 8×, and DAC frequency (fDAC) of 12 GSPS. JRx mode of 15C (L = 8, M = 8, F = 2, S = 1, K = 128, E = 1, N = 16, NP = 16). ADC datapath with a complex fIQ_DATA =1500 MSPS, decimation of 2×, and fADC of 3 GSPS. JTx mode of 16C (L = 8, M = 8, F = 2, S = 1, K = 128, E = 1, N = 16, NP = 16). Note that the AD9988 does not support the option to bypass the CDUC in the transmit data path and the CDDC in the receive data path. See the UG-1578 user guide for further information on the JESD204B and JESD204C mode configurations, and a detailed description of the settings referenced throughout this data sheet. A table showing other operational modes and the corresponding typical and maximum power consumption numbers is included. Table 2. Parameter Test Conditions/Comments CURRENTS AVDD2 (IAVDD2) BVDD2 (IBVDD2) + RVDD2 (IRVDD2) AVDD2_PLL (IAVDD2__PLL) + SVDD2_PLL (ISVDD2__PLL) Power Dissipation for 2 V Supplies PLLCLKVDD1 (IPLLCLKVDD1) AVDD1 (IAVDD1) + DCLKVDD1 (IDCLKVDD1) AVDD1_ADC (IAVDD1_ADC) CLKVDD1 (ICLKVDD1) FVDD1 (IFVDD1) VDD1_NVG (IVDD1_NVG) DAVDD1 (IDAVDD1) DVDD1 (IDVDD1) DVDD1_RT (IDVDD1_RT) SVDD1 (ISVDD1) + SVDD1_PLL (ISVDD1_PLL) Power Dissipation for 1 V Supplies 2.0 V supply 2.0 V supply 2.0 V supply 2.0 V supply total power dissipation 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply 1.0 V supply total power dissipation analog.com Min Typ Max Unit 190 295 45 1.06 15 1000 1620 60 45 280 1590 2780 565 1920 9.88 205 350 55 1.22 25 1185 1900 110 65 345 1835 3805 690 2570 12.53 mA mA mA W mA mA mA mA mA mA mA mA mA mA W Rev. A | 4 of 40 Data Sheet AD9988 SPECIFICATIONS Table 2. Parameter DVDD1P8 (IDVDD1P8) Total Power Dissipation Test Conditions/Comments Min 1.8 V supply Total power dissipation of 2 V and 1 V supplies Typ Max Unit 7 10.95 10 13.77 mA W DAC DC SPECIFICATIONS Nominal supplies with DAC output full-scale current (IOUTFS) = 26 mA, unless otherwise noted. ADC setup in 4 GSPS, full BW mode (all digital downconverters bypassed). For the minimum and maximum values, TJ = −40°C to +120°C, and for the typical values, TA = 25°C, which corresponds to TJ = 80°C, unless otherwise noted. Table 3. DAC DC Specifications Parameter DAC RESOLUTION DAC ACCURACY Gain Error Gain Matching Integral Nonlinearity (INL) Differential Nonlinearity (DNL) DAC ANALOG OUTPUTS Full-Scale Output Current Range AC Coupling DC Coupling DC Coupling Full-Scale Sinewave Output Power with AC Coupling2 IOUTFS = 26 mA IOUTFS = 40 mA Common-Mode Output Voltage (VCMOUT) AC Coupling DC Coupling Test Conditions/Comments Min Typ 16 Shuffling disabled Shuffling disabled DACxP and DACxN AC coupling, setting resistance (RSET) = 5 kΩ Output common-mode voltage (VCM) = 0 V 50 Ω shunt to a negative supply, forcing VCM = 0 V 50 Ω shunt to GND, forcing VCM = 0.3 V Ideal 2:1 balun interface to 50 Ω Bias each output to GND across a shunt inductor Bias each output to a negative voltage rail across a 25 Ω to 200 Ω resistor, selected such that VCMOUT = 0 V; VCMOUT = 0.3 V is with a 25 Ω resistor to GND and IFSC = 20 mA Differential Resistance 1.5 0.7 8.0 3.5 6.43 6.43 6.43 Unit Bit 26.5 3.3 7 0 0 0 100 1 For dc-coupled applications, the maximum full-scale output current is limited by the maximum VCMOUT specification. 2 The actual measured full-scale power is frequency dependent due to DAC sinc response, impedance mismatch loss, and balun insertion loss. analog.com Max %FSR %FSR LSB LSB 37.75 37.75 201 mA mA mA 0.3 dBm dBm V V V Ω Rev. A | 5 of 40 Data Sheet AD9988 SPECIFICATIONS ADC DC SPECIFICATIONS Nominal supplies with DAC output full-scale current (IOUTFS) = 26 mA, unless otherwise noted. ADC setup in 4 GSPS, full BW mode (all digital downconverters bypassed). For the minimum and maximum values, TJ = −40°C to +120°C, and for the typical values, TA = 25°C, which corresponds to TJ = 80°C, unless otherwise noted. Table 4. ADC DC Specifications Parameter ADC RESOLUTION ADC ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching DNL INL ADC ANALOG INPUTS Differential Input Voltage Full-Scale Sine Wave Input Power Common-Mode Input Voltage (VCMIN) Differential Input Impedance Return Loss analog.com Test Conditions/Comments Min Typ 12 Max Unit Bit Guaranteed −0.20 +0.05 −0.71 +1.2 ± 1.9 ± 0.5 %FSR %FSR %FSR %FSR LSB LSB 1.4 3.9 V p-p dBm 1 100//0.4 −4.3 −3.6 −2.9 V Ω//pF dB dB dB ADCxP and ADCxN Input power level resulting 0 dBFS tone level on fast Fourier transform (FFT) AC-coupled, equal to voltage at VCMx for ADCx input 1× fDAC = 12 GHz, main interpolation rate must be > 1× channel decimation rate must be > 1× fADC = 4 GHz, main decimation rate must be > 1× Typ −750 −6 −750 −2 Maximum FDUC NCO clock rate × 0.81 Maximum FDDC NCO clock rate × 0.8142 1 The 0.8 factor is because the total complex pass-band of the first interpolation filter is 80% of the filter input data rate. 2 The 0.814 factor is because the total complex pass-band of the decimation filter is 81.4% of the filter output data rate. Max Unit 1.5 12 1.5 4 GHz GHz GHz GHz +750 +6 +750 +2 MHz GHz MHz GHz 1200 1221 MHz MHz JESD204B AND JESD204C INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS Nominal supplies. For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, and for the typical values, TA = 25°C, which corresponds to TJ = 80°C, unless otherwise noted. Table 11. Serial Interface Rate Specifications Parameter Test Conditions/Comments Min JESD204B SERIAL INTERFACE RATE Unit Interval JESD204C SERIAL INTERFACE RATE Unit Interval Serial lane rate (bit repeat option disabled) 1.0 64.5 6.0 40.4 Serial lane rate (bit repeat option disabled) Typ Max Unit 15.5 1000.0 24.75 166.67 Gbps ps Gbps ps Max Unit Table 12. JESD204 Receiver (JRx) Electrical Specifications Parameter Test Conditions/Comments JESD204x DATA INPUTS Standards Compliance Differential Voltage, RVDIFF Differential Impedance, ZRDIFF Termination Voltage, VTT SYNCxOUTB± OUTPUTS1 Output Differential Voltage, VOD Output Offset Voltage, VOS SYNCxOUTB+ OUTPUT SERDINx±, where x = 0 to 7 1 Min Typ JESD204B and JESD204C 800 98 0.97 At dc AC-coupled Where x = 0 or 1 Driving 100 Ω differential load mV p-p Ω V 400 DVDD1P8/2 + 0.2 Refer to CMOS Pin Specifications CMOS output option mV V IEEE 1596.3 standard LVDS compatible. Table 13. JESD204 Transmitter (JTx) Electrical Specifications Parameter Test Conditions/Comments JESD204x DATA OUTPUTS SERDOUTx±, where x = 0 to 7 analog.com Min Typ Max Unit Rev. A | 11 of 40 Data Sheet AD9988 SPECIFICATIONS Table 13. JESD204 Transmitter (JTx) Electrical Specifications Parameter Standards Compliance Differential Output Voltage Differential Termination Impedance Rise Time, tR Fall Time, tF SYNCxINB± INPUT1 Logic Compliance Differential Input Voltage Input Common-Mode Voltage RIN (Differential) Input Capacitance (Differential) SYNCxINB+ INPUT 1 Test Conditions/Comments Min Typ Max 80 JESD204B and JESD204C 675 108 18 18 120 Maximum strength 20% to 80% into 100 Ω load 20% to 80% into 100 Ω load Where x = 0 or 1 240 DC-coupled CMOS input option LVDS 0.7 1900 0.675 2 18 1 Refer to CMOS Pin Specifications Unit mV p-p Ω ps ps mV p-p V kΩ pF IEEE 1596.3 standard LVDS compatible. analog.com Rev. A | 12 of 40 Data Sheet AD9988 SPECIFICATIONS Table 14. SYSREF Electrical Specifications Parameter SYSREF+ AND SYSREF- INPUTS Logic Compliance Differential Input Voltage Input Common-Mode Voltage Range Input Reference, RIN (Differential) Input Capacitance (Differential) 1 Test Conditions/Comments Min Typ Max Unit 1.9 2 V p-p V Ω pF LVDS/LVPECL1 DC-coupled 0.7 0.675 100 1 LVDS means low voltage differential signaling and LVPECL means low voltage positive/pseudo emitter-coupled logic. analog.com Rev. A | 13 of 40 Data Sheet AD9988 SPECIFICATIONS CMOS PIN SPECIFICATIONS For the minimum and maximum values, TJ = −40°C to +120°C, 1.7 V ≤ DVDD1P8 ≤ 2.1 V, other supplies nominal, unless otherwise noted. Table 15. Parameter Symbol INPUTS Min Typ Max Unit 0.3 × DVDD1P8 V V kΩ SDIO, SCLK, CSB, RESETB, RXEN0, RXEN1, TXEN0, TXEN1, SYNC0INB±, SYNC1INB±, and GPIOx Logic 1 Voltage Logic 0 Voltage Input Resistance OUTPUTS VIH VIL Logic 1 Voltage Logic 0 Voltage INTERRUPT OUTPUTS VOH VOL Logic 1 Voltage Logic 0 Voltage Test Conditions/Comments 0.70 × DVDD1P8 40 SDIO, SDO, GPIOx, ADCx_FDx, ADCx_SMONx, SYNC0OUTB±, and SYNC1OUTB±, 4 mA load DVDD1P8 − 0.45 0.45 V V 0.48 V V IRQB_0 and IRQB_1, pull-up resistor of 5 kΩ to DVDD1P8 VOH VOL 1.35 DAC AC SPECIFICATIONS Nominal supplies with TA = 25°C. Specifications represent the average of all four DAC channels with the DAC IOUTFS = 26 mA, unless otherwise noted. Table 16. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) Single-Tone, fDAC = 12 GSPS Output Frequency (fOUT) = 70 MHz fOUT = 100 MHz fOUT = 500 MHz fOUT = 900 MHz fOUT = 1900 MHz fOUT = 2600 MHz fOUT = 3700 MHz fOUT = 4500 MHz Single-Tone, fDAC = 9 GSPS fOUT = 100 MHz fOUT = 500 MHz fOUT = 900 MHz fOUT = 1900 MHz fOUT = 2600 MHz fOUT = 3700 MHz Single-Tone, fDAC = 6 GSPS fOUT = 100 MHz fOUT = 500 MHz fOUT = 900 MHz fOUT = 1900 MHz ADJACENT CHANNEL LEAKAGE RATIO Single Carrier 20 MHz LTE Downlink Test Vector fDAC = 12 GSPS analog.com Test Conditions/Comments Min Typ Max Unit 63 80 77 76 77 79 75 69 68 dBc dBc dBc dBc dBc dBc dBc dBc 78 78 77 80 80 72 dBc dBc dBc dBc dBc dBc 84 81 82 81 dBc dBc dBc dBc 77 76 dBc dBc −7 dBFS digital back off, shuffle enabled, 15C mode 61 −7 dBFS digital back off, shuffle enabled, 15C mode −7 dBFS digital back off, shuffle enabled, 15C mode −1 dBFS digital back off, 256 QAM fOUT = 1840 MHz fOUT = 2650 MHz Rev. A | 14 of 40 Data Sheet AD9988 SPECIFICATIONS Table 16. Parameter fDAC = 9 GSPS fDAC = 6 GSPS THIRD-ORDER INTERMODULATION DISTORTION (IMD3) fDAC = 12 GSPS fDAC = 9 GSPS fDAC = 6 GSPS NOISE SPECTRAL DENSITY (NSD) Test Conditions/Comments fOUT = 3500 MHz fOUT = 1900 MHz fOUT = 2650 MHz fOUT = 750 MHz fOUT = 1840 MHz Two tone test, 1 MHz spacing, 0 dBFS digital back off, −6 dBFS per tone fOUT = 1900 MHz fOUT = 2600 MHz fOUT = 3700 MHz fOUT = 1900 MHz fOUT = 2600 MHz fOUT = 900 MHz fOUT = 1900 MHz 0 dBFS, NSD measurement taken at 10% away from fOUT, shuffle off Single-Tone, fDAC = 12 GSPS fOUT = 150 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz fOUT = 4500 MHz Single-Tone, fDAC = 9 GSPS fOUT = 150 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz Single-Tone, fDAC = 6 GSPS fOUT = 150 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz SINGLE SIDEBAND PHASE NOISE OFFSET (PLL DISABLED) Direct device clock input at 6 dBm fOUT = 3.6 GHz, fDAC = 12 GSPS, CLKINx Frequency (fCLKIN) = 12 GHz Rohde & Schwarz SMA100B B711 option 1 kHz 10 kHz 100 kHz 600 kHz 1.2 MHz 1.8 MHz 6 MHz SINGLE SIDEBAND PHASE NOISE OFFSET (PLL ENABLED) Loop filter component values include C1 = 22 nF, R1 = 226 Ω, C2 = 2.2 nF, analog.com Min Typ Max 73 77 77 79 77 -69 -72 -72 -79 -76 -79 -90 Unit dBc dBc dBc dBc dBc -62 dBc dBc dBc dBc dBc dBc dBc −168 −167 −165 −162 −160 −155 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −168 −166 −164 −160 −158 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −168 −165 −163 −159 −157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −118 −129 −137 −144 −148 −149 −153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | 15 of 40 Data Sheet AD9988 SPECIFICATIONS Table 16. Parameter Test Conditions/Comments Min Typ Max Unit C3 = 33 nF, and phase detector frequency (PFD) = 500 MHz fOUT = 1.8 GHz, fDAC = 12 GSPS, fCLKIN = 0.5 GHz 1 kHz 10 kHz 100 kHz 600 kHz 1.2 MHz 1.8 MHz 6 MHz −106 −113 −120 −127 −134 −138 −150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ADC AC SPECIFICATIONS Nominal supplies with TA = 25°C. Input amplitude (AIN) = −1 dBFS, full bandwidth (no decimation) mode. For the minimum and maximum values, TJ = −40°C to +120°C. Specifications represent average of four ADC channels with DACs powered on. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Table 17. 3 GSPS Parameter NOISE DENSITY1 NOISE FIGURE2 CODE ERROR RATE (CER) SIGNAL-TO-NOISE RATIO (SNR) fIN = 450 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2700 MHz fIN = 3600 MHz fIN = 4500 MHz fIN = 5400 MHz fIN = 6300 MHz fIN = 7200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 450 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2700 MHz fIN = 3600 MHz fIN = 4500 MHz fIN = 5400 MHz fIN = 6300 MHz fIN = 7200 MHz SECOND-ORDER HARMONIC DISTORTION (HD2) fIN = 450 MHz fIN = 900 MHz fIN = 1800 MHz fIN = 2700 MHz fIN = 3600 MHz fIN = 4500 MHz analog.com Min Typ 4 GSPS Max Min Typ Max Unit −150.3 28 5 kΩ pull-up resistor to DVDD1P8 to prevent these pins from floating when unused. General-Purpose Input or Output Pins. These pins control auxiliary functions related to the Tx datapaths. Rev. A | 23 of 40 Data Sheet AD9988 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 21. Pin Function Descriptions Pin No. Mnemonic Type Description GPIO6 to GPIO10 Input/output General-Purpose Input or Output Pins. These pins control auxiliary functions related to the Rx datapaths and ADCs. SERDIN0+, SERDIN0− SERDIN1+, SERDIN1− SERDIN2+, SERDIN2− SERDIN3+, SERDIN3− SERDIN4+, SERDIN4− SERDIN5+, SERDIN5− SERDIN6+, SERDIN6− SERDIN7+, SERDIN7− SYNC0OUTB+, SYNC0OUTB− Input Input Input Input Input Input Input Input Output U12, V12 SYNC1OUTB+, SYNC1OUTB− Output A15, A14 Output Output JTx Lane 1 Outputs, Data True/Complement. Output JTx Lane 2 Outputs, Data True/Complement. Output JTx Lane 3 Outputs, Data True/Complement. Output JTx Lane 4 Outputs, Data True/Complement. Output JTx Lane 5 Outputs, Data True/Complement. Output JTx Lane 6 Outputs, Data True/Complement. Output JTx Lane 7 Outputs, Data True/Complement. B13, A13 SERDOUT0+, SERDOUT0− SERDOUT1+, SERDOUT1− SERDOUT2+, SERDOUT2− SERDOUT3+, SERDOUT3− SERDOUT4+, SERDOUT4− SERDOUT5+, SERDOUT5− SERDOUT6+, SERDOUT6− SERDOUT7+, SERDOUT7− SYNC0INB+, SYNC0INB− JRx Lane 0 Inputs, Data True/Complement. JRx Lane 1 Inputs, Data True/Complement. JRx Lane 2 Inputs, Data True/Complement. JRx Lane 3 Inputs, Data True/Complement. JRx Lane 4 Inputs, Data True/Complement. JRx Lane 5 Inputs, Data True/Complement. JRx Lane 6 Inputs, Data True/Complement. JRx Lane 7 Inputs, Data True/Complement. JRx Link 0 Synchronization Outputs for JESD204B interface. These pins are LVDS or CMOS configurable. These pins can also provide differential 100 Ω output impedance in LVDS mode. JRx Link 1 Synchronization Outputs for JESD204B Interface or CMOS Input to Control the Transmit Fast Frequency Hopping (FFH) Feature. For JRx link synchronization , these pins can be configured as LVDS or CMOS outputs and can provide differential 100 Ω output impedance in LVDS mode. JTx Lane 0 Outputs, Data True/Complement. Input B12, A12 SYNC1INB+, SYNC1INB− Input T4, T3 SYSREFP, SYSREFN JTx Link 0 Synchronization Inputs for JESD204B interface. These pins are LVDS or CMOS configurable and have selectable internal 100 Ω input impedance for LVDS operation. JTx Link 1 Synchronization Inputs for JESD204B interface or CMOS Inputs for Receive FFH via GPIOx pins. These pins are LVDS or CMOS configurable and have selectable internal 100 Ω input impedance for LVDS operation. Active High JESD204B/C System Reference Inputs. These pins are configurable for differential current mode logic (CML), PECL, and LVDS with internal 100 Ω termination or singleended CMOS. N13, M13, L13, K13, T12 JESD204B- or JESD204C-Compatible SERDES Data Lanes and Control Signals2 L18, L17 N18, N17 R18, R17 U18, U17 M15, M14 V15, V14 T15, T14 P15, P14 U13, V13 C15, C14 E15, E14 G15, G14 H18, H17 F18, F17 D18, D17 B18, B17 analog.com Input Rev. A | 24 of 40 Data Sheet AD9988 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 21. Pin Function Descriptions Pin No. Mnemonic Type Description No Connects and Do Not Connects J6, K6 H4, L4, L15, L16 NC DNC NC DNC No Connect. These pins can be left open or connected. Do Not Connect. The pins must be kept open. 1 CMOS inputs do not have pull-up or pull-down resistors. 2 SERDINx± and SERDOUTx± include 100 Ω internal termination resistors. analog.com Rev. A | 25 of 40 Data Sheet AD9988 TYPICAL PERFORMANCE CHARACTERISTICS DAC The data curves represent the average performance across all outputs with harmonics and spurs falling in the first Nyquist zone (