ADA4254ARUZ

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier ADA4254 Data Sheet SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Universal process control front ends Data acquisition systems Test and measurement systems GENERAL DESCRIPTION The ADA4254 is a zero drift, high voltage, low power programmable gain instrumentation amplifier (PGIA) designed for process control and industrial applications. The ADA4254 features 12 binary weighted gains ranging from 1/16 V/V to 128 V/V and three scaling gain options of 1 V/V, 1.25 V/V, and 1.375 V/V, resulting in 36 possible gain settings. The power consumption of the ADA4254 is a mere 22 mW, making the device an excellent choice for industrial systems that demand precision, robustness, and low power. The zero drift amplifier topology of the ADA4254 self calibrates dc errors and low frequency 1/f noise, achieving excellent dc precision over the entire specified temperature range. This high level of precision maximizes dynamic range and greatly reduces calibration requirements in many applications. Rev. B VDDH IOUT_HV EXCITATION CURRENTS ADA4254 AVDD IOUT_LV +IN1 –IN1 +IN2 –IN2 + – ROUT – EMI FILTER –OUT + VOCM RIN + – +OUT – + ROUT AVSS DIGITAL CONTROL 7 × GPIO SPI INTERFACE DVDD DVSS 15741-001 Optimized for ADC synchronization Low power: 22 mW (±12 V supplies) 12 binary gain steps from 1/16 V/V to 128 V/V 3 scaling gains: 1 V/V, 1.25 V/V, and 1.375 V/V ±60 V protected input multiplexer Excellent dc precision Low input offset voltage: ±14 μV maximum Low input offset voltage drift: ±0.08 μV/°C maximum Gain calibration via ROM Low gain drift: ±1 ppm/°C maximum High CMRR: 116 dB minimum, G = 1 V/V Low input bias current: ±1.5 nA maximum High input impedance Integrated input EMI filtering Wide input supply range: ±5 V to ±28 V Dedicated output amplifier supplies 7 GPIO ports with special functions Sequential chip select mode External multiplexer control Excitation current sources SPI port with checksum (CRC) support Internal fault detection Wire break test currents On-chip test multiplexer 28-lead, 5 mm × 5 mm LFCSP, 24-lead TSSOP Specified temperature range: −40°C to +105°C ±60V OVERVOLTAGE PROTECTED MUX FEATURES VSSH Figure 1. The input multiplexer provides ±60 V protection to the high impedance inputs of the amplifier, while providing the capability to switch between two input sources. In addition, integrated electromagnetic interference (EMI) filters block harsh RF noise from the sensitive inputs of the amplifier. Various safety features on the ADA4254 detect both internal and external faults. The serial port interface (SPI) supports cyclical redundancy check (CRC) error detection to ensure robust communication. These safety features ease system safety integrity level (SIL) certification. Seven general-purpose input/output (GPIO) pins, which can be configured to provide various special functions, are included in the ADA4254. An excitation current source output is available to bias sensors such as resistance temperature detectors (RTDs). The ADA4254 is specified over the −40°C to +105°C temperature range and is offered in a compact 5 mm × 5 mm, 28-lead LFCSP and a 24-lead TSSOP. COMPANION PRODUCTS ADCs: AD4007, AD7768, AD7175-2 ADC Drivers: ADA4945-1, LTC6363 Voltage References: ADR4550, ADR3450, LT6656 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4254 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  SPI Read/Write Error Detection .............................................. 35  Applications ...................................................................................... 1  SPI Command Length Error Detection .................................. 35  General Description ......................................................................... 1  Applications Information ............................................................. 36  Simplified Functional Block Diagram ........................................... 1  Input and Output Offset Voltage and Noise .......................... 36  Companion Products ....................................................................... 1  ADC Clock Synchronization .................................................... 36  Revision History ............................................................................... 3  Specifications .................................................................................... 4  Programmable Logic Controller (PLC) Voltage/Current Input ............................................................................................. 37  Timing Specifications .................................................................. 8  3-Wire RTD With Current Excitation .................................... 38  Absolute Maximum Ratings ........................................................... 9  High Rail Current Sensing ........................................................ 39  Thermal Resistance ...................................................................... 9  Register Summary .......................................................................... 40  ESD Caution.................................................................................. 9  Register Details ............................................................................... 42  Pin Configurations and Function Descriptions ......................... 10  GAIN_MUX Register Details ................................................... 42  Typical Performance Characteristics ........................................... 11  Software Reset Register (Reset) Details ................................... 43  Theory of Operation ...................................................................... 23  Clock Synchronization Configuration Register (SYNC_CFG) Details .......................................................................................... 44  Programmable Gain Instrumentation Amplifier .................. 23  Input Multiplexer ....................................................................... 24  EMI Reduction and Internal EMI Filter ................................. 24  Input Amplifier........................................................................... 25  Output Amplifier........................................................................ 25  Power Supplies ............................................................................ 26  ESD Map ...................................................................................... 26  Output Ripple Calibration Configuration .............................. 27  General-Purpose Inputs/Outputs (GPIOs) ............................ 27  Excitation Currents .................................................................... 27  External Clock Synchronization .............................................. 28  Sequential Chip Select (SCS) .................................................... 28  Gain Error Calibration .............................................................. 30  Digital Error Register (DIGITAL_ERR) Details.................... 45  Analog Error Register (ANALOG_ERR) Details .................. 46  GPIO Data Register (GPIO_DATA) Details ......................... 47  Internal Mux Control Register (INPUT_MUX) Details ...... 48  Wire Break Detect Register (WB_DETECT) Details ............ 49  GPIO Direction Register (GPIO_DIR) Details ..................... 50  Sequential Chip Select Register (SCS) Details........................ 50  Analog Error Mask Register (ANALOG_ERR_DIS) Details ... 51  Digital Error Mask Register (DIGITAL_ERR_DIS) Details ..... 52  Special Function Configuration Register (SF_CFG) Details .... 53  Error Configuration Register ................................................... 54  Test Multiplexer Register (TEST_MUX) Details .................. 55  Wire Break Detection ................................................................ 31  Excitation Current Configuration Register (EX_CURRENT_CFG) Details ................................................ 56  Test Multiplexer ......................................................................... 32  Gain Calibration Registers (GAIN_CALx) Details ............... 57  External Mux Control................................................................ 32  Trigger Calibration Register (TRIG_CAL) Details ............... 58  Digital Interface .............................................................................. 33  Master Clock Count Register (M_CLK_CNT) Details......... 58  SPI Interface ................................................................................ 33  Accessing the ADA4254 Register Map ................................... 33  DIE Revision Identification Register (DIE_REV_ID) Details ....................................................................................................... 58  Checksum Protection ................................................................ 33  Device Identification Registers (PART_ID) Details ............. 58  CRC Calculation ......................................................................... 35  Outline Dimensions ....................................................................... 59  Memory Map Checksum Protection ....................................... 35  Ordering Guide .......................................................................... 59  Read-Only Memory (ROM) Checksum Protection .............. 35  Rev. B | Page 2 of 59 Data Sheet ADA4254 REVISION HISTORY 6/2020—Rev. A to Rev. B Changes to Figure 10 ............................................................................ 11 Changes to Figure 23 ............................................................................ 13 Changes to Figure 37 ............................................................................ 16 Change to Input Multiplexer Section............................................... 24 Changes to External Clock Synchronization Section ....................... 28 Change to Wire Break Detection Section ........................................... 31 Changes to Figure 100 ............................................................................ 36 Change to 3-Wire RTD with Current Excitation Section ............... 38 Change to Table 21.................................................................................. 49 Change to Bits[7:0], DIE_REV_ID[7:0]—Die Revision Identification Number Section .......................................................... 58 11/2019—Rev. 0 to Rev. A Changes to Features Section and General Description Section ....... 1 Changes to Static Power Dissipation Parameter, Table 1 ........... 7 Changes to 3-Wire RTD With Current Excitation Section ...... 38 11/2019—Revision 0: Initial Version Rev. B | Page 3 of 59 ADA4254 Data Sheet SPECIFICATIONS TA = 25°C, VDDH = 28 V, VSSH = −28 V, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, DVSS = 0 V, VOCM = AVDD/2, and no load, unless otherwise noted. Table 1. Parameter OFFSET VOLTAGE Differential Offset Voltage Input Offset Voltage (VOSI) Output Offset Voltage (VOSO) Differential Offset Voltage Drift VOSI/T VOSO/T Differential Offset Voltage vs. VDDH and VSSH (Power Supply Rejection Ratio (PSRR)), RTI Gain (G) = 1/16 V/V G = 1 V/V G = 128 V/V Differential Offset Voltage vs. AVDD (PSRR), RTI G = 1/16 V/V G = 1 V/V G = 128 V/V Differential Offset vs. External Clock Frequency, RTI G = 1/16 V/V G = 1 V/V G = 128 V/V COMMON–MODE REJECTION RATIO (CMRR), RTI CMRR to 60 Hz G = 1/16 V/V G = 1 V/V G = 128 V/V G = 1/16 G=1 G = 128 Test Conditions/Comments Total offset, referred to input (RTI) = VOSI + VOSO Gain Min Typ Max Unit ±3 ±40 ±14 ±125 μV μV ±0.03 ±0.98 ±0.08 ±2.5 μV/°C μV/°C TA = −40°C to +105°C1, total offset drift, RTI = VOSI/T + VOSO / T Gain VDDH − VSSH = 10 V to 56 V 80 110 140 90 120 154 dB dB dB 66 90 118 76 100 136 dB dB dB ±0.2 ±0.1 ±0.002 μV/kHz μV/kHz μV/kHz 102 126 150 dB dB dB dB dB dB AVDD − AVSS = 2.7 V to 5.5 V Clock frequency = 0.8 MHz to 1.2 MHz +IN = −IN = −25 V to +25 V, scaling gain = 1 V/V 92 116 140 88 112 136 TA = −40°C to +105°C1 TA = −40°C to +105°C1 TA = −40°C to +105°C1 Rev. B | Page 4 of 59 Data Sheet Parameter GAIN Input Gain Range Output Gain Range Gain Error Before Calibration Using Calibration Coefficient All Gain Values Except as Follows: G = 1/16 V/V, All Scaling Gains G = 32 V/V, 64 V/V, All Scaling Gains G = 128 V/V, Scaling Gains 1 V/V, 1.25 V/V G = 128 V/V, Scaling Gain 1.375 V/V Nonlinearity NOISE ADA4254 Test Conditions/Comments Output voltage (VOUT) = 8.5 V p-p2 Min Typ 1/16 to 128 1, 1.25, 1.375 V/V V/V