ADA4961ACPZN-R7

Low Distortion, 3.2 GHz, RF DGA ADA4961 Data Sheet VCC3 VCC2 VCC1 PM PWUP FUNCTIONAL BLOCK DIAGRAM 24 23 22 21 20 19 EXPOSED PAD VIN+ ADA4961 17 VOUT+ 2 0dB TO 21dB ATTEN VIN– +15dB 16 VOUT– 3 18 DNC 15 DNC 11 12 13 6 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 12454-001 10 MODE 9 A0 8 LATCH 7 A1 14 DNC 1 A2/FA 5 A3/CS GND A4/CLK 4 SDIO GND GND High speed −3 dB bandwidth: 3.2 GHz −1 dB bandwidth: 1.8 GHz Slew rate: 12,000 V/μs Digitally adjustable gain Voltage gain: −6 dB to +15 dB Power gain: −3 dB to +18 dB 5-bit parallel or SPI bus gain control with fast attack IMD3/HD3 distortion, maximum gain, 5 V, high performance (HP) mode IMD3/HD3 at 1 GHz: −90 dBc/−83 dBc IMD3/HD3 at 1.5 GHz: −85 dBc/−75 dBc IMD3/HD3 at 2 GHz: −70 dBc/−70 dBc Low noise Noise density referred to output (RTO): −154 dBm/Hz Noise figure: 5.5 dB at AV = 15 dB, 1 GHz Differential impedances: 100 Ω input, 50 Ω output Low power mode operation, power-down control Single 3.3 V or 5 V supply operation Available in 24-lead, 4 mm × 4 mm LFCSP VCC4 FEATURES Figure 1. APPLICATIONS ADC driver for 10-bit to 14-bit GSPS converters RF/IF gain blocks Line drivers Instrumentation Satellite communications Data acquisition Military systems GENERAL DESCRIPTION The ADA4961 is a high performance, BiCMOS RF digital gain amplifier (DGA), optimized for driving heavy loads out to 2.0 GHz and beyond. The device typically achieves −90 dBc IMD3 performance at 500 MHz and −85 dBc at 1.5 GHz. This RF performance allows GHz converters to achieve their optimum performance with minimal limitations of the driver amplifier or constraints on overall power that typically result from GaAs amplifiers. This device can easily drive 10-bit to16-bit HS converters. For many receiver applications, antialias filter (AAF) designs can be simplified or not required. The ADA4961 has an internal differential input impedance of 100 Ω and a differential dynamic output impedance of 50 Ω, eliminating the need for external termination resistors. The Rev. C digital adjustability provides for 1 dB resolution, thus optimizing the signal-to-noise ratio (SNR) for input levels spanning 21 dB. The ADA4961 is optimized for wideband, low distortion performance at frequencies up to 2 GHz. These attributes, together with wide gain adjustment and relatively low power, make the ADA4961 the amplifier of choice for many high speed applications, including IF, RF, and broadband applications where dynamic range at very high frequencies is critical. The ADA4961 is ideally suited for driving not only analog-todigital converters (ADCs), but also mixers, pin diode attenuators, SAW filters, and multielement discrete devices. It is available in a 4 mm × 4 mm, 24-lead LFCSP and operates over a temperature range of −40°C to +85°C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4961 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  AC Characterization Output Filter .......................................... 15  Applications ....................................................................................... 1  Theory of Operation ...................................................................... 16  Functional Block Diagram .............................................................. 1  Digital Interface Overview ........................................................ 16  General Description ......................................................................... 1  Parallel Digital Interface ............................................................ 16  Revision History ............................................................................... 2  Serial Peripheral Interface (SPI) ............................................... 16  Specifications..................................................................................... 3  Applications Information .............................................................. 17  Noise/Harmonic Performance.................................................... 4  Basic Connections ...................................................................... 17  Timing Specifications .................................................................. 5  ADC Driving............................................................................... 18  Absolute Maximum Ratings............................................................ 6  Low-Pass Antialias Filtering for the ADC Interface .............. 20  Thermal Resistance ...................................................................... 6  Layout Considerations ............................................................... 21  ESD Caution .................................................................................. 6  Evaluation Board ........................................................................ 21  Pin Configuration and Function Descriptions ............................. 7  Outline Dimensions ....................................................................... 24  Typical Performance Characteristics ............................................. 8  Ordering Guide .......................................................................... 24  Characterization and Test Circuits ............................................... 14  REVISION HISTORY 7/2019—Rev. B to Rev. C Replaced Figure 11 ........................................................................... 9 10/2014—Revision 0: Initial Version 3/2019—Rev. A to Rev. B Changes to Figure 45 ...................................................................... 20 Updated Outline Dimension......................................................... 24 Changes to Ordering Guide .......................................................... 24 12/2014—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 2 ............................................................................ 4 Changes to Pin 13, Table 6............................................................... 7 Added Figure 33; Renumbered Sequentially .............................. 12 Added Figure 34 and Figure 35..................................................... 13 Changes to Table 10 ........................................................................ 17 Changes to Figure 52 ...................................................................... 23 Rev. C | Page 2 of 24 Data Sheet ADA4961 SPECIFICATIONS VS = 5 V, HP mode, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for twotone IMD3), unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth −1 dB Bandwidth Slew Rate Settling Time to 1.0% Overdrive Recovery Time Input Return Loss (S11) Output Return Loss (S22) GAIN Voltage Gain Power Gain Gain Step Size Gain Step Error INPUT STAGE Input Common-Mode Voltage Input Resistance Maximum AC-Coupled Input Level Input Capacitance Common-Mode Rejection Ratio (CMRR) OUTPUT STAGE Maximum Output Voltage Swing Differential Output Resistance DIGITAL LOGIC SPECIFICATIONS Input Voltage High, CS1, CLK1, SDIO (VIH) Input Voltage High, PM (VIH) Input Voltage Low, CS1, CLK1, SDIO, PM (VIL) Output Voltage High, CS1, CLK1, SDIO (VOH) Output Voltage Low, CS1, CLK1, SDIO (VOL) POWER SUPPLY Operating Range Quiescent Current 1 Test Conditions/Comments Min VO indicates small signal VO indicates small signal VO = 2 V step VO = 2 V step 500 MHz 500 MHz Maximum voltage gain Minimum voltage gain Maximum power gain Minimum power gain Differential Differential Single-ended VS = 5.0 V VS = 3.3 V IOH = −100 μA IOL = +100 μA 5.0 V, HP mode 5.0 V, low power (LP) mode 5.0 V, power-down mode 3.3 V, LP mode 3.3 V, power-down mode Typ Max Unit 3200 1800 12000 0.6 1.2 −40 −30 MHz MHz V/μs ns ns dB dB 15 −6 18 −3 1.0 ±0.2 dB 1.0 100 6 1.3 55 V Ω V p-p pF dB 5.0 3.0 50 V p-p V p-p Ω 1.4 2.8 0 1.4 0 dB dB dB 3.3 3.3 0.8 3.3 0.8 3.3 to 5.0 154 131 7.4 126 7.2 V V V V V V mA mA mA mA mA Dual function pin. Table 1 does not contain the full pin name, only the relevant function of the pin. See the Pin Configuration and Function Descriptions section for complete pin names and descriptions. Rev. C | Page 3 of 24 ADA4961 Data Sheet NOISE/HARMONIC PERFORMANCE VS = 5 V, HP mode, RS = 100 Ω differential, RL = 50 Ω differential, TA = 25°C, f = 500 MHz, VO = 1.2 V p-p (or 0.6 V p-p per tone for two tone IMD3), LC filter connected, unless otherwise noted. Table 2. Parameter AC PERFORMANCE, 100 MHz Second Harmonic (HD2) Third Harmonic (HD3) Third-Order Intermodulation Distortion (IMD3) 1 dB Compression Point (OP1dB) Noise Figure (NF) Noise Density Referred to Output (RTO) AC PERFORMANCE, 500 MHz Second Harmonic (HD2) Third Harmonic (HD3) Third-Order Intermodulation Distortion (IMD3) 1 dB Compression Point (OP1dB) Noise Figure (NF) Noise Density Referred to Output (RTO) AC PERFORMANCE, 1 GHz Second Harmonic (HD2) Third Harmonic (HD3) Third-Order Intermodulation Distortion (IMD3) 1 dB Compression Point (OP1dB) Noise Figure (NF) Noise Density Referred to Output (RTO) AC PERFORMANCE, 1.5 GHz Second Harmonic (HD2) Third Harmonic (HD3) Test Conditions/Comments Maximum gain Minimum gain Maximum gain Minimum gain VOUT = 1.2 V p-p composite (2 MHz spacing) Maximum gain Minimum gain AV = 15 dB AV = 15 dB AV = 15 dB Maximum gain Minimum gain Maximum gain Minimum gain VOUT = 1.2 V p-p composite (2 MHz spacing) Maximum gain Minimum gain AV = 15 dB AV = 15 dB AV = 15 dB 3.3 V Supply, Low Power Mode Operation1 Min Typ Max 5.0 V Supply, High Performance Mode Operation Min Typ Max Unit −75 −76 −85 −88 −81 −80 −88 −88 dBc dBc dBc dBc −100 −95 17.2 6.0 −154 −100 −100 18.8 5.8 −154 dBc dBc dBm dB dBm/Hz −77 −82 −75 −75 −80 −85 −81 −82 dBc dBc dBc dBc −90 −95 17.8 5.8 −154 −90 −90 19.3 5.6 −154 dBc dBc dBm dB dBm/Hz Maximum gain Minimum gain Maximum gain Minimum gain VOUT = 1.2 V p-p composite (2 MHz spacing) Maximum gain Minimum gain AV = 15 dB AV = 15 dB AV = 15 dB −83 −83 −78 −77 −84 −80 −83 −83 dBc dBc dBc dBc −87 −86 18.1 5.6 −154 −90 −92 21.1 5.5 −154 dBc dBc dBm dB dBm/Hz Maximum gain Minimum gain Maximum gain Minimum gain −73 −75 −75 −75 −76 −77 −75 −75 dBc dBc dBc dBc Rev. C | Page 4 of 24 Data Sheet ADA4961 Parameter Third-Order Intermodulation Distortion (IMD3) Test Conditions/Comments VOUT = 1.2 V p-p composite (2 MHz spacing) Maximum gain Minimum gain AV = 15 dB AV = 15 dB AV = 15 dB 1 dB Compression Point (OP1dB) Noise Figure (NF) Noise Density Referred to Output (RTO) AC PERFORMANCE, 2 GHz Second Harmonic (HD2) 5.0 V Supply, High Performance Mode Operation Min Typ Max −79 −77 16.4 6.0 −153 −85 −84 18.8 6.3 −153 dBc dBc dBm dB dBm/Hz −73 −76 −65 −66 −75 −77 −70 −69 dBc dBc dBc dBc −64 −65 14.5 8.8 −150 −70 −70 17.0 9.0 −150 dBc dBc dBm dB dBm/Hz Maximum gain Minimum gain Maximum gain Minimum gain VOUT = 1.2 V p-p composite (2 MHz spacing) Maximum gain Minimum gain AV = 15 dB AV = 15 dB AV = 15 dB Third Harmonic (HD3) Third-Order Intermodulation Distortion (IMD3) 1 dB Compression Point (OP1dB) Noise Figure (NF) Noise Density Referred to Output (RTO) 1 3.3 V Supply, Low Power Mode Operation1 Min Typ Max Unit 3.3 V high performance mode is not recommended because IMD performance degrades at hot temperatures. TIMING SPECIFICATIONS Table 3. Parameter tCLK tDS tDH tS tH tHIGH tLOW tACCESS tZ Description Serial Clock Period Setup Time Between Data and Rising Edge of SCLK Hold Time Between Data and Rising Edge of SCLK Setup Time Between Falling Edge of CS and SCLK Hold Time Between Rising Edge of CS and SCLK Minimum Period SCLK Can Be in Logic High State Minimum Period SCLK Can Be in Logic Low State Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation Maximum Time Delay Between CS Deactivation and SDIO Bus Return to High Impedance Min 50 5 5 Typ 25 25 Timing Diagram CS tLOW tS tHIGH tCLK tH SCLK tZ SDIO Figure 2. Rev. C | Page 5 of 24 12454-002 tACCESS tDH tDS Max Unit ns ns ns ns ns ns ns ns ns ADA4961 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage, VCCx PWUP, A4/CLK, A3/CS, A2/FA, A1, and A0 Input Voltage, VIN+ and VIN− θJA, Exposed Pad Soldered Down θJC at Exposed Pad Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 3.6 V +3.6 V to −1.2 V 50.92°C/W 42.24°C/W 140°C −40°C to +85°C −65°C to +150°C 240°C θJA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 24-Lead LFCSP ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 6 of 24 θJA 50.92 θJC 42.24 Unit °C/W Data Sheet ADA4961 20 PM 19 PWUP 22 VCC2 21 VCC1 24 VCC4 23 VCC3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 18 DNC VIN+ 2 17 VOUT+ ADA4961 VIN– 3 16 VOUT– TOP VIEW (Not to Scale) GND 4 GND 5 15 DNC 14 DNC MODE 6 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT THE EXPOSED PAD TO GROUND. 12454-003 A1 11 A0 12 9 A2/FA 10 A3/CS SDIO 7 A4/CLK 8 13 LATCH Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 4, 5 2, 3 6 Mnemonic GND VIN+, VIN− MODE 7 8 9 10 11 12 13 14, 15, 18 16, 17 19 20 SDIO A4/CLK A3/CS A2/FA A1 A0 LATCH DNC VOUT−, VOUT+ PWUP PM 21 22 23 24 VCC1 VCC2 VCC3 VCC4 EPAD Description Power Supply Ground. Connect to system ground plane. Differential Inputs. Mode Select Pin for Gain Control. Low indicates serial peripheral interface (SPI), and high (up to 3.3 V) indicates parallel interface. Serial Data Input/Output Pin for SPI Gain Control. Bit A4 for Parallel Gain Control/Serial Clock Pin for SPI Gain Control. Bit A3 for Parallel Gain Control/Chip Select Pin for SPI Gain Control. Bit A2 for Parallel Gain Control/Fast Attack Pin for SPI Gain Control. Bit A1 for Parallel Gain Control. Bit A0 for Parallel Gain Control. Latch Input Asserts Parallel Gain Control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. Do Not Connect. Do not connect to this pin. Differential Outputs. Power-Up Control Input Pin. A logic high (3.3 V) asserts power-up. A logic low asserts power-down. Power/Performance Control Input Pin. A logic low indicates high power and high performance, and a logic high indicates low power and nominal performance. Low power mode must be asserted with VMIN = 2.8 V. Positive Power Supply. Connect to 5 V or 3.3 V. Positive Power Supply. Connect to 5 V or 3.3 V. Positive Power Supply. Connect to 5 V or 3.3 V. Positive Power Supply. Connect to 5 V or 3.3 V. Exposed Pad. Connect the exposed pad to ground. Rev. C | Page 7 of 24 ADA4961 Data Sheet 18 18 16 16 14 14 12 12 10 10 8 8 GAIN (dB) 6 4 4 2 0 0 –2 –2 –6 10M GAIN = 0dB GAIN = 7dB GAIN = 15dB –4 100M 1G 4G FREQUENCY (Hz) –6 10M 12454-004 –4 25 16 24 4G GAIN = 0dB GAIN = 7dB GAIN = 15dB 23 14 22 21 10 20 OP1dB (dBm) 12 8 6 4 19 18 17 16 2 15 0 14 5V, HIGH PERFORMANCE MODE 5V, LOW POWER MODE 3V, LOW POWER MODE 13 12 GAIN = 0dB GAIN = 7dB GAIN = 15dB 11 100M 1G 4G FREQUENCY (Hz) 10 12454-005 –6 10M 1G Figure 7. Maximum Gain vs. Frequency at Three Temperatures, 3.3 V, with Low-Pass Filter 18 –4 100M FREQUENCY (Hz) Figure 4. Gain vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V –2 TA = –40°C TA = +25°C TA = +85°C 12454-007 2 GAIN (dB) 6 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 5. Gain vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 3.3 V 12454-008 GAIN (dB) TYPICAL PERFORMANCE CHARACTERISTICS Figure 8. OP1dB vs. Frequency at15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V, 3.3 V, with Low-Pass Filter 25 16.5 16.0 GAIN = 0dB 15.5 20 15.0 NOISE FIGURE (dB) 14.0 13.5 13.0 12.5 12.0 10.0 10M 10 5 TA = –40°C TA = +25°C TA = +85°C 100M FREQUENCY (Hz) 1G 4G 0 12454-006 11.0 GAIN = 8dB GAIN = 15dB 11.5 10.5 15 0 500 1000 FREQUENCY (MHz) Figure 6. Maximum Gain vs. Frequency at Three Temperatures, 5.0 V, with Low-Pass Filter 1500 2000 12454-009 GAIN (dB) 14.5 Figure 9. Noise Figure vs. Frequency at 15 dB, 8 dB, and 0 dB Gain Settings, 5.0 V, with Low-Pass Filter Rev. C | Page 8 of 24 Data Sheet ADA4961 25 70 50 GAIN = 8dB 10 40 5V, HP, AV15, –40°C 3.3V, LP, AV15,–40°C 5V, LP, AV15, –40°C 30 GAIN = 15dB 20 5V, HP, AV15, +25°C 3.3V, LP, AV15, +25°C 5V, LP, AV15, +25°C 10 5V, HP, AV15, +85°C 3.3V, LP, AV15, +85°C 5V, LP, AV15, +85°C 5 0 500 1000 1500 2000 FREQUENCY (MHz) 0 12454-011 400 600 800 1000 1200 1400 1600 1800 2000 Figure 13. OIP3 vs. Frequency at Three Temperatures, Maximum Gain, 5.0 V, 3.3 V, with Low-Pass Filter –150 50 –152 49 –154 48 500MHz 5V, GAIN = 15dB 5V, GAIN = 8dB 5V, GAIN = 0dB 3.3V, GAIN = 15dB 3.3V, GAIN = 8dB 3.3V, GAIN = 0dB –156 –158 –160 47 OIP3 (dBm) –162 1000MHz 46 45 44 1500MHz –164 43 –166 42 –168 1000 1500 2000 FREQUENCY (MHz) 40 –2 –1 0 1 2 3 4 5 6 TOTAL POWER (dBm) Figure 14. OIP3 vs. Total Power at Three Frequencies Figure 11. Total Input Referred Noise Spectral Density vs. Frequency at 15 dB, 8 dB, and 0 dB, Gain Settings 5.0 V and 3.3 V, with Low-Pass Filter 70 0 5V, HP, AV0, 25°C 5V, HP, AV15, 25°C 3.3V, LP, AV0, 25°C 3.3V, LP, AV15, 25°C 5V, LP, AV0, 25°C 5V, LP, AV15, 25°C 60 50 5V, GAIN = 7dB 3.3V, GAIN = 7dB IMD3 (dBc) OIP3 (dBm) 20 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 12454-013 0 Figure 12. OIP3 vs. Frequency at 15 dB and 0 dB Gain Settings, 5.0 V, 3.3 V, with Low-Pass Filter –80 5V –60 –100 –80 –120 3.3V –100 10 –60 5V, GAIN = 0dB 3.3V, GAIN = 0dB –40 30 –40 5V, GAIN = 15dB 3.3V, GAIN = 15dB –20 40 12454-015 500 12454-012 41 0 –120 0 200 400 600 800 –140 –160 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) IMD3 (dBc) TOTAL INPUT REFERRED NOISE SPECTRAL DENSITY (dBm/Hz) 200 FREQUENCY (MHz) Figure 10. Noise Figure vs. Frequency at 15 dB, 8 dB, and 0 dB Gain Settings, 3.3 V, with Low-Pass Filter –170 0 12454-016 0 12454-014 15 OIP3 (dBm) NOISE FIGURE (dB) 60 GAIN = 0dB 20 Figure 15. IMD3 vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V, 3.3 V, with Low-Pass Filter, Rev. C | Page 9 of 24 ADA4961 –70 –60 HP –100 LP –120 5V, GAIN = 15 5V, GAIN = 7 5V, GAIN = 0 3.3V, GAIN = 15 3.3V, GAIN = 7 3.3V, GAIN = 0 –90 –100 –110 –50 –60 –70 3.3V AND 5V LP –120 –80 –130 –90 –140 –160 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 16. IMD3 vs. Frequency at Maximum Gain, Three Temperatures, 5.0 V, 3.3 V, with Low-Pass Filter –20 –140 –60 HD2, HP (dBc) –100 –120 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 5V HP –80 5V, GAIN = 15dB 5V, GAIN = 7dB 5V, GAIN = 0dB 3.3V, GAIN = 15dB 3.3V, GAIN = 7dB 3.3V, GAIN = 0dB –90 –100 –110 3.3V AND 5V LP –30 5V HP –40 –110 –70 –130 –90 0 200 400 600 800 –100 1000 1200 1400 1600 1800 2000 Figure 20. HD2 vs. Frequency at Three Temperatures, +5.0 V, +3.3 V, with Low-Pass Filter –70 –40 –80 –70 –60 –80 –30 –60 3.3V AND 5V LP –50 –120 –60 –50 5V, TA = +85°C 5V, TA = +25°C 5V, TA = –40°C 3.3V, TA = +85°C 3.3V, TA = +25°C 3.3V, TA = –40°C –100 –20 HD2, LP (dBc) TA = 25°C –70 –20 GAIN = 15dB FREQUENCY (MHz) Figure 17. IMD3 vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, with and Without Low-Pass Filter, +5.0 V –60 –100 1000 1200 1400 1600 1800 2000 –90 –140 HD3, HP (dBc) 400 12454-018 200 800 –80 5V HP, GAIN = 0, FILTERED 5V HP, GAIN = 0, UNFILTERED 0 600 –70 –80 –140 400 FREQUENCY (MHz) 5V HP, GAIN = 7, FILTERED 5V HP, GAIN = 7, UNFILTERED –60 200 Figure 19. HD3 vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, +5.0 V, +3.3 V, with Low-Pass Filter 5V HP, GAIN = 15, FILTERED 5V HP, GAIN = 15, UNFILTERED –40 0 –20 GAIN = 15dB –30 5V HP –40 5V, TA = +85°C 5V, TA = +25°C 5V, TA = –40°C 3.3V, TA = +85°C 3.3V, TA = +25°C 3.3V, TA = –40°C –90 –100 –110 3.3V AND 5V LP –50 –60 –70 –80 –120 –80 –130 –90 –130 –90 0 200 400 600 800 –100 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 12454-019 –120 –140 12454-119 800 HD2, LP (dBc) 600 12454-020 400 Figure 18. HD2 vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, +5.0 V, +3.3 V, with Low-Pass Filter –140 0 200 400 600 800 HD3, LP (dBc) 200 12454-017 0 –100 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 21. HD3 vs. Frequency at Three Temperatures, 5.0 V, 3.3 V, with Low-Pass Filter Rev. C | Page 10 of 24 12454-120 –100 IMD3 (dBc) –40 –80 –80 HD2, HP (dBc) –30 5V HP –80 –60 –120 –20 TA = 25°C HD3, LP (dBc) –40 –60 HD3, HP (dBc) –20 IMD3 (dBc) –40 5V, TA = +100°C 3.3V, TA = +100°C 5V, TA = +85°C 3.3V, TA = +85°C 5V, TA = +25°C 3.3V, TA = +25°C 5V, TA = –40°C 3.3V, TA = –40°C IMD3 (dBc) 0 Data Sheet Data Sheet –50 ADA4961 500MHz 1000MHz 1500MHz –55 –60 –65 HD3 (dBc) –70 1 –75 –80 –85 2 –90 2 3 4 5 6 7 8 9 POWER (dBm) CH1 1V/DIV CH2 500mV/DIV Figure 22. HD3 vs. Output Power/Tone, with Low-Pass Filter –50 1V SCALE: 20ns/DIV Figure 25. Gain Step Response 2MHz TO 500MHz 2MHz TO 1000MHz 2MHz TO 1500MHz –55 CH1 12454-024 1 12454-021 –95 –100 OUTPUT –60 INPUT HD2 (dBc) –65 –70 –75 –80 –85 –90 1 2 3 4 5 6 7 8 9 POWER (dBm) INPUT 600mV/DIV OUTPUT 200mV/DIV Figure 23. HD2 vs. Output Power/Tone, with Low-Pass Filter CH1 –16mV 12454-025 –100 12454-022 –95 SCALE: 1ns/DIV Figure 26. Large Signal Pulse Response 85 GAIN = 0dB GAIN = 7dB GAIN = 15dB 80 75 70 65 CMRR (dB) 1 60 55 50 45 2 40 35 CH1 1V SCALE: 40ns/DIV Figure 24. Enable Response Time 25 10M 12454-023 CH1 1V/DIV CH2 500mV/DIV 100M FREQUENCY (Hz) 1G 4G 12454-026 30 Figure 27. CMRR vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V Rev. C | Page 11 of 24 ADA4961 80 16 75 10 8 4 50 2 45 1G 4G Figure 28. Group Delay vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V 1G 4G FREQUENCY (Hz) Figure 31. S22 RLC vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V 200 5V, HP 5V, LP 3.3V, LP 180 SUPPLY CURRENT (mA) 160 140 120 100 80 60 40 20 100M 1G 10G FREQUENCY (Hz) 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 32. Supply Current vs. Temperature Figure 29. S12 vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V 160 –50 100M 12454-028 –24 –25 GAIN = 0dB –26 GAIN = 7dB –27 GAIN = 15dB –28 –29 –30 –31 –32 –33 –34 –35 –36 –37 –38 –39 –40 –41 10M 40 12454-027 100M FREQUENCY (Hz) 180 0 60 55 6 S12 (dB) 65 COUT 70 12 ROUT GROUP DELAY 14 0 50 GAIN = 0dB GAIN = 7dB GAIN = 15dB 12454-030 18 85 GAIN = 0dB GAIN = 7dB GAIN = 15dB 12454-031 20 Data Sheet 50 GAIN = 0dB GAIN = 7dB GAIN = 15dB 40 140 120 30 1 CIN RIN 100 80 20 60 2 40 20 100M 1G FREQUENCY (Hz) 0 4G CH1 40mV/DIV CH2 500mV/DIV 12454-029 0 Figure 30. S11 Resistor-Inductor-Capacitor (RLC) vs. Frequency at 15 dB, 7 dB, and 0 dB Gain Settings, 5.0 V 10ns/DIV A CH2 350mV 12454-200 10 Figure 33. Fast Attack Assertion Time, High Gain to Low Gain, 8 dB Step Rev. C | Page 12 of 24 Data Sheet ADA4961 5 PHASE DELAY (Degrees) GAIN = +15dB 1 2 0 –5 –10 10ns/DIV A CH2 1.53V –15 12454-201 CH1 40mV/DIV CH2 500mV/DIV 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 FREQUENCY (GHz) Figure 34. Fast Attack Assertion Time, Low Gain to High Gain, 8 dB Step Rev. C | Page 13 of 24 Figure 35. Phase Delay vs. Frequency for all Gain Settings 12454-205 GAIN = –6dB ADA4961 Data Sheet CHARACTERIZATION AND TEST CIRCUITS VCCx 0.1µF EVALUATION BOARD + 470nH 0.1µF 0.1µF VIN+ 35.7Ω + + 50Ω 35.7Ω ADA4961 0.1µF 0.1µF VIN– 50Ω 35.7Ω + 35.7Ω 50Ω 50Ω 470nH SPI OR PARALLEL DIGITAL INTERFACE 12454-045 VCC Figure 36. Test Circuit for S-Parameters on Dedicated 50 Ω Differential to Differential Board VCCx 0.1µF EVALUATION BOARD + 0.5µH 0.1µF + 50Ω ADA4961 0.1µF –3dB 2nH 0.1µF VIN– –10dB 50Ω 50Ω 50Ω –10dB 50Ω + BAND-PASS FILTER 2nH 2pF 50Ω PICOSECOND 5310 BALUN 0.1µF VIN+ + –3dB 2pF 50Ω PICOSECOND 5310 BALUN 50Ω 50Ω 50Ω 0.5µH SPI OR PARALLEL DIGITAL INTERFACE 12454-046 VCC Figure 37. Test Circuit for Single Tone Distortion VCCx 0.1µF EVALUATION BOARD + 0.5µH BAND-PASS 0.1µF 50Ω + 50Ω –10dB 50Ω ADA4961 0.1µF –3dB 0.1µF VIN– 35.7Ω + –3dB PICOSECOND 5310 BALUN 35.7Ω 35.7Ω 50Ω SPLITTER/ COMBINER ZFSC-2-372-S+ 0.1µF VIN+ + –3dB 50Ω 35.7Ω –10dB PICOSECOND 5310 BALUN 50Ω 50Ω 50Ω 0.5µH BAND-PASS SPI OR PARALLEL DIGITAL INTERFACE VCC 12454-047 50Ω Figure 38. Test Circuit for IMD3/IMD2 Rev. C | Page 14 of 24 Data Sheet ADA4961 AC CHARACTERIZATION OUTPUT FILTER Figure 37 is used in part of the ac characterization of the ADA4961. The picosecond 5310 balun provides the differential input signal and the 100 Ω differential match to the device. The 3 dB pads make the picosecond balun 50 Ω impedance less reactive on one side, which balances the differential phase accuracy. On the outputs, the 2 nH and 2 pF create a two-pole low-pass filter, along with the two 50 Ω resistors in parallel with the pads and output picosecond balun. This filter creates the 50 Ω differential load. The output pads make the load more balanced. This is essential for good HD2 performance. This filter technique also creates a lighter load (slight peaking) for the device at higher frequencies, which improves the IMD3 performance. Though the filter bandwidth (BW) computes to 3.3 GHz, the parasitic C (not shown in Figure 37) across the 2 nH filter inductors reduces the 3 dB BW to about 2 GHz (see Figure 4). The filter, beyond reducing integrated output noise, also reduces the higher frequency second and third harmonics above 1 GHz and 700 MHz, respectively (see Figure 20 and Figure 21). Rev. C | Page 15 of 24 ADA4961 Data Sheet THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW Fast Attack The ADA4961 DGA has two digital gain control options: the parallel control interface and the serial peripheral interface. The desired gain control option is selected via the control pin, MODE (see Table 7 for the truth table for the mode control pins). The gain code is in a binary format. A voltage of 1.4 V to 3.3 V is required for a logic high. The fast attack feature, accessible via the SPI, allows the gain to reduce from its present setting by a predetermined step size. Four different attenuation step sizes are available. The truth table for fast attack is shown in Table 8. Two pins are common to both gain control options: PM and PWUP. PM allows the user to choose operation in low power mode (logic high) or high performance mode (logic low). PWUP is the power-up pin. The physical pins are shared between the two interfaces, resulting in two different functions per digital pin (see Table 2). Table 7. Digital Control Interface Selection Truth Table Mode 1 0 Interface Parallel control SPI The parallel digital interface uses five binary bits (Bits[A4:A0]) and a latch pin. The LATCH pin controls whether the input data latch is transparent or latched. In transparent mode, gain changes as input gain control bits change. In latched mode, gain is determined by the latched gain setting and does not change with changing input gain control bits. SERIAL PERIPHERAL INTERFACE (SPI) The SPI uses three pins: SDIO, A4/CLK, and A3/CS. The SPI data register consists of eight bits, five gain control bits, two fast attack attenuation step size address bits, and one read/write bit. SDIO is the serial data input and output pin. The A4/CLK pin is the serial clock, and A3/CS is the channel select pin. MSB LSB MSB FA1 FA0 D4 FAST ATTACK LSB D3 D2 D1 GAIN CONTROL D0 12454-154 R/W READ/ WRITE FA1 0 0 1 1 FA0 0 1 0 1 Step Size (dB) 1 2 4 8 SPI fast attack mode is controlled by the A2/FA pin. A logic high on the A2/FA pin results in an attenuation that is selected by Bits[FA1:FA0] in the SPI register. Table 9. Gain Code vs. Voltage Gain Lookup Table PARALLEL DIGITAL INTERFACE DATA Table 8. SPI 2-Bit Attenuation Step Size Truth Table Figure 39. 8-Bit SPI Register To write to the SPI register, A3/CS must be pulled low and eight clock pulses must be applied to A4/CLK. To read the SPI register value, the R/W bit must be set high, A3/CS must be pulled low, and the device must be clocked. After the register has been read during the next eight clock cycles, the SPI automatically enters write mode. 5-Bit Binary Gain Code 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 Rev. C | Page 16 of 24 Voltage Gain (dB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 −1 −2 −3 −4 −5 −6 Data Sheet ADA4961 APPLICATIONS INFORMATION because they are at bias voltages of about 1 V above ground. The ac coupling capacitors and the RF chokes are the principle limitations for operation at low frequencies. BASIC CONNECTIONS Figure 40 shows the basic connections for operating the ADA4961. Apply a voltage between 3.3 V and 5.0 V to the VCCx pins. Decouple each supply pin with at least one low inductance, surface-mount ceramic capacitor of 0.1 μF, placed as close as possible to the device. The digital pins (mode control pins, associated SPI and parallel gain control pins, PM, and PWUP) operate at a voltage of 3.3 V. 23 EXPOSED PAD VIN+ VCC1 20 19 21 ADA4961 2 VOUT+ 17 0dB TO 21dB ATTEN BALANCED 100Ω SOURCE VIN– 22 PWUP 24 VCC2 0.1µF (0402) VCC3 10µF (0603) VCC4 +5V PM To enable the ADA4961, the PWUP pin must be pulled to a logic high. Pulling PWUP low puts the ADA4961 in sleep mode, reducing current consumption to approximately 7 mA at ambient temperature. The outputs of the ADA4961 must be pulled up to the positive supply with 0.5 μH RF chokes. The differential outputs are biased to the positive supply and require ac coupling capacitors, preferably 0.1 μF. Similarly, the input pins require ac coupling BALANCED 50Ω LOAD +15dB 3 16 VOUT– 18 DNC 4 15 DNC 5 A3/CS A2/FA A1 12 13 6 SPI, PARALLEL INTERFACE NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 12454-048 11 MODE 10 A0 9 LATCH 8 A4/CLK GND 7 SDIO 14 DNC 1 Figure 40. Basic Connections Table 10. Basic Connections Pin No. 5 V Power 21 22 23 24 GND 1, 4, 5 RF Inputs 2 3 RF Outputs 17 16 Mnemonic Description Basic Connection VCC1 Amplifier core power supply Connect these pins to 5 V and decouple to GND using 10 μF and 0.1 μF capacitors close to the pins. GND Ground pins Connect to ground. VIN+ Differential RF inputs, differential input impedance is 100 Ω Connect these pins to the balanced output of the previous device in the signal chain. A balun can be used to convert from a single-ended signal to differential or to improve even order distortion if the previous device in the signal chain is differential. Differential RF inputs, differential output impedance is 50 Ω Connect these pins to the balanced input of the next device in the signal chain. A balun can be used to convert from the ADA4961 differential output to a single-ended signal or to improve even order distortion if the next device in the signal chain is differential. VCC2 VCC3 VCC4 VIN− VOUT+ VOUT− Rev. C | Page 17 of 24 ADA4961 Pin No. SPI/Parallel Control 6 Data Sheet Mnemonic Description Basic Connection MODE Connect this pin to a 3.3 V compliant logic control. Logic 0 asserts serial control, and Logic 1 asserts parallel control. Connect this pin to a 3.3 V compliant logic control. Connect this pin to a 3.3 V compliant logic control. 7 8 SDIO A4/SCLK 9 A3/CS 10 A2/FA 11 A1 12 A0 13 LATCH 19 PWUP Parallel, serial mode control SPI data IO SPI clock, parallel mode gain control, Bit 4 SPI chip select, parallel mode gain control, Bit 3 Fast attack enable, parallel mode gain control, Bit 2 Parallel mode gain control, Bit 1 Parallel mode gain control, Bit 0 Parallel mode latch control Power up 20 PM Performance mode Connect this pin to a 3.3 V compliant logic control. Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts FA enabled, and Logic 0 asserts FA disabled. Connect this pin to a 3.3 V compliant logic control. Connect this pin to a 3.3 V compliant logic control. Connect this pin to a 3.3 V compliant logic control. Logic 0 asserts transparent mode, and Logic 1 asserts latched mode. Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts power-up, and Logic 0 asserts power-down. Connect this pin to a 3.3 V compliant logic control. Logic 1 asserts low performance mode, and Logic 0 asserts high performance mode. +5.0V 0.1µF +5.0V 0.5µF 0.1µF 2nH 10Ω VIN+ 2nH 10Ω 50Ω ADA4961 0.1µF 50Ω AC 1.5pF AD9625 VIN– 0.5µF DIGITAL INTERFACE 100Ω VCOM +5.0V 12454-049 50Ω MARKI BAL-0006GSMG 0.1µF 1:2 BAND-PASS FILTER Figure 41. Wideband ADC Interfacing Example Featuring the ADA4961 and the AD9625 ADC DRIVING The ADA4961 is a high output linearity variable gain amplifier optimized for ADC interfacing. The output IMDs and noise floor remain constant throughout the 22 dB gain range. This is a valuable feature in a variable gain receiver, where it is desirable to maintain a constant, instantaneous dynamic range as the receiver range is modified. The output noise is 6.9 nV/√Hz, which is compatible with 14-bit or 16-bit ADCs. The two-tone IMDs are typically greater than −75 dBc for a 5.5 dBm composite signal into 50 Ω or a 1.2 V p-p composite output. The 50 Ω output impedance makes the task of designing a filter for the high input impedance ADCs more straightforward. Figure 41 shows the ADA4961 driving a two-pole, 1 GHz, lowpass filter into the AD9625. The AD9625 is a 12-bit, 2.5 GSPS ADC with a buffered wideband input that presents a 100 Ω differential input impedance and requires a 1.2 V input swing to reach full scale. For optimum performance, drive the ADA4961 differentially, using a high performance 1:2 matching balun. Rev. C | Page 18 of 24 Data Sheet ADA4961 0 10 –15 5 –30 0 –45 –60 (dB) (dB) –5 –10 –75 2 5 3 + 4 6 –90 –105 –15 –120 –20 FREQUENCY (MHz) 10000 –150 150M 300M 450M 600M 750M 900M 1.05G 1.2G FREQUENCY (Hz) Figure 43. Measured Single Tone Performance of the Circuit Shown in Figure 41 for a 1 GHz Input Signal using Maximum Gain (15 dB) Figure 42. Measured Frequency Response of the Wideband ADC Interface Shown in Figure 41 The two-tone 1 GHz IMDs of two 0.6 V p-p signals have an SFDR of greater than 75 dBc, as shown in Figure 44. 0 –15 –30 –45 –60 (dB) Figure 41 uses a 1:2 impedance transformer to provide the 100 Ω input impedance of the ADA4961 with a matched input. The open collector outputs of the ADA4961 are biased through the two 0.5 μH inductors, and the two 0.1 μF capacitors on the outputs decouple the 5 V inductor voltage from the input common-mode voltage of the ADA4961. The two 25 Ω resistors, in parallel with the 100 Ω input impedance of the AD9625, provide the 50 Ω load to the ADA4961, where the gain is load dependent. The 2 nH inductors and 1.5 pF internal capacitance of the AD9625 constitute the 1 GHz, 1 dB low-pass filter. The two 5 Ω isolation resistors suppress any switching currents from the ADC input sample-and-hold circuitry. The circuit shown in Figure 41 provides variable gain, isolation, filtering, and source matching for the AD9625. By using this circuit with the ADA4961 in a gain of 15 dB (maximum gain), a full-scale SNR (SNRFS) of 55 dB and an SFDR performance of 77 dBc are achieved at 1 GHz, as shown in Figure 43. 0 12454-051 1000 –75 F1 + F2 2F2 + F1 2F1 + F2 F2 – F1 –90 2F2 – F1 2F1 – F2 –105 –120 –135 –150 0 150M 300M 450M 600M 750M FREQUENCY (Hz) 900M 1.05G 1.2G 12454-052 100 12454-050 –25 10 –135 Figure 44. Measured Two-Tone Performance of the Circuit Shown in Figure 41 for a 1 GHz Input Signal Using Maximum Gain (15 dB) Rev. C | Page 19 of 24 ADA4961 Data Sheet LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE –50 The high frequency distortion performance of the ADA4961 can be enhanced by adding a low-pass filter to the output (see Figure 46 and Figure 47. A two-pole low-pass filter is used in the ADC Driving section to illustrate the distortion improvement capabilities and integrated noise reduction. Figure 49 shows a simplified diagram of a two-pole low-pass (LP) filter. The inductor capacitance (LC) values are 2 nH and 2 pF, respectively. This filter gives an overall −3 dB BW of 2 GHz when connected to the ADA4961. Ideally, the BW is 3.5 GHz without any parasitics. The parasitic, C, (about 1 pF) across the 2 nH inductor (not shown) reduces the BW to about 2.1 GHz. –60 IMD (dBc) –65 –75 NO FILTER –80 –90 WITH FILTER –100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 12454-061 –95 Figure 46. IMD vs. Frequency, with and Without LC Filter –50 –55 –60 –65 –70 NO FILTER –75 –80 WITH FILTER –85 –90 –100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 12454-062 –95 Figure 47. HD2 vs. Frequency, with and Without LC Filter –50 20 –55 NO FILTER 15 –60 10 –65 5 –70 HD3 (dBc) 0 –5 NO FILTER –75 –80 WITH FILTER FILTER –10 –85 –90 –15 –95 –20 –100 100M 1G FREQUENCY (MHz) 10G 12454-054 –25 10M Figure 45. Maximum Gain vs. Frequency, with and Without LC Filter Rev. C | Page 20 of 24 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 48. HD3 vs. Frequency, with and Without LC Filter 12454-063 MAXIMUM GAIN (dBc) –70 –85 HD2 (dBc) Take care to ensure that the physical length of the filter is less than 1/10 the wavelength of the 3 dB corner frequency. At 2 GHz, it is 75 mm. The Series L (along with the internal bond wire inductance) and C parasitic parallel create a parallel resonance that causes a reduction in overall BW. Other values and filter types can be used depending on the end user requirements, but care is needed to ensure that the Circuit Q does not exceed 1. The values of 2 nH and 2 pF show the relative improvement in distortion (single tone and IMD3) vs. no filter at frequencies out to 1.5 GHz. At frequencies above about 600 MHz, the HD3s begin to attenuate as is expected due to the LP roll-off of the L (2 nH) and Shunt C (2 pF). In addition, the inband IMD3s also improve. This improvement is due to the peaking that results at the amplifier output due to its internal parasitics interacting with the 2 nH inductor and its Shunt C parasitic. This peaking reduces the input signal to the amplifier (not shown), thus reducing inband third-order terms. –55 Data Sheet ADA4961 LAYOUT CONSIDERATIONS When designing the board, take care to minimize the parasitic capacitance caused by the routing that connects the RF outputs. A good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance. EVALUATION BOARD The ADA4961 evaluation board is a 4-layer board built on FR4 material. The board is configured for a single-ended input and a single-ended output. All RF input and output traces are 50 Ω. On the RF input, the Mini-Circuits® TCM2-43X balun, a 2:1 impedance balun, is used to match external 50 Ω generators to the 100 Ω differential input of the ADA4961. On the RF output, the Mini-Circuits TCM1-43X balun, a 1:1 impedance balun, is used to convert the differential output of the amplifier to the single-ended output of the evaluation board. The outstanding linearity performance over frequency is achieved in part by the RF outputs having a dc bias to the supply, typically 5 V for best performance. RF chokes provide the path to the bias supply from the RF output to the positive supply rail. It is highly recommended that Coilcraft 0805CS471XJLC 470 nH inductors be used for bias. The self resonant frequency of these inductors is high enough so that it does not impact the performance of the ADA4961 at up to 4 GHz. A complete description of operating the evaluation board and evaluation board software is given in the EV-ADA4961SDP1Z user guide. A bill of materials for the RF section of the evaluation board is given in Table 11. +5.0V +5.0V 50Ω BAND-PASS FILTER 470nH MARKI BAL-0006GSMG 0.1µF 1:2 0.1µF 0.1µF 2nH 0.1µF 2nH + ADA4961 AC + DIGITAL INTERFACE 50Ω 2pF 12454-053 470nH 2pF +5.0V Figure 49. ADC Interface Circuit Using a Low-Pass Antialias Filter Table 11. Reference Designator ADA4961ACPZN-R7 J1, J2 T1 L1, L2 T2 C1, C2, C3, C4 R1, R2 Description Device under test Input, output SMA connectors RF input balun 470 nH RF bias chokes RF output balun 0.1 μF RF dc blocking capacitors 8.87 Ω input matching pad Manufacturer Analog Devices, Inc. Johnson Mini-Circuits Coilcraft Mini-Circuits Murata-Erie Panasonic Rev. C | Page 21 of 24 Part Number ADA4961ACPZN-R7 142-0701-801 TCM2-43x+ 0805CS-471XJLC TCM1-43x+ GRM155R71C104KA88D ERJ2GEJ9R1X Data Sheet 12454-202 ADA4961 12454-203 Figure 50. ADA4961 Evaluation Board, Top Layer Figure 51. ADA4961 Evaluation Board, Bottom Layer Rev. C | Page 22 of 24 Figure 52. ADA4961 Evaluation Board Schematic J1 AGND 2 3 4 5 1 AGND JOHNSON142-0701-801 1 2 3 NC 5 T1 TCM2-43X+ 4 6 AGND AGND R1 R4 143 R5 143 AGND R19 20K R14 10K VCC C1 LE CLK TP8 1 YEL 0.1UF C3 0.1UF AGND R21 10K 50 OHM TRACES R29 143 GPIO5_SDP AGND 8.87 R2 8.87 R8 143 AGND R17 20K R12 10K VCC GND VIN+ VINGND GND MODE AGND R18 20K R13 10K VCC SDIO AGND 1 2 3 4 5 6 AGND C10 0.1UF VCC VCC PAD 24 23 22 21 20 19 PAD VCC4 VCC3 VCC2 VCC1 PM PWUP 18 17 16 15 14 13 L1 TP7 1 YEL TP9 1 YEL AGND R16 20K 50 OHM TRACES 470NH L2 VCC AGND R10 20K R9 10K C2 0.1UF 0.1UF C4 AGND GPIO6_SDP AGND R20 20K R15 10K VCC GPIO4_SDP AGND 470NH R11 10K VCC ADA4961 DNC VOUT+ VOUTDNC DNC LATCH U1 GPIO7_SDP TP10 1 YEL SDIO A4/CLK A3/CS FA/A2 A1 A0 7 8 9 10 11 12 Rev. C | Page 23 of 24 R7 35.7 R3 35.7 AGND R6 48.7 R30 48.7 AGND R31 48.7 R32 48.7 P N VCC TP2 1 RED AGND NC 5 1 2 3 C6 0.1UF T2 TCM1-43X+ C5 10UF VCC 4 6 AGND TP1 BLK C7 0.1UF AGND 1 C9 0.1UF AGND 5 4 3 2 C8 0.1UF J2 JOHNSON142-0701-801 12454-204 VDD Data Sheet ADA4961 ADA4961 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 0.50 BSC P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 24 19 18 1 2.65 2.50 SQ 2.45 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004462 SEATING PLANE 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 0.20 MIN 3.16 MIN 0.05 MAX 0.02 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD 09-05-2018-A PIN 1 INDICATOR AREA 4.10 4.00 SQ 3.90 Figure 53. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-7) Dimensions shown in millimeters ORDERING GUIDE Model1 ADA4961ACPZN-R7 EV-ADA4961SDP1Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 24-Lead LFCSP, 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part. ©2014–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12454-0-7/19(C) Rev. C | Page 24 of 24 Package Option CP-24-7