ADC1121

- -~. ... "~' . ..--..- - ~ ANALOG W DEVICES FEATURES 12 Bit Resolution and Accuracy CMOS Compatible Very Low Power Consumption Exceptional Power Supply Rejection Can Operate From Single Battery No Missing Codes, 0 to +70°C LowPower Analog Digital onverter to C ADC1121 :~~:':'::'. /, :::~~'f,:.:'o.,"':.' -""";' ,7'.':""':"< ,,~.' 0:~.r ... " ""-'~';-.. - .~. " :}:f;p;",-"'". ' . ,-. o.f 0"". ..'.,. .~'~?t~:.~.' o' .,:::t:~ '_0" ,-::.-:,:,,~,:,:'~'.~::~..::~..'" ",":,;:'" .,..,.-, '...,,~'::'?~::';::" ,:; '0: OBS 8 :~--;..~ .. , GENERAL DESCRIPTION The CMOS compatible ADC112I requires less than 6 microjoules of energy to perform a complete, 12 bit analog-to-digital conversion. In addition, it has :to.OI% relative accuracy, a 70fJ.s maximum conversion time, a maximum power consumption of IOOmWfor continuous conversions, and no missing codes from 0 to +70°C. Power may be supplied by a single +I2Y to +ISY source, but the logic portions of the converter may also be powered by a separate +SY to +ISY supply to permit logic level matching. If batteries are used as a power source, the resulting voltage droop will have little effect on the ADC112I accuracy due to its excellent power supply rejection. OLE CONVERT the LSB decision, the clock returns to logic' l' and the STATUS output returns to logic '0'. The serial data output is of the non-return-to-zero (NRZ) type. The data is available, MSB first, at the third and subsequent positive~oing dock transitions, COMMAND.-I CLOCK '-' 1 L L...-.... GATED ---,nnnnnr mUUUUUU MSB STATUS The ADC112I accepts analog inputs in the range of 0 to +SY, 0 to +IOY, :tSY, or :tIOY and produces both parallel and serial digital outputs. Parallel outputs are binary, offset binary, or two's complement coded; serial outputs are binary or offset binary coded. The special combination of high performance and low power exhibited by this 2" x 4" x 0.4" (SIx 102 x IOmm) module makes it ideal for use in applications such as remote and portable instrumentation, and large data handling networksTIMING When the convert command is set to logic" 1", the internal clock starts to run. The first '1' to '0' clock transition sets the STATUS output to logic '1' and sets the MSB through LSB and SERIAL output lines to logic '0'. The CONYERT COMMAND input may be returned to logic '0' lOOns after this clock transition but may also remain at logic '1' until SOOnsbefore the sixth clock transition. The MSB decision process starts on the second negative~oing clock edge and concludes one clock period later. The bit decisions continue at the rate of one per clock cycle until the LSB decision has finally been made. After .--J ' --_J:LIL- TE ~ .... .... .... ~ L 3 10) BIT2=~"" .3--BIT ~ LSB SERIAL OUTPUT : i 1 : L.J n L-.J L 10) BIT 2 11) n ---1 I Ms! t --_of LSB 101 Figure 1. Timing Diagram 8 Information furnished by Analog Devices is believed to be and reliable. However, no responsibility is assumed by Analog for itS use; nor for any infringementS of patents or other rights parties which may result from its use. No license is granted by tion or otherwise under any patent or patent rights of Analog accurate Devices of third implicaDevices. Route 1 Industrial Park; P.O. Box 280; Norwood, Mass. 02062 Tel: 617/3294700 TWX: 710/394-6577 West Coast Mid,West Texas 213/595-1783 312/894-3300 214/231,5094 ..... "'~.a£ ~...,_., .'- ,~,.-, ~.._,_.~-,--,.-- .__.- ---- ------ SPECIFICAIONS (typical @+25°C unlessotherwise noted) T RESOLUTION ACCURACY Error Relative to Full Scale Differential Nonlinearity Error Missing Codes TEMPERATURE Gain Unipolar , 12 Bits i'hLSB max i\-2LSB max No Missing Codes from 0 to +70oC OUTLINE DIMENSIONS AND PIN DESIGNATIONS Dimensions shown in inches and (mm). --- COEFFICIENT i20ppm/oC of Reading, max 1 i8ppm/C of Range, max2 i20ppm/C of Range, max2 :!:5ppm/C of Range, max2 JI 2.01 MAX(51.1) j 0.41 MAX (10.4) Zero Nonlinearity TIME3 Bipolar' Offset Differential u 36 37 u IrINI5,1) -. CONVERSION +5V Logic Supply + IOV Logic Supply +15V Logic Supply INPUT VOLTAGE RANGES 631ls (701ls max) HILs (611ls maxI HILs (591ls max) 0 to +5V, 0 to +IOV, :!:5V, :!:10V 400kn 144kn 144kn 120kn min min min min INPUT IMPEDANCE 0 to +5V Range 0 to +IOV Range :!:5V Range :!:10V Range DIGITAL OUTPUTS Logic Levels Parallel Output Codes Unipolar Bipolar Serial Output Codes Unipolar Bipolar OBS Status Output +12V to +15V +5V to +15V See Graphs on pg. 3 t\4LSB t\4LSB :!:\4LSB 19 t-t 18 54 +-+ 55 4.02 MAX 1102.1) CMOS Compatible (see pg. 4) Positive True Binary Positive True Offset Binary, or Two's Complement Positive True Binary, NRZ Format, MSB First Positive True Offset Binary, NRZ Format, MSB First Logic 'I' During Conversion INPUT CONVERT COMMAND Logic Levels Pulse Width Rise and Fall Times .POWER SUPPLY REQUIREMENTS4 Analog Supply (V s) Logic Supply (VDD) POWER CONSUMPTION POWER SUPPLY SENSITIVITYs Gain Unipolar Zero Bipolar Offset TEMPERATURE RANGE Operating Storage ADJUSTMENT RANGES Gain Offset PRICE (1-9) I Reading for bipolar operation is defined as; ActUal CMOS Compatible (see pg. 4) 61ls min, 151ls max; Ills max OLE BOTTOM VIEW COMeAR.TOR --1 I--GRIDO.I" 12.5) NOTE: Terminal pins installed only in shaded hole locations. All pins are gold plated half-hard brass (MIL-G-45204), 0.019" iO.001" (0.48 iO.03mm) dia. For plug-in mounting card order Board No. AC1521, $33.00 (1-9) TE 72 68 67 66 65 64 ANALOG INPUT B RANGE A PROGRAMMING ANALOG LOW REF OUT 8t BLOCK DIAGRAM 0 to +70oC -55 to +125°C 2 to.2% of Range 2 iO.2% of Range $229 Reading } - (-Full Scale) ANALOG SUPPLY COMMON GAIN 18 ADJUST { 19 GOG"AL TO ANALOG CONVERTER -0 160 LOGICSUPPLY , Range for unipolar operation is defined as; + Full Scale Range for bipolar operation is defined as, 2 (+ Full Scale) 'Conversion time is measured from the rising edge of the convert command pulse to the falling edge of the STATUS nutput. A graph showing conversion time as a function of logic supply voltage is shown on page 3. 4 Power supply current for both the analog and logic supplies is very transient in natUre; peak current for both is less than lOOrnA. s Maximum change as analog supply voltage varies from +12Y to +15Y. Specifications subject to change without norice. *" 1 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 LOGIC GND BIT 10 BIT 9 BIT 11 LSB BIT 6 BIT 7 81T 8 BIT 5 MS8 BIT 2 BIT 3 BIT4 STATUS STATUS GATEDCLKOUT SERIAL OUT CONY. COMM, ~ ANALOG SUPPL Y 26 I 0-- 18 t success, , v CLOCK mROXOMAnON LGG" -2- ~ Applying ADC1121 the 74 72 70 ""' 10" 10" ...... """, TI pl M be di; ~ 68 ... 66 :IE ;:: 64 is ~ 0 " ..... .......... ........... """'...... 62 60 ~ z -to-TYP 9 10 11 ~ I Z e 10" 10'" MAX ~ .. :IE 58 56 ~ " 0 10" 54 52 50 5 ffi10" ~ 12 13 14 15 6 8 LOGIC SUPPLY VOLTAGE - 5? 10., 'ANALOG SUPPLY@+15V ANALOGSUPPLY@+12V 10" 10" 10'" 10" 10" 10" 10. 10' RATE II I VDD 10' 10' 10< 10' Conversion Time Vs. Logic Supply Voltage THROUGHPUT - Hz OBS 70 60 50 Power Consumption Vs. Throughput Rate and Supply Voltages 100 90 ., ::> 0 ::> z ;:: 4D 30 3.0 0:: ~! 0= g., I-Z "0 ~~ z'" 0> ~ .. iSe 20 "":IE zI 15 ''is 0::" 10 9 8 7 6 5 OLE 70 80 2.0 1.5 ~ "z "0 60 1.0 0.9 ... 0.8 ~ :; 9i IZ 5t "':IE C:;!i!! 50 0::::> 0 0" .... ..: Z ..: 40 0.7 O!! Z' 0.6 z~ 30 0.5 1;:1 0.4 :it... ::>c "0 0.3 §:it 0:: ... ~ 0.2 5? 0.15 20 11.5 12.0 12.6 13.0 13.5 ANALOG SUPPLY VOLTAGE Analog Circuits Power Consumption TE 14.0 14.5 15.0 15.5 - Volts SE Th to. bi! po Fi! se! IS' tr~ ti< pu sel 6 8 LOGIC 9 10 11 12 VDD 13 14 0.1 15 SUPPLYVOLTAGE- Logic Circuits Power Consumption ANALOG INPUT CHARACTERISTICS The input circuit of the ADCl121 is shown below in block diagram form. 68 l00kil ANALOG INPUT sary to provide the comparator with a 0 to +5V input which is then compared to the 0 to +5V D/ A converter output. Table I, below, shows the range programming connections required for the various input ranges and also shows the resulting input impedances. INPUT IMPEDANCE 500kil 180kil 180kll 150kll min min min min SEI Cl 67 l00kil 66 B RANGE PROGRAM A } INPUT RANGE 0 to +5V 0 to +10V :t5V :tlOV CONNECTIONS PIN 66 TO: PIN 67 TO: 68 65 64 64 68 68 68 65 STt ~ FROM -- 65 ANALOG GROUND r 64 REFERENCE OUTPUT REFERENCE SOURCE Table I. Range Programming Figure 2. Analog Input Configuration Analog signals in the range of 0 to +5V, 0 to +10V, :t5V, or :t10V are applied between pins 68 and 65. The range programming circuitry serves to offset and divide these signals as neces-3... PARALLEL DATA OUTPUTS TheADC1l21 produces natural binary coded outputs when configured as a unipolar device; as a bipolar device it can produce either offset binary or two's complement output codes. n ro; th pu In! IS 51 /- ...0- The most significant bit is represented by pin 46 (the MSB output) for binary and offset binary codes and by pin 37 (the MSB output) for the two's complement code. Tables II and III, below, illustrate the relationship between the analog input and digital output for all three codes. ANALOG INPUT 0 TO +5Y RANGE +4.9988Y +2.5000Y +0.6250V +0.0012Y +O.OOOOY WGIC LEVELS The logic levels of the ADC1l21's CMOS digital outputs are as shown below: VDD;;' Logic "1";;' VDD - O.IV; where VDDis the logic supply voltage. O.IV;;' Logic "0";;' O.OV The logic power supply voltage (which is independent of the analog supply voltage) can be varied from +5V to +15V. This allows the user to match the converter's logic levels to the logic levels of other CMOS devices in his system. Although TTL logic levels can be achieved by setting the logic supply voltage to +5V, the MSB through LSB output gates do not have sufficient current sink capability to drive standard TTL logic. They can, however, readily drive low power TTL such as the series 74L devices. The remaining digital outputs (STATUS, STATUS, SERIAL OUT, CLOCK OUT, and MSB) have a 4mA current sink capability and, thus, can be used directly with standard TTL logic. CONVERT COMMAND, the only digital input, will respond to logic levels of: VDD;;;' Logic "1";;' 0.7 VDD 0.3 VDD ;;. Logic "0";;' O.OV DIGITAL OUTPUT BINARY CODE 0 TO +10Y RANGE +9.9976Y +5.0000Y +1.2500Y +0.0024Y +O.OOOOY 111111111111 100000000000 001000000000 000000000001 000000000000 Table II. Nominal Unipolar Input-Output ANALOG INPUT Relationships OBS . I DIGIT AL OUTPUT TWO'S :t5Y RANGE :tlOY RANGE OFFSET BINARY CODE COMPLEMENT CODE +4.9976Y +2.5000Y +0.0024V +o.OOOOY -5.0000Y +9.9951Y +5.0000Y +0.0049Y +O.OOOOY -lO.OOOOY 111111111111 110000000000 100000000001 100000000000 000000000000 011111111111 010000000000 000000000001 000000000000 100000000000 Table III. Nominal Bipolar Input-Output Relationships SERIAL DATA OUTPUTS The serial data output, available at pin 39, is of the non-returnto-zero format. The data, which is transmitted MSB first, is binary coded for unipolar units and offset binary coded for bipolar units. Figure 3, below, indicates one method for transmitting data serially using only three wires (plus a digital ground). The data is clocked into a receiving shift register by the positive-going transitions of the gated clock output. Since these clock transitions occur typically 250 to 5SOns after each bit of serial output data becomes valid, ample time is allowed for shift register set-up. LSB OLE 6 However, for minimum logic power supply consumption, Logic '1' should be kept as close to VDD as possible and Logic '0' as close to O.OVas possible. GAIN AND OFFSET ADJUSTMENTS The potentiometers used for making gain and offset adjustments are connected as shown in Figure 4. These potentiometers should be small 10 or 20 turn cermet type devices mounted as close to the module pins as possible. TE OFFSET ADJUST Ik!J GAIN ADJUST 2k!J MSB STATUS SERIAL OUTPUT 39 Figure 4. Adjustment Potentiometer Connections CLOCK OUTPUT 40 STATUS OUTPUT 42 Proper gain and offset calibration requires great care and the use of sensitive and accurate reference instruments. The voltage standard used as a signal source must be very stable. It should be capable of being set to within ::!:1/lOLSBof the desired value at both ends of its range. The gain and offset calibrations will be independent of each other if the offset adjustment is made first. These adjustments are not made with zero and full scale input signals and it may be helpful to understand why. An AID converter will produce a given digital word output for a small range of input signals, the nominal width of the range being lLSB. If the input test signal is set to a value which should cause the converter to be on the verge of switching between two adjacent digital outputs, the unit can be calibrated so that it does, in fact, switch at just that point. With a high speed convert command rate and a visu-4-- Figure 3. Serial Data Transmission The STATUS output goes from logic '1' to logic '0' approximately 100 to 450ns after the last '0' to '1' clock transition. If the shift register's propagation delay exceeds this CLOCK output to STATUS output delay, the parallel output data appearing at its terminals will not be stable when end-of-conversion is signalled. The introduction of a suitable delay into the STATUS output line will readily circumvent this problem. al display, these adjustments can be performed in a very accurate and sensitive way. Analog Devices' Conversion Handbook gives more detailed information on testing and calibrating A/D converters. 60 OFFSET CALIBRATION For 0 to +5V units set the input voltage precisely to +0.0006V; for 0 to +10V units set it to +0.0012V. Adjust the offset potentiometer until the converter is just on the verge of switching from 000000000000 to 000000000001. For :t5V units set the input voltage precisely to +0.0012V; for :tlOV units set it to +0.0024V. Adjust the offset potentiometer until offset binary coded units are just on the verge of switching from 100000000000 to 100000000001 and.two's complement coded units are just on the verge of switching from 000000000000 to 000000000001. GAIN CALIBRATION Set the input voltage precisely to +4.9982V for 0 to +5V units, to +9.9963V for 0 to +10V units, to +4.9963V for :t5V units, or to +9.9927V for :tlOV units. Note that these values are 1'hLSB's less than nominal full scale. Adjust the gain potentiometer until binary and offset binary coded units are just on the verge of switching from 111111111110 to 111111111111 and two's complement coded units are just on the verge of switch;ng from 011111111110 to 011111111111. 16 55 + 26 Figure 6. Single Source Connection OBS 60 16 55 26 POWER SUPPLY AND GROUNDING CONNECTIONS The ADC1121 has independent analog and logic supply inputs which may be powered from a single source or from separate sources. Figures 5 and 6, below, show the proper connections for both cases. The analog supply ground, pin 16, and the digital supply ground, pin 55, are not connected internally but should be jumpered together close to the module pins. Although the analog supply ground and analog signal ground, pin 65, are joined inside the module, pin 65 should never be used as a power supply return. Due to the transient nature of the supply currents encountered in a device of this type, it is recommended [hat 15,uF, 35V tantalum bypass capacitors be added across the analog and digital supplies at a location close to the module JInS. OLE THE AC1521 MOUNTING CARD Since battery-powered equipment is one of the prime areas of application for the ADC 1121, excellent power supply rejection has been provided. The ADC1121 will have less than a :t\4LSB gain shift and less than a :t\4LSB offset shift as the analog supply voltage changes from +15V to +12V during the course of a battery discharge cycle. REPETITIVE CONVERSIONS When making repetitive conversions, a new convert command pulse may be initiated any time after the' 1' to '0' transition of the STATUS output. If the STATUS output is connected to the CONVERT COMMAND input, a new conversion will automatically begin as soon as the conversion in progress has been completed. The STATUS line will remain in the logic' l' state for approximately 4,us betWeen conversions in this mode of operation. HANDLING CONSIDERATIONS Care must be taken in the handling of the ADC1121 to prevent electrostatic damage to its CMOS logic. The unit should be transported on conductive foam or other suitable material and should be handled only by properly grounded personnel. Ground connections must be made before power is applied. Electrostatic damage, should it occur, would be manifested by excessive logic current drain and/or complete failure of one or more logic IC's. TE The AC1521 mounting card is available to assist in the application of the ADC1121. This 4.5" x 4.4" (114 x I11mm) printed circuit card, shown in Figure 7, has sockets which allow an ADC1121 to be plugged directly onto it. It includes the necessary gain and offset adjustment potentiometers and bypass capacitors; it mates with a Cinch 251-22-30-160 (or equivalent) dual 22 pin edge connector which is supplied with every card. Figure 5. Two Source Connection -5. ---~------ 4.500 /114.301 0 L r J l GAIN 0 =::=1 " OFFSET ..0 The input voltage range is programmed by means of jumpers which the user installs as shown in Figure 8. The pin connections are as shown in Table IV. 0 e,