ADCLK954BCPZ

Data Sheet Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK954 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply LVPECL ADCLK954 Q0 Q0 Q1 Q1 APPLICATIONS Q2 Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation Q2 VREF0 Q3 REFERENCE Q3 Q4 VT0 Q4 CLK0 The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. Q5 VT1 Q5 CLK1 Q6 CLK1 Q6 Q7 IN_SEL VREF1 Q7 REFERENCE Q8 Q8 Q9 Q9 Q10 The ADCLK954 features 12 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. Q10 Q11 Q11 The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V. 07968-001 GENERAL DESCRIPTION CLK0 Figure 1. The ADCLK954 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADCLK954 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Functional Description .....................................................................9 Functional Block Diagram .............................................................. 1 Clock Inputs ...................................................................................9 Revision History ............................................................................... 2 Clock Outputs ................................................................................9 Specifications..................................................................................... 3 Clock Input Select (IN_SEL) Settings...................................... 10 Electrical Characteristics ............................................................. 3 PCB Layout Considerations ...................................................... 10 Absolute Maximum Ratings ............................................................ 5 Input Termination Options ....................................................... 11 Determining Junction Temperature .......................................... 5 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 12 Thermal Performance .................................................................. 5 REVISION HISTORY 8/2016—Rev. B to Rev. C Changed CP-40-8 to CP-40-16 .................................... Throughout Changes to Figure 2 and Table 7 ..................................................... 6 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 6/2010—Rev. A to Rev. B Changed Output Voltage Differential Parameter to Output Voltage, Single Ended Parameter, Table 1 ..................................... 3 Changes to Output Voltage, Single Ended Parameter, Table 1 ... 3 7/2009—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Negative Supply Current, Table 4............................... 4 Changes to Positive Supply Current, Table 4 ................................ 4 Changes to Figure 10 ........................................................................ 8 1/2009—Revision 0: Initial Version Rev. C | Page 2 of 12 Data Sheet ADCLK954 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter DC INPUT CHARACTERISTICS Input Common-Mode Voltage Input Differential Range Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current Hysteresis DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage, Single Ended Reference Voltage Output Voltage Output Resistance Symbol Min VICM VID CIN VEE + 1.5 0.4 VOH VOL VO VREF Typ Max Unit Test Conditions/Comments VCC − 0.1 3.4 ±1.7 V between input pins 0.4 V V p-p pF 50 100 50 20 10 Ω Ω kΩ µA mV Open VTx V V mV 50 Ω to (VCC − 2.0 V) 50 Ω to (VCC − 2.0 V) VOH − VOL, output static V Ω −500 µA to +500 µA Unit Test Conditions/Comments GHz See Figure 4 for differential output voltage vs. frequency, > 0.8 V differential output swing 20% to 80% measured differentially VCC − 1.26 VCC − 1.99 610 VCC − 0.76 VCC − 1.54 960 (VCC + 1)/2 235 Table 2. Timing Characteristics Parameter AC PERFORMANCE Maximum Output Frequency Symbol Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew1 Part-to-Part Skew Additive Time Jitter Integrated Random Jitter Broadband Random Jitter2 Crosstalk-Induced Jitter3 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise tR tF tPD fIN = 1 GHz 1 2 3 Min Typ 4.5 4.8 40 40 175 75 75 210 50 9 Max 90 90 245 25 45 28 75 90 −119 −134 −145 −150 −150 ps ps ps fs/°C ps ps fs rms fs rms fs rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz VICM = 2 V, VID = 1.6 V p-p VID = 1.6 V p-p BW = 12 kHz − 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V Input slew rate > 1 V/ns (see Figure 11, the phase noise plot, for more details) @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs. Rev. C | Page 3 of 12 ADCLK954 Data Sheet Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Symbol VIH VIL IIH IIL Min VCC − 0.4 VEE Typ 2 Max VCC 1.0 100 0.6 Unit V V μA mA pF Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection1 Output Swing Supply Rejection2 1 2 Symbol Min VCC − VEE 2.97 IVEE IVCC PSRVCC PSRVCC Typ 118 406 1.1 V p-p Figure 7. Propagation Delay vs. Temperature, VID = 1.6 V p-p 225 230 PROPAGATION DELAY (ps) 215 210 205 200 195 190 220 +85°C 210 +25°C 200 –40°C 180 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL INPUT VOLTAGE SWING (V) Figure 5. Propagation Delay vs. Differential Input Voltage 1.8 190 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) 2.7 2.9 3.1 07968-008 185 07968-005 PROPAGATION DELAY (ps) 220 Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns Rev. C | Page 7 of 12 ADCLK954 Data Sheet –90 ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –100 PHASE NOISE (dBc/Hz) –40°C 1.52 +25°C 1.50 +85°C 1.48 1.46 –110 –120 –130 ADCLK954 –140 –150 1.44 –160 1.42 2.75 –170 10 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 POWER SUPPLY (V) CLOCK SOURCE 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p Figure 11. Absolute Phase Noise Measured @1 GHz 300 500 450 ICC 250 400 RANDOM JITTER (fS rms) SUPPLY CURRENT (mA) 100 07968-011 1.54 07968-009 DIFFERENTIAL OUTPUT VOLTAGE SWING (V) 1.56 350 +85°C +25°C –40°C 300 250 200 200 150 100 50 150 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.7 Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature, All Outputs Loaded (50 Ω to VCC − 2 V) Rev. C | Page 8 of 12 0 0 5 10 15 20 25 INPUT SLEW RATE (V/ns) Figure 12. RMS Random Jitter vs. Input Slew Rate, VID Method 07968-012 3.0 07968-010 100 2.9 IEE Data Sheet ADCLK954 FUNCTIONAL DESCRIPTION Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK954 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower LVPECL driver. This can be an important consideration when driving long trace lengths, but is usually not an issue. VS_DRV ADCLK954 VS = VS_DRV Z0 = 50Ω CLOCK OUTPUTS The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK954 are designed to directly drive 800 mV into a 50 Ω cable or into microstrip/stripline transmission lines terminated with 50 Ω referenced to VCC − 2 V, as shown in Figure 14. The LVPECL output stage is shown in Figure 13. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion. 50Ω VCC – 2V 50Ω Z0 = 50Ω LVPECL 07968-014 The ADCLK954 accepts a differential clock input from one of two inputs and distributes the selected clock to all 12 LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). See the functional block diagram (Figure 1) and the General Description section for more clock input details. See Figure 19 through Figure 22 for various clock input termination schemes. Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK954 should equal VS of the receiving buffer. Although the resistor combination shown (in Figure 15) results in a dc bias point of VS_DRV − 2 V, the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the ADCLK954 LVPECL driver through the pull-down resistor. Figure 14. DC-Coupled, 3.3 V LVPECL VS_DRV VS_DRV ADCLK954 50Ω 127Ω 127Ω SINGLE-ENDED (NOT COUPLED) 50Ω VS LVPECL 83Ω 83Ω 07968-015 CLOCK INPUTS VCC Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination ADCLK954 Z0 = 50Ω Q Z0 = 50Ω Q VS = VS_DRV 50Ω 50Ω 50Ω LVPECL 07968-016 VS_DRV VS_DRV ADCLK954 VS 0.1nF Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage Figure 14 through Figure 17 depict various LVPECL output termination schemes. When dc-coupled, VS of the receiving buffer should match the VS_DRV. 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE 200Ω LVPECL 200Ω Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line Rev. C | Page 9 of 12 07968-017 VEE 07968-013 Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination ADCLK954 Data Sheet A Logic 0 on the IN_SEL pin selects the Input CLK0 and Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1. PCB LAYOUT CONSIDERATIONS The ADCLK954 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to GND plane assume that the VEE power plane is grounded for LVPECL operation. Note that for ECL operation, the VCC power plane becomes the ground plane. It is also important to adequately bypass the input and output supplies. Place a 1 µF electrolytic bypass capacitor within several inches of each VCC power supply pin to the GND plane. In addition, place multiple high quality 0.001 µF bypass capacitors as close as possible to each of the VCC supply pins and connect the capacitors to the GND plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines that can affect jitter performance. If the return is floated, the device exhibits a 100 Ω cross termination, but the source must then control the common-mode voltage and supply the input bias currents. There are ESD/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used. Exposed Metal Paddle The exposed metal paddle on the ADCLK954 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE power plane. When properly mounted, the ADCLK954 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK954. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer down to the VEE power plane (see Figure 18). The ADCLK954 evaluation board (ADCLK954/PCBZ) provides an example of how to attach the part to the PCB. In a 50 Ω environment, input and output matching have a significant impact on performance. The buffer provides internal 50 Ω termination resistors for both CLKx and CLKx inputs. Normally, the return side is connected to the reference pin that is provided. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are dccoupled to a source, take care to ensure that the pins are within the rated input differential and common-mode ranges. Rev. C | Page 10 of 12 VIAS TO VEE POWER PLANE 07968-018 CLOCK INPUT SELECT (IN_SEL) SETTINGS Figure 18. PCB Land for Attaching Exposed Paddle Data Sheet ADCLK954 INPUT TERMINATION OPTIONS VREF VREF VT VT 50Ω CLK 50Ω 50Ω CLK CLK 50Ω 07968-019 CLK CONNECT VT TO VCC. CONNECT VT TO VREF . Figure 19. Interfacing to CML Inputs 07968-021 VCC Figure 21. AC Coupling Differential Signals Inputs, Such As LVDS VREF VT 50Ω CLK VREF VT 50Ω CLK VCC – 2V 50Ω CLK 50Ω 07968-020 CONNECT VT TO VCC − 2V. CONNECT VT, VREF , AND CLK. PLACE A BYPASS CAPACITOR FROM VT TO GROUND. ALTERNATIVELY, VT, VREF , AND CLK CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180º PHASE SHIFT. 07968-022 CLK Figure 22. Interfacing to AC-Coupled Single-Ended Inputs Figure 20. Interfacing to PECL Inputs Rev. C | Page 11 of 12 ADCLK954 OUTLINE DIMENSIONS PIN 1 INDICATOR 6.10 6.00 SQ 5.90 0.30 0.23 0.18 40 31 30 0.50 BSC 1 PIN 1 INDICATOR 3.05 2.90 SQ 2.75 EXPOSED PAD 21 0.80 0.75 0.70 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-004333 SEATING PLANE 11 20 BOTTOM VIEW 4.50 REF 10 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-2. 08-22-2013-A TOP VIEW 0.50 0.40 0.30 Figure 23. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 mm Package Height (CP-40-16) Dimensions shown in millimeters ORDERING GUIDE Model1 ADCLK954BCPZ ADCLK954BCPZ-REEL7 ADCLK954/PCBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP] 40-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07968-0-8/16(C) Rev. C | Page 12 of 12 Package Option CP-40-16 CP-40-16