ADF4212LBRUZ

Dual Low Power PLL Frequency Synthesizer ADF4212L Data Sheet FEATURES GENERAL DESCRIPTION IDD total: 7.5 mA Bandwidth RF/IF: 2.4 GHz/1.0 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable dual modulus prescaler RF and IF: 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Fastlock mode Power-down mode 20-lead TSSOP and 20-lead LFCSP packages The ADF4212L is a dual frequency synthesizer that can be used to implement local oscillators (LO) in the up-conversion and down-conversion sections of wireless receivers and transmitters. It can provide the LO for both the RF and IF sections. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual modulus prescaler (P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 15-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phaselocked loop (PLL) can be implemented if the synthesizer is used with external loop filters and voltage controlled oscillators (VCOs). APPLICATIONS Control of all the on-chip registers is via a simple 3-wire interface with 1.8 V compatibility. The devices operate with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA, WCDMA) Base stations for wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Cable TV tuners (CATV) Communications test equipment FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 ADF4212L VP1 VP2 RSET IF PHASE FREQUENCY DETECTOR REFERENCE 12-BIT IF B-COUNTER IFIN CHARGE PUMP 6-BIT IF A-COUNTER IF CURRENT SETTING IF LOCK DETECT REF IN CPIF IF PRESCALER IFCP3 IFCP2 IFCP1 OSCILLATOR 15-BIT IF R-COUNTER DATA LE 22-BIT DATA REGISTER OUTPUT MUX RFCP3 RFCP2 RFCP1 15-BIT RF R-COUNTER RF LOCK DETECT REFERENCE CHARGE PUMP 12-BIT RF B-COUNTER RFIN MUXOUT SDOUT RF PRESCALER RF PHASE FREQUENCY DETECTOR 6-BIT RF A-COUNTER REFERENCE RSET FLO SWITCH DGNDRF AGNDRF DGNDIF CPRF AGNDIF FLO 02774-001 CLK Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4212L Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect...................................................... 14 Applications ....................................................................................... 1 Lock Detect ................................................................................. 14 General Description ......................................................................... 1 RF/IF Input Shift Register ......................................................... 14 Functional Block Diagram .............................................................. 1 IF R Counter Latch..................................................................... 16 Revision History ............................................................................... 2 IF N Counter Latch .................................................................... 17 Specifications..................................................................................... 3 RF R Counter Latch ................................................................... 18 Timing Characteristics ................................................................ 5 RF N Counter Latch ................................................................... 19 Absolute Maximum Ratings............................................................ 6 Program Modes .............................................................................. 20 ESD Caution .................................................................................. 6 IF and RF Power-Down ............................................................. 20 Pin Configurations and Function Descriptions ........................... 7 IF Section..................................................................................... 20 Typical Performance Characteristics ............................................. 9 RF Section ................................................................................... 21 Circuit Description ......................................................................... 13 Applications Information .............................................................. 22 Reference Input Section ............................................................. 13 Local Oscillator for GSM Handset Receiver............................... 22 RF/IF Input Stage........................................................................ 13 Wideband PLL ............................................................................ 23 Prescaler (P/P + 1)...................................................................... 13 Interfacing ................................................................................... 24 RF/IF A and B Counters ............................................................ 13 Pulse Swallow Function ............................................................. 13 PCB Design Guidelines for Lead Frame Chip Scale Package ..................................................................... 24 RF/IF R Counter ......................................................................... 13 Outline Dimensions ....................................................................... 25 Phase Frequency Detector (PFD) and Charge Pump ............ 14 Ordering Guide .......................................................................... 26 REVISION HISTORY 1/14—Rev. D to Rev. E Changes to Table 10 ........................................................................ 18 8/12—Rev. C to Rev D Changed CP-20-1 to CP-20-6 ........................................... Universal Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 11/10—Rev. B to Rev C Changes to VP1, VP2 to GND Parameter, Table 4 and VP1, VP2 to VDD1, VDD2 Parameter, Table 4 ................................................... 6 Changes to Ordering Guide .......................................................... 26 9/08—Rev. A to Rev B Updated Format .................................................................. Universal Changes to Figure 1 and General Description Section ............... 1 Changes to Prescaler Output Frequency Parameter and RF Input Frequency (RFIN) Parameter ................................................. 3 Changes to Table 3 and Figure 2 ..................................................... 5 Changes to Figure 4 .......................................................................... 7 Changes to Figure 27, RF/IF A and B Counters Section, Pulse Swallow Function Section, and RF/IF R Counter Section ........ 13 Changes to RF/IF Input Shift Register Section........................... 14 Changes to Programmable IF Reference (R) Counter Section, IF Program Modes Section, and IF Power-Down Section ........ 20 Changes to Programmable RF Reference (R) Counter Section, RF Program Modes Section, Programmable RF N Counter Section, and RF Power-Down Section......................................... 21 Changes to Figure 32...................................................................... 23 Changes to Figure 33 and Figure 34............................................. 24 Added PCB Design Guidelines for Lead Frame Chip Scale Package Section............................................................................... 24 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 3/03—Data Sheet changed from REV. 0 to REV. A Changes to General Description .....................................................1 Changes to Specifications .................................................................3 Changes to Table 9.......................................................................... 18 Changes to Table 11 ....................................................................... 20 Changes to Figure 31...................................................................... 23 11/02—Revision 0: Initial Version Rev. E | Page 2 of 28 Data Sheet ADF4212L SPECIFICATIONS VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter 1 RF/IF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity IF Input Frequency (IFIN) IF Input Sensitivity MAXIMUM ALLOWABLE Prescaler Output Frequency 3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1 VDD2 VP1, VP2 IDD (RF and IF) 5 RF Only IF Only IP (IP1 + IP2) Low Power Sleep Mode B Version B Chips 2 Unit Test Conditions/Comments 0.2/2.4 0.2/2.4 GHz min/max −10/0 100/1000 −10/0 −10/0 100/1000 −10/0 dBm min/max MHz min/max dBm min/max For lower frequencies, ensure that slew rate (SR) > 140 V/µs VDD = 3 V 188 188 MHz max 10/150 500 mV/VDD 10/150 500 mV/VDD MHz min/max V p-p min/max 10 ±100 10 ±100 pF max μA max 75 75 MHz max 5 625 2 1.5/5.6 1 6 2 2 5 625 2 1.5/5.6 1 6 2 2 mA typ μA typ % typ kΩ min/max nA max % typ % typ % typ 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max μA max pF max 1.4 0.4 1.4 0.4 V min V max 2.7/3.3 VDD1 VDD1/5.5 7.5/10 5.0/6 2.5/4 0.6 1 2.7/3.3 VDD1 VDD1/5.5 7.5/10 5.0/6 2.5/4 0.6 1 V min/max V min/max V min/max mA typ/max mA typ/max mA typ/max mA typ μA typ VDD = 3 V See Figure 26 for input circuit AC-coupled; when dc-coupled, 0 V to VDD maximum (CMOS compatible) Programmable, see Table 10 With RSET = 2.7 kΩ With RSET = 2.7 kΩ 0.5 V < VCP < VP − 0.5 V 0.5 V < VCP < VP − 0.5 V VCP = VP/2 Open-drain 1 kΩ pull-up to 1.8 V IOL = 500 μA Operating temperature range is as follows: B version: −40°C to +85°C. The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency less than this value. 4 Guaranteed by design. Sample tested to ensure compliance. 5 TA = 25°C. RF = 1 GHz; prescaler = 32/33. IF = 500 MHz; prescaler = 16/17. 1 2 3 Rev. E | Page 3 of 28 ADF4212L Data Sheet VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 V. Table 2. Parameter 1 NOISE CHARACTERISTICS RF Phase Noise Floor 3 Phase Noise Performance 4 IF: 540 MHz Output 5 IF: 900 MHz Output 6 RF: 900 MHz Output6 RF: 1750 MHz Output 7 RF: 2400 MHz Output 8 Spurious Signals IF: 540 MHz Output5 IF: 900 MHz Output6 RF: 900 MHz Output6 RF: 1750 MHz Output7 RF: 2400 MHz Output8 B Version B Chips 2 Unit Test Conditions/Comments −170 −162 −170 −162 dBc/Hz typ dBc/Hz typ −89 −87 −89 −84 −87 −89 −87 −89 −84 −87 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ 25 kHz PFD frequency 200 kHz PFD frequency VCO output 1 kHz offset and 200 kHz PFD frequency 1 kHz offset and 200 kHz PFD frequency 1 kHz offset and 200 kHz PFD frequency 1 kHz offset and 200 kHz PFD frequency 1 kHz Offset and 1 MHz PFD frequency −88/−90 −90/−94 −90/−94 −80/−82 −80/−82 −88/−90 −90/−94 −90/−94 −80/−82 −80/−82 dB typ dB typ dB typ dB typ dB typ 200 kHz/400 kHz and 200 kHz PFD frequency 200 kHz/400 kHz and 200 kHz PFD frequency 200 kHz/400 kHz and 200 kHz PFD frequency 200 kHz/400 kHz and 200 kHz PFD frequency 200 kHz/400 kHz and 200 kHz PFD frequency Operating temperature range is as follows: B version: −40°C to +85°C. The B Chip specifications are given as typical values. 3 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). See Figure 9. 4 The phase noise is measured with the EVAL-ADF4212EB and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz at 0 dBm). 5 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; loop B/W = 20 kHz 6 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz 7 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz 8 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 2400 MHz; N = 9800; loop B/W = 20 kHz 1 2 Rev. E | Page 4 of 28 Data Sheet ADF4212L TIMING CHARACTERISTICS VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 3. Parameter 1 t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time Data to clock setup time Data to clock hold time Clock high duration Clock low duration Clock to LE setup time LE pulse width Guaranteed by design but not production tested. t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 02774-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. E | Page 5 of 28 ADF4212L Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter1, 2 VDD1 to GND VDD1 to VDD2 VP1, VP2 to GND VP1, VP2 to VDD1, VDD2 Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN, IFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) LFCSP θJA Thermal Impedance (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +3.6 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to DVDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 150.4°C/W 122°C/W 216°C/W 215°C 220°C This device is a high performance RF integrated circuit with an ESD rating of