ADF4252BCP

a FEATURES 3.0 GHz Fractional-N/1.2 GHz Integer-N 2.7 V to 3.3 V Power Supply Separate V P Allows Extended Tuning Voltage to 5 V Programmable Dual Modulus Prescaler RF: 4/5, 8/9 IF: 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents 3-Wire Serial Interface Digital Lock Detect Power-Down Mode Programmable Modulus on Fractional-N Synthesizer Trade-Off Noise versus Spurious Performance APPLICATIONS Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications Test Equipment CATV Equipment Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 GENERAL DESCRIPTION The ADF4252 is a dual fractional-N/integer-N frequency synthesizer that can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Both the RF and IF synthesizers consist of a low noise digital PFD (phase frequency detector), a precision charge pump, and a programmable reference divider. The RF synthesizer has a - -based fractional interpolator that allows programmable fractional-N division. The IF synthesizer has programmable integer-N counters. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 VDD3 DVDD VP1 VP2 RSET ADF4252 REFERENCE 4-BIT R COUNTER REFIN 2 DOUBLER PHASE FREQUENCY DETECTOR CHARGE PUMP CPRF REFOUT LOCK DETECT RFINA RFINB MUXOUT OUTPUT MUX FRACTIONAL N RF DIVIDER CLK DATA LE 24-BIT DATA REGISTER INTEGER N IF DIVIDER IFINB IFINA 2 DOUBLER 15-BIT R COUNTER PHASE FREQUENCY DETECTOR CHARGE PUMP CPIF R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. AGND1 AGND2 DGND CPGND1 CPGND2 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. V 3 3 R referred TT ADF4252–SPECIFICATIONS1 (V 1==2.7 k2 =, VdBm = DV = to V50 1,0%,=DV DD DD DD DD SET A DD MIN < VP1, VP2 < 5.5 V, GND = 0 V, to TMAX, unless otherwise noted.) Parameter RF CHARACTERISTICS RF Input Frequency (RFINA, RFINB)2 RF Input Sensitivity RF Input Frequency (RFINA, RFINB)2 RF Phase Detector Frequency Allowable Prescaler Output Frequency IF CHARACTERISTICS IF Input Frequency (IFINA, IFINB)2 IF Input Sensitivity IF Phase Detector Frequency Allowable Prescaler Output Frequency REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Current REFIN Input Capacitance CHARGE PUMP RF ICP Sink/Source IF ICP Sink/Source High Value Low Value High Value Low Value B Version 0.25/3.0 –10/0 0.1/3.0 30 375 50/1200 –10/0 55 150 250 0.5/VDD1 ± 100 10 4.375 625 5 625 1 2 1.5/1.6 2 2 2 1.35 0.6 ±1 10 VDD – 0.4 0.4 2.7/3.3 VDD1 VDD1/5.5 13 10 4 1 –141 –90 –95 –103 Unit GHz min/max dBm min/max GHz min/max MHz max MHz max MHz min/max dBm min/max MHz max MHz max MHz max V p-p min/max µA max pF max mA typ µA typ mA typ µA typ nA typ % typ k typ % typ % typ % typ V min V max µA max pF max V min V max V min/V max V min/V max mA typ mA typ mA typ µA typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Test Conditions/Comments Input Level = –8/0 dBm min/max Guaranteed by Design Guaranteed by Design For f < 10 MHz, use dc-coupled square wave (0 to VDD). AC-coupled. When dc-coupled, use 0 to VDD max (CMOS compatible). See Table V See Table IX ICP Three-State Leakage Current RF Sink and Source Current Matching RSET Range IF Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1, VDD2, VDD3 DVDD VP1, VP2 IDD3 Power-Down Mode RF NOISE AND SPURIOUS CHARACTERISTICS Noise Floor In-Band Phase Noise Performance4 Lowest Spur Mode Low Noise and Spur Mode Lowest Noise Mode Spurious Signals 0.5 V < VCP < VP – 0.5 See Table V 0.5 V < VCP < VP – 0.5 VCP = VP /2 IOH = 0.2 mA IOL = 0.2 mA RF + IF RF Only IF Only 16 mA max 13 mA max 5.5 mA max @ 20 MHz PFD Frequency @ VCO Output RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz RFOUT = 1.8 GHz, PFD = 20 MHz See Typical Performance Characteristics NOTES 1 Operating Temperature Range (B Version): –40 °C to +85 °C. 2 Use a square wave for frequencies less than f MIN. 3 RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, V DD = 3 V, VP1 = 5 V, and VP2 = 3 V. 4 The in-band phase noise is measured with the EVAL-ADF4252EB2 evaluation board and the HP5500E phase noise test system. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). fOUT = 1.74 GHz, fREF = 20 MHz, N = 87, Mod = 100, Channel Spacing = 200 kHz, V DD = 3.3 V, and VP = 5 V. Specifications subject to change without notice. –2– R EV. B ADF4252 TIMING CHARACTERISTICS* unless otherwise noted.) Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 10 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min (VDD1 = VDD2 = VDD3 = DVDD = 3 V 10%, DVDD < VP1, VP2 < 5.5 V, GND = 0 V, Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width *Guaranteed by design, but not production tested. t4 CLOCK t5 t2 DATA DB23 (MSB) DB22 t3 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) LE t1 t7 t6 LE Figure 1. Timing Diagram R EV. B –3– ADF4252 ABSOLUTE MAXIMUM RATINGS 1, 2 ORDERING GUIDE Mode Temperature Range Package Option* VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C CSP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 122°C/W Soldering Reflow Temperature Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of 91, P = 8/9 should be used for optimum noise performance. Filter Design—ADIsimPLL SCLK DT TFS SCLK SDATA LE CE A filter design and analysis program is available to help users implement their PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. INTERFACING I/O FLAGS MUXOUT (LOCK DETECT) ADSP-21xx The ADF4252 has a simple SPI compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Control Bit Truth Table. The maximum allowable serial clock rate is 20 MHz, which means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 µs. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. ADF4252 Figure 9. ADSP-21xx to ADF4252 Interface ADSP-2181 Interface SCLOCK MOSI SCLK SDATA LE Figure 9 shows the interface between the ADF4252 and the ADSP-21xx digital signal processor. Each latch of the ADF4252 needs (at most) a 24-bit word. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE I/O PORTS CE MUXOUT (LOCK DETECT) The leads on the chip scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This will ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz copper to plug the via. The user should connect the printed circuit board to AGND. ADuC812 ADF4252 Figure 8. ADuC812 to ADF4252 Interface ADuC812 Interface Figure 8 shows the interface between the ADF4252 and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The microconverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4252 needs (at most) a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third R EV. B –25– ADF4252 VVCO R48 0 VP R44 0 VDD R1 20 VDD’ C3 22 F IFOUT J6 C9 22 F C5 22 F R43 0 C7 22 F C11 22 F C29 22 F RFOUT J7 VP VVCO R49 0 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V C4 10pF C10 10pF C6 10pF DVDD VDD1 VDD2 VDD3 C8 10pF C12 10pF C30 10pF C15 100pF R12 18 R13 C16 18 100pF R14 18 R15 51 14 VCC 10 RF OUT VIN 2 R17 13k C20 82pF C19 2.2nF R16 7.5k C18 270pF VP2 CPIF U1 VP1 CPRF C23 10nF C24 100nF R19 270 14 R20 470 C25 3.3nF VCC 2V IN RFOUT 10 C27 100pF R22 18 C26 R21 100pF 18 R23 18 R24 51 C28 100pF VCO2 VCO190–540T ADF4252BCP CPGND1 IFINA RFINA RFINB VCO1 VCO190–1730T C17 100pF REFIN T13 J5 5V C13 1nF R11 51 C14 1nF C43 100pF R27 2.7k LE MUXOUT AGND1 DGND AGND2 CPGND2 T14 C44 100pF R27 10k T16 R28 10k VDD R29 10k D4 R45 0 3V R46 0 R47 0 3 O/P 4 B+ GND Y3 C32 33pF 2 DATA CLK C46 22 F C45 10pF Y2 10MHz C31 33pF R4 1M R26 1k R39 0 REFOUT J8 4 R38 0 1 U6 2 VCC 3V R34 0 5V R35 0 Figure 10. Typical PLL Circuit Schematic –26– R EV. B ADF4252 OUTLINE DIMENSIONS 24-Lead Lead Frame Chip Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters 4.0 BSC SQ 0.60 MAX 0.60 MAX 19 18 24 1 PIN 1 INDICATOR 2.25 2.10 SQ 1.95 7 6 PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 BOTTOM VIEW 13 12 0.25 MIN 2.50 REF 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 R EV. B –27– ADF4252 Revision History Location 10/03—Data Sheet changed from REV. A to REV. B. Page Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Inserted Lock Detect section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 C02946–0–10/03(B) –28– R EV. B