ADF4360-9BCPZRL7

Clock Generator PLL with Integrated VCO ADF4360-9 Data Sheet FEATURES GENERAL DESCRIPTION Primary output frequency range: 65 MHz to 400 MHz Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Software power-down mode The ADF4360-9 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). External inductors set the ADF4360-9 center frequency. This allows a VCO frequency range of between 65 MHz and 400 MHz. An additional divider stage allows division of the VCO signal. The CMOS level output is equivalent to the VCO signal divided by the integer value between 2 and 31. This divided signal can be further divided by 2, if desired. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS System clock generation Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD RSET ADF4360-9 REFIN CLK DATA LE LD 14-BIT R COUNTER 24-BIT DATA REGISTER LOCK DETECT 24-BIT FUNCTION LATCH MUTE PHASE COMPARATOR CHARGE PUMP CP VVCO VTUNE L1 L2 CC CN VCO CORE 13-BIT B COUNTER OUTPUT STAGE RFOUTA RFOUTB N=B DIVIDE-BY-A (2 TO 31) DIVIDE-BY-2 AGND DGND CPGND DIVOUT 07139-001 MULTIPLEXER Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com ADF4360-9 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 10 Applications ....................................................................................... 1 VCO ............................................................................................. 11 General Description ......................................................................... 1 Output Stage................................................................................ 12 Functional Block Diagram .............................................................. 1 DIVOUT Stage............................................................................ 12 Revision History ............................................................................... 2 Latch Structure ........................................................................... 13 Specifications..................................................................................... 3 Power-Up ..................................................................................... 17 Timing Characteristics ................................................................ 5 Control Latch .............................................................................. 18 Absolute Maximum Ratings............................................................ 6 N Counter Latch ......................................................................... 19 Transistor Count ........................................................................... 6 R Counter Latch ......................................................................... 19 ESD Caution .................................................................................. 6 Applications Information .............................................................. 20 Pin Configuration and Function Descriptions ............................. 7 Choosing the Correct Inductance Value ................................. 20 Typical Performance Characteristics ............................................. 8 Encode Clock for ADC.............................................................. 20 Circuit Description ......................................................................... 10 GSM Test Clock .......................................................................... 21 Reference Input Section ............................................................. 10 Interfacing ................................................................................... 22 N Counter .................................................................................... 10 PCB Design Guidelines for Chip Scale Package .................... 22 R Counter .................................................................................... 10 Output Matching ........................................................................ 23 PFD and Charge Pump .............................................................. 10 Outline Dimensions ....................................................................... 24 Lock Detect ................................................................................. 10 Ordering Guide .......................................................................... 24 REVISION HISTORY 5/2016—Rev. C to Rev. D Changed ADF4360 Family to ADF4360-9 and ADSP-21xx to ADSP-2181 ........................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 11/2012—Rev. B to Rev. C Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 24 2/2012—Rev. A to Rev. B Added EPAD Note ............................................................................ 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/2008—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Figure 23 ...................................................................... 14 Changes to Output Matching Section .......................................... 23 1/2008—Revision 0: Initial Version Rev. D | Page 2 of 24 Data Sheet ADF4360-9 SPECIFICATIONS AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency B Version Unit Test Conditions/Comments 10/250 MHz min/MHz max 0.7/AVDD 0 to AVDD 5.0 ±60 V p-p min/V p-p max V max pF max µA max For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave, slew rate > 21 V/µs AC-coupled CMOS-compatible 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.5 2 mA typ mA typ kΩ min/kΩ max nA typ % typ % typ % typ 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD − 0.4 500 0.4 V min µA max V max 3.0/3.6 AVDD AVDD 5 2.5 12.0 3.5 to 11.0 7 V min/V max 400 MHz Minimum VCO Output Frequency VCO Output Frequency 65 90/108 MHz MHz min/MHz max VCO Frequency Range VCO Sensitivity 1.2 2 Ratio MHz/V typ Lock Time 6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) 400 0.24 10 −16 µs typ MHz/V typ Hz typ dBc typ REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 2 CHARGE PUMP ICP Sink/Source 3 High Value Low Value RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output High Current, IOH Output Low Voltage, VOL POWER SUPPLIES AVDD DVDD VVCO AIDD 4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode4 RF OUTPUT CHARACTERISTICS5 Maximum VCO Output Frequency With RSET = 4.7 kΩ mA typ mA typ mA typ mA typ µA typ Rev. D | Page 3 of 24 1.25 V ≤ VCP ≤ 2.5 V 1.25 V ≤ VCP ≤ 2.5 V VCP = 2.0 V CMOS output chosen IOL = 500 µA ICORE = 5 mA RF output stage is programmable ICORE = 5 mA; depending on L1 and L2; see the Choosing the Correct Inductance Value section L1, L2 = 270 nH; see the Choosing the Correct Inductance Value section for other frequency values fMAX/fMIN L1, L2 = 270 nH; see the Choosing the Correct Inductance Value section for other sensitivity values To within 10 Hz of final frequency Into 2.00 VSWR load ADF4360-9 Parameter Harmonic Content (Third) Output Power5, 7 Data Sheet B Version −21 −9/0 Unit dBc typ dBm typ −14/−9 dBm typ Output Power Variation VCO Tuning Range VCO NOISE CHARACTERISTICS VCO Phase Noise Performance 9,10 ±3 1.25/2.5 dB typ V min/V max −91 −117 −139 −140 −147 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ At 10 kHz offset from carrier At 100 kHz offset from carrier At 1 MHz offset from carrier At 3 MHz offset from carrier At 10 MHz offset from carrier Normalized In-Band Phase Noise 10, 11 In-Band Phase Noise10, 11 RMS Integrated Jitter 12 Spurious Signals Due to PFD Frequency 13 DIVOUT CHARACTERISTICS12 Integrated Jitter Performance (Integrated from 100 Hz to 1 GHz) DIVOUT = 180 MHz DIVOUT = 95 MHz DIVOUT = 80 MHz DIVOUT = 52 MHz −218 −110 1.4 −75 dBc/Hz typ dBc/Hz typ ps typ dBc typ At 1 kHz offset from carrier Measured at RFOUTA Output Power5, 8 DIVOUT = 45 MHz DIVOUT = 10 MHz DIVOUT Duty Cycle A Output A/2 Output Test Conditions/Comments Using tuned load, programmable in 3 dB steps; see Figure 35 Using 50 Ω resistors to VVCO, programmable in 3 dB steps; see Figure 33 VCO frequency = 320 MHz to 380 MHz 1.4 1.4 1.4 1.4 ps rms ps rms ps rms ps rms 1.4 1.6 ps rms ps rms 1/A × 100 50 % typ % typ A = 2, A output selected A = 2, A/2 output selected A = 2, A/2 output selected A = 3, A/2 output selected (VCO = 312 MHz, PFD = 1.6 MHz) A = 4, A/2 output selected A = 18, A/2 output selected (VCO = 360 MHz, PFD = 1.6 MHz) Divide-by-A selected Divide-by-A/2 selected Operating temperature range is −40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V. 5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2. 6 Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 For more detail on using tuned loads, see the Output Matching section. 8 Using 50 Ω resistors to VVCO into a 50 Ω load. 9 The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH. 10 The phase noise is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. 11 fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value) and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN. 12 The jitter is measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz, unless otherwise noted. 13 The spurious signals are measured with the EV-ADF4360-9EB1Z evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFIN = 10 MHz at 0 dBm. fREFIN = 10 MHz; fPFD = 1 MHz; N = 360; loop bandwidth = 40 kHz. 1 2 3 Rev. D | Page 4 of 24 Data Sheet ADF4360-9 TIMING CHARACTERISTICS 1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Refer to the Power-Up section for the recommended power-up procedure for this device. t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 07139-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. D | Page 5 of 24 ADF4360-9 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital Input/Output Voltage to GND Analog Input/Output Voltage to GND REFIN to GND Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Lead Temperature, Soldering Reflow 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to + 85°C −65°C to +150°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of