ADG3308BRUZ

FEATURES FUNCTIONAL BLOCK DIAGRAM VCCA Bidirectional logic level translation Operates from 1.15 V to 5.5 V Low quiescent current < 1 μA No direction pin VCCY ADG3308/ADG3308-1 A1 Y1 APPLICATIONS A2 Y2 Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communication devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 EN GND 04865-001 Data Sheet Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators ADG3308/ADG3308-1 Figure 1. GENERAL DESCRIPTION The ADG3308/ADG3308-1 are bidirectional level translators containing eight bidirectional channels. They can be used in multivoltage digital system applications, such as a data transfer between a low voltage DSP controller and a higher voltage device. The internal architecture allows the device to perform bidirectional level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCCA sets the logic levels on the A side of the device, and VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA compatible logic signals applied to the A side of the device appear as VCCY compatible levels on the Y side. Similarly, VCCY compatible logic levels applied to the Y side of the device appear as VCCA compatible logic levels on the A side. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. For normal operation, EN should be driven high. Rev. E The ADG3308 is available in a compact 20-lead TSSOP and a 20-lead LFCSP. The ADG3308-1 is available in a 20-ball WLCSP. The EN pin is referred to the VCCY supply voltage for the ADG3308 and to the VCCA supply voltage for the ADG3308-1. The ADG3308/ADG3308-1 are guaranteed to operate over the 1.15 V to 5.5 V supply voltage range and the extended −40°C to +85°C temperature range. PRODUCT HIGHLIGHTS 1. Bidirectional logic level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308) and 20-ball WLCSP (ADG3308-1). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG3308/ADG3308-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Level Translator Architecture ................................................... 16 Functional Block Diagram .............................................................. 1 Input Driving Requirements ..................................................... 16 General Description ......................................................................... 1 Output Load Requirements ...................................................... 16 Product Highlights ........................................................................... 1 Enable Operation ....................................................................... 16 Revision History ............................................................................... 2 Power Supplies ............................................................................ 16 Specifications..................................................................................... 3 Data Rate ..................................................................................... 17 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 18 ESD Caution .................................................................................. 6 Layout Guidelines....................................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 20 Test Circuits ..................................................................................... 12 Terminology .................................................................................... 15 REVISION HISTORY 3/16—Rev. D to Rev. E Changed CP-20-1 to CP-20-6 ...................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 10/13—Rev. C to Rev. D Removed ADG3308-2 (Throughout) ............................................ 1 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 9/07—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 19 7/07—Rev. A to Rev. B Added Backside-Coated WLCSP Package ...................... Universal Changes to Input Driving Requirements Section ...................... 16 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 7/06—Rev. 0 to Rev. A Added WLCSP Package…………………………..……Universal Added Figure 4………………………………………………......7 Updated Outline Dimensions……………………………….…19 Changes to Ordering Guide………………………………....…19 1/05—Revision 0: Initial Version Rev. E | Page 2 of 20 Data Sheet ADG3308/ADG3308-1 SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Y Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Enable (EN) Input High Voltage3 ADG3308 (TSSOP, LFCSP) ADG3308-1 (WLCSP) Input Low Voltage3 ADG3308 (TSSOP, LFCSP) ADG3308-1 (WLCSP) Leakage Current Capacitance3 Enable Time3 SWITCHING CHARACTERISTICS3 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions Min VIHA VIHA VILA VOHA VOLA CA ILA, HIGH-Z VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 0.65 × VCCA VY = VCCY, IOH = 20 μA, see Figure 29 VY = 0 V, IOL = 20 μA, see Figure 29 f = 1 MHz, EN = 0, see Figure 34 VA = 0 V or VCCA, EN = 0, see Figure 31 VCCA − 0.4 VIHY VILY VOHY VOLY CY ILY, HIGH-Z Typ2 Max 0.35 × VCCA 0.4 10 ±1 0.65 × VCCY 0.35 × VCCY VA = VCCA, IOH = 20 μA, see Figure 30 VA = 0 V, IOL = 20 μA, see Figure 30 f = 1 MHz, EN = 0, see Figure 35 VY = 0 V or VCCY, EN = 0, see Figure 32 VCCY − 0.4 0.4 6.8 ±1 Unit V V V V V pF μA V V V V pF μA VIHEN VCCA = 1.15 V VCCA = 1.2 V to 5.5 V 0.65 × VCCY VCCA − 0.3 0.65 × VCCA V V V VILEN ILEN CEN tEN 0.35 × VCCY 0.35 × VCCA ±1 VEN = 0 V or VCCY, VA = 0 V, see Figure 33 RS = RT = 50 Ω, VA = 0 V or VCCA (A→Y), VY = 0 V or VCCY (Y→A), see Figure 36 V V μA pF μs 4.5 1 1.8 6 2 2 10 3.5 3.5 2 4 3 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 4 7 ns 1 3 ns 3 7 2 3.5 2 ns Mbps ns ns 50 Rev. E | Page 3 of 20 ADG3308/ADG3308-1 Parameter 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Data Sheet Symbol Conditions Min Typ2 Max Unit 8 11 ns 2 2 5 5 2 4 4 ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 5 8 ns 2 2 3.5 3.5 2 3 ns ns Mbps ns 3 ns 9 3 2 18 5 5 2 5 10 ns ns ns Mbps ns ns 5 2 2 9 4 4 2 4 4 12 7 3 25 12 5 2 5 15 ns ns ns Mbps ns ns 14 5 2.5 35 16 6.5 ns ns ns 6.5 23.5 Mbps ns ns 50 RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 40 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 25 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 25 3 Rev. E | Page 4 of 20 Data Sheet Parameter 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current ADG3308/ADG3308-1 Symbol Min Typ2 Max Unit 7 10 ns 2.5 2 4 5 1.5 2 4 ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 60 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A VCCA VCCY ICCA ICCY Three-State Mode Power Supply Current Conditions IHIGH-ZA IHIGH-ZY 5 8 ns 1 3 4 5 2 3 ns ns Mbps ns 3 ns 0.17 5.5 5.5 1 V V μA 0.27 1 μA 0.1 0.1 1 1 μA μA 60 VCCA ≤ VCCY VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 1 Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP. All typical values are at TA = 25°C, unless otherwise noted. 3 Guaranteed by design; not subject to production test. 2 Rev. E | Page 5 of 20 1.15 1.65 ADG3308/ADG3308-1 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Extended Industrial Range (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance 20-Lead TSSOP 20-Lead LFCSP 20-Ball WLCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (