ADG442BN

a FEATURES 44 V Supply Maximum Ratings VSS to VDD Analog Signal Range Low On Resistance (< 70 Ω) Low ∆RON (9 Ω max) Low RON Match (3 Ω max) Low Power Dissipation Fast Switching Times tON < 110 ns tOFF < 60 ns Low Leakage Currents ( 3 nA max) Low Charge Injection (6 pC max) Break-Before-Make Switching Action Latch-Up Proof Plug-In Upgrade for DG201A/ADG201A, DG202A/ADG202A, DG211/ADG211A Plug in Replacement for DG441/DG442/DG444 APPLICATIONS Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Battery Powered Systems Sample Hold Systems Communication Systems GENERAL DESCRIPTION IN1 LC2MOS Quad SPST Switches ADG441/ADG442/ADG444 FUNCTIONAL BLOCK DIAGRAMS S1 IN1 D1 S2 IN2 IN2 D1 S2 S1 ADG441 ADG444 IN3 D2 S3 IN3 D3 S4 ADG442 D2 S3 D3 S4 IN4 IN4 D4 D4 SWITCHES SHOWN FOR A LOGIC "1" INPUT Each switch conducts equally well in both directions when ON and has an input signal range that extends to the power supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS The ADG441, ADG442 and ADG444 are monolithic CMOS devices comprising four independently selectable switches. They are designed on an enhanced LC2MOS process that provides low power dissipation yet gives high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range ensuring good linearity and low distortion when switching audio signals. High switching speed also makes the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments. The ADG441, ADG442 and ADG444 contain four independent SPST switches. Each switch of the ADG441 and ADG444 turns on when a logic low is applied to the appropriate control input. The ADG442 switches are turned on with a logic high on the appropriate control input. The ADG441 and ADG444 switches differ in that the ADG444 requires a 5 V logic power supply which is applied to the VL pin. The ADG441 and ADG442 do not have a VL pin, the logic power supply being generated internally by an on-chip voltage generator. 1. Extended Signal Range The ADG441/ADG442/ADG444 are fabricated on an enhanced LC2MOS, trench-isolated process, giving an increased signal range that extends to the supply rails. 2. Low Power Dissipation 3. Low RON 4. Trench Isolation Guards Against Latch Up A dielectric trench separates the P and N channel transistors thereby preventing latch up even under severe overvoltage conditions. 5. Break-Before-Make Switching This prevents channel shorting when the switches are configured as a multiplexer. 6. Single Supply Operation For applications where the analog signal is unipolar, the ADG441/ADG442/ADG444 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADG441/ADG442/ADG444–SPECIFICATIONS1 Dual Supply (V DD = +15 V ± 10%, VSS = –15 V ± 10%, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted) B Version –40°C to +25°C +85°C VSS to VDD 40 70 85 4 9 1 3 40 70 T Version –55°C to +25°C +125°C VSS to VDD 85 4 9 1 3 Parameter ANALOG SWITCH Analog Signal Range RON ∆RON RON Match LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ADG441/ADG442 ADG444 ISS IL (ADG444 Only) Units V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max ns typ ns max ns typ ns max ns typ pC typ pC max dB typ dB typ pF typ pF typ pF typ Test Conditions/Comments VD = ± 8.5 V, IS = –10 mA VDD = +13.5 V, VSS = –13.5 V –8.5 V ≤ VD ≤ +8.5 V VD = 0 V, IS = –10 mA VDD = +16.5 V, VSS = –16.5 V VD = ± 15.5 V, VS = 15.5 V; Test Circuit 2 VD = ± 15.5 V, VS = 15.5 V; Test Circuit 2 VS = VD = ± 15.5 V; Test Circuit 3 ± 0.01 ± 0.5 ± 0.01 ± 0.5 ± 0.08 ± 0.5 ±3 ±3 ±3 2.4 0.8 ± 0.00001 ± 0.5 ± 0.01 ± 0.5 ± 0.01 ± 0.5 ± 0.08 ± 0.5 ± 20 ± 20 ± 40 2.4 0.8 ± 0.00001 ± 0.5 VIN = VINL or VINH 85 110 45 60 30 1 6 60 100 4 4 16 170 80 85 110 45 60 30 1 6 60 100 4 4 16 170 80 RL = 1 kΩ, CL = 35 pF; VS = ± 10 V; Test Circuit 4 RL = 1 kΩ, CL = 35 pF; VS = ± 10 V; Test Circuit 4 RL = 1 kΩ, CL = 35 pF; VS = 0 V, RS = 0 Ω, CL= 1 nF; VDD = +15 V, VSS = –15 V; Test Circuit 5 RL = 50 Ω, CL = 5 pF; f = 1 MHz; Test Circuit 6 RL = 50 Ω, CL = 5 pF; f = 1 MHz; Test Circuit 7 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = –16.5 V Digital Inputs = 0 V or 5 V 80 0.001 1 0.0001 1 0.001 2.5 2.5 0.001 1 0.0001 1 0.001 80 2.5 2.5 µA max µA typ µA max µA typ µA max µA typ 1 2.5 1 2.5 µA max VL = +5.5 V NOTES 1 Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55 °C to +125°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG441/ADG442/ADG444 Single Supply (V Parameter ANALOG SWITCH Analog Signal Range RON ∆RON RON Match LEAKAGE CURRENT Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF tOPEN Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ADG441/ADG442 ADG444 IL (ADG444 Only) DD = +12 V ± 10%, VSS = 0 V, VL = +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted) B Version –40°C to +25°C +85°C 0 to VDD 70 110 130 4 9 1 3 70 110 T Version –55°C to +25°C +125°C 0 to VDD 130 4 9 1 3 Units V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max ns typ ns max ns typ ns max ns typ pC typ pC max dB typ dB typ pF typ pF typ pF typ Test Conditions/Comments VD = +3 V, +8 V, IS = –10 mA; VDD = +10.8 V +3 V ≤ VD ≤ +8 V VD = 6 V, IS = –10 mA VDD = +13.2 V VD = 12.2 V/1 V, VS = 1 V/12.2 V; Test Circuit 2 VD = 12.2 V/1 V, VS = 1 V/12.2 V; Test Circuit 2 VS = VD = 12.2 V/1 V; Test Circuit 3 ± 0.01 ± 0.5 ± 0.01 ± 0.5 ± 0.08 ± 0.5 ±3 ±3 ±3 2.4 0.8 ± 0.00001 ± 0.5 ± 0.01 ± 0.5 ± 0.01 ± 0.5 ± 0.08 ± 0.5 ± 20 ± 20 ± 40 2.4 0.8 ± 0.00001 ± 0.5 VIN = VINL or VINH 105 150 40 60 50 2 6 60 100 7 10 16 220 100 105 150 40 60 50 2 6 60 100 7 10 16 220 100 RL = 1 kΩ, CL = 35 pF; VS = +8 V; Test Circuit 4 RL = 1 kΩ, CL = 35 pF; VS = +8 V; Test Circuit 4 RL = 1 kΩ, CL = 35 pF; VS = 6 V, RS = 0 Ω, CL = 1 nF; VDD = +12 V, VSS = 0 V; Test Circuit 5 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +13.2 V Digital Inputs = 0 V or 5 V 80 0.001 1 0.001 1 2.5 2.5 0.001 1 0.001 1 80 2.5 2.5 µA max µA typ µA max µA typ µA max VL = +5.5 V NOTES 1 Temperature ranges are as follows: B Versions: –40 °C to +85°C; T Versions: –55 °C to +125 °C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. ORDERING GUIDE Table I. Truth Table Model1 Switch Condition ON OFF ADG441BN ADG441BR ADG441TQ ADG442BN ADG442BR ADG444BN ADG444BR NOTES 1 Temperature Range –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option2 N-16 R-16A Q-16 N-16 R-16A N-16 R-16A ADG441/ADG444 IN 0 1 ADG442 IN 1 0 To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers. 2 N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip. REV. 0 –3– ADG441/ADG442/ADG444 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) TERMINOLOGY VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Analog, Digital Inputs2 . . . . . . . . . . . . VSS – 2 V to VDD + 2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +300°C Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 177°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +260°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 77°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C NOTES Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. 1 VDD VSS VL GND S D IN RON RON Match IS (OFF) ID (OFF) ID, IS (ON) VD ( V S ) CS (OFF) CD (OFF) CD, CS (ON) tON tOFF tOPEN Crosstalk Off Isolation Charge Injection Most Positive Power Supply Potential. Most Negative Power Supply Potential in dual supplies. In single supply applications, it may be connected to ground. Logic Power Supply (+5 V). Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. Difference between the RON of any two channels. Source leakage current with the switch “OFF.” Drain leakage current with the switch “OFF.” Channel leakage current with the switch “ON.” Analog voltage on terminals D, S. “OFF” Switch Source Capacitance. “OFF” Switch Drain Capacitance. “ON” Switch Capacitance. Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. Break-Before-Make Delay when switches are configured as a multiplexer. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an “OFF” switch. A measure of the glitch impulse transferred from the digital input to the analog output during switching. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ADG441/ADG442 PIN CONFIGURATION (DIP/SOIC) ADG444 PIN CONFIGURATION (DIP/SOIC) IN1 D1 S1 VSS GND S4 D4 IN4 1 2 3 4 5 6 7 8 16 IN2 15 D2 14 S2 IN1 D1 S1 VSS GND S4 D4 IN4 1 2 3 4 5 6 7 8 16 IN2 15 D2 ADG441 ADG442 14 S2 13 VDD ADG444 13 VDD TOP VIEW 12 NC (Not to Scale) 11 S3 10 D3 9 IN3 TOP VIEW 12 VL (Not to Scale) 11 S3 10 D3 9 IN3 NC = NO CONNECT –4– REV. 0 ADG441/ADG442/ADG444 TRENCH ISOLATION In the ADG441, ADG442 and ADG444, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, the result being a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A silicon-controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current which, in turn, leads to latch up. With trench isolation, this diode is removed, the result being a latch-up proof switch. Trench isolation also leads to lower leakage currents. The ADG441, ADG442 and ADG444 have a leakage current of 0.5 nA as compared with a leakage current of several nanoamperes in non-trench isolated switches. Leakage current is an important parameter in sample-and-hold circuits, this current being responsible for the discharge of the holding capacitor with time causing droop. The ADG441/ADG442/ADG444’s low leakage current, along with its fast switching speeds, make it suitable for fast and accurate sample-and-hold circuits. NMOS PMOS LOCOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER SUBSTRATE (BACK GATE) Figure 1. Trench Isolation Typical Performance Characteristics 100 TA = +25°C VDD = +5V VSS = –5V 170 150 130 110 V DD = +12V V SS = 0V V DD = +10V V SS = 0V V DD = +5V V SS = 0V TA = +25°C 80 RON – Ω RON – Ω 60 VDD = +12V VSS = –12V VDD = +10V VSS = –10V 90 70 40 VDD = +15V VSS = –15V 20 –15 –10 –5 0 VD (V S) – Volts 5 10 15 50 30 10 0 3 6 9 VD (V S) – Volts 12 15 VDD = +15V VSS = 0V Figure 2. RON as a Function of VD (VS): Dual Supply Figure 3. RON as a Function of VD (VS): Single Supply REV. 0 –5– ADG441/ADG442/ADG444 100 VDD = +15V VSS = –15V 80 120 VDD = +12V VSS = 0V 100 +125°C R ON – Ω +125°C 60 R ON – Ω 80 +85°C 60 +25°C +85°C 40 +25°C 40 20 –15 20 –10 –5 0 VD (V S) – Volts 5 10 15 0 2 4 6 VD (V S) – Volts 8 10 12 Figure 4. RON as a Function of VD (VS) for Different Temperatures 0.02 V DD = +15V V SS = –15V T A = +25° C Figure 7. RON as a Function of VD (VS) for Different Temperatures 0.010 V DD = +12V V SS = 0V T A = +25°C ID (OFF) LEAKAGE CURRENT – nA LEAKAGE CURRENT – nA 0.01 0.005 ID (ON) IS (OFF) 0.000 0.00 ID (ON) IS (OFF) ID (OFF) –0.005 –0.01 –0.02 –15 –0.010 –10 –5 0 VS , V D – Volts 5 10 15 0 2 4 6 VS, VD – Volts 8 10 12 Figure 5. Leakage Currents as a Function of VS (VD) 120 110 V DD = +15V V SS = –15V Figure 8. Leakage Currents as a Function of VS (VD) 20 CL = 1nF 10 100 CROSSTALK 90 Q – pC dB 0 VDD = +15V VSS = –15V V DD = +12V V SS = 0V 80 OFF ISOLATION 70 60 –20 –15 –10 50 1k 10k 100k FREQUENCY – Hz 1M 10M –12 –9 –6 –3 0 3 VS – Volts 6 9 12 15 Figure 6. Crosstalk and Off Isolation vs. Frequency Figure 9. Charge Injection vs. Source Voltage –6– REV. 0 ADG441/ADG442/ADG444 120 VIN = +8V 100 120 160 V IN = +8V 140 tON t – ns 80 tON t – ns 100 80 60 60 tOFF tOFF 40 ±10 ±12 ±16 ±14 SUPPLY VOLTAGE – Volts ±18 ±20 40 20 8 10 12 14 16 SUPPLY VOLTAGE – Volts 18 20 Figure 10. Switching Time vs. Bipolar Supply Figure 11. Switching Time vs. Single Supply Test Circuits IDS V1 S VS RON = V 1 /I DS D VS IS (OFF) A S D ID (OFF) A VD VS S D ID (ON) A VD Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage 0.1µF +15V +5V 0.1µF VIN 3V 50% 50% VDD S VL D RL 1k Ω VOUT CL 35pF ADG441/ADG444 3V VIN ADG442 50% 50% VS IN VSS GND VOUT 0.1µF 90% 90% tON –15V tOFF Test Circuit 4. Switching Times REV. 0 –7– ADG441/ADG442/ADG444 +15V +5V OUTLINE DIMENSIONS Dimensions shown in inches and (mm). VDD RS S VL D CL 1nF PIN 1 1 8 0.25 0.31 (6.35) (7.87) VOUT Plastic DIP (N-16) VS IN VSS GND –15V 3V 0.18 (4.57) 0.87 (22.1) MAX 0.035 (0.89) 0.18 (4.57) MAX 0.011 (0.28) 0.3 (7.62) 0.018 (0.46) 0.033 (0.84) 0.1 (2.54) BSC SEATING PLANE VIN 0.125 (3.18) MIN VOUT QINJ = C L × ∆VOUT ∆VOUT Small Outline IC (R-16A) Test Circuit 5. Charge Injection 16 9 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) +15V 0.1µF +5V 0.1µF PIN 1 1 8 VDD S VL D RL 50 Ω 0.0098 (0.25) 0.0040 (0.10) 0.3937 (10.00) 0.3859 (9.80) 0.0196 (0.50) × 45 ° 0.0099 (0.25) 0° – 8 ° VOUT 0.0688 (1.75) 0.0532 (1.35) 0.0099 (0.25) 0.0075 (0.19) SEATING PLANE IN VS GND VIN 0.1µF –15V VSS 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) 0.0160 (0.41) Cerdip (Q-16) Test Circuit 6. Off Isolation PIN 1 16 9 0.310 (7.87) 0.220 (5.59) +15V 0.1µF +5V 0.1µF 1 0.840 (21.34) MAX 8 VDD S VL D 50 Ω 0.200 (5.08) MAX 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) VIN1 VS VIN2 VOUT RL 50 Ω S GND VSS NC SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.78) 0.30 (0.76) 0.150 (3.81) MIN 0.015 (0.381) 0.008 (0.204) 0.1µF –15V CHANNEL-TO-CHANNEL CROSSTALK = 20 × LOG VS /V OUT  Test Circuit 7. Channel-to-Channel Crosstalk –8– REV. 0 PRINTED IN U.S.A. C1890–18–4/94 16 9 ADG441/ADG442/ADG444 FOR CATALOG ORDERING GUIDE Model1 ADG441BN ADG441BR ADG441TQ ADG442BN ADG442BR ADG444BN ADG444BR Temperature Range –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option2 N-16 R-16A Q-16 N-16 R-16A N-16 R-16A NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers. 2 N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip. For outline information see Package Information section. REV. 0 –9–