ADG613SRUZ-EP

1 pC Charge Injection, 100 pA Leakage, CMOS, ±5 V/5 V/3 V, Quad SPST Switches ADG613-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM 1 pC charge injection ±0.1 nA maximum at 25°C leakage currents 85 Ω on resistance Rail-to-rail switching operation Fast switching times 16-lead TSSOP Typical power consumption: ≤11 nW TTL-/CMOS-compatible inputs VSS to VDD analog signal range ±2.7 V to ±5.5 V dual supply operation 2.7 V to 5.5 V single-supply operation Fully specified at ±5 V, 3 V, and 5 V ADG613-EP S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 D4 14533-001 S4 IN4 Figure 1. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly site 1 test site 1 fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Communications systems Sample-and-hold systems Audio signal routing Relay replacement Avionics GENERAL DESCRIPTION The ADG613-EP is a monolithic CMOS device containing four independently selectable switches. This switch offers ultralow charge injection of 1 pC over the full input signal range and typical leakage currents of 0.01 nA at 25°C. The device is fully specified for ±5 V, 5 V, and 3 V supplies. It contains four independent single-pole, single-throw (SPST) switches. The ADG613-EP contains two switches with digital control logic that turns on with logic low and two switches in which the logic is inverted. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The Rev. A ADG613-EP exhibits break-before-make switching action. The ADG613-EP is available in a small, 16-lead TSSOP package. The ADG613-EP is also a TTL-compatible device. Additional application and technical information can be found in the ADG613 data sheet. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Ultralow charge injection (1 pC typically). Dual ±2.7 V to ±5.5 V or single 2.7 V to 5.5 V operation. Temperature range: −55°C to +125°C. Small, 16-lead TSSOP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 78 1.32 9.47 00 ©2016 Analog Devices, Inc. All rights reserved. Technica l Support www.analog.com ADG613-EP Enhanced Product TABLE OF CONTENTS Features .....................................................................................1 Single-Supply Operation........................................................ 4 Enhanced Product Features .......................................................1 Absolute Maximum Ratings...................................................... 6 Applications...............................................................................1 ESD Caution .......................................................................... 6 Functional Block Diagram.........................................................1 Pin Configuration and Function Descriptions .......................... 7 General Description ..................................................................1 Typical Performance Characteristics ......................................... 8 Product Highlights ....................................................................1 Test Circuits ............................................................................ 10 Revision History ........................................................................2 Outline Dimensions ................................................................ 12 Specifications.............................................................................3 Ordering Guide ................................................................... 12 Dual-Supply Operation..........................................................3 REVISION HISTORY 10/2016—Rev. 0 to Rev. A Changes to Features Section and Enhanced Product Features Section.........................................................................1 6/2016—Revision 0: Initial Revision Rev. A | Page 2 of 12 Enhanced Product ADG613-EP SPECIFICATIONS DUAL-SUPPLY OPERATION VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. VS is the source voltage. VD is the drain voltage. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ΔRON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, I S(OFF) Drain Off Leakage, I D(OFF) Channel On Leakage, I D(ON), I S(ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, I INL or I INH 25°C 85 115 2 4 25 40 ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 −55°C to +125°C Unit VSS to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 160 6.5 60 ±2 ±2 ±6 2.4 0.8 Delay from Digital Control Input and Output Switching Off, t OFF Break-Before-Make Time Delay, tBBM 2 45 ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 0.005 90 ns max ns typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 40 15 50 ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 RL = 50 Ω, CL = 5 pF; see Figure 22 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V −0.5 −65 −90 680 5 5 5 0.001 1.0 Negative Supply Current, I SS 0.001 1.0 ±2.7 ±5.5 VDD/VSS Power Consumption 1 VIN = VINL or VINH VIN = VINL or VINH 65 25 10 Charge Injection Off Isolation Channel to Channel Crosstalk −3 dB Bandwidth Off Switch Source Capacitance, CS(OFF) Off Switch Drain Capacitance, CD(OFF) On Switch Capacitance, CD(ON), CS(ON) POWER REQUIREMENTS Positive Supply Current, I DD VS = ±3 V, I S = −1 mA; see Figure 14 VS = ±3 V, I S = −1 mA; see Figure 14 VS = ±3 V, I S = −1 mA VS = ±3 V, I S = −1 mA VS = ±3 V, I S = −1 mA VS = ±3 V, I S = −1 mA VDD = +5.5 V, VSS = −5.5 V VD = ±4.5 V, VS = +4.5 V; see Figure 15 VD = ±4.5 V, VS = +4.5 V; see Figure 15 VD = ±4.5 V, VS = +4.5 V; see Figure 15 VD = ±4.5 V, VS = +4.5 V; see Figure 15 VD = VS = ±4.5 V; see Figure 16 VD = VS = ±4.5 V; see Figure 16 V min V max μA typ μA max pF typ ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Delay from Digital Control Input and Output Switching On, t ON nA typ nA max nA typ nA max nA typ nA max Test Conditions/Comments 11 11 Guaranteed by design; not subject to production test. Rev. A | Page 3 of 12 μA typ μA max μA typ μA max V min V max nW typ µW max ADG613-EP Enhanced Product SINGLE-SUPPLY OPERATION VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. VS is the source voltage. VD is the drain voltage. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ΔRON LEAKAGE CURRENTS Source Off Leakage, I S(OFF) Drain Off Leakage, I D(OFF) Channel On Leakage, I D(ON), I S(ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, I INL or I INH 25°C −55°C to +125°C Unit Test Conditions/Comments 0 to VDD V Ω typ Ω max Ω typ VS = 3.5 V, I S = −1 mA; see Figure 14 VS = 3.5 V, I S = −1 mA; see Figure 14 VS = 3.5 V, I S = −1 mA 210 290 3 380 10 13 ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±2 nA typ nA max nA typ nA max VS = 3.5 V, I S = −1 mA VDD = 5.5 V VS = 1 V or 4.5 V, VD = 4.5 V or VS = 1 V or 4.5 V, VD = 4.5 V or VS = 1 V or 4.5 V, VD = 4.5 V or VS = 1 V or 4.5 V, VD = 4.5 V or ±6 nA typ nA max VS = VD = 1 V or 4.5 V; see Figure 16 VS = VD = 1 V or 4.5 V; see Figure 16 ±2 2.4 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 t ON t OFF Break-Before-Make Time Delay, t BBM 2 70 100 25 40 25 150 50 10 Charge Injection Off Isolation Channel to Channel Crosstalk −3 dB Bandwidth CS(OFF) CD(OFF) CD(ON), CS(ON) POWER REQUIREMENTS I DD 1 −62 −90 680 5 5 5 0.001 1.0 2.7 5.5 VDD Power Consumption 1 5.5 5.5 Ω max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF typ pF typ μA typ μA max V min V max nW typ µW max Guaranteed by design; not subject to production test. Rev. A | Page 4 of 12 1 V; see Figure 15 1 V; see Figure 15 1 V; see Figure 15 1 V; see Figure 15 VIN = VINL or VINH VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 3.0 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.0 V; see Figure 18 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 RL = 50 Ω, CL = 5 pF; see Figure 22 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or 5.5 V Digital inputs = 0 V or 5.5 V Enhanced Product ADG613-EP VDD = 3 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. VS is the source voltage. VD is the drain voltage. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON LEAKAGE CURRENTS Source Off Leakage, I S(OFF) Drain Off Leakage, I D(OFF) Channel On Leakage, I D(ON), I S(ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, I INL or I INH 25°C −55°C to +125°C Unit 380 0 to VDD 460 V Ω typ ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±2 ±2 ±6 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 t ON t OFF Break-Before-Make Time Delay, t BBM 2 130 185 40 55 50 260 65 10 Charge Injection Off Isolation Channel to Channel Crosstalk −3 dB Bandwidth CS(OFF) CD(OFF) CD(ON), CS(ON) POWER REQUIREMENTS I DD 1.5 −62 −90 680 5 5 5 0.001 1.0 2.7 5.5 VDD Power Consumption 1 3.3 3.3 nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF typ pF typ μA typ μA max V min V max nW typ µW max Guaranteed by design; not subject to production test. Rev. A | Page 5 of 12 Test Conditions/Comments VS = 1.5 V, I S = −1 mA; see Figure 14 VDD = 3.3 V VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 VS = 1 V or 3 V, VD = 3 V or 1 V; see Figure 15 VS = VD = 1 V or 3 V; see Figure 16 VS = VD = 1 V or 3 V; see Figure 16 VIN = VINL or VINH VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS = 2 V; see Figure 17 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V; see Figure 18 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 20 RL = 50 Ω, CL = 5 pF, f = 10 MHz; see Figure 21 RL = 50 Ω, CL = 5 pF; see Figure 22 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 3.3 V Digital inputs = 0 V or 3.3 V Digital inputs = 0 V or 3.3 V ADG613-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 4. Parameter VDD to VSS 1 VDD to GND1 VSS to GND1 Analog Inputs 2 Digital Inputs2 Peak Current, Sx or Dx Continuous Current, Sx or Dx 3 V Operation, 85°C to 125°C Operating Temperature Range Storage Temperature Range Junction Temperature θJA Thermal Impedance 16-Lead TSSOP Lead Soldering Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (