ADG715BRU

FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI/QSPI/MICROWIRE-compatible interface (ADG714) ADG715: I2C-compatible interface (ADG715) 2.7 V to 5.5 V single supply ±2.5 V dual supply 2.5 Ω on resistance 0.6 Ω on resistance flatness 0.1 nA leakage currents Octal SPST Power-on reset Fast switching times TTL/CMOS compatible 24-lead TSSOP and 24-lead LFCSP ADG714 S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 INPUT SHIFT REGISTER 00043-001 DOUT SCLK DIN SYNC RESET APPLICATIONS Figure 1. ADG714 Functional Block Diagram Data acquisition systems Communication systems Relay replacement Audio and video switching ADG715 GENERAL DESCRIPTION The ADG714/ADG715 are complementary metal-oxide semiconductor (CMOS), octal single-pole, single-throw (SPST) switches, controlled via either a 2- or 3-wire serial interface. On resistance is closely matched between the switches and is flat over the full signal range. Each switch conducts equally well in both directions, and the input signal range extends to the supplies. Data is written to these devices in the form of 8 bits, each bit corresponding to one channel. The ADG714 uses a 3-wire serial interface that is compatible with serial peripheral interface (SPI), QSPI™, MICROWIRE™ interface standards, and most digital signal processing (DSP) interface standards. The output of the shift register DOUT enables a number of these devices to be daisy-chained. The ADG715 uses a 2-wire serial interface that is compatible with the I2C interface standard. The ADG715 has four hardwired addresses, selectable from two external address pins (A0 and A1). The pins allow the two LSBs of the 7-bit slave address to be set by the user. A maximum of four of these devices may be connected to the bus. On power-up of these devices, all switches are in the off condition, and the internal registers contain all zeros. S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 INTERFACE LOGIC RESET SDA SCL A0 A1 00043-002 Data Sheet CMOS, Low Voltage Serially Controlled, Octal SPST Switches ADG714/ADG715 Figure 2. ADG715 Functional Block Diagram and the ADG715 is available in a 24-lead TSSOP. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 2- or 3-wire serial interface. Single-/dual-supply operation. The ADG714 and ADG715 are fully specified and guaranteed with 3 V, 5 V, and ±2.5 V supply rails. Low on resistance, typically 2.5 Ω. Low leakage. Power-on reset. A 24-lead TSSOP for both the ADG714 and the ADG715. A 24-lead LFCSP for the ADG714. A low power consumption and operating supply range of 2.7 V to 5.5 V make these devices ideal for many applications. These devices can also be supplied from a dual ±2.5 V supply. The ADG714 is available in a 24-lead TSSOP and a 24-lead LFCSP, Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2000–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADG714/ADG715 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ......................... 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 13 General Description ......................................................................... 1 Terminology .................................................................................... 16 Functional Block Diagrams ............................................................. 1 Theory of Operation ...................................................................... 17 Product Highlights ........................................................................... 1 Power-On Reset .......................................................................... 17 Revision History ............................................................................... 2 Serial Interface ............................................................................ 17 Specifications..................................................................................... 3 Applications Information .............................................................. 19 5 V Single Supply .......................................................................... 3 Multiple Devices on One Bus ................................................... 19 3 V Single Supply .......................................................................... 4 Daisy-Chaining Multiple ADG714 Devices ........................... 19 ±2.5 V Dual Supply ...................................................................... 5 Power Supply Sequencing ......................................................... 19 Timing Characteristics ................................................................ 7 Decoding Multiple ADG714 Devices Using the ADG739 ... 20 Absolute Maximum Ratings............................................................ 9 Outline Dimensions ....................................................................... 21 Thermal Resistance ...................................................................... 9 Ordering Guide .......................................................................... 21 ESD Caution .................................................................................. 9 REVISION HISTORY 6/2018—Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Features Section, General Description Section, and Product Highlights Section ............................................................. 1 Added Figure 2; Renumbered Sequentially .................................. 1 Added 5 V Single Supply Section ................................................... 3 Changes to Table 1 ............................................................................ 3 Added 3 V Single Supply Section ................................................... 4 Changes to Table 2 ............................................................................ 4 Changed Dual Supply Section to ±2.5 V Dual Supply Section .. 5 Changes to ±2.5 V Dual Supply Section and Table 3 ................... 5 Changed ADG714 Timing Characteristics Section to Timing Characteristics Section..................................................................... 7 Changes to ADG714 Section, Table 4, ADG715 Section, and Table 5 ................................................................................................ 7 Added Timing Diagrams Section ................................................... 8 Moved Figure 4 ................................................................................. 8 Changes to Table 6 ............................................................................ 9 Added Thermal Resistance Section and Table 7; Renumbered Sequentially ....................................................................................... 9 Changes to Figure 5 ........................................................................ 10 Added Figure 6 and Table 9 ........................................................... 11 Changes to Figure 14 Caption, Figure 16 Caption, Figure 17 Caption, Figure 18, and Figure 19 ................................................ 14 Changes to Figure 20 ...................................................................... 15 Added Figure 23.............................................................................. 15 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 21 10/2015—Rev. C to Rev. D Changes to ADG714 Timing Characteristics Table and Figure 1 ...............................................................................................5 Changes to Ordering Guide .......................................................... 16 1/2013—Rev. B to Rev. C Changes to Dual Supply Table Summary and IDD Test Conditions/Comments .....................................................................4 Changes to Ordering Guide .......................................................... 16 11/2002—Rev. A to Rev. B Edits to Features.................................................................................1 Edits to General Description ...........................................................1 Edits to Product Highlights..............................................................1 Edits to Specifications .................................................................. 3, 4 Edits to TPCs 2 and 5 ..................................................................... 10 Edits to TPCs 8 and 9 ..................................................................... 11 Edits to TPCs 14 ............................................................................. 12 Edits to Figure 8 .............................................................................. 15 4/2000—Revision 0: Initial Version Rev. E | Page 2 of 21 Data Sheet ADG714/ADG715 SPECIFICATIONS 5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, and GND = 0 V, unless otherwise noted. Temperature range is −40°C to +85°C. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON +25°C 2.5 4.5 On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 5 0.4 0.8 0.6 1.2 LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID (ON), IS (ON) DIGITAL INPUTS Input Voltage High, VINH Low, VINL High or Low Input Current, IINH or IINL ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.3 ±0.3 2.4 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DIGITAL OUTPUT, ADG714, DOUT Output Voltage Low, VOL Digital Output Capacitance, COUT DIGITAL INPUTS, SCL, SDA Input Voltage High, VINH 3 Input Leakage Current, IIN V max pF typ 0.7 × VDD VDD + 0.3 −0.3 0.3 × VDD V min V max V min V max µA typ µA max V min pF typ 0.005 ±1 Input Hysteresis, VHYST Input Capacitance, CIN LOGIC OUTPUT, SDA Output Voltage Low, VOL DYNAMIC CHARACTERISTICS On Time, tON ADG714 0.05 × VDD 6 0.4 0.6 20 32 ADG715 V min V max µA typ µA max pF typ 0.4 4 High, VINH nA typ nA max nA typ nA max nA typ nA max 95 140 Rev. E | Page 3 of 21 Test Conditions/Comments VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V VD = VS = 1 V or 4.5 V VIN = VINL or VINH ISINK = 6 mA VIN = 0 V to VDD V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 3 V, RL = 300 Ω, CL = 35 pF ADG714/ADG715 Data Sheet Parameter Off Time, tOFF ADG714 +25°C −40°C to +85°C 8 15 ADG715 85 130 Break-Before-Make Time Delay, tD 8 1 Charge Injection, QINJ Off Isolation ±3 −60 −80 −70 −90 155 −0.3 11 11 22 Channel to Channel Crosstalk −3 dB Bandwidth Insertion Loss Off Switch Source Capacitance, CS (OFF) Off Switch Drain Capacitance, CD (OFF) On Switch Capacitance, C D (ON), C S (ON) POWER REQUIREMENTS Positive Power Supply Current, IDD 10 20 Unit Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ VS = 3 V, RL = 300 Ω, CL = 35 pF µA typ µA max VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 3 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF VDD = 5.5 V Digital inputs = 0 V or 5.5 V 3 V SINGLE SUPPLY VDD = 3 V ± 10%, VSS = 0 V, and GND = 0 V, unless otherwise noted. Temperature range is −40°C to +85°C. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON +25°C 6 11 Drain OFF Leakage, ID (OFF) Channel ON Leakage, ID (ON), IS (ON) DIGITAL INPUTS Input Voltage High, VINH Low, VINL High or Low Input Current, IINH or IINL Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ 12 0.4 1.2 3.5 On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source OFF Leakage, IS (OFF) −40°C to +85°C ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.3 ±0.3 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DIGITAL OUTPUT, ADG714, DOUT Output Voltage Low, VOL Digital Output Capacitance, COUT 3 0.4 4 Rev. E | Page 4 of 21 nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ V max pF typ Test Conditions/Comments VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V VS = 1 V/3 V, VD = 3 V/1 V VS = VD = 1 V or 3 V VIN = VINL or VINH ISINK = 6 mA Data Sheet Parameter DIGITAL INPUTS, SCL, SDA Input Voltage High, VINH ADG714/ADG715 +25°C Low, VINL Input Leakage Current, IIN −40°C to +85°C Unit 0.7 × VDD VDD + 0.3 −0.3 0.3 × VDD V min V max V min V max µA typ µA max V min pF typ 0.005 ±1 Input Hysteresis, VHYST Input Capacitance, CIN LOGIC OUTPUT, (SDA) Output Voltage Low, VOL DYNAMIC CHARACTERISTICS On Time, tON ADG714 0.05 × VDD 6 0.4 0.6 35 65 ADG715 130 200 Off Time, tOFF ADG714 11 20 ADG715 115 180 Break-Before-Make Time Delay, tD 8 1 Charge Injection, QINJ Off Isolation Channel to Channel Crosstalk –3 dB Bandwidth Insertion Loss Off Switch Source Capacitance, CS (OFF) Off Switch Drain Capacitance, CD (OFF) On Switch Capacitance, C D (ON), C S (ON) POWER REQUIREMENTS Positive Power Supply Current, IDD ±2 −60 −80 −70 −90 155 −0.4 11 11 22 10 Test Conditions/Comments V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max VS = 2 V, RL = 300 Ω, CL = 35 pF ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ VS = 2 V, RL = 300 Ω, CL = 35 pF µA typ µA max 20 VIN = 0 V to VDD VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 2 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF VDD = 3.3 V Digital inputs = 0 V or 3.3 V ±2.5 V DUAL SUPPLY VDD = +2.5 V ± 10%, VSS = −2.5 V ± 10%, and GND = 0 V, unless otherwise noted. Temperature range is −40°C to +85°C. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON +25°C 2.5 4.5 On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) −40°C to +85°C Unit VSS to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 5 0.4 0.8 0.6 1 Rev. E | Page 5 of 21 Test Conditions/Comments VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA VS = VSS to VDD, IDS = 10 mA ADG714/ADG715 Parameter LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID (ON), IS (ON) DIGITAL INPUTS Input Voltage High, VINH Low, VINL High or Low Input Current, IINH or IINL Data Sheet +25°C −40°C to +85°C ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.3 ±0.3 1.7 0.7 0.005 ±0.1 Digital Input Capacitance, CIN DIGITAL OUTPUT, ADG714, DOUT Output Voltage Low, VOL Digital Output Capacitance, COUT DIGITAL INPUTS, SCL, SDA Input Voltage High, VINH 3 Input Leakage Current, IIN DYNAMIC CHARACTERISTICS On Time, tON ADG714 0.7 × VDD VDD + 0.3 −0.3 0.3 × VDD V min V max V min V max µA typ µA max V min pF typ 0.005 0.05 × VDD 6 0.4 0.6 20 32 ADG715 133 200 Off Time, tOFF ADG714 8 18 ADG715 124 190 Break-Before-Make Time Delay, tD 8 1 Charge Injection, QINJ Off Isolation Channel to Channel Crosstalk −3 dB Bandwidth Insertion Loss V min V max µA typ µA max pF typ V max pF typ ±1 Input Hysteresis, VHYST Input Capacitance, CIN LOGIC OUTPUT, SDA Output Voltage Low, VOL nA typ nA max nA typ nA max nA typ nA max 0.4 4 High, VINH Unit ±3 −60 −80 −70 −90 155 −0.3 Rev. E | Page 6 of 21 Test Conditions/Comments VDD = +2.75 V, VSS = −2.75 V VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V VS = +2.25 V/−1.25 V, VD = −1.25 V/+2.25 V VS = VD = +2.25 V/−1.25 V VIN = VINL or VINH ISINK = 6 mA VIN = 0 V to VDD V max V max ISINK = 3 mA ISINK = 6 mA ns typ ns max ns typ ns max VS = 1.5 V, RL = 300 Ω, CL = 35 pF ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ dB typ VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 1.5 V, RL = 300 Ω, CL = 35 pF VS = 0 V, RS = 0 Ω, CL = 1 nF RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz RL = 50 Ω, CL = 5 pF Data Sheet ADG714/ADG715 Parameter Off Switch Source Capacitance, CS (OFF) Off Switch Drain Capacitance, CD (OFF) On Switch Capacitance, C D (ON), C S (ON) POWER REQUIREMENTS Positive Power Supply Current, IDD +25°C 11 11 22 −40°C to +85°C 15 µA typ µA max µA typ µA max 25 Negative Power Supply Current, ISS Unit pF typ pF typ pF typ 15 25 Test Conditions/Comments VDD = +2.75 V, VSS = −2.75 V Digital inputs = 0 V or VDD TIMING CHARACTERISTICS ADG714 VDD = 2.7 V to 5.5 V. All specifications are from −40°C to +85°C, unless otherwise noted. See Figure 3. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Table 4. Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 1 Limit at TMIN, TMAX 30 33 13 13 0 5 4.5 0 33 20 0 6 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns max Conditions/Comments SCLK cycle frequency SCLK cycle time SCLK high time SCLK low time SYNC to SCLK rising edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SCLK rising edge to DOUT valid SCLK falling edge to SYNC falling edge SYNC rising edge to SCLK rising edge CL = 20 pF, RL = 1 kΩ. ADG715 VDD = 2.7 V to 5.5 V. All specifications are from −40°C to +85°C, unless otherwise noted. See Figure 4. Table 5. Parameter fSCL t1 t2 t3 t4 t5 t61 t7 t8 t9 t10 t11 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 20 + 0.1Cb2 250 300 0.1Cb2 Unit kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns max ns min Conditions/Comments SCL clock frequency SCL cycle time SCL high time, tHIGH SCL low time, tLOW Start/repeated start condition hold time, tHD, STA Data setup time, tSU, DAT Data hold time, tHD, DAT Setup time for repeated start, tSU, STA Stop condition setup time, tSU, STO Bus free time between a stop condition and a start condition, tBUF Rise time of both SCL and SDA when receiving, tR Fall time of SDA when receiving, tF Fall time of SDA when transmitting, tF Rev. E | Page 7 of 21 ADG714/ADG715 Parameter Cb tSP3 Data Sheet Limit at TMIN, TMAX 400 50 Unit pF max ns max Conditions/Comments Capacitive load for each bus line Pulse width of spike suppressed A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD. 3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. 1 2 Timing Diagrams t1 t10 SCLK t8 t3 t2 t11 t7 t4 SYNC t6 t5 DB7 DIN DB0 t9 DB6* DB2* DB1* DB0* 00043-003 DB7* DOUT *DATA FROM PREVIOUS WRITE CYCLE Figure 3. 3-Wire Serial Interface Timing Diagram SDA t3 t9 t4 t11 t10 SCL t6 t2 t5 START CONDITION t7 REPEATED START CONDITION Figure 4. 2-Wire Serial Interface Timing Diagram Rev. E | Page 8 of 21 t1 t8 STOP CONDITION 00043-004 t4 Data Sheet ADG714/ADG715 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 6. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Continuous Current, Sx or Dx Operating Temperature Range Storage Temperature Range Junction Temperature Lead Temperature, Soldering (10 sec) Infrared Reflow (20 sec) 1 Rating 7V −0.3 V to +7 V +0.3 V to −3.5 V VSS −0.3 V to VDD +0.3 V or 30 mA, whichever occurs first –0.3 V to VDD +0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA −40°C to +85°C −65°C to +150°C 150°C 300°C 235°C Careful attention to PCB thermal design is required. θJA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 7. Thermal Resistance Package Type RU-24 CP-24-10 θJA 128 127.991 θJC 42 15.382 Unit °C/W °C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD-51. 2 Thermal impedance simulated values are based on a cool plate location at the top of the package and measured at the bottom of the exposed paddle of the LFCSP. 1 ESD CAUTION Overvoltages at the DIN pin, Sx, or Dx are clamped by internal diodes. Limit current to the given maximum ratings. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 9 of 21 ADG714/ADG715 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK 1 24 SYNC VDD 2 23 RESET DIN 3 22 DOUT GND 4 21 VSS 5 6 ADG714 20 S8 TOP VIEW 19 D8 (Not to Scale) S2 7 18 S7 D2 8 17 D7 S3 9 16 S6 D3 10 15 D6 S4 11 14 S5 D4 12 13 D5 00043-005 S1 D1 Figure 5. ADG714 TSSOP Pin Configuration Table 8. ADG714 Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 3 VDD DIN 4 5, 7, 9, 11, 14, 16, 18, 20 6, 8, 10, 12, 13, 15, 17, 19 21 22 GND Sx Dx VSS DOUT 23 RESET 24 SYNC Description Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices accommodate serial input rates of up to 30 MHz. Positive Analog Supply Voltage. Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input. Ground Reference. Source. These pins may be an input or an output. Drain. These pins may be an input or an output. Negative Analog Supply Voltage. For single-supply operation, tie this pin to ground. Serial Data Output. This pin allows a number of devices to be daisy-chained. Data is clocked out of the input shift register on the rising edge of SCLK. DOUT is an open-drain output that is pulled to the supply with an external pull-up resistor. Active Low Control Input. This pin clears the input register and turns all switches to the off condition. Active Low Control Input. This pin is the frame synchronization signal for the input data. When SYNC goes low, this pin powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the falling edges of the following clock cycle. Taking SYNC high updates the switches. Rev. E | Page 10 of 21 19 DOUT 21 SYNC 20 RESET 22 SCLK 24 DIN ADG714/ADG715 23 VDD Data Sheet 18 VSS GND 1 S1 2 17 S8 D1 3 ADG714 16 D8 S2 4 TOP VIEW (Not to Scale) 15 S7 D2 5 14 D7 S3 6 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 00043-006 D6 12 S5 11 D5 10 D4 9 S4 8 D3 7 13 S6 Figure 6. ADG714 LFCSP Pin Configuration Table 9. ADG714 Pin Function Descriptions Pin No. 1 2, 4, 6, 8, 11, 13, 15, 17 3, 5, 7, 9, 10, 12, 14, 16 18 Mnemonic GND Sx Dx VSS 19 DOUT 20 RESET 21 SYNC 22 SCLK 23 24 VDD DIN EP EP Description Ground (0 V) Reference. Source. These pins may be an input or an output. Drain. These pins may be an input or an output. Most Negative Power Supply Potential. In single-supply applications, VSS is connected to ground. Serial Data Output. This pin is used for daisy-chaining a number of these devices together or for reading back data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output to the supply with an external resistor. RESET. Under normal operation, drive the RESET pin with a 2.7 V to 5 V supply. Pull the pin low (