ADM1062

Multisupply Supervisor/Sequencer with Margining Control and Temperature Monitoring Preliminary Technical Data FEATURES 10 supply fault detectors enabling supervision of supplies to better than 1% accuracy 5 selectable input attenuators allow supervision: Supplies up to 14.4 V on VH Supplies up to 6 V on VP1-4 5 dual function inputs VX1-5: High impedance input to supply fault detector with thresholds between 0.573 V and 1.375 V General-purpose logic input Device powered by the highest of VP1–4, VH 2.048 V reference (±0.25%) on REFOUT pin 12-bit ADC for read-back of all supervised voltages Reference input, REFIN—2 input options: Driven directly from REFOUT More accurate external reference for improved ADC performance 6 voltage output 8-bit DACs (0.300 V to 1.551 V) Internal temperature sensor Remote temperature sensor 10 programmable output drivers (PDO1-10) Open collector with external pull-up Push-pull output, driven to VDDCAP or VPn Open collector with weak pull-up to VDDCAP or VPn Internally charge pumped high drive for use with external N-FET (PDO1–6 only) Sequencing Engine (SE) implements State Machine control of PDO outputs: State changes conditional on input events Can enable complex control of boards Power up and power down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus User EEPROM—256 Bytes Industry standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPn = 1.2V 40-lead LFCSP and 48-lead TQFP packages ADM1062 APPLICATIONS Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In circuit testing of margined supplies FUNCTIONAL BLOCK DIAGRAM Figure 1. GENERAL DESCRIPTION The ADM1062 is a configurable super visor y/sequencing device which offers a single chip solution for supply monitoring and sequencing in multiple supply systems. (continued on Page 3) Rev. PrJ Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. ADM1062 TABLE OF CONTENTS General Description ......................................................................... 3 ADM1062 Specifications ................................................................. 5 Pin Configurations and Functional Descriptions ........................ 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 ESD Caution .................................................................................. 9 Typical Performance Characteristics ........................................... 10 ADM1062 Inputs ............................................................................ 13 Powering the ADM1062 ............................................................ 13 Supply Supervision ..................................................................... 14 Input Comparator Hysteresis.................................................... 14 Input Glitch Filtering ................................................................. 14 Supply Supervision with VXN Inputs ...................................... 15 Supply Supervision Using the ADC ......................................... 15 VXN Pins as Digital Inputs ....................................................... 16 ADM1062 Outputs ......................................................................... 17 ADM1062 Sequencing Engine...................................................... 19 Warnings ...................................................................................... 19 SW Flow-Unconditional Jump ................................................. 19 End of Step Detector .................................................................. 20 Monitoring Fault Detector ........................................................ 20 Preliminary Technical Data Timeout Detector ....................................................................... 21 Closed Loop Supply Margining ................................................ 21 Writing to the DACs .................................................................. 22 Choosing the Size of the Feedback Resistor ........................... 22 DAC Limiting/Other Safety Features ...................................... 22 Temperature Measurement System .............................................. 23 Remote Temperature Measurement ........................................ 23 Communicating with the ADM1062 ........................................... 25 Configuration Download at Power-Up ................................... 25 Updating the Configuration of the ADM1062 ....................... 25 Updating the Sequencing Engine of the ADM1062 .............. 26 Internal Registers of the ADM1062 ......................................... 26 ADM1062 EEPROM .................................................................. 26 Serial Bus Interface..................................................................... 27 Identifying the ADM1062 on the SMBUS .............................. 27 General SMBUS Timing ............................................................ 27 SMbus Protocols for RAM and EEPROM .............................. 27 ADM1062 WRITE Operations ................................................. 29 ADM1062 READ Operations ................................................... 30 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 REVISION HISTORY Revision PrJ: Preliminary Version Rev. PrJ | Page 2 of 32 Preliminary Technical Data GENERAL DESCRIPTION (continued from Page 1) In addition to these functions the ADM1062 integrates a 12-bit ADC and six 8-bit voltage output DACs. These circuits can be used to implement a closed loop margining system. This enables supply adjustment by altering either the feedback node or reference of a DC/DC Converter using the DAC outputs. The supply margining can be performed, with a minimum of external components, to an accuracy of 0.5%. The margining loop can be used at In Circuit Testing of a board during production (to verify the board’s functionality at say −5% of nominal supplies), or can be used dynamically to accurately control the output voltage of a DC/DC converter. The device also provides up to ten programmable inputs for monitoring Under, Over, or out-of-window faults on up to ten supplies. In addition, ten programmable outputs are provided. These can be used as logic enables. Six of them can also provide ADM1062 up to a +12V output for driving the gate of an N- Channel FET which may be placed in the path of a supply. Temperature measurement is possible with the ADM1062. The device contains one internal temperature sensor and a differential input for a remote thermal diode. These are measured using the 12- bit ADC. The logical core of the device is a Sequencing Engine. This is a state machine based construction, providing up to 63 different states. This enables very flexible sequencing of the outputs, based on the condition of the inputs. The device is controlled via configuration data which can programmed into an EEPROM. All of this configuration can be programmed using an intuitive GUI based software package provided by ADI. Rev. PrJ | Page 3 of 32 ADM1062 Preliminary Technical Data Figure 2. Detailed Block Diagram Rev. PrJ | Page 4 of 32 Preliminary Technical Data ADM1062 SPECIFICATIONS1 VH = 3.0 V to 14.4 V, VPn = 3.0 V to 6.0 V2, TA = −40°C to 85°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY ARBITRATION VH, VPn VP VH POWER SUPPLY Supply Current, IVH, IVPn (DAC’s, Temp Sensor and ADC off) Additional Currents All PDO FET Drivers on Current available from VDDCAP DAC’s Supply Current ADC Supply Current EEPROM Erase Current SUPPLY FAULT DETECTORS VH Pin Input Impedance Input attenuator error Detection Ranges High Range Mid Range VPn Pins Input Impedance Detection Ranges Mid Range Low Range Ultra Low Range VX Pins Input Impedance Detection Ranges Ultra Low Range Absolute Accuracy Min 3.0 6.0 14.4 Typ Max Unit V V V Test Conditions/Comments Min. of VDDCAP=2.7V required Max VDDCAP= 5.1V, Typical VDDCAP = 4.75V ADM1062 6 mA VDDCAP=4.75V, no PDO FET Drivers on, no loaded PDO pullups to VDDCAP VDDCAP=4.75V, (loaded with 1µA), no PDO pullups to VDDCAP. Max. additional load that can be drawn from PDO pullups to VDDCAP 6 DAC’s on with 100µA max load on each Running Round Robin loop 1ms duration only 4 2 2 1 10 mA mA mA mA mA 26.7 0.25 6 2.5 80 2.5 1.25 0.573 1 0.573 1.375 1 6 3 1.375 14.4 6 kΩ % V V kΩ V V V MΩ V % From VH to GND Low, Mid and High ranges on VH, VPn From VPn to GND Input attenuator error + Vref Error + DAC Non Linearity + Comparator Offset Error See Figure x. 8 filter length options Die temp higher than ambient due to ADM1062 power consumption 0°C DPLIMn. In this way it is possible for the user to make it ver y difficult for the DAC output buffers to be turned on at all in normal system operation by programming the limit registers in this way (these are among the registers downloaded from EEPROM at startup). Rev. PrJ | Page 22 of 32 Preliminary Technical Data TEMPERATURE MEASUREMENT SYSTEM The ADM1062 contains an on-chip band gap temperature sensor, whose output is digitized by the on-chip 12-bit ADC. Theoretically, the temperature sensor and ADC can measure temperatures from −128°C to +127°C with a resolution of 0.125°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside this range are not possible. Temperature measurement from −127°C to +127°C is possible using a remote sensor. The code out is in offset binar y format, with −128°C given by code 400h, 0°C given by 800h and +127°C given by C00h. As with the other analog inputs to the ADC, a limit register is provided for each of the temperature input channels. Thus, a temperature limit can be set, such that if it is exceeded, a Warning is generated and is available as an input to the sequencing engine. This enables the user to control their sequence or monitor functions based on an over temperature or under temperature event. ADM1062 Figure 33 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2N3904/06. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the DN input and the emitter to the DP input. If an NPN transistor is used, the emitter is connected to the DN input and the base to the DP input. Figure 34 and Figure 35 shows how to connect the ADM1062 to an NPN or PNP transistor for temperature measurement. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the DN input. To measure ∆Vbe, the sensor is switched between operating currents of I and N × I. The resulting waveform is passed through a 65kHz low pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to ∆Vbe,. This voltage is measured by the ADC to give a temperature output in 12-bit offset binar y. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 600µs. The results of remote temperature measurements are stored in 12 bit, offset binar y format, as illustrated in. This gives temperature readings with a resolution of 0.125°C. REMOTE TEMPERATURE MEASUREMENT The ADM1062 can measure the temperature of a remote diode sensor or diode-connected transistor, connected to pins 37 and 38 on the LFCSP package and pins 44 and 45 on the TQFP package (pins DN and DP). The for ward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about −2mV/°C. Unfortunately, the absolute value of Vbe varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. The technique used in the ADM1062 is to measure the change in Vbe when the device is operated at two different currents. This is given by : ∆Vbe = KT q × In( N ) where: K is Boltzmann’s constant. q is charge on the carrier. T is absolute temperature in Kelvin. N is ratio of the two currents. Rev. PrJ | Page 23 of 32 ADM1062 Preliminary Technical Data Figure 33. Signal Conditioning for Remote Diode temperature Sensors Table 7. Temperature Data Format Temperature −128°C −125°C −100°C −75°C −50°C −25°C −10°C 0°C +10.25°C +25.5°C +50.75°C +75°C +100°C +125°C +128°C Digital Output (Hex) 400 418 4E0 5A8 600 670 7B0 800 852 8CC 996 A58 B48 BE8 C00 Digital Output (Bin) 010000000000 010000011000 010011100000 010110101000 011000000000 011001110000 011110110000 100000000000 100001010010 100011001100 100110010110 101001011000 101101001000 101111101000 110000000000 Figure 34. Measuring Temperature Using a NPN Transistor Figure 35. Measuring Temperature Using a PNP Transistor Rev. PrJ | Page 24 of 32 Preliminary Technical Data COMMUNICATING WITH THE ADM1062 CONFIGURATION DOWNLOAD AT POWER-UP The configuration of the ADM1062– the UV/OV thresholds, glitch filter timeouts, PDO configurations etc, is dictated by the contents of RAM. The RAM is comprised of digital latches which are local to each of the functions on the device. The latches are “double buffered” and actually comprised of two identical latches, Latch A and Latch B. Thus, the update of a function first updates the contents of Latch A and then updates the contents of Latch B with identical data. The advantage of the architecture is explained in detail below. These latches are volatile memory and lose their contents at power- down. Therefore, at power- up the configuration in the RAM must be restored. This is achieved by downloading the contents of the EEPROM (non- volatile memory) to the local latches. This download occurs in a number of steps. 1. 2. With no power applied to the device, the PDO’s are all high impedance. Once 1V appears on any of the inputs connected to the VDD Arbitrator (VH or VPn), the PDO’s are all weakly pulled to GND with a 20kΩ impedance. Once the supply rises above the Under voltage Lockout of the device (UVLO is 2.5V), the EEPROM starts to download to the RAM. The EEPROM downloads its contents to all Latch A’s. Once the contents of the EEPROM are completely downloaded to Latch A’s, the device controller signals all Latch A’s to download to all Latch B’s simultaneously, thus completing the configuration download. 0.5ms after the configuration download, the first state definition is downloaded from EEPROM into the Sequencing Engine ADM1062 The ADM1062 provides a number of options which allow the user to update the configuration differently over the SMBus interface. All of these options are controlled in the register UPDCFG. The options are: 1. Update the configuration in real time. The user writes to RAM across the SMBus and the configuration is updated immediately. Update A Latches without updating the B Latches. With this method, the configuration of the ADM1062 will remain unchanged and continue to operate in the original setup until the instruction is given to update the B Latches. Change EEPROM register contents without changing the RAM contents, and then download the revised EEPROM contents to the RAM registers. Again, with this method, the configuration of the ADM1062 will remain unchanged and continue to operate in the original setup until the instruction is given to update the RAM. 2. 3. 3. 4. 5. The instruction to download from the EEPROM in option 3 above is also a useful way to restore the original EEPROM contents if revisions to the configuration are unsatisfactory. If the user alters, say, an OV threshold they can do this by updating the RAM register as described in 1 above. If they are not satisfied with this change and wish to revert to the original programmed value, then the device controller can issue a command to download the EEPROM contents to the RAM again, thus restoring the ADM1062 to its original configuration. This type of operation is possible because of the topology of the ADM1062. The Local (volatile) registers, or RAM, are all double buffered latches. Setting bit 0 of the UPDCFG register to 1 leaves the double buffered latches open at all times. If bit 0 is set to 0, then when RAM write occurs across the SMBus only the first side of the double buffered latch is written to. The user must then write a 1 to bit 1 of the UPDCFG register. This generates a pulse to update all of the second latches at once. Similarly with EEPROM writes. A final bit in this register is used to enable EEPROM page erasure. If this bit is set high, then the contents of an EEPROM page can all be set to 1. If low, then the contents of a page cannot be erased, even if the command code for page erasure is programmed across the SMBus. The bitmap for register UPDCFG is shown in AN-698. A flow chart for download at power up and subsequent configuration updates is shown in Figure 36 overleaf. 6. Note– Any attempt to communicate with the device prior to this download completion will result in a NACK being issued from the ADM1062. UPDATING THE CONFIGURATION OF THE ADM1062 Once powered up, with all of the configuration settings loaded from EEPROM into the RAM registers, the user may wish to alter the configuration of functions on the ADM1062 (eg) change the UV or OV limit of an SFD, change the fault output of an SFD, change the rise time delay of one of the PDO’s etc. Rev. PrJ | Page 25 of 32 ADM1062 Preliminary Technical Data Figure 36. Configuration Update Flow Diagram UPDATING THE SEQUENCING ENGINE OF THE ADM1062 The update of the SE functions differently to the regular configuration latches. The SE has its own dedicated 512 byte EEPROM for storing State definitions, providing 63 individual states with a 64- bit word each (one state is reser ved). At powerup, the first state is loaded from the SE EEPROM into the engine itself. When the conditions of this state are met, the next state is loaded from EEPROM into the engine, and so on. The loading of each new state takes approximately 20µs. If a state is to be altered, then the required changes must be made directly to EEPROM. RAM for each state does not exist. The relevant alterations must be made to the 64- bit word, which is then uploaded directly to EEPROM. (EEPROM), from register addresses F800h to FBFFh. This may be used for permanent storage of data that will not be lost when the ADM1062 is powered down, one EEPROM cell containing the configuration data of the device, the other containing the State definitions for the Sequencing Engine. Although referred to as Read Only Memor y, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The only major differences between the E2PROM and other registers are: 1. 2. 3. An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. Writing to EEPROM is slower than writing to RAM. Writing to the EEPROM should be restricted because it has a limited write/cycle life of typically 10,000 write operations, due to the usual EEPROM wear-out mechanisms. INTERNAL REGISTERS OF THE ADM1062 The ADM1062 contains a large number of data registers. A brief description of the principal registers is given below. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1062, the first byte of data is always a register address, which is written to the Address Pointer Register. Configuration Registers: Provide control and configuration for various operating parameters of the ADM1062. The first EEPROM is split into 16 (0 to 15) pages of 32 Bytes each. Pages 0 to 6, starting at address F800, hold the configuration data for the applications on the ADM1062 (the SFD’s, PDO’s etc.). These EEPROM addresses are the same as the RAM register addresses, prefixed by F8. Page 7 is reser ved. Pages 8 to 15 are for customer use. Data can be downloaded from EEPROM to RAM in one of two ways:– 1. 2. At Power- up, pages 0 to 6 are downloaded. Setting bit 0 of the UDOWNLD Register (D8h) performs a user download of pages 0 to 6. ADM1062 EEPROM The ADM1062 has two 512 byte cells of non-volatile, Electrically-Erasable Programmable Read-Only Memor y Rev. PrJ | Page 26 of 32 Preliminary Technical Data SERIAL BUS INTERFACE Control of the ADM1062 is carried out via the serial System Management Bus (SMBus). The ADM1062 is connected to this bus as a slave device, under the control of a master device. It takes approximately 1ms after power up for the ADM1062 to download from it's EEPROM. Therefore access is restricted to the ADM1062 until the download is completed. 2. ADM1062 master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the 9th clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition IDENTIFYING THE ADM1062 ON THE SMBUS The ADM1060 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The five MSB's of the address are set to 00101, the two LSB's are determined by the logical states of pin A1 and A0. This allows the connection of 4 ADM1062’s to the one SMBus. The device also has a number of identification registers (read only) which can be read across the SMBus. Table 8 lists these registers, their values, and functions. Table 8. Name Address MANID F4h REVID F5h MARK1 F6h MARK2 F7h Value 41h --h --h --h Function Manufacturer ID for Analog Devices Silicon Revision S/w brand S/w brand 3. GENERAL SMBUS TIMING Figure 37, Figure 38 and Figure 39 show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operation, which are discussed later. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the SMBUS PROTOCOLS FOR RAM AND EEPROM The ADM1062 contains volatile registers (RAM) and nonvolatile EEPROM. User RAM occupies address locations from 00h to DFh, whilst EEPROM occupies addresses from F800h to FBFFh. Data can be written to and read from both RAM and EEPROM as single data bytes. Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location it is first necessary to erase it. EEPROM erasure cannot be done at the byte level, the EEPROM is arranged as 32 pages of 32 bytes, and an entire page must be erased. Page erasure is enabled by setting bit 2 in register UPDCFG (address 90h) to 1. If this is not set then page erasure cannot occur, even if the command byte (FEh) is programmed across the SMBus. Rev. PrJ | Page 27 of 32 ADM1062 Preliminary Technical Data Figure 37. General SMBus Write Timing Diagram Figure 38. General SMBus Read Timing Diagram Figure 39. Diagram for Serial Bus Timing Rev. PrJ | Page 28 of 32 Preliminary Technical Data ADM1062 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1062 are discussed below. The following abbreviations are used in the diagrams: S P R – – – START Figure 41. EEPROM Page Erasure ADM1062 for page erasure to take place, the page address has to be given in the previous write word transaction (see write byte below). Also, bit 2 in register UPDCFG (address 90h) must be set to 1. STOP READ WRITE ACKNOWLEDGE NO ACKNOWLEDGE W– A A – – As soon as the ADM1062 receives the command byte, page erasure begins. The master device can send a STOP command as soon as it sends the command byte. Page erasure takes approximately 20ms. If the ADM1062 is accessed before erasure is complete, it will respond with a NACK. Write Byte/Word In this operation the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master sends a data byte (or may assert STOP at this point). The slave asserts ACK on SDA. The ADM1062 uses the following SMBus write protocols: Send Byte In this operation the master device sends a single command byte to a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a STOP condition on SDA and the transaction ends. In the ADM1062, the send byte protocol is used for two purposes. 1. To write a register address to RAM for a subsequent single byte read from the same address or block read or write starting at that address. This is illustrated in Figure 40. 10. The master asserts a STOP condition on SDA to end the transaction. In the ADM1062, the write byte/word protocol is used for three purposes. 1. Write a single byte of data to RAM. In this case the command byte is the RAM address from 00h to DFh and the (only) data byte is the actual data. This is illustrated in Figure 42 Figure 40. Setting A RAM Address For Subsequent Read 2. Erase a page of EEPROM memor y. EEPROM memor y can be written to only if it is unprogrammed. Before writing to one or more EEPROM memor y locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memor y is erased by writing a command byte. The master sends a command code that tells the slave device to erase the page. The ADM1062 command code for a pages(s) erasure is FEh (11111110). Note that, in order Figure 42. Single Byte Write To RAM 2. Set up a two byte EEPROM address for a subsequent read, write, block read, block write or page erase. In this case the command byte is the high byte of the EEPROM address from F8h to FBh. The (only) data byte is the low byte of the Rev. PrJ | Page 29 of 32 ADM1062 EEPROM address. This is illustrated in Figure 43. Preliminary Technical Data 10. The master asserts a STOP condition on SDA to end the transaction. Figure 43. Setting An EEPROM Address Figure 45. Block Write To EEPROM Or RAM Note for page erasure that as a page consists of 32 bytes only the three MSB’s of the address low byte are important. The lower 5 bits of the EEPROM address low byte only specify addresses within a page and are ignored during an erase operation. 3. Write a single byte of data to EEPROM. In this case the command byte is the high byte of the EEPROM address from F8h to FBh. The first data byte is the low byte of the EEPROM address and the second data byte is the actual data. This is illustrated in Figure 44 Unlike some EEPROM devices which limit block writes to within a page boundar y, there is no limitation on the start address when performing a block write to EEPROM, except: 1. There must be at least N locations from the start address to the highest EEPROM address (FBFFh), to avoiding writing to invalid addresses. If the addresses cross a page boundar y, both pages must be erased before programming. 2. Figure 44. Single Byte Write To EEPROM Note that the ADM1062 features a clock extend function for writes to EEPROM. Programming an EEPROM byte takes approximately 250µs, which would limit the SMBus clock for repeated or block write operations. The ADM1062 pulls SCL low and extends the clock pulse when it cannot accept any more data. Block Write In this operation the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the ADM1062 this is done by a Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address. 1. 2. 3. 4. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block write. The ADM1062 command code for a block write is FCh (11111100). The slave asserts ACK on SDA. The master sends a data byte that tells the slave device how many data bytes will be sent. The SMBus specification allows a maximum of 32 data bytes to be sent in a block write. The slave asserts ACK on SDA. The master sends N data bytes. ADM1062 READ OPERATIONS The ADM1062 uses the following SMBus read protocols: Receive Byte In this operation the master device receives a single byte from a slave device, as follows: 1. 2. 3. 4. 5. 6. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts ACK on SDA. The master receives a data byte. The master asserts NO ACK on SDA. The master asserts a STOP condition on SDA and the transaction ends. 5. 6. In the ADM1062, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or write byte/word operation. This is illustrated in Figure 46. 7. 8. 9. Figure 46. Single Byte Read From EEPROM Or RAM The slave asserts ACK on SDA after each data byte. Rev. PrJ | Page 30 of 32 Preliminary Technical Data Block Read In this operation the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1062 this is done by a Send Byte operation to set a RAM address, or a Write Byte/Word operation to set an EEPROM address. The block read operation itself consists of a Send Byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. 2. 3. 4. The master device asserts a START condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code that tells the slave device to expect a block read. The ADM1062 command code for a block read is FDh (11111101). The slave asserts ACK on SDA. The master asserts a repeat start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts ACK on SDA. The ADM1062 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1062 will always return 32 data bytes (20h), which is the maximum allowed by the SMBus 1.1 specification. ADM1062 Figure 47. Block Read From EEPROM or RAM Error Correction The ADM1062 provides the option of issuing a PEC (Packet Error Correction) byte after a write to RAM, a write to EEPROM, a block write to RAM/EEPROM or a block read from RAM/EEPROM. This enables the user to verify that the data received by or sent from the ADM1062 is correct. The PEC byte is an optional byte sent after that last data byte has been written to or read from the ADM1062. The protocol is as follows:– 1. The ADM1062 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. A NACK is generated after the PEC byte to signal the end of the read. 5. 6. 7. 8. 9. 2. Note: The PEC byte is calculated using CRC-8. The Frame Check Sequence (FCS) conforms to CRC-8 by the polynomial:– C(x ) = x 8 + x 2 + x 1 + 1 Consult SMBus 1.1 specification for more information. An example of a block read with the optional PEC byte is shown in Figure 48 below. 10. The master asserts ACK on SDA. 11. The master receives 32 data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The master asserts a STOP condition on SDA to end the transaction. Figure 48. Block Read From EEPROM or RAM with PEC Rev. PrJ | Page 31 of 32 ADM1062 OUTLINE DIMENSIONS Preliminary Technical Data Figure 49. 40-Lead 6×6 Chip Scale Package (CP-40) Dimensions shown in millimeters Figure 50. 48-Lead 7×7 TQFP Package (SU-48) Dimensions shown in millimeters ORDERING GUIDE Model ADM1062ACP ADM1062ASU Temperature Range −40°C to +85°C −40°C to +85°C Package Description 40-Lead LFCS 48-Lead TQFP Package Option CP-40 SU-48 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04433–0–12/03(PrJ) Rev. PrJ | Page 32 of 32