ADM2485_07

High Speed, Isolated RS-485 Transceiver with Integrated Transformer Driver ADM2485 FEATURES Half-duplex, isolated RS-485 transceiver Integrated oscillator driver for external transformer PROFIBUS® compliant Complies with ANSI/TIA/EIA RS-485-A-98 and ISO 8482:1987(E) Data rate: 16 Mbps 5 V or 3.3 V operation (VDD1) 50 nodes on bus High common-mode transient immunity: >25 kV/μs Isolated DE OUT status output Thermal shutdown protection Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Reinforced insulation, VIORM = 560 V peak Operating temperature range: –40°C to +85°C Wide-body, 16-lead SOIC package FUNCTIONAL BLOCK DIAGRAM VDD1 D1 D2 VDD2 OSC GALVANIC ISOLATION ADM2485 DE OUT RTS TxD A B RxD RE GND1 GND2 Figure 1. APPLICATIONS Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems GENERAL DESCRIPTION The ADM2485 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI/TIA/EIA RS-485-A-98 and ISO 8482:1987(E). The device employs Analog Devices, Inc., iCoupler® technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. An on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power with an external transformer. The logic side of the device can be powered with either a 5 V or a 3.3 V supply, and the bus side is powered with an isolated 5 V supply. The ADM2485 driver has an active high enable. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when VDD1 or VDD2 = 0 V. Also provided is an active high receiver disable that causes the receive output to enter a high impedance state. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body SOIC package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06021-001 ADM2485 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Package Characteristics ............................................................... 6 Regulatory Information............................................................... 6 Insulation and Safety-Related Specifications............................ 6 VDE 0884-2 Insulation Characteristics..................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Circuit Description......................................................................... 14 Electrical Isolation...................................................................... 14 Truth Tables................................................................................. 14 Thermal Shutdown .................................................................... 14 Receiver Fail-Safe Inputs ........................................................... 14 Magnetic Field Immunity.......................................................... 15 Applications Information .............................................................. 16 PCB Layout ................................................................................. 16 Transformer Suppliers ............................................................... 16 Applications Diagram................................................................ 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17 REVISION HISTORY 12/07—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Features Section............................................................ 1 Changes to Table 4............................................................................ 6 Changes to VDE 0884-2 Insulation Characteristics Section ...... 7 Changes to PCB Section and Figure 34 ....................................... 16 Updated Outline Dimensions ....................................................... 17 1/07—Revision 0: Initial Version Rev. A | Page 2 of 20 ADM2485 SPECIFICATIONS 2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DRIVER Differential Outputs Differential Output Voltage, VOD Min Typ Max Unit Test Conditions/Comments 2.1 2.1 2.1 Δ|VOD| for Complementary Output States Common-Mode Output Voltage, VOC Δ|VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Bus Enable Output Output High Voltage 60 60 VDD2 − 0.1 VDD2 − 0.3 VDD2 − 0.4 5 5 5 5 0.2 3 0.2 200 200 V V V V V V V mA mA V V V V V V V V μA R = ∞, see Figure 21 R = 50 Ω (RS-422), see Figure 21 R = 27 Ω (RS-485), see Figure 21 VTST = –7 V to +12 V, VDD1 ≥ 4.75 V, see Figure 22 R = 27 Ω or 50 Ω, see Figure 21 R = 27 Ω or 50 Ω, see Figure 21 R = 27 Ω or 50 Ω, see Figure 21 −7 V ≤ VOUT ≤ +12 V −7 V ≤ VOUT ≤ +12 V IODE = 20 μA IODE = 1.6 mA IODE = 4 mA IODE = −20 μA IODE = −1.6 mA IODE = −4 mA TxD, RTS, RE TxD, RTS, RE TxD, RTS, RE = VDD1 or 0 V VDD2 − 0.1 VDD2 − 0.2 0.1 0.2 0.1 0.3 0.4 Output Low Voltage Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, RTS, RE) RECEIVER Differential Inputs Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output Output High Voltage Output Low Voltage 0.7 VDD1 −10 +0.01 0.25 VDD1 +10 −200 20 70 30 +200 0.6 −0.35 VDD1 − 0.1 VDD1 − 0.4 mV mV kΩ mA mA V V V V mA μA kHz kHz Ω V −7 V ≤ VCM ≤ +12V −7 V ≤ VCM ≤ +12V −7 V ≤ VCM ≤ +12V VIN = +12 V VIN = −7 V IOUT = +20 μA, VA − VB = +0.2 V IOUT = +1.5 mA, VA − VB = +0.2 V IOUT = −20 μA, VA − VB = −0.2 V IOUT = −4 mA, VA − VB = −0.2 V VOUT = GND or VCC 0.4 V ≤ VOUT ≤ 2.4 V VDD1 = 5.5 V VDD1 = 3.3 V VDD1 − 0.2 0.2 0.1 0.4 85 ±1 600 430 1.5 2.5 Output Short-Circuit Current Tristate Output Leakage Current TRANSFORMER DRIVER Oscillator Frequency Switch-On Resistance Start-Up Voltage 7 400 230 500 330 0.5 2.2 Rev. A | Page 3 of 20 ADM2485 Parameter POWER SUPPLY CURRENT Logic Side Min Typ Max 2.5 2.3 5.0 1.26 1.5 2.9 1.7 49.0 55.0 COMMON-MODE TRANSIENT IMMUNITY 1 HIGH FREQUENCY COMMON-MODE NOISE IMMUNITY 1 Unit mA mA mA mA mA mA mA mA mA kV/μs mV Test Conditions/Comments RTS = 0 V, VDD1 = 5.5 V 2.5 Mbps, VDD1 = 5.5 V, see Figure 23 16 Mbps, VDD1 = 5.5 V, see Figure 23 RTS = 0 V, VDD1 = 3.3 V 2.5 Mbps, VDD1 = 3.3 V, see Figure 23 16 Mbps, VDD1 = 3.3 V, see Figure 23 RTS = 0 V 2.5 Mbps, RTS = VDD1, see Figure 23 for load conditions 16 Mbps, RTS = VDD1, see Figure 23 for load conditions Transient magnitude = 800 V, VCM = 1 kV VHF = +5 V, −2 V < VTEST2 < +7 V, 1 MHz < fTEST < 50 MHz, see Figure 24 6.5 Bus Side 2.5 75.0 25 100 CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 4 of 20 ADM2485 TIMING SPECIFICATIONS 2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DRIVER Maximum Data Rate Propagation Delay Input-to-Output tPLH, tPHL RTS-to-DE OUT Propagation Delay Driver Output-to-Output, tSKEW Rise/Fall Time, tR, tF Enable Time Disable Time Enable Skew, |tAZH − tBZL|, |tAZL − tBZH| Disable Skew, |tAHZ − tBLZ|, |tALZ − tBHZ| RECEIVER Propagation Delay, tPLH, tPHL Differential Skew, tSKEW Enable Time Disable Time Min 16 25 20 45 35 2 5 43 43 1 2 25 45 3 3 55 55 5 15 53 55 3 5 55 5 13 13 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns ns ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 25 See Figure 26 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 2 and Figure 25 RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 2 and Figure 25 See Figure 4 and Figure 27 See Figure 4 and Figure 27 See Figure 4 and Figure 27 See Figure 4 and Figure 27 CL = 15 pF, see Figure 3 and Figure 28 CL = 15 pF, see Figure 3 and Figure 28 RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29 RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29 Test Conditions/Comments Timing Diagrams 3V 1.5V 0V 1.5V tPLH B 1/2VOUT VOUT A tPHL 0.7VDD1 RTS 0.5VDD1 0.5VDD1 tZL tSKEW = |tPLH – tPHL | 90% POINT 90% POINT tLZ 2.3V 0.3VDD1 +VOUT 0V –VOUT A–B VOH + 0.5V 10% POINT 10% POINT 06021-012 tZH 2.3V tHZ VOH – 0.5V VOL VOH 06021-014 tR tF A–B 0V Figure 2. Driver Propagation Delay, Rise/Fall Timing Figure 4. Driver Enable/Disable Timing 0.7VDD1 RE 0.5VDD1 0.5VDD1 0.3VDD1 A–B 0V 0V tZL 1.5V OUTPUT LOW tLZ tPLH tPHL VOH RxD VOH + 0.5V tZH OUTPUT HIGH RxD 0V tHZ VOH – 0.5V VOL RxD 1.5V tSKEW = |tPLH – tPHL| 1.5V VOH 06021-015 VOL Figure 3. Receiver Propagation Delay 06021-013 1.5V Figure 5. Receiver Enable/Disable Timing Rev. A | Page 5 of 20 ADM2485 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance 1 2 Symbol RI-O CI-O CI θJCI θJCO Min Typ 1012 3 4 33 28 Max Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION Table 4. ADM2485 Approvals Organization UL Approval Type Recognized under the Component Recognition Program of Underwriters Laboratories, Inc. Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Notes In accordance with UL 1577, each ADM2485 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADM2485 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). VDE INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (External Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 5.15 min 5.5 min 0.017 min >175 IIIa Unit V rms mm mm mm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance along body Insulation distance through insulation DIN IEC 112/VDE 0303-1 Material Group (DIN VDE 0110: 1989-01, Table 1) CTI Rev. A | Page 6 of 20 ADM2485 VDE 0884-2 INSULATION CHARACTERISTICS This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on packages denotes DIN V VDE V 0884-10 approval. Table 6. Description Installation Classification per DIN VDE 0110 for Rated Mains Voltage ≤150 V rms ≤300 V rms ≤400 V rms Climatic Classification Pollution Degree (DIN VDE 0110: 1989-01, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage Method B1: VIORM × 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC Method A (After Environmental Tests, Subgroup 1): VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge 200 mV and low when (A − B) < −200 mV. The output is tristated when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver; driving it high disables the receiver. Driver Enable Input. Driving this input high enables the driver; driving it low disables the driver. Driver Input. Data to be transmitted by the driver is applied to this input. Ground, Bus Side. Driver Enable Status Output. Noninverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, Pin A is put in a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled or VDD1 or VDD2 is powered down, Pin B is put in a high impedance state to avoid overloading the bus. Power Supply, Bus Side (Isolated 5 V Supply). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 μF and 0.1 μF. Rev. A | Page 9 of 20 ADM2485 TYPICAL PERFORMANCE CHARACTERISTICS 2.40 2.35 IDD1 _RE_ENABLE_V DD1 = 5.5V SUPPLY CURRENT (mA) 60 DRIVER PROPAGATION DELAY (ns) 50 2.30 2.25 2.20 2.15 2.10 IDD2 _DE_ENABLE_V DD1 = 5.5V 2.05 2.00 –40 tPLHA 40 tPHLB 30 tPLHB tPHLA 20 10 06021-016 –20 0 20 40 60 80 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Unloaded Supply Current vs. Temperature 5.0 RECEIVER PROPAGATION DELAY (ns) Figure 10. Driver Propagation Delay vs. Temperature 60 4.5 IDD1 SUPPLY CURRENT (mA) IDD1 _PROFIBUS LOAD_TxD = 16Mbps_V DD1 = 5.00V 50 Rx PROP DELAY, tPLH_VDD2 = 5.00V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 06021-017 IDD1 _NO LOAD_TxD = 16Mbps_V DD1 = 5.00V IDD1 _PROFIBUS LOAD_TxD = 2Mbps_VDD1 = 5.00V 40 Rx PROP DELAY, tPHL _VDD2 = 5.00V 30 20 IDD1 _NO LOAD_TxD = 2Mbps_VDD1 = 5.00V 10 –20 0 20 40 60 80 –20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Logic Side Supply Current (IDD1 = 1 mA) vs. Temperature 60 IDD2 _ PROFIBUS LOAD_TxD = 16Mbps_VDD2 = 5.00V 50 IDD2 SUPPLY CURRENT (mA) Figure 11. Receiver Propagation Delay vs. Temperature 40 IDD2 _PROFIBUS LOAD_TxD = 2Mbps_VDD2 = 5.00V 3 DI 30 B 20 IDD2 _NO LOAD_TxD = 16Mbps_VDD2 = 5.00V IDD2 _NO LOAD_TxD = 2Mbps_VDD2 = 5.00V –20 0 20 40 60 80 06021-018 10 2 A TEMPERATURE (°C) CH1 2.0V Ω CH2 2.0V Ω M20.0ns 1.25GS/s A CH3 CH3 2.0V Ω IT 8.0ps/pt 2.60V Figure 9. Bus Side Supply Current (IDD2 = 2 mA) vs. Temperature Figure 12. Driver/Receiver Propagation Delay, Low to High (RLDIFF = 54 Ω, CL1 = CL2 = 100 pF) Rev. A | Page 10 of 20 06021-021 0 –40 06021-020 0 –40 0 –40 06021-019 0 –40 ADM2485 60 50 OUTPUT CURRENT (mA) 40 1 30 20 10 3 CH1 1.0V Ω CH2 1.0V Ω CH3 2.0V Ω M10.0ns A CH1 T 19.8000ns 120mV 06021-022 0 1 2 3 4 5 OUTPUT VOLTAGE (V) Figure 13. Driver/Receiver Propagation Delay, High to Low (RLDIFF = 54 Ω, CL1 = CL2 = 100 pF) 350 300 SAFETY-LIMITING CURRENT (mA) Figure 16. Output Current vs. Receiver Output Low Voltage 4.75 4.74 4.73 4.72 4.71 4.70 4.69 4.68 4.67 –40 250 SIDE 2 200 150 SIDE 1 100 50 0 OUTPUT VOLTAGE (V) 06021-023 0 50 100 150 CASE TEMPERATURE (°C) 200 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 14. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884-2 0 –10 Figure 17. Receiver Output High Voltage vs. Temperature (IDD2 = –4 mA) 0.32 0.30 OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA) –20 –30 –40 –50 –60 –70 0 1 2 3 4 5 OUTPUT VOLTAGE (V) 0.28 0.26 0.24 0.22 06021-024 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 15. Output Current vs. Receiver Output High Voltage Figure 18. Receiver Output Low Voltage vs. Temperature (IDD2 = –4 mA) Rev. A | Page 11 of 20 06021-032 0.20 –40 06021-031 06021-025 0 ADM2485 D1 D1 1 1 D2 D2 2 06021-033 CH1 2.0V Ω CH2 2.0V Ω M400ns 125MS/s 8.0ns/pt A CH2 1.52V CH1 2.0V Ω CH2 2.0V Ω M80ns 625MS/s 1.6ns/pt A CH2 1.52V Figure 19. Switching Waveforms (50 Ω Pull-Up to VDD1 on D1 and D2) Figure 20. Switching Waveforms (Break-Before-Make, 50 Ω Pull-Up to VDD1 on D1 and D2) Rev. A | Page 12 of 20 06021-034 ADM2485 TEST CIRCUITS R VOD 06021-003 A RLDIFF VOC CL1 CL2 06021-007 R B Figure 21. Driver Voltage Measurement 375Ω Figure 25. Driver Propagation Delay GALVANIC ISOLATION VOD3 60Ω VTEST 06021-004 RTS DE OUT 150Ω 50pF 375Ω TxD Figure 22. Driver Voltage Measurement RxD A B 06021-008 RTS GALVANIC ISOLATION DE OUT 150Ω RE VDD1 GND1 VDD2 GND2 Figure 26. RTS to DE OUT Propagation Delay VDD2 A B 195Ω 110Ω TxD VCC A TxD 06021-005 RxD RE VDD1 GND1 S1 B 50pF 110Ω VOUT S2 06021-009 06021-010 195Ω GND2 VDD2 GND2 RTS Figure 23. Supply-Current Measurement Test Circuit Figure 27. Driver Enable/Disable A RTS GALVANIC ISOLATION DE OUT B RE VOUT CL TxD VCM (HF) 2.2kΩ GND2 RE VDD1 100nF VDD2 A B 195Ω 110Ω 195Ω GND2 50Ω 470nF 50Ω 110nF 22kΩ 06021-006 Figure 28. Receiver Propagation Delay FTEST , VHF +1.5V S1 –1.5V RE RxD VCC RL CL VOUT S2 06021-011 GND1 VDD2 100nF GND2 VTEST2 RE IN Figure 24. High Frequency, Common-Mode Noise Test Circuit Figure 29. Receiver Enable/Disable Rev. A | Page 13 of 20 ADM2485 CIRCUIT DESCRIPTION ELECTRICAL ISOLATION In the ADM2485, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 30). Driver input and data enable, applied to the TxD and RTS pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. Table 10. Transmitting Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off RTS H H L X X X Inputs TxD H L X X X X A H L Z Z Z Z Outputs B DE OUT L H H H Z L Z L Z L Z L iCoupler Technology The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted. VDD1 D1 D2 ISOLATION BARRIER VDD2 Table 11. Receiving Supply Status VDD1 On On On On On On Off Off VDD2 On On On On On Off On Off Input A−B >+0.2 V 1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Figure 32 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances from the ADM2485 transformers. 1000 DISTANCE = 1m 100 (1) MAXIMUM ALLOWABLE CURRENT (kA) DISTANCE = 5mm 10 DISTANCE = 100mm 0 where, if the pulses at the transformer output are greater than 1.0 V in amplitude: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of nth turn in the receiving coil (cm). The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin where induced voltages can be tolerated. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 31. 100 0.1 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 32. Maximum Allowable Current for Various Current-to-ADM2485 Spacings MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS) 10 At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board (PCB) traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care must be taken in the layout of such traces to avoid this possibility. 1 0.1 0.01 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 31. Maximum Allowable External Magnetic Flux Density vs. Magnetic Field Frequency Rev. A | Page 15 of 20 06021-027 0.001 1k 06021-028 0.01 ADM2485 APPLICATIONS INFORMATION PCB LAYOUT The ADM2485 isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 33). Bypass capacitors are most conveniently connected between Pin 3 and Pin 4 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value must be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. Bypassing between Pin 9 and Pin 16 is also recommended unless the ground wires on the VDD2 side are connected close to the package. D1 D2 GND1 VDD1 RxD RE RTS TxD VDD2 GND2 GND2 B A GND2 DE OUT GND2 APPLICATIONS DIAGRAM The ADM2485 integrates a transformer driver that, when used with an external transformer and LDO, generates an isolated 5 V power supply, to be supplied between VDD2 and GND2. D1 and D2 of the ADM2485 drive the center-tapped Transformer T1. A pair of Schottky diodes and a smoothing capacitor is used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated 5 V power supply to the ADM2485 bus-side circuitry (VDD2), as shown in Figure 34. When the ADM2485 is powered by 3.3 V on the logic side, a 1CT:2.2CT Transformer T1 is required to step up the 3.3 V to 6 V, ensuring enough headroom for the ADP3330 LDO to output a regulated 5 V output. If ADM2485 is powered by 5 V on the logic side, a 1CT:1.5CT Transformer T1 is required, ensuring enough headroom for the ADP3330 LDO to output a regulated 5 V output. ISOLATION BARRIER 1N5817 VCC 10µF MLC T1 1N5817 VCC 100nF VDD1 D1 D2 VDD2 ISO 5V 100nF 22µF ERR IN SD NR OUT 5V 10µF ADM2485 Figure 33. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the device absolute maximum ratings, thereby leading to latch-up or permanent damage. 06021-029 ADP3330 GND TRANSFORMER SUPPLIERS The transformer primarily used with the ADM2485 must be a center-tapped transformer winding. The turns ratio of the transformer must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum input voltage. Table 12 shows ADM2485 transformer suppliers. Table 12. Transformer Suppliers Manufacturer Coilcraft C&D Technologies Primary Voltage 3.3 V DA2304-AL 782485/35C Primary Voltage 5 V DA2303-AL 782485/55C GND1 ADM2485 GND2 06021-030 Figure 34. Applications Diagram Rev. A | Page 16 of 20 ADM2485 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 8 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 45° SEATING PLANE 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 35. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model ADM2485BRWZ 1 ADM2485BRWZ-REEL71 1 Data Rate (Mbps) 16 16 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W 032707-B Package Option RW-16 RW-16 Z = RoHS Compliant Part. Rev. A | Page 17 of 20 ADM2485 NOTES Rev. A | Page 18 of 20 ADM2485 NOTES Rev. A | Page 19 of 20 ADM2485 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06021-0-12/07(A) Rev. A | Page 20 of 20