Full-Duplex, Low Power,
Slew Rate Limited, EIA RS-485 Transceivers
ADM488/ADM489
APPLICATIONS
Low power RS-485 and RS-422 systems
DTE-DCE interface
Packet switching
Local area networks
Data concentration
Data multiplexers
Integrated services digital network (ISDN)
ADM488
A
R
RO
B
Z
DI
D
Y
00079-001
Meets EIA RS-485 and RS-422 standards
250 kbps data rate
Single 5 V ± 10% supply
−7 V to +12 V bus common-mode range
12 kΩ input impedance
2 kV EFT protection meets IEC1000-4-4
High EM immunity meets IEC1000-4-3
Reduced slew rate for low EM interference
Short-circuit protection
Excellent noise immunity
30 μA supply current
FUNCTIONAL BLOCK DIAGRAMS
Figure 1.
ADM489
A
R
RO
B
RE
DE
Z
DI
D
Y
00079-002
FEATURES
Figure 2.
GENERAL DESCRIPTION
The ADM488 and ADM489 are low power, differential line
transceivers suitable for communication on multipoint bus
transmission lines. They are intended for balanced data
transmission and comply with both Electronics Industries
Association (EIA) RS-485 and RS-422 standards. Both products
contain a single differential line driver and a single differential
line receiver, making them suitable for full-duplex data transfer.
The ADM489 contains an additional receiver and driver enable
control.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM488/ADM489 are fabricated on BiCMOS, an
advanced mixed technology process combining low power
CMOS with fast switching bipolar technology.
The ADM488/ADM489 are fully specified over the industrial
temperature range and are available in PDIP, SOIC, and TSSOP
packages.
The input impedance is 12 kΩ, allowing 32 transceivers to be
connected on the bus.
The ADM488/ADM489 operate from a single 5 V ± 10% power
supply. Excessive power dissipation caused by bus contention or
output shorting is prevented by a thermal shutdown circuit.
This feature forces the driver output into a high impedance state
if, during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADM488/ADM489
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Applications....................................................................................... 1
EFT Transient Protection Scheme ........................................... 11
General Description ......................................................................... 1
Fast Transient Burst Immunity (IEC1000-4-4)...................... 11
Functional Block Diagrams............................................................. 1
Radiated Immunity (IEC1000-4-3) ......................................... 12
Specifications..................................................................................... 3
EMI Emissions............................................................................ 13
Timing Specifications .................................................................. 4
Conducted Emissions ................................................................ 13
Absolute Maximum Ratings............................................................ 5
Application Information................................................................ 14
ESD Caution.................................................................................. 5
Differential Data Transmission ................................................ 14
Pin Configurations and Function Descriptions ........................... 6
Cable and Data Rate................................................................... 14
Test Circuits................................................................................... 7
Outline Dimensions ....................................................................... 15
Switching Characteristics ............................................................ 8
Ordering Guide .......................................................................... 16
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
4/06—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
11/04—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Receiving Truth Table Inputs Data Section ............ 11
Renamed General Information to Theory of Operation........... 12
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
5/01—Rev. A to Rev. B
Changes to Absolute Maximum Ratings Section......................... 3
3/01—Rev. 0 to Rev. A
Changes to ESD Specification, Absolute Maximum Ratings...... 3
6/97—Revision 0: Initial Version
Rev. D | Page 2 of 16
ADM488/ADM489
SPECIFICATIONS
VCC = 5 V ± 10%. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
DRIVER
Differential Output Voltage, VOD
2.0
1.5
1.5
Δ|VOD| for Complementary Output States
Common-Mode Output Voltage, VOC
Δ|VOC| for Complementary Output States
Output Short-Circuit Current (VOUT = High)
Output Short-Circuit Current (VOUT = Low)
CMOS Input Logic Threshold Low, VINL
CMOS Input Logic Threshold High, VINH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, VTH
Input Voltage Hysteresis, Δ VTH
Input Resistance
Input Current (A, B)
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL
CMOS Output Voltage High, VOH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
ICC
2.0
1.4
1.4
Max
Unit
Test Conditions/Comments
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
V
V
V
V
V
V
V
mA
mA
V
V
μA
R = ∞, see Figure 6
VCC = 5 V, R = 50 Ω (RS-422), see Figure 6
R = 27 Ω (RS-485), see Figure 6
VTST = –7 V to +12 V, see Figure 7, VCC = 5 V ± 5%
R = 27 Ω or 50 Ω, see Figure 6
R = 27 Ω or 50 Ω, see Figure 6
R = 27 Ω or 50 Ω
−7 V ≤ VO ≤ +12 V
−7 V ≤ VO ≤ +12 V
−7 V ≤ VCM ≤ +12 V
VCM = 0 V
−7 V ≤ VCM ≤ +12 V
VIN = 12 V
VIN = –7 V
85
±1.0
V
mV
kΩ
mA
mA
μA
V
V
mA
μA
60
74
μA
μA
±1.0
−0.2
+0.2
70
12
1
−0.8
±1
0.4
4.0
7
30
37
Rev. D | Page 3 of 16
IOUT = +4.0 mA
IOUT = −4.0 mA
VOUT = GND or VCC
0.4 V ≤ VOUT ≤ +2.4 V
Outputs unloaded, receivers enabled
DE = 0 V (disabled)
DE = 5 V (enabled)
ADM488/ADM489
TIMING SPECIFICATIONS
VCC = 5 V ± 10%. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
DRIVER
Propagation Delay Input to Output, TPLH, TPHL
Min
Max
Unit
Test Conditions/Comments
2000
ns
800
ns
250
2000
ns
250
300
250
2000
3000
ns
ns
kbps
RL Differential = 54 Ω, CL1 = CL2 = 100 pF,
see Figure 10
RL Differential = 54 Ω, CL1 = CL2 = 100 pF,
see Figure 10
RL Differential = 54 Ω, CL1 = CL2 = 100 pF,
see Figure 10
RL = 500 Ω, CL = 100 pF, see Figure 7
RL = 500 Ω, CL = 15 pF, see Figure 7
2000
ns
ns
ns
ns
kbps
250
100
Driver O/P to OP, TSKEW
Driver Rise/Fall Time, TR, TF
Driver Enable to Output Valid
Driver Disable Timing
Data Rate
RECEIVER
Propagation Delay Input to Output, TPLH, TPHL
Skew |TPLH − TPHL|
Receiver Enable, TEN1
Receiver Disable, TEN2
Data Rate
Typ
250
100
10
10
50
50
250
Rev. D | Page 4 of 16
CL = 15 pF, see Figure 10
RL = 1 kΩ, CL = 15 pF, see Figure 9
RL = 1 kΩ, CL = 15 pF, see Figure 9
ADM488/ADM489
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC
Inputs
Driver Input (DI)
Control Inputs (DE, RE)
Receiver Inputs (A, B)
Outputs
Driver Outputs
Receiver Output
Power Dissipation 8-Lead PDIP
θJA, Thermal Impedance
Power Dissipation 8-Lead SOIC
θJA, Thermal Impedance
Power Dissipation 14-Lead PDIP
θJA, Thermal Impedance
Power Dissipation 14-Lead SOIC
θJA, Thermal Impedance
Power Dissipation 16-Lead TSSOP
θJA, Thermal Impedance
Operating Temperature Range
Industrial (A Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
ESD Association S5.1 HBM Standard
EFT Rating, IEC1000-4-4
Rating
7V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−14 V to +14 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−14 V to +12.5 V
−0.5 V to VCC + 0.5 V
700 mW
120°C/W
520 mW
110°C/W
800 mW
140°C/W
800 mW
120°C/W
800 mW
150°C/W
−40°C to +85°C
−65°C to +150°C
300°C
215°C
220°C
3 kV
2 kV
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 5 of 16
ADM488/ADM489
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 2
8
ADM488
A
B
TOP VIEW
DI 3 (Not to Scale) 6 Z
GND 4
5 Y
7
00079-003
VCC 1
Figure 3. ADM488 8-Lead PDIP/SOIC Pin Configuration
Table 4. ADM488 Pin Function Descriptions
Description
Power Supply, 5 V ± 10%.
Receiver Output. When A > B by 200 mV, RO = high. If A < B by 200 mV, RO = low.
Driver Input. A logic low on DI forces Y low and Z high, while a logic high on DI forces Y high and Z low.
Ground Connection, 0 V.
Noninverting Driver, Output Y.
Inverting Driver, Output Z.
Inverting Receiver, Input B.
Noninverting Receiver, Input A.
VCC
1
16
NC
NC
2
15
A
14
B
13
NC
NC
1
14
VCC
RO
3
RO
2
13
NC
RE
4
RE
3
12
A
DE
5
12
Z
DE
4
11
B
DI
6
11
Y
DI
5
10
Z
GND
10
NC
9
Y
7
6
GND
8
NC
GND
8
9
NC
GND
ADM489
TOP VIEW
(Not to Scale)
7
NC = NO CONNECT
ADM489
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 4. ADM489 14-Lead PDIP/SOIC Pin Configuration
00079-005
Mnemonic
VCC
RO
DI
GND
Y
Z
B
A
00079-004
Pin No.
1
2
3
4
5
6
7
8
Figure 5. ADM489 16-Lead TSSOP Pin Configuration
Table 5. ADM489 Pin Function Descriptions
PDIP/SOIC
Pin No.
1, 8, 13
Mnemonic
NC
Description
No Connect. No connections are required to this pin.
2
TSSOP
Pin No.
2, 9, 10, 13,
16
3
RO
3
4
RE
4
5
DE
5
6
DI
6, 7
9
10
11
12
14
7, 8
11
12
14
15
1
GND
Y
Z
B
A
VCC
Receiver Output. When enabled, if A > B by 200 mV then RO = high. If A < B by 200 mV then
RO = low.
Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a
high impedance state.
Driver Output Enable. A high level enables the driver differential outputs, Y and Z. A low level
places it in a high impedance state.
Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, while a logic
high on DI forces Y high and Z low.
Ground Connection, 0 V.
Noninverting Driver, Output Y.
Inverting Driver, Output Z.
Inverting Receiver, Input B.
Noninverting Receiver, Input A.
Power Supply, 5 V ± 10%.
Rev. D | Page 6 of 16
ADM488/ADM489
TEST CIRCUITS
VCC
R
A
VOC
RL
S1
DE
00079-019
R
0V OR 3V
B
S2
CL
VOUT
00079-021
VOD
DE IN
Figure 8. Driver Voltage Measurement Test Circuit 2
Figure 6. Driver Voltage Measurement Test Circuit
VCC
+1.5V
S1
60Ω
375Ω
RE
–1.5V
VTST
00079-020
VOD3
RL
S2
CL
VOUT
00079-022
375Ω
RE IN
Figure 9. Receiver Enable/Disable Test Circuit
3V
DE
Figure 7. Driver Enable/Disable Test Circuit
CL1
Y
DI
A
RLDIFF
D
CL2
B
RE
00079-023
Z
RO
R
Figure 10. Driver/Receiver Propagation Delay Test Circuit
Rev. D | Page 7 of 16
ADM488/ADM489
SWITCHING CHARACTERISTICS
3V
1.5V
3V
1.5V
TPLH
0V
DE
1.5V
1.5V
TPHL
B
0V
TZL
1/2VO
TLZ
VO
+VO
2.3V
VOL + 0.5V
TSKEW
TSKEW
90% POINT
90% POINT
VOL
THZ
TZH
VOH
10% POINT
TR
TF
A, B
VOH – 0.5V
2.3V
0V
Figure 13. Driver Enable/Disable Timing
Figure 11. Driver Propagation Delay, Rise/Fall Timing
3V
RE
1.5V
1.5V
0V
TZL
TLZ
0V
0V
R
1.5V
VOL + 0.5V
O/P LOW
TPLH
VOL
TPHL
TZH
VOH
RO
1.5V
THZ
O/P HIGH
1.5V
VOL
R
1.5V
VOH
VOH – 0.5V
0V
Figure 14. Receiver Enable/Disable Timing
Figure 12. Receiver Propagation Delay
Rev. D | Page 8 of 16
00079-009
A–B
00079-007
–VO
10% POINT
00079-006
0V
00079-008
A, B
A
ADM488/ADM489
40
0
35
–10
–20
30
OUTPUT CURRENT (mA)
25
20
15
10
–30
–40
–50
–60
–70
5
0
0.5
2.0
1.0
1.5
OUTPUT VOLTAGE (V)
2.5
–90
00079-010
0
–80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
4.0
4.5
00079-013
OUTPUT CURRENT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
5.0
Figure 15. Output Current vs. Receiver Output Low Voltage
Figure 18. Output Current vs. Driver Output High Voltage
0
80
70
60
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
–5
–10
–15
50
40
30
20
3.8
4.0
4.2
4.4
OUTPUT VOLTAGE (V)
4.6
4.8
5.0
Figure 16. Output Current vs. Receiver Output High Voltage
0
0
0.5
1.0
1.5
2.5
2.0
3.0
OUTPUT VOLTAGE (V)
3.5
4.0
00079-014
3.6
00079-011
10
–20
3.4
4.5
Figure 19. Output Current vs. Driver Differential Output Voltage
90
80
T
100
90
60
T
50
40
RO
T
30
20
10
0
0.5
1.5
1.0
2.0
OUTPUT VOLTAGE (V)
2.5
3.0
00079-015
0%
10
0
DI
00079-012
OUTPUT CURRENT (mA)
70
Figure 17. Output Current vs. Driver Output Low Voltage
Figure 20. Driving 4000 Ft. of Cable
Rev. D | Page 9 of 16
ADM488/ADM489
80
70
100
LIMIT
60
90
10dB/DIV
dB (µV)
50
40
30
20
10
0%
500kHz/DIV
5MHz
0
80
70
60
LIMIT
30
20
10
30
200
FREQUENCY (MHz)
00079-017
dB (µV)
50
0
0.6
1
3
6
10
log FREQUENCY (0.15–30) (MHz)
Figure 21. Driver Output Waveform and FFT Plot Transmitting at 150 kHz
40
0.3
Figure 22. Radiated Emissions
Rev. D | Page 10 of 16
Figure 23. Conducted Emissions
30
00079-018
0
00079-016
10
ADM488/ADM489
THEORY OF OPERATION
The ADM488/ADM489 are ruggedized RS-485 transceivers
that operate from a single 5 V supply. They contain protection
against radiated and conducted interference and are ideally
suited for operation in electrically harsh environments or where
cables can be plugged/unplugged. They are also immune to
high RF field strengths without special shielding precautions.
They are intended for balanced data transmission and comply
with both EIA RS-485 and RS-422 standards. They contain a
differential line driver and a differential line receiver, and are
suitable for full-duplex data transmission.
Table 6 and Table 7 show the truth tables for transmitting and
receiving.
Table 6. Transmitting Truth Table
1
The input impedance on the ADM488/ADM489 is 12 kΩ,
allowing up to 32 transceivers on the differential bus. The
ADM488/ADM489 operate from a single 5 V ± 10% power
supply. A thermal shutdown circuit prevents excessive power
dissipation caused by bus contention or by output shorting.
This feature forces the driver output into a high impedance state
if, during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.
1
VCC
RO
R
B
ADM488
DI
D
ADM489
RS-485/RS-422 LINK
Z
B
Y
A
R
GND
GND
Figure 24. ADM488/ADM489 Full-Duplex Data Link
The communications network can be extended to include
multipoint connections, as shown in Figure 30. As many as
32 transceivers can be connected to the bus.
0
1
Hi-Z
Hi-Z
1
0
Hi-Z
Hi-Z
X = Don’t care.
RE
DE
A to B
Output
RO
0
0
0
1
0
0
0
0
≥ +0.2 V
≤ −0.2 V
Inputs O/C
X1
1
0
1
Hi-Z
X = Don’t care.
RO
RE
DE
1
0
X1
X1
The fast transient burst test, defined in IEC1000-4-4, simulates
this arcing, and its waveform is illustrated in Figure 25. It
consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
DI
D
Z
1
1
0
0
IEC1000-4-4 (previously 801-4) covers electrical fast transient
burst (EFT) immunity. Electrical fast transients occur as a result
of arcing contacts in switches and relays. The tests simulate the
interference generated when, for example, a power relay disconnects
an inductive load. A spark is generated due to the well known
back EMF effect. In fact, the spark consists of a burst of sparks
as the relay contacts separate. The voltage appearing on the line,
therefore, consists of a burst of extremely fast transient impulses.
A similar effect occurs when switching on fluorescent lights.
DE
Y
Y
X1
X1
0
1
FAST TRANSIENT BURST IMMUNITY (IEC1000-4-4)
0.1µF
A
Outputs
The ADM488/ADM489 use protective clamping structures on
their inputs and outputs that clamp the voltage to a safe level
and dissipate the energy present in ESD (electrostatic) and EFT
(electrical fast transients) discharges.
5V
VCC
Z
EFT TRANSIENT PROTECTION SCHEME
00079-024
RE
DI
Inputs
The ADM488/ADM489 can transmit at data rates up to
250 kbps. A typical application for the ADM488/ADM489 is
illustrated in Figure 24 showing a full-duplex link where data is
transferred at rates of up to 250 kbps. A terminating resistor is
shown at both ends of the link. This termination is not critical
because the slew rate is controlled by the ADM488/ADM489
and reflections are minimized.
0.1µF
Inputs
DE
Table 7. Receiving Truth Table
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating). A
high level of robustness is achieved using internal protection
circuitry, eliminating the need for external protection components such as tranzorbs or surge suppressors. Furthermore,
low electromagnetic emissions are achieved using slew limited
drivers, minimizing interference both conducted and radiated.
5V
RE
Four severity levels are defined in terms of an open-circuit voltage
as a function of installation environment. The installation
environments are defined as
•
Well protected
•
Protected
•
Typical industrial
•
Severe industrial
Rev. D | Page 11 of 16
ADM488/ADM489
V
Test results are classified according to the following:
t
300ms
•
Normal performance within specification limits.
•
Temporary degradation or loss of performance that is selfrecoverable.
•
Temporary degradation or loss of function or performance
that requires operator intervention or system reset.
•
Degradation or loss of function that is not recoverable due
to damage.
16ms
V
5ns
50ns
00079-025
t
0.2/0.4ms
Figure 25. IEC1000-4-4 Fast Transient Waveform
Table 8 shows the peak voltages for each of the environments.
Table 8. Peak Voltages
Level
1
2
3
4
VPEAK (kV) PSU
0.5
1
2
4
VPEAK (kV) I/O
0.25
0.5
1
2
RADIATED IMMUNITY (IEC1000-4-3)
A simplified circuit diagram of the actual EFT generator is
shown in Figure 26.
These transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp is 1 m long and completely surrounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typical) between the clamp and the cable. High
energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns), as specified by the standard, result in very
effective coupling. This test is very severe because high voltages
are coupled onto the signal lines. The repetitive transients often
cause problems, while single pulses do not. Destructive latch-up
can be induced due to the high energy content of the transients.
Note that this stress is applied while the interface products are
powered up and transmitting data. The EFT test applies hundreds of pulses with higher energy than ESD. Worst-case
transient current on an I/O line can be as high as 40 A.
RC
RM CD
L
CC
ZS
IEC1000-4-3 (previously IEC801-3) describes the measurement
method and defines the levels of immunity to radiated electromagnetic fields. It was originally intended to simulate the
electromagnetic fields generated by portable radio transceivers
or any other device that generates continuous wave-radiated
electromagnetic energy. Its scope has been broadened to include
spurious EM energy, which can be radiated from fluorescent
lights, thyristor drives, inductive loads, and so on.
Testing for immunity involves irradiating the device with an
EM field. Test methods include the use of anechoic chamber,
stripline cell, TEM cell, and GTEM cell. These consist of two
parallel plates with an electric field developed between them.
The device under test is placed between the plates and exposed
to the electric field. The three severity levels have field strengths
ranging from 1 V/m to 10 V/m. Results are classified as follows:
•
Normal operation.
•
Temporary degradation or loss of function that is selfrecoverable when the interfering signal is removed.
•
Temporary degradation or loss of function that requires
operator intervention or system reset when the interfering
signal is removed.
•
Degradation or loss of function that is not recoverable due
to damage.
50Ω
OUTPUT
00079-026
HIGH
VOLTAGE
SOURCE
The ADM488/ADM489 have been tested under worst-case
conditions using unshielded cables, and meet Classification 2 at
Severity Level 4. Data transmission during the transient
condition is corrupted, but it can be resumed immediately
following the EFT event without user intervention.
Figure 26. EFT Generator
Rev. D | Page 12 of 16
ADM488/ADM489
The ADM488/ADM489 comfortably meet Classification 1 at
the most stringent (Level 3) requirement. In fact, field strengths
up to 30 V/m showed no performance degradation, and errorfree data transmission continued even during irradiation.
Table 9. Field Strengths
Level V/m
1
2
3
Field Strength
1
3
10
The objective is to control the level of both conducted and
radiated emissions.
For ease of measurement and analysis, conducted emissions are
assumed to predominate below 30 MHz, while radiated
emissions predominate above this frequency.
CONDUCTED EMISSIONS
EMI EMISSIONS
The ADM488/ADM489 contain internal slew rate limiting to
minimize the level of electromagnetic interference generated.
Figure 27 shows an FFT plot when transmitting a 150 kHz data
stream.
Conducted emissions are a measure of noise that is conducted
onto the main power supply. The noise is measured using a
LISN (line impedance stabilizing network) and a spectrum
analyzer. The test setup is shown in Figure 28. The spectrum
analyzer is set to scan the spectrum from 0 MHz to 30 MHz.
Figure 29 shows that the level of conducted emissions from the
ADM488/ADM489 is well below the maximum allowable
limits.
SPECTRUM
ANALYZER
90
DUT
LISN
PSU
00079-028
100
Figure 28. Conducted Emissions Test Setup
10dB/DIV
80
70
10
60
0%
LIMIT
5MHz
40
Figure 27. Driver Output Waveform and FFT Plot Transmitting at 150 kHz
30
The slew limiting attenuates the high frequency components.
EMI is, therefore, reduced, as are reflections due to improperly
terminated cables.
20
10
0
EN55022, CISPR22 defines the permitted limits of radiated and
conducted interference from information technology
equipment (ITE).
Rev. D | Page 13 of 16
0.3
0.6
36
1
log FREQUENCY (0.15–30) (MHz)
10
Figure 29. Conducted Emissions
30
00079-029
500kHz/DIV
dB (µV)
0
00079-027
50
ADM488/ADM489
APPLICATION INFORMATION
DIFFERENTIAL DATA TRANSMISSION
CABLE AND DATA RATE
Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals, which appear as common-mode voltages on
the line. Two main standards that specify the electrical
characteristics of transceivers used in differential data
transmission are approved by the EIA.
The transmission line of choice for RS-485 communications is a
twisted pair. Twisted-pair cable tends to cancel common-mode
noise and also causes cancellation of the magnetic fields generated by the current flowing through each wire, thereby reducing
the effective inductance of the pair.
The RS-422 standard specifies data rates up to 10 MBaud and
line lengths up to 4000 ft. A single driver can drive a transmission line with up to 10 receivers.
To cater to true multipoint communications, the RS-485 standard was defined to meet or exceed the requirements of RS-422.
It also allows up to 32 drivers and 32 receivers to be connected
to a single bus. An extended common-mode range of −7 V to
+12 V is defined. The most significant difference between the
RS-422 and RS-485 is that the RS-485 drivers can be disabled,
thereby allowing up to 32 receivers to be connected to a single
line. Only one driver should be enabled at a time, but the RS485 standard contains additional specifications to guarantee
device safety in the event of line contention.
The ADM488/ADM489 are designed for bidirectional data
communications on multipoint transmission lines. A typical
application showing a multipoint transmission network is
illustrated in Figure 30. An RS-485 transmission line can have
up to 32 transceivers on the bus. Only one driver can transmit
at a particular time, but multiple receivers can be simultaneously enabled.
As with any transmission line, it is important that reflections be
minimized. This can be achieved by terminating the extreme
ends of the line using resistors equal to the characteristic impedance of the line. Stub lengths of the main line should also be
kept as short as possible. A properly terminated transmission
line appears purely resistive to the driver.
Table 10. Comparison of RS-422 and RS-485 Interface Standards
Specification
Transmission Type
Maximum Data Rate
Maximum Cable Length
Minimum Driver Output Voltage
Driver Load Impedance
Receiver Input Resistance
Receiver Input Sensitivity
Receiver Input Voltage Range
Number of Drivers/Receivers per Line
RS-422
Differential
10 MB/s
4000 ft.
±2 V
100 Ω
4 kΩ minimum
±200 mV
−7 V to +7 V
1/10
RT
RS-485
Differential
10 MB/s
4000 ft.
±1.5 V
54 Ω
12 kΩ minimum
±200 mV
−7 V to +12 V
32/32
RT
D
D
R
R
R
R
D
Figure 30. Typical RS-485 Network
Rev. D | Page 14 of 16
00079-030
D
ADM488/ADM489
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
4
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
1
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210
(5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
7
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
0.25 (0.0098)
0.10 (0.0040)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
Figure 31. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
8.75 (0.3445)
8.55 (0.3366)
5
6.20 (0.2440)
4 5.80 (0.2284)
1.27 (0.0500)
BSC
0.060 (1.52)
MAX
0.210
(5.33)
MAX
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
8
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
4.00 (0.1574)
3.80 (0.1497) 1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
PIN 1
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
8
4.00 (0.1575)
3.80 (0.1496)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
14
8
1
7
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.50 (0.0197)
× 45°
0.25 (0.0098)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions show in millimeters and (inches)
Figure 34. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. D | Page 15 of 16
ADM488/ADM489
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM488AN
ADM488ANZ1
ADM488AR
ADM488AR-REEL
ADM488AR-REEL7
ADM488ARZ 1
ADM488ARZ-REEL1
ADM488ARZ-REEL71
ADM489AN
ADM489ANZ1
ADM489AR
ADM489AR-REEL
ADM489AR-REEL7
ADM489ARZ1
ADM489ARZ-REEL1
ADM489ARZ-REEL71
ADM489ARU
ADM489ARU-REEL
ADM489ARU-REEL7
ADM489ARUZ1
ADM489ARUZ-REEL1
ADM489ARUZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00079-0-4/06(D)
Rev. D | Page 16 of 16
Package Option
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-14
N-14
R-14
R-14
R-14
R-14
R-14
R-14
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
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