ADM691AR

a Microprocessor Supervisory Circuits ADM691A/ADM693A/ADM800L/M FEATURES Low Power Consumption: Precision Voltage Monitor 62% Tolerance on ADM800L/M Reset Time Delay—200 ms, or Adjustable 1 mA Standby Current Automatic Battery Backup Power Switching Fast Onboard Gating of Chip Enable Signals Also Available in TSSOP Package (ADM691A) APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical mP Power Monitoring FUNCTIONAL BLOCK DIAGRAM BATT ON 4.65V1 VCC VOUT VBATT CHIP ENABLE OUTPUT CONTROL The ADM691A/ADM693A/ADM800L/ADM800M family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power-failure warning. The family of products provides an upgrade for the MAX691A/93A/800M family of products. All parts are available in 16-pin DIP and SO packages. The ADM691A is also available in a space-saving TSSOP package. The following functionality is provided: 1. Power-on reset output during power-up, power-down and brownout conditions. The circuitry remains operational with VCC as low as 1 V. 2. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic. 3. A reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V. CEOUT CEIN OSC IN OSC SEL RESET & WATCHDOG TIMEBASE RESET & GENERATOR RESET RESET WATCHDOG INPUT (WDI) GENERAL DESCRIPTION LOW LINE WATCHDOG TRANSITION DETECTOR WATCHDOG OUTPUT (WDO) WATCHDOG TIMER POWER FAIL INPUT (PFI) POWER FAIL OUTPUT (PFO) 1.25V ADM691A/ADM693A ADM800L/ADM800M 1VOLTAGE INPUT POWER DETECTOR = 4.4V (ADM693A/ADM800M) +5V 7805 0.1µF VCC CMOS RAM R1 VCC VBATT BATTERY PFI GND R2 NC BAT ON VOUT CEOUT ADM691A CEIN ADM693A ADM800L ADM800M WDI PFO OSC IN OSC SEL LOW LINE ADDRESS DECODE RESET A0–A15 µP POWER I/O LINE NMI µP RESET WDO SYSTEM STATUS INDICATORS Figure 1. Typical Application REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. 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Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 ADM691A/ADM693A/ADM800L/M–SPECIFICATIONS (VCC = 4.75 V to 5.5 V (ADM691A, ADM800L) 4.5 V to 5.5 V (ADM693A, ADM800M) VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted) Parameter BATTERY BACKUP SWITCHING VCC, VBATT Operating Voltage Range VOUT Output Voltage VCC to VOUT Output Resistance VOUT in Battery Backup Mode Min 0 VCC – 0.05 VCC – 0.3 Typ V V V Ω V V V Ω Ω Ω µA µA 1.2 70 0.04 12 20 25 100 1 –0.1 –1.0 BATT ON Output Short Circuit Current 1 4.5 4.25 4.55 4.3 140 1.0 70 Watchdog Timeout Period, External Clock Minimum WDI Input Pulse Width RESET Output Voltage 5.5 VBATT – 0.3 VBATT – 0.25 VBATT – 0.15 Battery Switchover Threshold VCC–VBATT Battery Switchover Hysteresis BATT ON Output Voltage Low RESET AND WATCHDOG TIMER Reset Voltage Threshold ADM691A, ADM800L ADM693A, ADM800M ADM800L, VCC Falling ADM800M, VCC Falling Reset Threshold Hysteresis VCC to RESET Delay LOW LINE to RESET Delay Reset Timeout Period Internal Oscillator Reset Timeout Period External Clock Watchdog Timeout Period, Internal Oscillator Unit VCC – 0.02 VCC – 0.2 0.8 VBATT to VOUT Output Resistance Supply Current (Excludes IOUT) Supply Current in B. Backup (Excludes IOUT) Battery Standby Current (+ = Discharge, – = Charge) Max +0.02 +0.02 VBATT + 0.03 VBATT – 0.03 60 0.1 0.4 0.7 1.5 60 15 100 4.65 4.40 15 80 800 200 2048 1.6 100 4096 1024 4.75 4.50 4.70 4.45 280 2.25 140 100 0.004 0.1 0.3 0.4 7 0.4 20 3.5 RESET Output Short Circuit Current RESET Output Voltage Low LOW LINE Output Voltage LOW LINE Short Circuit Source Current WDO Output Voltage 0.1 0.4 3.5 1 15 100 0.4 3.5 WDO Short Circuit Source Current WDI Input Threshold Logic Low Logic High WDI Input Current POWER FAIL DETECTOR PFI Input Threshold ADM69xA PFI Input Threshold ADM800L/M PFI Input Current PFO Output Voltage PFO Short Circuit Source Current PFI to PFO Delay 3 0.75 × VCC –50 1.2 1.225 3.5 1 10 0.8 –10 20 1.25 1.25 ± 0.01 15 25 60 –2– µA µA V V mV V V mA µA V V V V mV µs ns ms Cycles s ms Cycles Cycles ns V V V mA V V V µA V V mA 50 V V µA µA 1.3 1.275 ± 25 0.4 V V nA V 100 µA µs µs Test Conditions/Comments IOUT = 25 mA IOUT = 250 mA VCC = 4.5 V VBATT = 4.5 V, IOUT = 20 mA VBATT = 2.8 V, IOUT = 10 mA VBATT = 2.0 V, IOUT = 5 mA VBATT = 4.5 V VBATT = 2.8 V VBATT = 2.0 V VCC > (VBATT – 1 V) VCC < (VBATT – 1.2 V), VBATT = 2.8 V 5.5 V > VCC > VBATT + 0.2 V (VBATT +0.2 V) < VCC , TA = +25°C (VBATT +0.2 V) < VCC Power Up Power Down ISINK = 3.2 mA ISINK = 25 mA Sink Current Source Current TA = +25°C TA = +25°C Power Down Power Up Power Up Long Period Short Period Long Period Short Period VIL = 0.4, VIH = 0.75 × VCC ISINK = 50 µA, VCC = 1 V, VBATT = 0 V ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 1.6 mA, VCC = 5 V ISINK = 3.2 mA ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 1 µA, VCC = 5 V ISINK = 3.2 mA, VCC = 4.25 V ISOURCE = 500 µA, VCC = 5 V WDI = 0 V WDI = VOUT VCC = 5 V VCC = 5 V ISINK = 3.2 mA ISOURCE = 1 µA VIN = –20 mV VIN = 20 mV REV. 0 ADM691A/ADM693A/ADM800L/M Parameter Min CHIP ENABLE GATING CEIN Leakage Current CEIN to CEOUT Resistance CEIN to CEOUT Propagation Delay CEOUT Short-Circuit Current CEOUT Output Voltage 0.1 3.5 2.7 RESET to CEOUT Propagation Delay OSCILLATOR OSC IN Input Current OSC In Input Pullup Current OSC SEL Input Pullup Current OSC IN Frequency Range OSC IN Threshold Voltage Typ Max Units Test Conditions/Comments ± 0.005 40 6 0.75 ±1 150 10 2.0 µA Ω ns mA V V µs Disable Mode Enable Mode RIN = 50 Ω, CLOAD = 50 pF Disable Mode, CEOUT = 0 V VCC = 5 V, IOUT = –100 µA VCC = 0 V, VBATT = 2.8 V, IOUT = 1 µA Power Down ±5 100 100 µA µA µA kHz V V kHz OSC SEL = 0 V OSC SEL = VOUT or Floating OSC SEL = 0 V OSC SEL = 0 V VIH VIL OSC SEL = 0 V, COSC = 47 pF 12 0.1 10 10 500 VOUT – 0.6 3.65 100 VOUT – 0.4 OSC IN Frequency with Ext Capacitor 2.00 NOTES 1 Either V CC or VBATT can be 0 V if the other > +2.0 V. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (TA = 25°C unless otherwise noted) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V Input Current VCC (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mA VCC (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA VBATT (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA GND, BATT ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . 842 mW θϑA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, R-16 Narrow SOIC . . . . . . . . . . . 700 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 110°W Power Dissipation, R-16 Wide SOIC . . . . . . . . . . . . . 762 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . 500 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Model Temperature Range Package Option ADM691AAN ADM691AARN ADM691AARW ADM691AARU ADM693AAN ADM693AARN ADM693AARW ADM800LAN ADM800LARN ADM800LARW ADM800MAN ADM800MARN ADM800MARW –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C N-16 R-16N R-16W RU-16 N-16 R-16N R-16W N-16 R-16N R-16W N-16 R-16N R-16W *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. Table I. Product Selection Table Part No. Power On Reset Time Low VCC Threshold Watchdog Timeout Battery Backup Switching Base Drive Ext PNP Chip Enable Signals ADM691A ADM693A ADM800M ADM800L 200 ms or Adj. 200 ms or Adj. 200 ms or Adj. 200 ms or Adj. 4.65 V ± 3% 4.4 V ± 3% 4.4 V ± 2% 4.65 V ± 2% 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. 100 ms, 1.6 s, Adj. Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes REV. 0 –3– ADM691A/ADM693A/ADM800L/M PIN DESCRIPTIONS Pin Mnemonic Function 1 VBATT 2 VOUT 3 4 5 VCC GND BATT ON 6 LOW LINE 7 OSC IN 8 OSC SEL 9 PFI 10 PFO 11 WDI 12 CEOUT 13 14 CEIN WDO 15 RESET 16 RESET Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is not used. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to VCC if a backup battery is not being used. Power Supply Input; +5 V. 0 V. Ground reference for all signals. Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an external PNP transistor to increase the output current above the 250 mA rating of VOUT. Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises above the reset threshold. Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period. (See Table II and Figure 4.) Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 10 µA internal pullup. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than 1.25 V, PFO goes low. Connect PFI to GND or VOUT when not used. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply. Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when reset is asserted, CEOUT will remain low for 15 µs or until CEIN goes high, whichever occurs first. Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI is unconnected. Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after VCC goes above the reset threshold. Logic Output. RESET is an open-drain output. It is the inverse of RESET. PIN CONFIGURATIONS VBATT 1 16 RESET VOUT 2 15 RESET VCC 3 GND 4 BATT ON 5 LOW LINE 6 OSC IN OSC SEL ADM691A ADM693A ADM800L ADM800M 14 WDO 13 CEIN 12 CEOUT 11 WDI TOP VIEW 7 (Not to Scale) 10 PFO 8 9 –4– PFI REV. 0 Typical Performance Curves– ADM691A/ADM693A/ADM800L/M 1.2 100 VCC TO VOUT ON RESISTANCE – R VCC SUPPLY CURRENT – µA 90 80 70 60 50 40 1.1 1.0 0.9 0.8 0.7 30 20 –50 –25 0 25 50 75 TEMPERATURE – °C 100 0.6 –50 125 –30 –10 10 30 50 TEMPERATURE – °C 70 90 Figure 5. VCC to VOUT ON-Resistance vs. Temperature Figure 2. ICC vs. Temperature: Normal Operation 80 60 60 VCC TO VOUT – mV BATTERY SUPPLY CURRENT – nA 70 55 50 45 40 ROUT = 0.67Ω 50 40 30 20 35 10 30 –50 –30 –10 10 30 50 TEMPERATURE – °C 70 0 40 90 60 80 IOUT – mA 100 120 Figure 6. VCC to VOUT Voltage Drop vs. Current Figure 3. IBATT vs. Temperature: Battery Backup Mode 70 80 60 ROUT = 7Ω VBATT TO VOUT – mV CEON RESISTANCE – Ω 70 60 50 40 30 20 –50 40 30 20 10 0 –25 0 25 50 75 TEMPERATURE – °C 100 4 125 6 8 10 IOUT – mA Figure 7. VBATT to VOUT Voltage Drop vs. Current Figure 4. Chip Enable ON-Resistance vs. Temperature REV. 0 50 –5– ADM691A/ADM693A/ADM800L/M 16 10 VBATT = 2.8V 9 14 PROPAGATION DELAY – ns 8 IBATT – µA 7 6 5 4 3 2 0.5 1.0 1.5 2.0 2.5 3.0 VCC – V 3.5 4.0 4.5 5.0 6 4 0 50 100 150 200 250 300 LOAD CAPACITANCE – pF Figure 11. Chip Enable Propagation Delay vs. Load Capacitance 100 230 220 LONG WATCHDOG TIMEOUT PERIOD RESET DELAY – ms WATCHDOG AND RESET TIMEOUT PERIOD – s 8 0 0 Figure 8. Battery Current vs. Input Supply Voltage 10 RESET ACTIVE TIMEOUT PERIOD = > 1 SHORT WATCHDOG TIMEOUT PERIOD 210 200 190 180 0.1 10 100 COSC – pF 170 –50 1k 1200 6.5 1000 RESET OUTPUT RESISTANCE – Ω 7.0 6.0 5.5 5.0 4.5 4.0 –50 –25 0 25 50 75 TEMPERATURE – °C 100 –30 –10 10 30 50 TEMPERATURE – °C 70 90 Figure 12. Reset Timeout Relay vs. Temperature Figure 9. Watchdog and Reset Timeout Period vs. OSC IN Capacitor PROPAGATION DELAY – ns 10 2 1 0 12 600 400 Figure 10. Chip Enable Propagation Delay vs. Temperature VCC = 0V, VBATT = 2.8V SINKING CURRENT 200 0 –50 125 VCC = 5V, VBATT = 2.8V SOURCING CURRENT 800 –20 40 70 10 TEMPERATURE – °C 100 130 Figure 13. RESET Output Resistance vs. Temperature –6– REV. 0 ADM691A/ADM693A/ADM800L/M 100 100 90 90 10 10 0% 0% 1V 400ms 1V Figure 14. RESET Output Voltage vs. Supply POWER FAIL RESET OUTPUT RESET is an active low output that provides a reset signal to the Microprocessor whenever VCC is at an invalid level. When VCC falls below the reset threshold, the RESET output is forced low. The reset voltage threshold is 4.65 V (ADM691A/ ADM800L) or 4.4 V (ADM693A/ADM800M). On power-up RESET will remain low for 200 milliseconds after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize. On powerdown, the RESET output remains low with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. If RESET is required to be low for voltages below 1 V, this may be achieved by connecting a pull-down resistor on the RESET line. The resistor will help maintain RESET low down to VCC = 0 V. Note that this is only necessary if VBATT is below 2 V. With battery voltages ≥2 V RESET will function correctly with VCC from 0 V to +5.5 V. 10µs Figure 15. RESET Response Time The normal (short) timeout period becomes effective following the first transition of WDI after reset has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 seconds). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). If floating, an internal resistor network biases WDI to around 1.6 V. BATT ON 4.65V1 LOW LINE VCC VOUT This reset active time is adjustable by using an external oscillator or by connecting an external capacitor to the OSC IN pin. Refer to Table II. VBATT CHIP ENABLE OUTPUT CONTROL The guaranteed minimum and maximum thresholds of the ADM691A/ADM800L are 4.5 V and 4.75 V, while the guaranteed thresholds of the ADM693A/ADM800M are 4.25 V and 4.5 V. The ADM691A/ADM800L is therefore compatible with 5 V supplies with a +10%, –5% tolerance while the ADM693A/ ADM800M is compatible with 5 V ± 10% supplies. CEOUT CEIN OSC IN OSC SEL RESET & WATCHDOG TIMEBASE WATCHDOG TRANSITION DETECTOR REV. 0 WATCHDOG TIMER POWER FAIL INPUT (PFI) WATCHDOG OUTPUT (WDO) POWER FAIL OUTPUT (PFO) 1.25V ADM691A/ADM693A ADM800L/ADM800M Watchdog Timer Reset The watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on WDI or by VCC falling below the reset threshold. RESET RESET WATCHDOG INPUT (WDI) In addition to RESET an active high RESET output is provided. This is the complement of RESET and is useful for processors requiring an active high RESET signal. The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a reset pulse is generated. The watchdog timeout period may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. Note that even if the short timeout period is selected, the first time out immediately following a reset is 1.6 sec. This is to allow additional time for the microprocessor to regain control following a reset. RESET & GENERATOR 1VOLTAGE DETECTOR = 4.4V (ADM693A/ADM800M) Figure 16. Functional Block Diagram Watchdog Output (WDO) The Watchdog Output WDO provides a status output that goes low if the watchdog timer “times out” and remains low until set high by the next transition on the watchdog input. WDO is also set high when VCC goes below the reset threshold. If WDI remains high or low indefinitely, RESET and RESET will generate 200 ms pulses every 1.6 sec. –7– ADM691A/ADM693A/ADM800L/M When VCC is below the reset threshold, the watchdog function is disabled and WDI goes high impedance as it is disconnected from its internal resistor network. Changing the Watchdog and Reset Timeout The watchdog and reset timeout periods may be controlled using OSC SEL and OSC IN. Please refer to Table II. With both these inputs floating (or connected to VOUT) as in Figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure 16, the reset timeout period remains at 200 ms but a short (100 ms) watchdog timeout period is selected (except immediately following a reset where it reverts to 1.6 sec). By connecting OSC SEL to GND it is possible to select alternative timeout periods by either connecting a capacitor from OSC IN to GND or by overdriving OSC IN with an external clock. With an external capacitor, the watchdog timeout period is The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods. VCC OSC SEL tRS RESET THRESHOLD tRS 80µs 80µs RESET Twd (ms) = 600 (C/47 pF) RESET and the reset active period is Treset (ms) = 1200 (C/47 pF) CEIN With an external clock connected to OSC IN, the timeout periods become 12µs CEOUT Twd = 1024 (1/fCLK) Treset = 2048 (1/fCLK) Figure 17. RESET and Chip Enable Timing Battery-Switchover Section During normal operation with VCC higher than the reset threshold and higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typical on-resistance of 0.75 Ω and can supply up to 250 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 250 mA. If this is the case then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used. 8 OSC SEL ADM69_A ADM800_ 7 CLOCK 0 TO 250kHz OSC IN Figure 18a. External Clock Source If the continuous output current requirement at VOUT exceeds 250 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor. NC 8 OSC SEL ADM69_A ADM800_ NC If VCC drops below VBATT and below the reset threshold, battery backup is selected. A 7 Ω MOSFET switch connects the VBATT input to VOUT. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.04 µA. 7 OSC IN Figure 18b. Internal Oscillator (1.6 s Watchdog) 8 OSC SEL ADM69_A ADM800_ 7 High value capacitors, either standard electrolytic or the faradsize double layer capacitors, can also be used for short-term memory backup. OSC IN COSC If the battery-switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. Figure 18c. External Capacitor Table II. Reset Pulse Width and Watchdog Timeout Selections OSC SEL OSC IN Watchdog Timeout Period Normal Immediately After Reset Reset Active Period Low Low Floating Floating External Clock Input External Capacitor Low Floating or VOUT 1024 clks 600 ms × C/47 pF 100 ms 1.6 s 2048 clks 1200 ms × C/47 pF 200 ms 200 ms –8– 4096 clks 2.4 s × C/47 pF 1.6 s 1.6 s REV. 0 ADM691A/ADM693A/ADM800L/M 8 INPUT POWER OSC SEL R1 ADM69_A ADM800_ 7 OSC IN POWER FAIL INPUT 1.25V PFO POWER FAIL OUTPUT R2 COSC Figure 20. Power Fail Comparator Figure 18d. Internal Oscillator (100 ms Watchdog) Table III. Input and Output Status in Battery Backup Mode WDI Signal Status VBATT VOUT Supply Current is