ADM696SQ

a FEATURES Superior Upgrade for MAX696/MAX697 Specified Over Temperature Adjustable Low Line Voltage Monitor Power OK/Reset Time Delay Reset Assertion Down to 1 V VCC Watchdog Timer—100 ms, 1.6 s, or Adjustable Low Switch On Resistance 1.5 V Normal, 20 V in Backup 600 nA Standby Current Automatic Battery Backup Switching (ADM696) Fast On-Board Gating of Chip Enable Signals (ADM697) Voltage Monitor for Power Fail or Low Battery Warning Microprocessor Supervisory Circuits ADM696/ADM697 FUNCTIONAL BLOCK DIAGRAMS BATT ON VBATT VOUT VCC LLIN LOW LINE RESET RESET GENERATOR RESET OSC IN APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical mP Power Monitoring OSC SEL TIMEBASE FOR RESET AND WATCHDOG WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER WATCHDOG OUTPUT (WDO) ADM696 POWER FAIL INPUT (PFI) POWER FAIL OUTPUT (PFO) 1.3V GENERAL DESCRIPTION The ADM696/ADM697 supervisory circuits offer complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup-battery switchover, watchdog timer, CMOS RAM write protection, and power failure warning. The ADM696/ADM697 are available in 16-pin DIP and small outline packages and provide the following functions: CEIN CEOUT LLIN LOW LINE RESET RESET GENERATOR RESET OSC IN 1. Power-On Reset output during power-up, power-down and brownout conditions. The RESET voltage threshold is adjustable using an external voltage divider. The RESET output remains operational with VCC as low as 1 V. OSC SEL TIMEBASE FOR RESET AND WATCHDOG WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR 2. A Reset pulse if the optional watchdog timer has not been toggled within specified time. POWER FAIL INPUT (PFI) 3. Separate watchdog time-out and low line status outputs. WATCHDOG TIMER WATCHDOG OUTPUT (WDO) ADM697 1.3V POWER FAIL OUTPUT (PFO) 4. Adjustable reset and watchdog timeout periods. 5. A 1.3 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than VCC. 6. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic (ADM696). 7. Write protection of CMOS RAM or EEPROM (ADM697). The ADM696/ADM697 is fabricated using an advanced epitaxial CMOS process combining low power consumption (5 mW), extremely fast Chip Enable gating (5 ns) and high reliability. RESET assertion is guaranteed with VCC as low as 1 V. In addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased output current drive of up to 100 mA without the need for an external pass transistor. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADM696/ADM697–SPECIFICATIONS Parameter VCC Operating Voltage Range VBATT Operating Voltage Range BATTERY BACKUP SWITCHING (ADM696) VOUT Output Voltage VOUT in Battery Backup Mode Supply Current (Excludes IOUT) Supply Current in Battery Backup Mode Battery Standby Current (+ = Discharge, – = Charge) Min 3.0 2.0 VCC – 0.05 VCC – 0.5 VBATT – 0.05 Minimum WDI Input Pulse Width RESET Output Voltage @ VCC = +1 V RESET, RESET Output Voltage Units 5.5 VCC – 0 3 V V +0.02 +0.02 70 50 20 0.4 0.5 Watchdog Timeout Period, External Clock Max VCC – 0.025 VCC – 0.25 VBATT – 0.02 1 1.95 0.6 1 –0.1 –1 Battery Switchover Threshold VCC – VBATT Battery Switchover Hysteresis BATT ON Output Voltage BATT ON Output Short Circuit Current RESET AND WATCHDOG TIMER Low Line Threshold (LLIN) Reset Timeout Delay Watchdog Timeout Period, Internal Oscillator Typ (VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to TMAX unless otherwise noted.) 1.25 35 1.0 70 4032 960 50 7 1 25 1.3 50 1.6 100 1.35 70 2.25 140 4097 1025 4 200 0.4 0.4 3.5 LOW LINE, WDO Output Voltage Output Short Circuit Source Current WDI Input Threshold Logic Low Logic High WDI Input Current POWER FAIL DETECTOR PFI Input Threshold PFI–LLIN Threshold Difference PFI Input Current LLIN Input Current PFO Output Voltage PFO Short Circuit Source Current 0.4 3.5 1 3 25 0.8 3.5 20 –15 50 –50 1.2 –50 –25 –50 1.3 ± 15 ± 0.01 ± 0.01 1.4 +50 +25 +50 0.4 3.5 1 3 25 CHIP ENABLE GATING (ADM697) CEIN Threshold 0.8 3.0 CEIN Pullup Current CEOUT Output Voltage 3 0.4 VCC – 0.5 CE Propagation Delay OSCILLATOR OSC IN Input Current OSC SEL Input Pullup Current OSC IN Frequency Range OSC IN Frequency with Ext. Capacitor 5 25 ±2 5 0 250 4 V V V mA µA µA µA mV mV mV V mA µA Test Conditions/Comments IOUT = 1 mA IOUT ≤ 100 mA IOUT = 250 µA, VCC < VBATT – 0.2 V IOUT = 100 mA V CC = 0 V, VBATT = 2.8 V 5.5 V > V CC > VBATT + 0.2 V TA = +25°C Power-Up Power-Down ISINK = 1.6 mA BATT ON = VOUT = 2.4 V Sink Current BATT ON = VOUT, VCC = 0 V, Source Current V VCC = +5 V, +3 V ms OSC SEL = HIGH, V CC= 5 V, TA = +25°C s Long Period, VCC = 5 V, TA = +25°C ms Short Period, VCC = 5 V, TA = +25°C Cycles Long Period Cycles Short Period ns V IL = 0.4, VIH = 3.5 V, VCC = 5 V mV ISINK = 10 µA, VCC = 1 V V ISINK = 400 µA, VCC = 2 V, VBATT = 0 V V ISINK = 1.6 mA, 3 V < VCC < 5.5 V V ISOURCE = 1 µA, VCC = 5 V V ISINK = 1.6 mA, V ISOURCE = 1 µA, VCC = 5 V µA VCC = 5 V1 V V µA WD1 = VOUT, (VCC) TA = +25°C µA WD1 = 0 V, TA = +25°C V mV nA nA V V µA V CC = +3 V, +5 V V CC = +3 V, +5 V V V µA V V ns V IL V IH, VCC = 5 V µA µA kHz kHz ISINK = 1.6 mA ISOURCE = 1 µA, VCC = 5 V PFI = Low, PFO = 0 V ISINK = 1.6 mA ISOURCE = 800 µA OSC SEL = 0 V OSC SEL = 0 V, COSC = 47 pF NOTE 1 WDI is a three-level input which is internally biased to 38% of V CC and has an input impedance of approximately 125 kΩ. Specifications subject to change without notice. –2– REV. 0 ADM696/ADM697 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM696/ADM697 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE PIN CONFIGURATIONS Model Temperature Range Package Option ADM696AN ADM696AR ADM696AQ ADM696SQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C N-16 R-16 Q-16 Q-16 ADM697AN ADM697AR ADM697AQ ADM697SQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C N-16 R-16 Q-16 Q-16 VBATT 1 16 RESET VOUT 2 15 RESET V 3 GND 4 CC BATT ON 5 IN 12 NC 6 11 WDI OSC IN 7 10 PFO OSC SEL 8 9 TEST 1 16 RESET NC 2 15 RESET CC PFI 14 WDO 3 ADM697 13 CE LL 4 GND 5 LOW LINE 6 11 WDI OSC IN 7 10 PFO OSC SEL 8 9 IN –3– 13 LL TOP VIEW (Not to Scale) LOW LINE V REV. 0 14 WDO ADM696 TOP VIEW (Not to Scale) IN 12 CE OUT PFI ADM696/ADM697 PIN FUNCTION DESCRIPTION Mnemonic Pin No. ADM696 ADM697 VCC VBATT VOUT 3 1 2 3 — — GND RESET 4 15 5 15 WDI 11 11 PFI 9 9 PFO 10 10 CEIN CEOUT — — 13 12 BATT ON 5 — LOW LINE 6 6 RESET OSC SEL 16 8 16 8 OSC IN 7 7 WDO 14 14 NC LLIN 12 13 2 4 TEST — 1 Function Power Supply Input +3 V to +5 V. Backup Battery Input. Connect to Ground if a backup battery is not used. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used. 0 V. Ground reference for all signals. Logic Output. RESET goes low whenever LLIN falls below 1.3 V or when VCC falls below the VBATT input voltage. RESET remains low for 50 ms after LLIN goes above 1.3 V, RESET also goes low for 50 ms if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted as shown in Table I. Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition at the WDI input. The watchdog timer is disabled when WDI is left floating or is driven to midsupply. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The comparator is turned off and PFO goes low when VCC is below VBATT. Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when LLIN is above 1.3 V. If LLIN is below 1.3 V, CEOUT is forced high. Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output typically sinks 7 mA and can directly drive the base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT. Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as LLIN rises above 1.3 V. Logic Output. RESET is an active high output. It is the inverse of RESET. Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pullup. See Table I and Figure 4. Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the reset delay and the watchdog time-out period. The timing can also be adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the watchdog time-out period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high when LOW LINE goes low. No Connect. It should be left open. Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V reference voltage. This input is normally used to monitor the power supply voltage. The output of the comparator generates a LOW LINE output signal. It also generates a RESET/RESET output. This is a special test pin using during device manufacture. It should be connected to GND. –4– REV. 0 ADM696/ADM697 CIRCUIT INFORMATION Battery-Switchover Section (ADM696) Low Line RESET OUTPUT RESET is an active low output which provides a RESET signal to the microprocessor whenever the Low Line Input (LLIN) is below 1.3 V. The LLIN input is normally used to monitor the power supply voltage. An internal timer holds RESET low for 50 ms after the voltage on LLIN rises above 1.3 V. This is intended as a power-on RESET signal for the processor. It allows time for the power supply and microprocessor to stabilize. On power-down, the RESET output remains low with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. The battery switchover circuit compares VCC to the VBATT input, and connects VOUT to whichever is higher. Switchover occurs when VCC is 50 mV higher than VBATT as VCC falls, and when VCC is 70 mV greater than VBATT as VCC rises. This 20 mV of hysteresis prevents repeated rapid switching if VCC falls very slowly or remains nearly equal to the battery voltage. During normal operation with VCC higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typical on resistance of 1.5 Ω and can supply up to 100 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 100 mA. If this is the case, then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used. The LLIN comparator has approximately 12 mV of hysteresis for enhanced noise immunity. In addition to RESET, an active high RESET output is also available. This is the complement of RESET and is useful for processors requiring an active high RESET. If the continuous output current requirement at VOUT exceeds 100 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can directly drive the base of the external transistor. LL RESET A 20 Ω MOSFET switch connects the VBATT input to VOUT during battery backup. This MOSFET has very low input-tooutput differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.6 µA. t1 t1 V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 Figure 2. Power-Fail Reset Timing Watchdog Timer RESET The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a RESET pulse is generated. The ADM696/ADM697 may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. If the “short” period is selected some systems may be unable to service the watchdog timer immediately after a reset, so a “long” timeout is automatically initiated directly after a reset is issued. The watchdog timer is restarted at the end of Reset, whether the Reset was caused by lack of activity on WDI or by LLIN falling below the reset threshold. VOUT VBATT GATE DRIVE The normal (short) timeout period becomes effective following the first transition of WDI after RESET has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 s). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI) or by connecting it to midsupply. BATT ON (ADM691, ADM693, ADM695, ADM696) Figure 1. Battery Switchover Schematic REV. 0 V1 V1 = RESET VOLTAGE THRESHOLD LOW VCC 700 mV V2 t1 = RESET TIME If the battery-switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. INTERNAL SHUT DOWN SIGNAL WHEN VBATT > (VCC + 0.7V) V1 LOW LINE The ADM696 operates with battery voltages from 2.0 V to VCC –0.3 V). High value capacitors, either standard electrolytic or the farad-size double layer capacitors, can also be used for shortterm memory backup. A small charging current of typically 10 nA (0.1 µA max) flows out of the VBATT terminal. This current is useful for maintaining rechargeable batteries in a fully charged condition. This extends the life of the backup battery by compensating for its self discharge current. Also note that this current poses no problem when lithium batteries are used for backup since the maximum charging current (0.1 µA) is safe for even the smallest lithium cells. 100 mV V2 IN –5– ADM696/ADM697 Table I. ADM696, ADM697 Reset Pulse Width and Watchdog Timeout Selections Watchdog Timeout Period Immediately After Reset OSC SEL OSC IN Normal Low Low Floating or High Floating or High External Clock Input External Capacitor Low Floating or High 1024 CLKS 400 ms × C/47 pF 100 ms 1.6 s Reset Active Period 4096 CLKS 1.6 s × C/47 pF 1.6 s 1.6 s 512 CLKS 200 ms × C/47 pF 50 ms 50 ms NOTE With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF). 8 OSC SEL WDI ADM69x 7 OSC IN WDO COSC t2 t3 Figure 4b. External Capacitor RESET NC t1 t1 8 OSC SEL t1 ADM69x t1 = RESET TIME t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET 7 NC Figure 4c. Internal Oscillator (1.6 s Watchdog) Figure 3. Watchdog Timeout Period and Reset Active Time The watchdog timeout period defaults to 1.6 s and the reset pulse width defaults to 50 ms but these times to be adjusted as shown in Table I. Figure 4 shows the various oscillator configurations which can be used to adjust the reset pulse width and watchdog timeout period. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods. In either case, immediately after a reset the timeout period is 1.6 s. This gives the microprocessor time to reinitialize the system. If OSC IN is low, then the 100 ms watchdog period becomes effective after the first transition of WDI. The software should be written such that the I/O port driving WDI is left in its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 70 ms. 8 OSC IN NC 8 OSC SEL ADM69x 7 OSC IN Figure 4d. Internal Oscillator (100 ms Watchdog) Watchdog Output (WDO) The Watchdog Output WDO provides a status output which goes low if the watchdog timer “times out” and remains low until set high by the next transition on the watchdog input. WDO is also set high when LLIN goes below the reset threshold. OSC SEL ADM69x CLOCK 0 TO 250kHz 7 OSC IN Figure 4a. External Clock Source –6– REV. 0 ADM696/ADM697 Fail Output (PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider which senses either the unregulated dc input to the system’s 5 V regulator or the regulated 5 V output. The voltage divider ratio can be chosen such that the voltage at PFI falls below 1.3 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shutdown procedure executed before power is lost. CE Gating and RAM Write Protection (ADM697) The ADM697 contains memory protection circuitry which ensures the integrity of data in memory by preventing write operations when LLIN is below the threshold voltage. When LLIN is greater than 1.3 V, CEOUT is a buffered replica of CEIN, with a 5 ns propagation delay. When LLIN falls below the 1.3 V threshold, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS, or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. INPUT POWER If the 5 ns typical propagation delay of CEOUT is excessive, connect CEIN to GND and use the resulting CEOUT to control a high speed external logic gate. R1 1.3V R2 POWER FAIL INPUT PFO POWER FAIL OUTPUT ADM69x ADM697 CEIN CEOUT Figure 7. Power Fail Comparator LLIN LOW = 0 LLIN OK = 1 Table II. Input and Output Status In Battery Backup Mode Figure 5. Chip Enable Gating LL IN RESET V2 V1 V2 t1 V1 Signal Status VOUT (ADM696) VOUT is connected to VBATT via an internal PMOS switch. RESET Logic low. RESET Logic high. The open circuit output voltage is equal to VOUT. LOW LINE Logic low. BATT ON (ADM696) Logic high. The open circuit voltage is equal to VOUT. WDI WDI is ignored. It is internally disconnected from the internal pullup resistor and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. WDO Logic high. The open circuit voltage is equal to VOUT. PFI The Power Fail Comparator is turned off and has no effect on the Power Fail Output. t1 LOW LINE CEIN CE OUT t1 = RESET TIME PFO Logic low. CEIN CEIN is ignored. It is internally disconnected from its internal pullup and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. CEOUT Logic high. The open circuit voltage is equal to VOUT. OSC IN OSC IN is ignored. OSC SEL OSC SEL is ignored. V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 Figure 6. Chip Enable Timing Power Fail Warning Comparator An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input (PFI) is compared to an internal +1.3 V reference. The Power REV. 0 –7– ADM696/ADM697–Typical Performance Curves 53 5.00 VCC = +5V VCC = +5V TA = +25°C RESET ACTIVE TIME – ms VOUT – V 4.95 4.90 SLOPE = 1.5Ω 4.85 52 51 50 4.80 49 0 20 40 60 80 100 20 40 60 80 100 120 TEMPERATURE – °C IOUT – mA Figure 11. RESET Active Time vs. Temperature Figure 8. VOUT vs. IOUT Normal Operation 2.80 VCC = 0V VBATT = +2.8V TA = +25°C A4 3.36 V 100 2.79 VOUT – V 90 2.78 SLOPE = 20Ω AAAAAAA AAA AAAAA AAAAA AA 2.77 10 0% 1V 2.76 0 200 400 600 800 1000 1V 500ms IOUT – µA Figure 12. RESET Output Voltage vs. Supply Voltage Figure 9. VOUT vs. Battery Backup 1.303 5.5 TA = +25°C 1.302 4.5 VCC – Volts PFI INPUT THRESHOLD – V 5.0 1.301 4.0 3.5 3.0 1.300 2.5 1.299 2.0 20 40 60 80 100 10 120 TEMPERATURE – °C Figure 10. PFI Input Threshold vs. Temperature 100 1000 TIME DELAY – ms 10000 Figure 13. RESET Timeout Delay vs. VCC –8– REV. 0 ADM696/ADM697 APPLICATIONS INFORMATION Increasing the Drive Current (ADM696) If the continuous output current requirements at VOUT exceeds 100 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output (ADM696) can directly drive the base of the external transistor. This circuit is not entirely foolproof, and it is possible that a software fault could erroneously 3-state the buffer. This would then prevent the ADM69x from detecting that the microprocessor is no longer operating correctly. In most cases a better +5V VCC R4 PNP TRANSISTOR +5V INPUT POWER 7805 +7V TO +15V INPUT POWER R1 1.3V 0.1µF PFO 0.1µF TO µP NMI PFI VCC BATT ON ADM69x R2 VOUT VBATT BATTERY R3 ADM696 R R 1 1 + ––– VH = 1.3V 1+ ––– R R 3 ( ) 2 R1 R1 (5V – 1.3V) VL = 1.3V 1+ ––– – ––––––––––––– R2 1.3V (R3 + R4) ( ASSUMING R < < R THEN 4 3 R 1 HYSTERESIS VH – VL = 5V ––– R Figure 14. Increasing the Drive Current ( Using a Rechargeable Battery for Backup (ADM696) If a capacitor or a rechargeable battery is used for backup, then the charging resistor should be connected to VOUT since this eliminates the discharge path that would exist during powerdown if the resistor is connected to VCC. +5V INPUT POWER I= VOUT – VBATT R 0.1µF R 0.1µF VOUT VCC VBATT RECHARGABLE BATTERY ) ) 2 Figure 16. Adding Hysteresis to the Power Fail Comparator method is to extend the watchdog period rather than disabling the watchdog. This may be done under program control using the circuit shown in Figure 17b. When the control input is high, the OSC SEL pin is low and the watchdog timeout is set by the external capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of 100 s. When the control input is low, the OSC SEL pin is driven high, selecting the internal oscillator. The 100 ms or the 1.6 s period is chosen, depending on which diode in Figure 17b is used. With D1 inserted, the internal timeout is set at 100 ms while with D2 inserted the timeout is set at 1.6 s. ADM696 WATCHDOG STROBE WDI ADM69x CONTROL INPUT Figure 15. Rechargeable Battery Adding Hysteresis to the Power Fail Comparator For increased noise immunity, hysteresis may be added to the power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 16. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, the series combination of R3 and R4 source current into the PFI summing junction. This results in differing trip levels for the comparator. Figure 17a. Programming the Watchdog Input CONTROL INPUT* D1 ADM69x D2 OSC IN Alternate Watchdog Input Drive Circuits *LOW = INTERNAL TIMEOUT HIGH = EXTERNAL TIMEOUT The watchdog feature can be enabled and disabled under program control by driving WDI with a 3-state buffer (Figure 17a). When three-stated, the WDI input will float thereby disabling the watchdog timer. REV. 0 OSC SEL Figure 17b. Programming the Watchdog Input –9– ADM696/ADM697 Replacing the Back-Up Battery If the watchdog timer is not needed the WDI input should be left floating. When changing the back-up battery with system power on, spurious resets can occur when the battery is removed. This occurs because the leakage current flowing out of the VBATT pin will charge up the stray capacitance. If the voltage on VBATT reaches within 50 mV of VCC, a reset pulse is generated. Power Fail Detector If spurious resets during battery replacement are acceptable, then no action is required. If not, then one of the following solutions should be considered: 1. A capacitor from VBATT to GND. This gives time while the capacitor is charging up to change the battery. The leakage current will charge up the external capacitor towards the VCC level. The time taken is related to the charging current, the size of external capacitor and the voltage differential between the capacitor and the charging voltage supply. t = CEXT × VDIFF/I The Power Fail Input, PFI, monitors the input power supply via a resistive divider network R1 and R2. This input is intended as an early warning power fail input. The voltage on the PFI input is compared with a precision 1.3 V internal reference. If the input voltage drops below 1.3 V, a power fail output (PFO) signal is generated. This warns of an impending power failure and may be used to interrupt the processor so that the system may be shut down in an orderly fashion. The resistors in the sensing network are ratioed to give the desired power fail threshold voltage VT. The threshold should be set at a higher voltage than the RESET threshold so that there is sufficient time available to complete the shutdown procedure before the processor is RESET and power is lost. The maximum leakage (charging) current is 1 µA over temperature and VDIFF = VCC VBATT. Therefore, the capacitor size should be chosen such that sufficient time is available to make the battery replacement. +5V R3 R1 VCC CEXT = TREQD (1 µA/(VCC – VBATT)) If a replacement time of 5 s is allowed and assuming a VCC of 4.5 V and a VBATT of 3 V, µP POWER CMOS RAM POWER VOUT PFI LLIN RESET R4 CEXT = 3.33 µF µP SYSTEM ADM696 R2 µP RESET RESET VBATT + 2. A resistor from VBATT to GND. This will prevent the voltage on VBATT from rising to within 50 mV of VCC during battery replacement. PFO µP NMI WDI I/O LINE BATTERY GND R = (VCC – 50 mV)/1 µA Note that the resistor will discharge the battery slightly. With a VCC supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V battery, this will draw around 700 nA. This will be negligible in most cases. TYPICAL APPLICATIONS ADM696 Figure 18 shows the ADM696 in a typical power monitoring, battery backup application. VOUT powers the CMOS RAM. Under normal operating conditions with VCC present, VOUT is internally connected to VCC. If a power failure occurs, VCC will decay and VOUT will be switched to VBATT, thereby maintaining power for the CMOS RAM. Figure 18a. ADM696 Typical Application Circuit A Figure 18b shows a similar application for the ADM696 but in this case the PFI input monitors the unregulated input to the 7805 voltage regulator. This gives an earlier warning of an impending power failure. It is useful with processors operating at low speeds or where there are a significant number of housekeeping tasks to be completed before the power is lost. INPUT POWER 7805 0.1µF Power Fail RESET 3V BATTERY R1 The VCC power supply is also monitored by the Low Line Input, LLIN. A RESET pulse is generated when LLIN falls below 1.3 V. RESET will remain low for 50 ms after LLIN returns above 1.3 V. This allows for a power-on reset and prevents repeated toggling of RESET if the VCC power supply is unstable. Resistors R3 and R4 should be chosen to give the desired VCC reset threshold. 0.1µF BATT ON VCC V V OUT BATT ADM696 PFI GND A0–A15 WDI I/O LINE PFO NMI R2 R3 NC OSC IN OSC SEL VCC CMOS RAM RESET µP POWER µP RESET LL IN Watchdog Timer R4 The Watchdog Timer Input (WDI) monitors an I/O line from the µP system. This line must be toggled once every 1.6 s to verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program and may be tied up in an endless loop. If this happens, a reset pulse is generated to initialize the processor. RESET LOW LINE WDO SYSTEM STATUS INDICATORS Figure 18b. ADM696 Typical Application Circuit B –10– REV. 0 ADM696/ADM697 RAM Write Protection This application also shows an optional, external transistor which may be used to provide in excess of 100 mA current on VOUT. When VCC is higher than VBATT, the BATT ON output goes low, providing 25 mA of base drive for the external PNP transistor. The maximum current available is dependent on the power rating of the external transistor. The ADM697 CEOUT line drives the Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as long as LLIN is above the reset threshold. If LLIN falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM during power-up, power-down, brownouts and momentary power interruptions. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP (N-16) 1 6 9 0.280 (7.11) 0.240 (6.10) PIN 1 1 8 0.325 (8.25) 0.300 (7.62) 0.840 (21.33) 0.745 (18.93) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) 0.150 (3.81) 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.195 (4.95) 0.115 (2.93) 16-Pin Cerdip (Q-16) 9 16 0.310 (7.87) 0.220 (5.59) PIN 1 1 8 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN SEATING PLANE 0.022 (0.558) 0.014 (0.356) 0.320 (8.13) 0.290 (7.37) 0.015 (0.381) 0.008 (0.204) 0.070 (1.78) 0.30 (0.76) 0.100 (2.54) BSC 16-Lead SOIC (R-16) 16 9 0.419 (10.65) 0.299 (7.60) 1 8 0.030 (0.75) 0.413 (10.50) 0.012 (0.3) 0.104 (2.65) 0.05 (1.27) REF REV. 0 0.019 (0.49) 0.013 (0.32) –11– 0.042 (1.07) –12– PRINTED IN U.S.A. C1783–18–4/93