ADM706

a FEATURES Precision Supply-Voltage Monitor +2.63 V (ADM706P/R, ADM708R) +2.93 V (ADM706S, ADM708S) +3.08 V (ADM706T, ADM708T) 100 A Quiescent Current 200 ms Reset Pulsewidth Debounced Manual Reset Input ( MR) Independent Watchdog Timer—1.6 sec Timeout (ADM706x) Reset Output Active High (ADM706P) Active Low (ADM706R/S/T) Both Active High and Active Low (ADM708R/S/T) Voltage Monitor for Power-Fail or Low Battery Warning Guaranteed RESET Valid with VCC = 1 V Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Critical P Monitoring Automotive Systems Battery Operated Systems Portable Instruments GENERAL DESCRIPTION +3 V, Voltage Monitoring P Supervisory Circuits ADM706P/R/S/T, ADM708R/S/T FUNCTIONAL BLOCK DIAGRAMS WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER WATCHDOG OUTPUT(WDO) VCC 70 A MR RESET & WATCHDOG TIMEBASE RESET GENERATOR RESET, (P = RESET) VCC VREF* ADM706 POWER FAIL INPUT (PFI) 1.25V POWER FAIL OUTPUT (PFO) *VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) VCC RESET 70 A MR RESET GENERATOR RESET VCC VREF* POWER FAIL INPUT (PFI) 1.25V ADM708 POWER FAIL OUTPUT (PFO) The ADM706P/R/S/T and the ADM708R/S/T microprocessor supervisory circuits are suitable for monitoring either 3 V or 3.3 V power supplies. The ADM706P/R/S/T provide the following functions: 1. Power-supply monitoring circuitry which generates a Reset output during power-up, power-down and brownout conditions. The reset output remains operational with VCC as low as 1 V. 2. Independent watchdog monitoring circuitry which is activated if the watchdog input has not been toggled within 1.6 seconds. 3. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor an additional power supply. 4. An active low debounced manual reset input (MR). The ADM706R, ADM706S, ADM706T are identical except for the reset threshold monitor levels which are 2.63 V, 2.93 V, and 3.08 V respectively. The ADM706P is identical to the ADM706R in that the reset threshold is 2.63 V. It differs only in that it has an active high reset output. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. *VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) The ADM708R/S/T provide the same functionality as the ADM706R/S/T and only differ in that: 1. A watchdog timer function is not available. 2. An active high reset output (RESET) in addition to the active low (RESET) output is available. All parts are available in 8-lead DIP and narrow SOIC packages. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ADM706P/R/S/T, ADM708R/S/T–SPECIFICATIONS (V VCC = 3.00 V to 5.5 V (ADM70_S), VCC = 3.15 V to 5.5 V (ADM70_T), TA = TMIN to TMAX unless otherwise noted.) Parameter VCC Operating Voltage Range Supply Current Reset Threshold (VRST) Reset Threshold Hysteresis Reset Pulsewidth 160 160 Min 1.0 100 150 2.55 2.85 3.00 2.63 2.93 3.08 20 200 200 200 Typ Max 5.5 200 350 2.70 3.00 3.15 280 280 Units V µA µA V V V mV ms ms ms V V V V V V V V V V V V V sec CC = 2.70 V to 5.5 V (ADM70_P/R), Test Conditions/Comments VCC < 3.6 V VCC < 5.5 V ADM70_P/R ADM70_S ADM70_T ADM70_P/R, VCC = 3 V ADM70_S/T, VCC = 3.3 V VCC = 5.0 V ADM70_R/S/T VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA VCC = 1 V, ISINK = 100 µA ADM706P VRST (max) < VCC < 3.6 V, ISOURCE = 215 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA ADM708_ VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 500 µA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA ADM70_P/R; VCC = 3 V. ADM70_S/T, VCC = 3.3 V VIL = 0.4 V, VIH = (VCC) × (0.8) VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ADM706_ VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V VCC = 5.0 V VCC = 5.0 V WDI = 0 V or VCC VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 500 µA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 1.2 mA MR = 0 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V RESET Output Voltage VOH VOL VOH VOL VOL RESET Output Voltage VOH VOL VOH VOL RESET Output Voltage VOH VOL VOH VOL Watchdog Timeout Period WDI Pulsewidth 0.8 × VCC 0.3 VCC–1.5 V 0.4 0.3 VCC–0.6 V 0.3 VCC–1.5 V 0.4 0.8 × VCC 0.3 VCC–1.5 V 0.4 1.00 1.60 2.25 100 50 WDI Input Threshold VIL VIH VIL VIH WDI Input Current WDO Output Voltage VOH VOL VOH VOL MR Pull Up Current 25 100 MR Pulsewidth 500 150 MR Input Threshold VIL VIH VIL VIH 0.6 0.8 2.0 70 250 250 600 0.7 × VCC 3.5 –1.0 0.8 × VCC 0.3 VCC–1.5 V 0.4 0.02 0.6 0.8 1.0 ns ns V V V V µA V V V V µA µA ns ns V V V V 0.7 × VCC –2– REV. A ADM706P/R/S/T, ADM708R/S/T Parameter MR to Reset Output Delay PFI Input Threshold PFI Input Current PFO Output Voltage VOH VOL VOH VOL 1.2 –25 0.8 × VCC 0.3 VCC–1.5 V 0.4 1.25 0.01 Min Typ Max 750 250 1.3 25 Units ns ns V nA V V V V VRST (max) < VCC < 3.6 V, ISOURCE = 500 µA VRST (max) < VCC < 3.6 V, ISINK = 1.2 mA 4.5 V < VCC < 5.5 V, ISOURCE = 800 µA 4.5 V < VCC < 5.5 V, ISINK = 3.2 mA Test Conditions/Comments VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V ADM70_P/R; VCC = 3 V. ADM70_S/T, VCC = 3.3 V, PFI falling ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) Model ADM706PAN ADM706PAR ADM706RAN ADM706RAR ADM706SAN ADM706SAR ADM706TAN ADM706TAR ADM708RAN ADM708RAR ADM708SAN ADM708SAR ADM708TAN ADM708TAR Temperature Range –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C –40°C to +85° C Package Options N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 N-8 SO-8 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . . –65° C to +150°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. REV. A –3– ADM706P/R/S/T, ADM708R/S/T PIN FUNCTION DESCRIPTIONS Mnemonic MR Pin No. ADM706 1 Pin No. ADM708 1 Function Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be driven from TTL, CMOS logic or from a manual reset switch as it is internally debounced. An internal 70 µA pull-up current holds the input high when floating. Power Supply Input. 0 V. Ground reference for all signals. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected to GND. Power Fail Output. PFO is the output from the Power Fail Comparator. It goes low when PFI is less than 1.25 V. Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, the watchdog output WDO goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition will clear the counter. The internal timer is also cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is left floating or connected to a three-state buffer. No Connect. Logic Output. RESET goes low for 200 ms when triggered. It can be triggered either by VCC being below the reset threshold or by a low signal on the manual reset (MR) input. RESET will remain low whenever VCC is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold or MR goes from low to high. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Logic Output. RESET is an active high output suitable for systems which use active high RESET logic. It is the inverse of RESET. Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog timer times out as a result of inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, WDO goes high immediately. PIN CONFIGURATIONS VCC GND PFI 2 3 4 2 3 4 PFO WDI 5 6 5 N/A NC RESET N/A 7 (R/S/T Only) 6 7 RESET WDO 7 (P Only) 8 8 N/A MR VCC GND PFI 1 2 3 4 8 WDO MR VCC GND PFI 1 2 3 4 8 WDO MR VCC GND PFI 1 2 3 4 8 RESET ADM706 P 7 RESET 6 WDI ADM706 R/S/T 7 RESET 6 WDI ADM708 R/S/T 7 RESET 6 NC TOP VIEW (Not to Scale) 5 PFO TOP VIEW (Not to Scale) 5 PFO TOP VIEW (Not to Scale) 5 PFO NC = NO CONNECT –4– REV. A ADM706P/R/S/T, ADM708R/S/T Manual Reset WATCHDOG INPUT (WDI) WATCHDOG TRANSITION DETECTOR WATCHDOG TIMER WATCHDOG OUTPUT(WDO) VCC 70 A MR RESET & WATCHDOG TIMEBASE The manual reset input (MR) allows other reset sources such as a manual reset switch to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The MR input is TTL/CMOS compatible so it may also be driven by any logic reset output. If unused, the MR input may be tied high or left floating. VRT VCC VRT RESET GENERATOR RESET, (P = RESET) VCC VREF* RESET tRS tRS ADM706 POWER FAIL INPUT (PFI) 1.25V POWER FAIL OUTPUT (PFO) MR MR EXTERNALLY DRIVEN LOW *VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T) Figure 1. ADM706 Functional Block Diagram VCC RESET 70 A MR RESET GENERATOR RESET WDO NOTE: RESET = COMPLEMENT OF RESET Figure 3. RESET, MR and WDO Timing Watchdog Timer (ADM706) VCC VREF* POWER FAIL INPUT (PFI) 1.25V ADM708 POWER FAIL OUTPUT (PFO) *VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T) Figure 2. ADM708 Functional Block Diagram CIRCUIT INFORMATION Power Fail Reset The watchdog timer circuit may be used to monitor the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the timeout period (1.6 sec), the watchdog output (WDO) is driven low. The WDO output may be connected to a nonmaskable interrupt (NMI) on the processor. Therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine should then be used to rectify the problem. The watchdog timer is cleared by either a high-to-low or by a low-to-high transition on WDI. Pulses as narrow as 50 ns are detected. The timer is also cleared by RESET/RESET going active. Therefore the watchdog timeout period begins after reset goes inactive. When VCC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally this would generate an interrupt but it is overridden by RESET/ RESET going active. The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The WDO output can now be used as a low line output since it will only go low when VCC falls below the reset threshold. tWP WDI The reset output provides a reset (RESET or RESET) output signal to the Microprocessor whenever the VCC input is below the reset threshold. The actual reset threshold voltage is dependent on whether a P/R, S, or T suffix device is used. An internal timer holds the reset output active for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on reset signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after powerup. If a power supply brownout or interruption occurs, the reset line is similarly activated and remains active for 200 ms after the supply recovers. If another interruption occurs during an active reset period, then the reset timeout period continues for an additional 200 ms. The reset output is guaranteed to remain valid with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply starts up. The ADM706P provides an active high reset (RESET) signal; the ADM706R/S/T provides an active low (RESET) signal; while the ADM708R/S/T provides both RESET and RESET. tWD tWD tWD WDO RESET RESET EXTERNALLY TRIGGERED BY MR tRS Figure 4. Watchdog Timing REV. A –5– ADM706P/R/S/T, ADM708R/S/T Power-Fail Comparator The power-fail comparator is an independent comparator which may be used to monitor the input power supply. The comparator’s inverting input is internally connected to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low indicating a power failure. For early warning of power failure the comparator may be used to monitor the preregulator input simply by choosing an appropriate resistive divider network. The PFO output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. INPUT POWER  1.25 V CC – 1.25  V L = 1.25 + R1  –   R2  R3  R1 + R 2  V MID 1.25    R2  Valid RESET Below 1 V VCC The ADM70x family of products are guaranteed to provide a valid reset level with VCC as low as 1 V. Please refer to the Typical Performance Characteristics. As VCC drops below 1 V, the internal transistor will not have sufficient drive to hold it ON so the voltage on RESET will no longer be held at 0 V. A pulldown resistor as shown in Figure 7 may be connected externally to hold the line low if it is required. R1 1.25V PFO POWER-FAIL OUTPUT ADM70x RESET R1 GND POWER-FAIL PFI INPUT R2 ADM70x Figure 5. Power-Fail Comparator Adding Hysteresis to the Power-Fail Comparator Figure 7. RESET Valid Below 1 V For increased noise immunity, hysteresis may be added to the power-fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 6. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, resistor R3 sources current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity may be achieved by connecting a capacitor between PFI and GND. ADM663A INPUT POWER R1 1.25V PFI R2 +3.3V VCC PFO TO P NMI Typical Performance Characteristics VCC RESET ADM70x 400ms/DIV R3 Figure 8. ADM706/ADM708 RESET Output Voltage vs. Supply Voltage 3.3V PFO 0V 0V VL VIN VH VCC Figure 6. Adding Hysteresis to the Power-Fail Comparator   R2 + R 3   V H = 1.25 1 +   R1     R2 × R 3   RESET 400ms/DIV Figure 9. RESET Output Voltage vs. Supply Voltage –6– REV. A ADM706P/R/S/T, ADM708R/S/T VCC = +5V TA = +25 C 1.3V PFI +1.2V +3V +3V +3V RESET RESET VCC = VRT TA = +25 C PFO 0V 0V 0V 500ns/DIV 100ns/DIV Figure 10. PFI Assertion Response Time Figure 13. RESET, RESET Deassertion TA = +25 C +3V VCC +1.3V PFI +2V VCC = +5V TA = +25 C 1.2V +3V +3V RESET PFO 0V 0V 500ns/DIV 2 s/DIV Figure 11. PFI Deassertion Response Time Figure 14. ADM706/ADM708 RESET Response Time VCC = VRT TA = +25 C APPLICATIONS +3V +3V RESET RESET A typical operating Circuit is shown in Figure 15. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistors R1 and R2 should be selected such that when the supply voltage drops below the desired level (e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold thereby generating an interrupt to the µP. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost. ADM666A IN GND OUT +3.3V 0V 0V UNREGULATED DC 100ns/DIV Figure 12. RESET, RESET Assertion PFI MR VCC RESET WDI VCC RESET I/O LINE ADM706 WDO PFO GND MANUAL RESET NMI P INTERRUPT GND Figure 15. Typical Application Circuit REV. A –7– ADM706P/R/S/T, ADM708R/S/T Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines should toggle this line at least once every 1.6 seconds. If a problem occurs and this line is not toggled, then WDO goes low and a nonmaskable interrupt is generated. This interrupt routine may be used to clear the problem. If, in the event of inactivity on the WDI line, a system reset is required, then the WDO output should be connected to the input as shown in Figure 16. RESET RESET VX +3V/+3.3V VCC R1 RESET WDI RESET ADM706 PFI MR GND PFO P Figure 17. Monitoring 3 V/3.3 V and an Additional Supply, VX P ADM706 PFI MR WDI WDO GND I/O LINE Ps with Bidirectional RESET Figure 16. RESET from WDO Monitoring Additional Supply Levels In order to prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor should be inserted between the ADM70x RESET output pin and the µP reset pin. This will limit the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is required for other uses, then it should be buffered as shown in Figure 18. +3V/+3.3V BUFFERED RESET It is possible to use the power-fail comparator to monitor a second supply as shown in Figure 17. The two sensing resistors R1 and R2 are selected such that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The PFO output may be connected to the MR input so that a RESET is generated when the supply drops out of tolerance. In this case if either supply drops out of tolerance, a RESET will be generated. VCC ADM70x RESET GND RESET P GND Figure 18. Bidirectional I-O RESET OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8 5 4 1 4 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) SEATING PLANE 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE –8– REV. A PRINTED IN U.S.A. 0.210 (5.33) MAX 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 0.0099 (0.25) 45 C1998a–0–12/99 R2