ADM8660AN

a FEATURES ADM660: Inverts or Doubles Input Supply Voltage ADM8660: Inverts Input Supply Voltage 100 mA Output Current Shutdown Function (ADM8660) 2.2 F or 10 F Capacitors 0.3 V Drop at 30 mA Load +1.5 V to +7 V Supply Low Power CMOS: 600 A Quiescent Current Selectable Charge Pump Frequency (25 kHz/120 kHz) Pin Compatible Upgrade for MAX660, MAX665, ICL7660 Available in 16-Lead TSSOP Package APPLICATIONS Handheld Instruments Portable Computers Remote Data Acquisition Op Amp Power Supplies GENERAL DESCRIPTION CMOS Switched-Capacitor Voltage Converters ADM660/ADM8660 TYPICAL CIRCUIT CONFIGURATIONS +1.5V TO +7V INPUT FC V+ ADM660 CAP+ C1 10µF GND CAP– OSC LV OUT C2 10µF INVERTED NEGATIVE OUTPUT Voltage Inverter Configuration (ADM660) +1.5V TO +7V INPUT FC CAP+ C1 10µF SHUTDOWN CONTROL GND CAP– SD LV OUT C2 10µF INVERTED NEGATIVE OUTPUT V+ ADM8660 The ADM660/ADM8660 is a charge-pump voltage converter that can be used to either invert the input supply voltage giving VOUT = –VIN or double it (ADM660 only) giving VOUT = 2 × VIN. Input voltages ranging from +1.5 V to +7 V can be inverted into a negative –1.5 V to –7 V output supply. This inverting scheme is ideal for generating a negative rail in single power supply systems. Only two small external capacitors are needed for the charge pump. Output currents up to 50 mA with greater than 90% efficiency are achievable, while 100 mA achieves greater than 80% efficiency. A Frequency Control (FC) input pin is used to select either 25 kHz or 120 kHz charge-pump operation. This is used to optimize capacitor size and quiescent current. With 25 kHz selected, a 10 µF external capacitor is suitable, while with 120 kHz the capacitor may be reduced to 2.2 µF. The oscillator frequency on the ADM660 can also be controlled with an external capacitor connected to the OSC input or by driving this input with an external clock. In applications where a higher supply voltage is desired it is possible to use the ADM660 to double the input voltage. With input voltages from 2.5 V to 7 V, output voltages from 5 V to 14 V are achievable with up to 100 mA output current. The ADM8660 features a low power shutdown (SD) pin instead of the external oscillator (OSC) pin. This can be used to disable the device and reduce the quiescent current to 300 nA. Voltage Inverter Configuration with Shutdown (ADM8660) The ADM660 is a pin compatible upgrade for the MAX660, MAX665, ICL7660 and LTC1046. The ADM660/ADM8660 is available in 8-pin DIP and narrowbody SOIC. The ADM660 is also available in a 16-lead TSSOP package. ADM660/ADM8660 Options Option Inverting Mode Doubling Mode External Oscillator Shutdown Package Options SO-8 N-8 RU-16 ADM660 Y Y Y N Y Y Y ADM8660 Y N N Y Y Y N REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 ADM660/ADM8660–SPECIFICATIONS Parameter Input Voltage, V+ 3.5 1.5 2.5 Supply Current 0.6 2.5 Output Current Output Resistance Charge-Pump Frequency OSC Input Current Power Efficiency (FC = Open) 90 90 99 2.4 0.8 Shutdown Exit Time 500 100 9 25 120 ±5 ± 25 94 93 81.5 99.96 0.3 5 15 1 4.5 7.0 7.0 7.0 Min Typ Max (V+ = +5 V, C1, C2 = 10 F,1 TA = TMIN to TMAX unless otherwise noted) Units V V V mA mA mA Ω kHz kHz µA µA % % % % µA V V µs Test Conditions/Comments RL = 1 kΩ Inverting Mode, LV = Open Inverting Mode, LV = GND Doubling Mode, LV = OUT No Load FC = Open (ADM660), GND (ADM8660) FC = V+, LV = Open IL = 100 mA FC = Open (ADM660), GND (ADM8660) FC = V+ FC = Open (ADM660), GND (ADM8660) FC = V+ RL = 1 kΩ Connected from V+ to OUT RL = 500 Ω Connected from OUT to GND IL = 100 mA to GND No Load ADM8660, SHDN = V+ SHDN High = Disabled SHDN Low = Enabled IL = 100 mA Voltage Conversion Efficiency Shutdown Supply Current, ISHDN Shutdown Input Voltage, VSHDN NOTES 1 C1 and C2 are low ESR (2000 V *This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model ADM660AN ADM660AR ADM660ARU ADM8660AN ADM8660AR Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Options* N-8 SO-8 RU-16 N-8 SO-8 *N = Plastic DIP; RU = Thin Shrink Small Outline; SO = Small Outline. –2– REV. A ADM660/ADM8660 PIN FUNCTION DESCRIPTIONS Inverter Configuration Doubler Configuration (ADM660 Only) Mnemonic FC Function Frequency Control Input for Internal Oscillator and Charge Pump. With FC = Open (ADM660) or connected to GND (ADM8660), fCP = 25 kHz; with FC = V+, fCP = 120 kHz Positive Charge-Pump Capacitor Terminal. Power Supply Ground. Negative Charge-Pump Capacitor Terminal. Output, Negative Voltage. Low Voltage Operation Input. Connect to GND when input voltage is less than 3.5 V. Above 3.5 V, LV may be connected to GND or left unconnected. ADM660: Oscillator Control Input. OSC is connected to an internal 15 pF capacitor. An external capacitor may be connected to slow the oscillator. An external oscillator may also be used to overdrive OSC. The charge-pump frequency is equal to 1/2 the oscillator frequency. ADM8660: Shutdown Control Input. This input, when high, is used to disable the charge pump thereby reducing the power consumption. Positive Power Supply Input. Mnemonic FC Function Frequency Control Input for Internal Oscillator and Charge Pump. With FC = Open, fCP = 25 kHz; with FC = V+, fCP = 120 kHz. Positive Charge-Pump Capacitor Terminal. Positive Input Supply. Negative Charge-Pump Capacitor Terminal. Ground. Low Voltage Operation Input. Connect to OUT. Must be left unconnected in this mode. Doubled Positive Output. CAP+ GND CAP– OUT LV OSC V+ CAP+ GND CAP– OUT LV OSC SD V+ PIN CONNECTIONS 8-Lead FC 1 CAP+ 2 8 V+ FC 1 CAP+ 2 8 V+ ADM660 7 OSC TOP VIEW GND 3 (Not to Scale) 6 LV CAP– 4 5 OUT 7 SD TOP VIEW GND 3 (Not to Scale) 6 LV 5 OUT ADM8660 CAP– 4 16-Lead NC 1 NC 2 FC 3 CAP+ 4 GND 5 16 NC 15 NC 13 OSC TOP VIEW 12 LV (Not to Scale) 11 OUT CAP– 6 NC 7 NC 8 10 NC 9 NC ADM660 RU-16 14 V+ NC = NO CONNECT REV. A –3– ADM660/ADM8660–Typical Performance Characteristics 3 100 IL = 10mA 2.5 SUPPLY CURRENT – mA POWER EFFICIENCY – % 90 VOLTAGE DOUBLER LV = OUT IL = 1mA 2 80 70 60 1.5 IL = 50mA 1 LV = GND 0.5 LV = OPEN 0 1.5 50 IL = 80mA 40 30 3.5 5.5 SUPPLY VOLTAGE – Volts 7.5 1k 10k 100k CHARGE-PUMP FREQUENCY – Hz 1M Figure 1. Power Supply Current vs. Voltage Figure 4. Efficiency vs. Charge-Pump Frequency –3 100 3.5 3 EFFICIENCY –3.4 OUTPUT VOLTAGE – Volts 80 SUPPLY CURRENT – mA 2.5 –3.8 60 EFFICIENCY – % 2 LV = GND VOLTAGE DOUBLER 1.5 1 –4.2 VOUT –4.6 40 20 0.5 LV = GND VOLTAGE INVERTER –5 0 20 40 60 LOAD CURRENT – mA 80 0 100 0 1 100 10 CHARGE-PUMP FREQUENCY – kHz 1000 Figure 2. Output Voltage and Efficiency vs. Load Current Figure 5. Power Supply Current vs. Charge-Pump Frequency 120 V+ = +6.5V V+ = +5.5V V+ = +4.5V 1.6 OUTPUT VOLTAGE DROP FROM SUPPLY VOLTAGE – Volts 100 1.2 V+ = +3.5V EFFICIENCY – % 80 V+ = +2.5V 0.8 V+ = +1.5V V+ = +5.5V 0.4 V+ = +4.5V V+ = +3.5V 60 V+ = +1.5V 40 V+ = +2.5V 20 0 0 20 40 60 LOAD CURRENT – mA 80 100 0 0 20 40 60 LOAD CURRENT – mA 80 100 Figure 3. Output Voltage Drop vs. Load Current Figure 6. Power Efficiency vs. Load Current – 4– REV. A ADM660/ADM8660 5 4.5 4 LOAD = 10mA CHARGE-PUMP FREQUENCY – kHz 35 LOAD = 1mA 30 25 OUTPUT VOLTAGE – Volts 3.5 LOAD = 50mA 3 2.5 2 1.5 1 0.5 0 1 10 100 CHARGE-PUMP FREQUENCY – kHz 1000 LOAD = 80mA 20 15 10 LV = GND FC = OPEN C1, C2 = 10µF 5 0 –40 –20 0 20 40 TEMPERATURE – °C 60 80 Figure 7. Output Voltage vs. Charge-Pump Frequency Figure 10. Charge-Pump Frequency vs. Temperature 30 1k OUTPUT SOURCE RESISTANCE – Ω 25 CHARGE-PUMP FREQUENCY – kHz 100 FC = V+ LV = GND 20 15 10 FC = OPEN LV = GND 10 1 5 0 1.5 0.1 2.5 3.5 4.5 SUPPLY VOLTAGE – Volts 5.5 6.5 1 10 100 CAPACITANCE – pF 1k Figure 8. Output Source Resistance vs. Supply Voltage Figure 11. Charge-Pump Frequency vs. External Capacitance 140 30 LV = GND CHARGE-PUMP FREQUENCY – kHz LV = OPEN 20 FC = OPEN OSC = OPEN C1, C2 = 10µF 10 CHARGE-PUMP FREQUENCY – kHz 120 100 LV = GND LV = OPEN 80 60 40 FC = V+ OSC = OPEN C1, C2 = 2.2µF 20 0 0 1.5 2.5 4.5 3.5 5.5 SUPPLY VOLTAGE – Volts 6.5 3 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE – Volts 6.5 7 Figure 9. Charge-Pump Frequency vs. Supply Voltage Figure 12. Charge-Pump Frequency vs. Supply Voltage REV. A –5– ADM660/ADM8660 160 140 120 100 80 60 40 20 0 –40 LV = GND FC = V+ C1, C2 = 2.2µF 60 CHARGE-PUMP FREQUENCY – kHz OUTPUT SOURCE RESISTANCE – Ω 50 40 30 V+ = +1.5V 20 V+ = +3V 10 V+ = +5V –20 0 20 40 60 TEMPERATURE – °C 80 100 0 –40 –20 0 20 40 60 TEMPERATURE – °C 80 100 Figure 13. Charge-Pump Frequency vs. Temperature GENERAL INFORMATION Figure 14. Output Resistance vs. Temperature Switched Capacitor Theory of Operation The ADM660/ADM8660 is a switched capacitor voltage converter that can be used to invert the input supply voltage. The ADM660 can also be used in a voltage doubling mode. The voltage conversion task is achieved using a switched capacitor technique using two external charge storage capacitors. An onboard oscillator and switching network transfers charge between the charge storage capacitors. The basic principle behind the voltage conversion scheme is illustrated in Figures 15 and 16. S1 V+ S2 C1 CAP– Φ1 ÷2 OSCILLATOR Φ2 S4 OUT = –V+ C2 CAP+ S3 As already described, the charge pump on the ADM660/ ADM8660 uses a switched capacitor technique in order to invert or double the input supply voltage. Basic switched capacitor theory is discussed below. A switched capacitor building block is illustrated in Figure 17. With the switch in position A, capacitor C1 will charge to voltage V1. The total charge stored on C1 is q1 = C1V1. The switch is then flipped to position B discharging C1 to voltage V2. The charge remaining on C1 is q2 = C1V2. The charge transferred to the output V2 is, therefore, the difference between q1 and q2, so ∆q = q1–q2 = C1 (V1–V2). A V1 C2 C1 RL B V2 Figure 15. Voltage Inversion Principle S1 V+ S2 C1 CAP– Φ1 ÷2 OSCILLATOR Φ2 S4 V+ C2 CAP+ S3 VOUT = 2V+ Figure 17. Switched Capacitor Building Block As the switch is toggled between A and B at a frequency f, the charge transfer per unit time or current is I = f ( ∆q ) = f ( C1)(V 1 – V 2) Therefore I = (V 1 – V 2)/(1 / fC1) = (V 1 – V 2)/( R EQ ) where REQ = 1/fC1 The switched capacitor may, therefore, be replaced by an equivalent resistance whose value is dependent on both the capacitor size and the switching frequency. This explains why lower capacitor values may be used with higher switching frequencies. It should be remembered that as the switching frequency is increased the power consumption will increase due to some charge being lost at each switching cycle. As a result, at high frequencies the power efficiency starts decreasing. Other losses include the resistance of the internal switches and the equivalent series resistance (ESR) of the charge storage capacitors. REQ V1 C2 REQ = 1 /fC1 RL V2 Figure 16. Voltage Doubling Principle Figure 15 shows the voltage inverting configuration, while Figure 16 shows the configuration for voltage doubling. An oscillator generating antiphase signals φ1 and φ2 controls switches S1, S2 and S3, S4. During φ1, switches S1 and S2 are closed charging C1 up to the voltage at V+. During φ2, S1 and S2 open and S3 and S4 close. With the voltage inverter configuration during φ2, the positive terminal of C1 is connected to GND via S3 and the negative terminal of C1 connects to VOUT via S4. The net result is voltage inversion at VOUT wrt GND. Charge on C1 is transferred to C2 during φ2. Capacitor C2 maintains this voltage during φ1. The charge transfer efficiency depends on the onresistance of the switches, the frequency at which they are being switched and also on the equivalent series resistance (ESR) of the external capacitors. The reason for this is explained in the following section. For maximum efficiency, capacitors with low ESR are, therefore, recommended. The voltage doubling configuration reverses some of the connections but the same principle applies. Figure 18. Switched Capacitor Equivalent Circuit –6– REV. A ADM660/ADM8660 Inverting Negative Voltage Generator Table II. ADM8660 Charge-Pump Frequency Selection Figures 19 and 20 show the ADM660/ADM8660 configured to generate a negative output voltage. Input supply voltages from 1.5 V up to 7 V are allowable. For supply voltage less than 3 V, LV must be connected to GND. This bypasses the internal regulator circuitry and gives best performance in low voltage applications. With supply voltages greater than 3 V, LV may be either connected to GND or left open. Leaving it open facilitates direct substitution for the ICL7660. +1.5V TO +7V INPUT FC CAP+ C1 10µF GND CAP– FC GND V+ GND or V+ GND OSC Open Open Ext Cap Ext CLK Charge Pump C1, C2 25 kHz 10 µF 120 kHz 2.2 µF See Typical Characteristics Ext CLK Frequency/2 +1.5V TO +7V INPUT CLK OSC ADM660 V+ OSC LV OUT C2 10µF INVERTED NEGATIVE OUTPUT C1 FC CAP+ GND CAP– ADM660 ADM8660 V+ OSC LV OUT CMOS GATE C2 INVERTED NEGATIVE OUTPUT Figure 19. ADM660 Voltage Inverter Configuration +1.5V TO +7V INPUT FC CAP+ C1 10µF SHUTDOWN CONTROL GND CAP– SD LV OUT C2 10µF INVERTED NEGATIVE OUTPUT V+ Figure 21. ADM660/ADM8660 External Oscillator Voltage Doubling Configuration ADM8660 Figure 22 shows the ADM660 configured to generate increased output voltages. As in the inverting mode, only two external capacitors are required. The doubling function is achieved by reversing some connections to the device. The input voltage is applied to the GND pin and V+ is used as the output. Input voltages from 2.5 V to 7 V are allowable. In this configuration, pins LV, OUT must be connected to GND. The unloaded output voltage in this configuration is 2 (VIN). Output resistance and ripple are similar to the voltage inverting configuration. Note that the ADM8660 cannot be used in the voltage doubling configuration. FC CAP+ +2.5V TO +7V INPUT 10µF GND CAP– LV OUT Figure 20. ADM8660 Voltage Inverter Configuration OSCILLATOR FREQUENCY The internal charge-pump frequency may be selected to be either 25 kHz or 120 kHz using the Frequency Control (FC) input. With FC unconnected (ADM660) or connected to GND (ADM8660), the internal charge pump runs at 25 kHz while, if FC is connected to V+, the frequency is increased by a factor of five. Increasing the frequency allows smaller capacitors to be used for equivalent performance or, if the capacitor size is unchanged, it results in lower output impedance and ripple. If a charge-pump frequency other than the two fixed values is desired, this is made possible by the OSC input, which can either have a capacitor connected to it or be overdriven by an external clock. Please refer to the Typical Performance Characteristics, which shows the variation in charge-pump frequency versus capacitor size. The charge-pump frequency is one-half the oscillator frequency applied to the OSC pin. If an external clock is used to overdrive the oscillator, its levels should swing to within 100 mV of V+ and GND. A CMOS driver is, therefore, suitable. When OSC is overdriven, FC has no effect but LV must be grounded. Note that overdriving is permitted only in the voltage inverter configuration. Table I. ADM660 Charge-Pump Frequency Selection ADM660 V+ OSC 10µF DOUBLED POSITIVE OUTPUT Figure 22. Voltage Doubler Configuration Shutdown Input The ADM8660 contains a shutdown input that can be used to disable the device and hence reduce the power consumption. A logic high level on the SD input shuts the device down reducing the quiescent current to 0.3 µA. During shutdown the output voltage goes to 0 V. Therefore, ground referenced loads are not powered during this state. When exiting shutdown it takes several cycles (approximately 500 µs) for the charge pump to reach its final value. If the shutdown function is not being used, then SD should be hardwired to GND. Capacitor Selection FC Open V+ Open or V+ Open REV. A OSC Open Open Ext Cap Ext CLK Charge Pump C1, C2 25 kHz 10 µF 120 kHz 2.2 µF See Typical Characteristics Ext CLK Frequency/2 –7– The optimum capacitor value selection depends the chargepump frequency. With 25 kHz selected, 10 µF capacitors are recommended, while with 120 kHz selected, 2.2 µF capacitors may be used. Other frequencies allow other capacitor values to be used. For maximum efficiency in all cases, it is recommended that capacitors with low ESR are used for the charge pump. Low ESR capacitors give both the lowest output resistance and lowest ripple voltage. High output resistance degrades the overall power efficiency and causes voltage drops, especially at high ADM660/ADM8660 output current levels. The ADM660/ADM8660 is tested using low ESR, 10 µF, capacitors for both C1 and C2. Smaller values of C1 increase the output resistance, while increasing C1 will reduce the output resistance. The output resistance is also dependent on the internal switches on resistance as well as the capacitors ESR so the effect of increasing C1 becomes negligible past a certain point. Figure 23 shows how the output resistance varies with oscillator frequency for three different capacitor values. At low oscillator frequencies, the output impedance is dominated by the 1/fC term. This explains why the output impedance is higher for smaller capacitance values. At high oscillator frequencies, the 1/fC term becomes insignificant and the output impedance is dominated by the internal switches on resistance. From an output impedance viewpoint, therefore, there is no benefit to be gained from using excessively large capacitors. 500 C1 = C2 = 2.2µF 400 OUTPUT RESISTANCE – Ω Bypass Capacitor The ac impedance of the ADM660/ADM8660 may be reduced by using a bypass capacitor on the input supply. This capacitor should be connected between the input supply and GND. It will provide instantaneous current surges as required. Suitable capacitors of 0.1 µF or greater may be used. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C2053a–5–5/97 0.195 (4.95) 0.115 (2.93) 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 1 5 4 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) PIN 1 0.210 (5.33) MAX 0.060 (1.52) 0.015 (0.38) 300 C1 = C2 = 1µF 200 C1 = C2 = 10µF 100 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.070 (1.77) SEATING PLANE 0.100 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) 8-Lead Narrow-Body SOIC (SO-8) 100 0 0.1 1 10 OSCILLATOR FREQUENCY – kHz 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 Figure 23. Output Impedance vs. Oscillator Frequency Capacitor C2 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) The output capacitor size C2 affects the output ripple. Increasing the capacitor size reduces the peak-peak ripple. The ESR affects both the output impedance and the output ripple. Reducing the ESR reduces the output impedance and ripple. For convenience it is recommended that both C1 and C2 be the same value. Table III. Capacitor Selection PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) Charge-Pump Frequency 25 kHz 120 kHz Capacitor C1, C2 10 µF 2.2 µF 16 16-Lead TSSOP (RU-16) 0.193 (4.90) Power Efficiency and Oscillator Frequency Tradeoff 0.177 (4.50) 0.169 (4.30) 9 0.256 (6.50) While higher switching frequencies allow smaller capacitors to be used for equivalent performance, or improved performance with the same capacitors, there is a tradeoff to be considered. As the oscillator frequency is increased, the quiescent current increases. This happens as a result of a finite charge being lost at each switching cycle. The charge loss per unit cycle at very high frequencies can be significant, thereby reducing the power efficiency. Since the power efficiency is also degraded at low oscillator frequencies, due to an increase in output impedance, this means that there is an optimum frequency band for maximum power transfer. Please refer to the Typical Performance Characteristics section. –8– 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.246 (6.25) SEATING PLANE 8° 0° 0.028 (0.70) 0.020 (0.50) REV. A PRINTED IN U.S.A. 0.201 (5.10)