FEATURES
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VOUT
VCC
RESET
GENERATOR 2
4.65V 1
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
(1.6sec)
PRODUCT HIGHLIGHTS
POWER-FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE DETECTOR = 4.65V
2RESET PULSE WIDTH = 50ms
Figure 1. ADM8690
BATT ON
2.
3.
4.
Power-on reset output during power-up, power-down,
and brownout conditions. The RESET output remains
operational with VCC as low as 1 V.
Battery backup switching for CMOS RAM, CMOS microprocessor, or other low power logic.
Reset pulse if the optional watchdog timer is not toggled
within a specified time.
1.3 V threshold detector for power-fail warning, low battery
detection, or to monitor a power supply other than 5 V.
The ADM8691 and ADM8695 are available in 16-lead PDIP
and small outline packages (including TSSOP) and provide
three additional functions:
1.
2.
3.
ADM8691/
ADM8695
VBATT
VOUT
VCC
CEIN
The ADM8690 is available in 8-lead PDIP and SOIC packages
and provides the following functions:
1.
ADM8690
POWER-FAIL
INPUT (PFI)
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Automotive systems
RESET
00093-001
Upgrade for the ADM690, ADM691, ADM695 and
for the MAX690, MAX691, MAX695
Specified over temperature
Low power consumption: 0.7 mW
Precision voltage monitor
Reset assertion down to 1 V VCC
Low switch on resistance: 0.7 Ω normal, 7 Ω in backup
High current drive: 100 mA
Watchdog timer: 100 ms, 1.6 sec, or adjustable
Standby current: 400 nA
Automatic battery backup power switching
Extremely fast gating of chip enable signals (3 ns)
Voltage monitor for power fail
Available in TSSOP package
CEOUT
LOW LINE
4.65V1
RESET
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
RESET AND
WATCHDOG
TIME BASE
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
POWER-FAIL
INPUT (PFI)
RESET
WATCHDOG
OUTPUT (WDO)
POWER-FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE DETECTOR = 4.65V
00093-002
Data Sheet
Microprocessor
Supervisory Circuits
ADM8690/ADM8691/ADM8695
Figure 2. ADM8691/ADM8695
Write protection of CMOS RAM or EEPROM.
Adjustable reset and watchdog timeout periods.
Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
ADM8690/ADM8691/ADM8695
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-Fail Warning Comparator ............................................. 14
Applications ....................................................................................... 1
Applications Information .............................................................. 15
Product Highlights ........................................................................... 1
Increasing the Drive Current .................................................... 15
Functional Block Diagrams ............................................................. 1
Using a Rechargeable Battery for Backup ............................... 15
Revision History ............................................................................... 2
Adding Hysteresis to the Power-Fail Comparator ................. 15
General Description ......................................................................... 3
Monitoring the Status of the Battery ....................................... 15
Specifications..................................................................................... 4
Alternate Watchdog Input Drive Circuits ............................... 16
Absolute Maximum Ratings............................................................ 6
Typical Applications ....................................................................... 17
ESD Caution .................................................................................. 6
ADM8690 Applications ............................................................. 17
Pin Configurations and Function Descriptions ........................... 7
ADM8691/ADM8695 Applications ......................................... 17
Typical Performance Characteristics ............................................. 9
RESET Output ............................................................................ 18
Circuit Information ........................................................................ 11
Power-Fail Detector ................................................................... 18
Battery Switchover Section........................................................ 11
RAM Write Protection............................................................... 18
Power-Fail RESET Output......................................................... 11
Watchdog Timer ......................................................................... 18
Watchdog Timer RESET............................................................ 12
Outline Dimensions ....................................................................... 19
Watchdog Output (WDO) (ADM8691/ADM8695) ................. 13
Ordering Guide .......................................................................... 22
CE Gating and RAM Write Protection
(ADM8691/ADM8695) ............................................................. 13
REVISION HISTORY
12/11—Rev. B to Rev. C
Deleted ADM8692 and ADM8693 ............................. Throughout
Changes to Table 4 ............................................................................ 7
Change to Power-Fail RESET Output Section ............................ 11
Changes to ADM8691/ADM8695 Applications Section .......... 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 22
9/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Absolute Maximum Ratings ........................................6
Updated Ordering Guide .............................................................. 20
2/97—Revision 0: Initial Version
6/11—Rev. A to Rev. B
Deleted ADM8694 ......................................................... Throughout
Updated Figure 11, Figure 12, and Figure 13 ................................ 9
Updated Outline Dimensions ....................................................... 18
Rev. C | Page 2 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
GENERAL DESCRIPTION
The ADM8690/ADM8691/ADM8695 supervisory circuits offer
complete single-chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These functions include microprocessor reset, backup battery switchover,
watchdog timer, CMOS RAM write protection, and power failure
warning. The complete family provides a variety of configurations
to satisfy most microprocessor system requirements.
The ADM8690/ADM8691/ADM8695 are fabricated using an
advanced epitaxial CMOS process that combines low power
consumption (0.7 mW), extremely fast chip enable gating (3 ns),
and high reliability. RESET assertion is guaranteed with VCC as
low as 1 V. In addition, the power switching circuitry is designed
for minimal voltage drop, thereby permitting increased output
current drive of up to 100 mA without the need for an external
pass transistor.
See Table 1 for a product selection guide listing the characteristics of each device. To place an order, see the Ordering Guide.
Table 1. Product Selection Guide
Part No.
ADM8690
ADM8691
ADM8695
Nominal Reset
Time
50 ms
50 ms or ADJ
200 ms or ADJ
Nominal VCC
Reset Threshold
4.65 V
4.65 V
4.65 V
Nominal Watchdog
Timeout Period
1.6 sec
100 ms, 1.6 sec, ADJ
100 ms, 1.6 sec, ADJ
Rev. C | Page 3 of 24
Battery Backup
Switching
Yes
Yes
Yes
Base Drive,
Ext PNP
No
Yes
Yes
Chip Enable
Signals
No
Yes
Yes
ADM8690/ADM8691/ADM8695
Data Sheet
SPECIFICATIONS
VCC = full operating range, VBATT = 2.8 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
VBATT Operating Voltage Range
VOUT Output Voltage
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT)
Supply Current in Battery Backup Mode
Battery Standby Current
+ = Discharge, − = Charge
Battery Switchover Threshold
VCC − VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short-Circuit Current
Min
4.75
2.0
VCC − 0.005
VCC − 0.2
VBATT − 0.005
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage at VCC = 1 V
RESET, LOW LINE Output Voltage
VCC − 0.0025
VCC − 0.125
VBATT − 0.002
140
0.4
−0.1
Max
Unit
5.5
4.25
V
V
V
V
V
μA
μA
200
1
+0.02
70
50
20
0.3
0.5
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
Reset Threshold Hysteresis
Reset Timeout Delay
ADM8690 and ADM8691
ADM8695
Watchdog Timeout Period, Internal
Oscillator
Typ
55
2.5
25
PFO Short-Circuit Source Current
PFO Short-Circuit Sink Current
ISINK = 3.2 mA
BATT ON = VOUT = 4.5 V, sink current
BATT ON = 0 V, source current
4.65
40
4.73
V
mV
35
140
1.0
50
200
1.6
70
280
2.25
ms
ms
Seconds
OSC SEL = high
OSC SEL = high
Long period
70
3840
768
50
100
4064
1011
140
4097
1025
4
0.05
20
0.4
ms
Cycles
Cycles
ns
mV
V
V
V
V
μA
mA
Short period
Long period
Short period
VIL = 0.4 V, VIH = 3.5 V
ISINK = 10 μA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 μA
ISINK = 1.6 mA
ISOURCE = 1 μA
3.5
POWER-FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
IOUT = 1 mA
IOUT ≤ 100 mA
IOUT = 250 μA, VCC < VBATT − 0.2 V
IOUT = 100 μA
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
TA = 25°C
Power-up
Power-down
4.5
0.4
RESET, WDO Output Voltage
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
WDI Input Threshold 1
Logic Low
Logic High
WDI Input Current
μA
mV
mV
mV
V
mA
μA
Test Conditions/Comments
3.5
1
10
25
25
0.8
3.5
1
−1
10
−10
1.25
−25
1.3
±0.01
1.35
+25
0.4
3.5
1
3
25
Rev. C | Page 4 of 24
25
V
V
μA
μA
V
nA
V
V
μA
mA
WDI = VOUT
WDI = 0 V
VCC = 5 V
ISINK = 3.2 mA
ISOURCE = 1 μA
PFI = low, PFO = 0 V
PFI = high, PFO = VOUT
Data Sheet
Parameter
CHIP ENABLE GATING
CEIN Threshold
ADM8690/ADM8691/ADM8695
Min
Typ
Max
Unit
Test Conditions/Comments
0.8
V
V
μA
V
V
V
ns
VIL
VIH
3.0
3
CEIN Pull-Up Current
CEOUT Output Voltage
0.4
VOUT − 1.5
VOUT − 0.05
3
CE Propagation Delay
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
1
7
±2
5
0
500
4
μA
μA
kHz
kHz
WDI is a three-level input that is internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.
Rev. C | Page 5 of 24
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 μA, VCC = 0 V
OSC SEL = 0 V
OSC SEL = 0 V, COSC = 47 pF
ADM8690/ADM8691/ADM8695
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VCC
VBATT
All Other Inputs
Input Current
VCC
VBATT
GND
Digital Output Current
Power Dissipation, 8-Lead PDIP
θJA Thermal Impedance
Power Dissipation, 8-Lead SOIC
θJA Thermal Impedance
Power Dissipation, 16-Lead PDIP
θJA Thermal Impedance
Power Dissipation, 16-Lead TSSOP
θJA Thermal Impedance
Power Dissipation, 16-Lead SOIC_N
θJA Thermal Impedance
Power Dissipation, 16-Lead SOIC_W
θJA Thermal Impedance
Operating Temperature Range
Industrial (A Version)
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VOUT + 0.5 V
200 mA
50 mA
20 mA
20 mA
400 mW
120°C/W
400 mW
120°C/W
600 mW
135°C/W
600 mW
158°C/W
600 mW
110°C/W
600 mW
73°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
300°C
−65°C to +150°C
Rev. C | Page 6 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VBATT 1
16 RESET
VOUT 2
15 RESET
VCC 3
GND 4
13 CEIN
TOP VIEW
12 CEOUT
(Not to Scale)
11 WDI
LOW LINE 6
8 VBATT
ADM8690
7 RESET
TOP VIEW
(Not to Scale)
6 WDI
5 PFO
PFI 4
BATT ON 5
OSC IN 7
00093-003
VCC 2
GND 3
14 WDO
OSC SEL 8
Figure 3. ADM8690 Pin Configuration,
8-Lead PDIP and 8-Lead SOIC_N
10 PFO
9 PFI
00093-004
VOUT 1
ADM8691/
ADM8695
Figure 4. ADM8691/ADM8695 Pin Configuration, 16-Lead PDIP,
16-Lead SOIC_N, 16-Lead SOIC_W, and 16-Lead TSSOP
Table 4. Pin Function Descriptions
8-Lead
8
Pin No.
16-Lead
1
Mnemonic
VBATT
1
2
VOUT
2
3
VCC
3
N/A
4
5
GND
BATT ON
N/A
6
LOW LINE
N/A
7
OSC IN
N/A
8
OSC SEL
4
9
PFI
5
10
PFO
6
11
WDI
N/A
12
CEOUT
N/A
N/A
13
14
CEIN
WDO
Description
Backup Battery Input. VBATT or VCC is internally switched to VOUT, depending on which is at the
highest potential.
Output Voltage. VCC or VBATT is internally switched to VOUT, depending on which is at the highest
potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT
are not used.
Power Supply Input. 5 V nominal. VCC or VBATT is internally switched to VOUT, depending on which is
at the highest potential.
Ground. This is the 0 V ground reference for all signals.
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low
when VOUT is internally switched to VCC. The output typically sinks 35 mA and can directly drive the
base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT.
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as
soon as VCC rises above the reset threshold.
Oscillator Logic Input. When OSC SEL is low, OSC IN can be driven by an external clock signal, or
an external capacitor can be connected between OSC IN and GND. This sets both the reset active
pulse timing and the watchdog timeout period (see Table 5 and Figure 17 through Figure 20).
When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is
fixed at 50 ms typical (ADM8691) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects either the fast (100 ms) or slow (1.6 sec) watchdog timeout period. In both modes, the
timeout period immediately after a reset is 1.6 sec typical.
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal
oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled (see Table 5). OSC SEL has a 5 μA internal pull-up.
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than
1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used.
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less
than 1.3 V. The comparator is turned off and PFO goes low when VCC is below VBATT.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than
the watchdog timeout period, RESET pulses low and WDO goes low. The timer is reset with each
transition on the WDI line. The watchdog timer can be disabled if WDI is left floating or is driven
to midsupply.
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figure 21 and Figure 22.
Logic Input. Input to the CE gating circuit. When not in use, connect this pin to GND or VOUT.
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer
than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is
unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also
goes high when LOW LINE goes low.
Rev. C | Page 7 of 24
ADM8690/ADM8691/ADM8695
8-Lead
7
N/A
Pin No.
16-Lead
15
16
Mnemonic
RESET
RESET
Data Sheet
Description
Logic Output. RESET goes low if VCC falls below the reset threshold or if the watchdog timer is not
serviced within its timeout period. The reset threshold is typically 4.65 V. RESET remains low for
50 ms (ADM8690/ADM8691) or 200 ms (ADM8695) after VCC returns above the threshold. RESET
also goes low for 50 ms (ADM8690/ADM8691) or 200 ms (ADM8695) if the watchdog timer is
enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on
the ADM8691/ADM8695, as shown in Table 5. The RESET output has an internal 3 μA pull-up and
can either connect to an open-collector reset bus or directly drive a CMOS gate without an
external pull-up resistor.
Logic Output. RESET is an active high output. It is the inverse of RESET.
Rev. C | Page 8 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
TYPICAL PERFORMANCE CHARACTERISTICS
1.315
5.00
1.310
PFI INPUT THRESHOLD (V)
4.99
4.97
4.96
4.95
1.300
1.295
1.290
1.285
20
30
40
50
60
IOUT (mA)
70
80
90
100
1.280
–60
00093-015
4.94
10
1.305
–30
0
30
60
TEMPERATURE (°C)
90
00093-018
VOUT (V)
4.98
120
Figure 8. PFI Input Threshold vs. Temperature
Figure 5. VOUT vs. IOUT, Normal Operation
2.800
53
VCC = 5V
RESET ACTIVE TIME (ms)
2.798
2.794
2.792
2.790
52
51
50
250
350
450
550
650
IOUT (µA)
750
850
950
1050
49
20
00093-016
2.786
150
40
Figure 6. VOUT vs. IOUT, Battery Backup
60
80
TEMPERATURE (°C)
100
120
00093-019
ADM8690/
ADM8691
2.788
Figure 9. Reset Active Time vs. Temperature
4.69
VCC = 5V
3.36V
100
90
10
0%
1V
1V
500ms
4.67
4.65
4.63
4.61
4.59
4.57
4.55
–60
–30
0
30
60
TEMPERATURE (°C)
90
Figure 10. Reset Voltage Threshold vs. Temperature
Figure 7. Reset Output Voltage vs. Supply Voltage
Rev. C | Page 9 of 24
120
00093-020
RESET VOLTAGE THRESHOLD (V)
A4
00093-017
VOUT (V)
2.796
ADM8690/ADM8691/ADM8695
6
6
VCC = 5V
TA = 25°C
PFO
5
4
4
3
3
VPFI
PFO
2
1.3V
30pF
1
0
0
PFI
1.25
0.1
0.2
0.3
0.4
0.5
TIME (µs)
0.6
0.7
00093-021
0
0.8
Figure 11. Power-Fail Comparator Response Time, Falling
5
1.3V
PFO
30pF
VCC = 5V
TA = 25°C
2
VPFI
1
1.3V
PFO
30pF
PFO
1.35
10
20
30
40
50
TIME (µs)
60
70
80
90
00093-022
PFI
0
PFI
0.2
0.4
0.6
0.8
1.0
TIME (µs)
1.2
1.4
1.6
1.8
Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor
3
1.25
PFO
0
4
0
10kΩ
VPFI
1.35
1.25
6
5V
2
1
1.35
VCC = 5V
TA = 25°C
00093-023
5
Data Sheet
Figure 12. Power-Fail Comparator Response Time, Rising
Rev. C | Page 10 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
CIRCUIT INFORMATION
BATTERY SWITCHOVER SECTION
The battery switchover circuit compares VCC to the VBATT
input and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This 20 mV
hysteresis prevents repeated rapid switching if VCC falls very
slowly or remains nearly equal to the battery voltage.
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
POWER-FAIL RESET OUTPUT
RESET is an active low output that provides a RESET signal to
the microprocessor whenever VCC is at an invalid level. When
VCC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V.
VCC
VOUT
VCC
V2
V1
V2
V1
VBATT
RESET
GATE DRIVE
INTERNAL
SHUTDOWN SIGNAL
WHEN
VBATT > (VCC + 0.7V)
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
00093-005
700
mV
BATT ON
(ADM8691,
ADM8695)
t1
Figure 14. Battery Switchover Schematic
During normal operation, with VCC higher than VBATT, VCC
is internally switched to VOUT through an internal PMOS transistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the VOUT terminal. VOUT is
normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to VOUT. The
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.
If the continuous output current requirements at VOUT exceed
100 mA or if a lower VCC − VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8695) can directly drive the base of the external transistor
(see Figure 24).
A 7 Ω MOSFET switch connects the VBATT input to VOUT during
battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery backup of CMOS RAM or other low power CMOS
circuitry. The supply current in battery backup is typically 0.4 μA.
The ADM8690/ADM8691/ADM8695 operate with battery
voltages from 2.0 V to 4.25 V. High value capacitors, either standard
electrolytic or the farad-size, double-layer capacitors, can also be
used for short-term memory backup. A small charging current
of typically 10 nA (0.1 μA maximum) flows out of the VBATT
terminal. This current is useful for maintaining rechargeable
batteries in a fully charged condition. This extends the life of the
backup battery by compensating for its self-discharge current.
Also note that this current poses no problem when lithium
batteries are used for backup because the maximum charging
current (0.1 μA) is safe for even the smallest lithium cells.
Figure 15. Power-Fail Reset Timing
On power-up, RESET remains low for 50 ms (200 ms for the
ADM8695) after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor
to stabilize. On power-down, the RESET output remains low
with VCC as low as 1 V. This ensures that the microprocessor is
held in a stable shutdown condition.
The RESET active time is adjustable on the ADM8691/
ADM8695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. See Table 5 and Figure 17
through Figure 20.
The guaranteed minimum and maximum reset thresholds for
the ADM8690/ADM8691/ADM8695 are 4.5 V and 4.73 V. The
ADM8690/ADM8691/ADM8695 are, therefore, compatible with
5 V supplies with a +10%, −5% tolerance. The reset threshold
comparator typically has 40 mV of hysteresis. The response time
of the reset voltage comparator is less than 1 μs. If glitches are
present on the VCC line that could cause spurious reset pulses,
VCC should be decoupled close to the device.
In addition to RESET, the ADM8691/ADM8695 provide an
active high RESET output. This output is the complement of
RESET and is intended for processors that require an active
high reset signal.
Rev. C | Page 11 of 24
00093-006
100
mV
t1
ADM8690/ADM8691/ADM8695
Data Sheet
WATCHDOG TIMER RESET
WDI
The nominal watchdog timeout period is preset at 1.6 sec on
the ADM8690. The ADM8691/ADM8695 can be configured for
a fixed timeout period—short (100 ms) or long (1.6 sec)—or for
an adjustable timeout period. Some systems are unable to service
the watchdog timer immediately after a reset; in this case, if the
short period is selected for the ADM8691/ADM8695, the device
automatically selects the long timeout period directly after a
reset is issued. The watchdog timer is restarted at the end of a
reset, regardless of whether the reset was caused by lack of
activity on WDI or by VCC falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur by the end of the minimum timeout period. If WDI
remains permanently high or low, reset pulses are issued after
each long (1.6 sec) timeout period. The watchdog monitor can
be deactivated by allowing the watchdog input (WDI) to float
or by connecting it to midsupply.
On the ADM8690 the watchdog timeout period is fixed at
1.6 sec, and the reset pulse width is fixed at 50 ms. The ADM8691/
ADM8695 allow these times to be adjusted, as shown in Table 5.
Figure 17, Figure 18, Figure 19, and Figure 20 show the various
oscillator configurations that can be used to adjust the reset pulse
width and watchdog timeout period.
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
00093-007
The watchdog timer circuit monitors the activity of the microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the selected
timeout period, a RESET pulse is generated.
Figure 16. Watchdog Timeout Period and Reset Active Time
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects either the 1.6 sec watchdog timeout period or the 100 ms watchdog timeout period.
When OSC IN is connected high or left floating, the 1.6 sec
timeout period is selected; when OSC IN is connected low, the
100 ms timeout period is selected. In either case, the timeout
period is 1.6 sec immediately after a reset. This gives the microprocessor time to reinitialize the system. If OSC IN is low, the
100 ms watchdog timeout period becomes effective after the
first transition of WDI. The software should be written such
that the input/output port driving WDI is left in its power-up
reset state until the initialization routines are completed and the
microprocessor is able to toggle WDI at the minimum watchdog
timeout period of 70 ms.
Table 5. ADM8691 and ADM8695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
Low 1
Low1
Floating or high
Floating or high
1
OSC IN
External clock input
External capacitor
Low
Floating or high
Watchdog Timeout Period
Normal
Immediately After Reset
1024 CLKs
4096 CLKs
400 ms × C/47 pF
1.6 sec × C/47 pF
100 ms
1.6 sec
1.6 sec
1.6 sec
Reset Active Period
ADM8691
ADM8695
512 CLKs
2048 CLKs
200 ms × C/47 pF
520 ms × C/47 pF
50 ms
200 ms
50 ms
200 ms
When the OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with an external capacitor is fOSC (Hz) = 184,000/C (pF).
Rev. C | Page 12 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
WATCHDOG OUTPUT (WDO) (ADM8691/ADM8695)
The watchdog output (WDO pin on the ADM8691/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when VCC goes
below the reset threshold.
OSC SEL
ADM8691/
ADM8695
CLOCK
0 TO 500kHz
OSC IN
00093-008
7
Figure 17. External Clock Source
8
OSC SEL
The ADM8691/ADM8695 include memory protection circuitry
that ensures the integrity of data in memory by preventing write
operations when VCC is at an invalid level. Two additional pins
(CEIN and CEOUT) can be used to control the chip enable or write
inputs of CMOS RAM. When VCC is present, CEOUT is a buffered
replica of CEIN, with a 3 ns propagation delay. When VCC falls
below the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
CEOUT typically drives the CE, CS, or write input of battery
backed-up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an
invalid level. Similar protection of EEPROMs can be achieved
using the CEOUT pin to drive the store or write inputs.
ADM8691/
ADM8695
ADM8691/
ADM8695
OSC IN
00093-009
7
COSC
CEIN
CEOUT
Figure 18. External Capacitor
NC
8
VCC LOW = 0
VCC OK = 1
OSC SEL
Figure 21. Chip Enable Gating
7
OSC IN
00093-010
ADM8691/
ADM8695
NC
00093-012
8
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8695)
VCC
V2
V1
V2
V1
Figure 19. Internal Oscillator (1.6 Second Watchdog)
NC
8
RESET
OSC IN
00093-011
ADM8691/
ADM8695
7
t1
t1
OSC SEL
LOW LINE
Figure 20. Internal Oscillator (100 ms Watchdog)
CEIN
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
Figure 22. Chip Enable Timing
Rev. C | Page 13 of 24
00093-013
CEOUT
ADM8690/ADM8691/ADM8695
Data Sheet
PFO is normally used to interrupt the microprocessor so
that data can be stored in RAM and the shutdown procedure
executed before power is lost.
POWER-FAIL WARNING COMPARATOR
An additional comparator is provided for early warning of
failure in the microprocessor power supply. The power-fail
input (PFI) is compared to an internal 1.3 V reference. The
power-fail output (PFO) goes low when the voltage at PFI is
less than 1.3 V.
INPUT
POWER
Typically, PFI is driven by an external voltage divider that senses
either the unregulated dc input to the system 5 V regulator or
the regulated 5 V output. The voltage divider ratio can be chosen
such that the voltage at PFI falls below 1.3 V several milliseconds
before the 5 V power supply falls below the reset threshold.
R2
PFO
POWER- PFI
FAIL
INPUT
POWERFAIL
OUTPUT
00093-014
1.3V
R1
Figure 23. Power-Fail Comparator
Table 6. Input and Output Status in Battery Backup Mode
Signal
VOUT
RESET
RESET
LOW LINE
BATT ON
WDI
WDO
PFI
PFO
CEIN
CEOUT
OSC IN
OSC SEL
Status
VOUT is connected to VBATT via an internal PMOS switch.
Logic low.
Logic high. The open circuit output voltage is equal to VOUT.
Logic low.
Logic high. The open circuit voltage is equal to VOUT.
WDI is ignored. It is internally disconnected from its internal pull-up resistor and does not source or sink current as long as
its input voltage is between GND and VOUT. The input voltage does not affect supply current.
Logic high. The open circuit voltage is equal to VOUT.
The power-fail comparator is turned off and has no effect on the power-fail output.
Logic low.
CEIN is ignored. It is internally disconnected from its internal pull-up resistor and does not source or sink current as long as
its input voltage is between GND and VOUT. The input voltage does not affect supply current.
Logic high. The open circuit voltage is equal to VOUT.
OSC IN is ignored.
OSC SEL is ignored.
Rev. C | Page 14 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
APPLICATIONS INFORMATION
INCREASING THE DRIVE CURRENT
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC − VOUT voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8695) can directly drive the base of the external transistor.
7V TO 15V
INPUT
POWER
7805
5V
VCC
R1
R4
1.3V
PFO
PFI
TO
MICROPROCESSOR
NMI
R2
R3
PNP TRANSISTOR
0.1µF
0.1µF
VCC
BATT
ON
VBATT
(
VL = 1.3V 1+
PFO
00093-024
ADM8691/
ADM8695
BATTERY
(
R1 R1
VH = 1.3V 1+ R2 + R3
5V
VOUT
)
R1
R1 (5V – 1.3V)
–
R2 R3 (1.3V (R3 + R4))
)
ASSUMING R4 < < R3 THEN
0V
0V
VL
VIN
HYSTERESIS VH – VL = 5V
VH
( R1
R2 )
00093-026
5V INPUT
POWER
Figure 26. Adding Hysteresis to the Power-Fail Comparator
Figure 24. Increasing the Drive Current
USING A RECHARGEABLE BATTERY FOR BACKUP
MONITORING THE STATUS OF THE BATTERY
If a capacitor or a rechargeable battery is used for backup, the
charging resistor should be connected to VOUT to eliminate the
discharge path that would exist during power-down if the
resistor were connected to VCC.
The power-fail comparator can be used to monitor the status
of the backup battery instead of the power supply, if desired
(see Figure 27). The PFI input samples the battery voltage and
generates an active low PFO signal when the battery voltage
drops below a selected threshold. It may be necessary to apply
a test load to determine the loaded battery voltage. This is done
under processor control using CEOUT. Because CEOUT is forced
high during the battery backup mode, the test load is not applied
to the battery while it is in use, even if the microprocessor is not
powered.
I=
VOUT – VBATT
0.1µF
R
R
VCC
RECHARGEABLE
BATTERY
0.1µF
VOUT
VBATT
00093-025
5V INPUT
POWER
5V INPUT
POWER
Figure 25. Rechargeable Battery
VBATT
BATTERY
For increased noise immunity, hysteresis can be added to
the power-fail comparator. Because the comparator circuit is
noninverting, hysteresis can be added simply by connecting a
resistor between the PFO output and the PFI input, as shown in
Figure 26. When PFO is low, Resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 sources current into the PFI summing
junction. This results in differing trip levels for the comparator.
R1
VCC
PFO
10MΩ
PFI
20kΩ
OPTIONAL
TEST LOAD
Rev. C | Page 15 of 24
R2
10MΩ
CEIN
CEOUT
LOW BATTERY
SIGNAL TO
MICROPROCESSOR
I/O PIN
FROM
MICROPROCESSOR
I/O PIN APPLIES
TEST LOAD
TO BATTERY
Figure 27. Monitoring the Battery Status
00093-027
ADDING HYSTERESIS TO THE POWER-FAIL
COMPARATOR
ADM8690/ADM8691/ADM8695
Data Sheet
WATCHDOG
STROBE
CONTROL
INPUT
WDI
ADM8690/
ADM8691/
ADM8695
00093-028
The watchdog feature can be enabled and disabled under
program control by driving WDI with a three-state buffer (see
Figure 28). When three-stated, the WDI input floats, thereby
disabling the watchdog timer.
Figure 28. Enabling and Disabling the Watchdog Input
For the ADM8691/ADM8695, the watchdog period can be
extended under program control using the circuit shown in
Figure 29. When the control input is high, the OSC SEL pin is
low and the watchdog timeout is set by the external capacitor.
A 0.01 μF capacitor sets a watchdog timeout delay of 100 sec.
When the control input is low, the OSC SEL pin is driven high,
selecting the internal oscillator. The 100 ms or the 1.6 sec
period is chosen, depending on which diode is used, as shown
in Figure 29. With D1 inserted, the internal timeout is set to
100 ms; with D2 inserted, the timeout is set to 1.6 sec.
This circuit is not entirely foolproof, and it is possible for a
software fault to erroneously three-state the buffer, preventing
the ADM8690/ADM8691/ADM8695 from detecting that the
microprocessor is no longer operating correctly. In most cases,
a better method is to extend the watchdog period rather than
disable the watchdog.
Rev. C | Page 16 of 24
CONTROL
INPUT1
OSC SEL
D1
ADM8691/
ADM8695
D2
OSC IN
1LOW
= INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 29. Extending the Watchdog Period
00093-029
ALTERNATE WATCHDOG INPUT DRIVE CIRCUITS
Data Sheet
ADM8690/ADM8691/ADM8695
TYPICAL APPLICATIONS
Figure 31 shows a similar application, but in this case the PFI
input monitors the unregulated input to the 7805 voltage regulator. This circuit provides an earlier warning of an impending
power failure. It is useful with processors that operate at low
speeds or where there are a significant number of housekeeping
tasks to be completed before the power is lost.
ADM8690 APPLICATIONS
Figure 30 shows the ADM8690 in a typical power monitoring,
battery backup application. VOUT powers the CMOS RAM.
Under normal operating conditions with VCC present, VOUT
is internally connected to VCC. If a power failure occurs, VCC
decays and VOUT is switched to VBATT, thereby maintaining
power for the CMOS RAM. A RESET pulse is also generated
when VCC falls below 4.65 V for the ADM8690. RESET remains
low for 50 ms after VCC returns to 5 V.
INPUT
POWER
V > 8V
5V
7805
0.1µF
R1
VCC
5V
0.1µF
R2
0.1µF
R2
CMOS RAM
POWER
BATTERY
VBATT
RESET
PFO
GND WDI
RESET
RESET
PFO
NMI
I/O LINE
GND WDI
MICROPROCESSOR
SYSTEM
ADM8690
+
BATTERY
VBATT
+
RESET
00093-031
VOUT
Figure 31. ADM8690 Typical Application, Circuit B
NMI
I/O LINE
Figure 30. ADM8690 Typical Application, Circuit A
The watchdog timer input (WDI) monitors an input/output
line from the microprocessor system. This line must be toggled
once every 1.6 sec to verify correct software execution. Failure
to toggle the line indicates that the microprocessor system is
not correctly executing its program and may be tied up in an
endless loop. If this happens, a reset pulse is generated to
initialize the microprocessor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The power-fail input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is
compared with a precision 1.3 V internal reference. If the input
voltage drops below 1.3 V, a power-fail output (PFO) signal is
generated. This signal warns of an impending power failure and
can be used to interrupt the processor so that the system can be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power-fail threshold
voltage (VT).
ADM8691/ADM8695 APPLICATIONS
Figure 32 shows a typical connection for the ADM8691/ADM8695.
CMOS RAM is powered from VOUT. When 5 V power is present,
this voltage is routed to VOUT. If VCC fails, VBATT is routed to VOUT.
VOUT can supply up to 100 mA from VCC, but if more current is
required, an external PNP transistor can be added. When VCC is
higher than VBATT, the BATT ON output goes low, providing up
to 35 mA of base drive for the external transistor. A 0.1 μF capacitor is connected to VOUT to supply the transient currents for
CMOS RAM. When VCC is lower than VBATT, an internal 20 Ω
MOSFET connects the backup battery to VOUT.
INPUT POWER
5V
0.1µF
0.1µF
VCC
3V
BATTERY
VBATT
R1
PFI
GND
R2
NC
BATT
ON
VOUT
CEOUT
ADM8691/
ADM8695
OSC IN
OSC SEL
CEIN
CMOS
RAM
ADDRESS
DECODE
A0 TO A15
WDI
I/O LINE
PFO
NMI
RESET
LOW LINE WDO
RESET
RESET
0.1µF MICROPROCESSOR
VT = (1.3 R1/R2) + 1.3 V
SYSTEM STATUS
INDICATORS
R1/R2 = (VT/1.3) − 1
Figure 32. ADM8691/ADM8695 Typical Application
Rev. C | Page 17 of 24
SYSTEM
00093-032
PFI
MICROPROCESSOR
SYSTEM
ADM8690
POWER
VCC
00093-030
R1
POWER
CMOS RAM
POWER
VOUT
PFI
ADM8690/ADM8691/ADM8695
Data Sheet
RESET OUTPUT
RAM WRITE PROTECTION
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor reset line low when
VCC is below 4.65 V. An internal timer holds RESET low for
50 ms (200 ms for the ADM8695) after VCC rises above 4.65 V.
This prevents repeated toggling of RESET, even if the 5 V
power drops out and recovers with each power line cycle.
The ADM8691/ADM8695 CEOUT line drives the chip select
inputs of the CMOS RAM. CEOUT follows CEIN as long as VCC
is above the 4.65 V reset threshold.
The crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize.
Because most microprocessors need several clock cycles to
reset, RESET must be held low until the microprocessor clock
oscillator has started. The power-up RESET pulse lasts 50 ms
(200 ms for the ADM8695) to allow for this oscillator start-up
time. If a different reset pulse width is required, a capacitor
should be connected to OSC IN, or an external clock can be
used (see Table 5 and Figure 17 through Figure 20). The manual
reset switch and the 0.1 μF capacitor connected to the reset line
can be omitted if a manual reset is not needed. An inverted,
active high RESET output is also available on the ADM8691/
ADM8695.
POWER-FAIL DETECTOR
The 5 V VCC power line is monitored via a resistive potential
divider connected to the power-fail input (PFI). When the voltage
at PFI falls below 1.3 V, the power-fail output (PFO) drives the
processor’s NMI input low. For example, if a power-fail threshold
of 4.8 V is set with Resistor R1 and Resistor R2 and VCC falls from
4.8 V to 4.65 V, the microprocessor has time to save data into RAM.
An earlier power-fail warning can be generated if the unregulated
dc input to the 5 V regulator is available for monitoring. This
allows more time for microprocessor housekeeping tasks to be
completed before power is lost.
If VCC falls below the reset threshold, CEOUT goes high, independent
of the logic level at CEIN. This prevents the microprocessor from
writing erroneous data into RAM during power-up, power-down,
brownouts, and momentary power interruptions.
WATCHDOG TIMER
The microprocessor drives the watchdog input (WDI) with an
input/output line. When OSC IN and OSC SEL are unconnected,
the microprocessor must toggle the WDI pin once every 1.6 sec
to verify proper software execution. If a hardware or software failure occurs such that WDI is not toggled, the ADM8691 issues a
50 ms (200 ms for the ADM8695) RESET pulse after 1.6 sec. This
typically restarts the microprocessor power-up routine. A new
RESET pulse is issued every 1.6 sec until WDI is again strobed.
If a different watchdog timeout period is required, a capacitor
should be connected to OSC IN or an external clock can be
used (see Table 5 and Figure 17 through Figure 20).
The watchdog output (WDO) goes low if the watchdog timer is
not serviced within its timeout period. After WDO goes low, it
remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
The RESET output has an internal 3 μA pull-up and can either
connect to an open-collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
Rev. C | Page 18 of 24
Data Sheet
ADM8690/ADM8691/ADM8695
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
4
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 33. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. C | Page 19 of 24
012407-A
4.00 (0.1574)
3.80 (0.1497)
ADM8690/ADM8691/ADM8695
Data Sheet
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
9
1
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
8
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
073106-B
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 35. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 36. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. C | Page 20 of 24
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Data Sheet
ADM8690/ADM8691/ADM8695
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
6.20 (0.2441)
5.80 (0.2283)
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
060606-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 38. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 21 of 24
0.75
0.60
0.45
ADM8690/ADM8691/ADM8695
Data Sheet
ORDERING GUIDE
Model 1
ADM8690AN
ADM8690ANZ
ADM8690ARN
ADM8690ARN-REEL
ADM8690ARNZ
ADM8691ANZ
ADM8691ARN
ADM8691ARN-REEL
ADM8691ARNZ
ADM8691ARW
ADM8691ARW-REEL
ADM8691ARWZ
ADM8691ARU
ADM8691ARU-REEL
ADM8691ARUZ
ADM8695ARW
ADM8695ARW-REEL
ADM8695ARWZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
Z = RoHS Compliant Part.
Rev. C | Page 22 of 24
Package Option
N-8
N-8
R-8
R-8
R-8
N-16
R-16
R-16
R-16
RW-16
RW-16
RW-16
RU-16
RU-16
RU-16
RW-16
RW-16
RW-16
Data Sheet
ADM8690/ADM8691/ADM8695
NOTES
Rev. C | Page 23 of 24
ADM8690/ADM8691/ADM8695
Data Sheet
NOTES
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00093-0-12/11(C)
Rev. C | Page 24 of 24
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