ADM8696ARU

a FEATURES Upgrade for ADM696/ADM697, MAX696/MAX697 Specified Over Temperature Adjustable Low Line Voltage Monitor Power OK/Reset Time Delay Reset Assertion Down to 1 V VCC Watchdog Timer—100 ms, 1.6 s, or Adjustable Low Switch On Resistance 0.7 Normal, 7 in Backup 400 nA Standby Current Automatic Battery Backup Switching (ADM8696) Fast On-Board Gating of Chip Enable Signals (ADM8697) Voltage Monitor for Power Fail or Low Battery Warning Also Available in TSSOP Package APPLICATIONS Microprocessor Systems Computers Controllers Intelligent Instruments Automotive Systems Critical P Power Monitoring GENERAL DESCRIPTION VBATT Microprocessor Supervisory Circuits ADM8696/ADM8697 FUNCTIONAL BLOCK DIAGRAMS BATT ON VOUT VCC LLIN LOW LINE RESET RESET GENERATOR RESET OSC IN OSC SEL TIMEBASE FOR RESET AND WATCHDOG WATCHDOG TIMER WATCHDOG INPUT (WDI) POWER FAIL INPUT (PFI) 1.3V WATCHDOG TRANSITION DETECTOR WATCHDOG OUTPUT (WDO) ADM8696 POWER FAIL OUTPUT (PFO) The ADM8696/ADM8697 supervisory circuits offer complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. These functions include µP reset, backup battery switchover, watchdog timer, CMOS RAM write protection and power failure warning. The ADM8696/ADM8697 are available in 16-pin DIP and small outline packages (including TSSOP) and provide the following functions: 1. Power-On Reset output during power-up, power-down and brownout conditions. The RESET voltage threshold is adjustable using an external voltage divider. The RESET output remains operational with VCC as low as 1 V. 2. A Reset pulse if the optional watchdog timer has not been toggled within specified time. 3. Separate watchdog timeout and low line status outputs. 4. Adjustable reset and watchdog timeout periods. 5. A 1.3 V threshold detector for power fail warning, low battery detection or to monitor a power supply other than VCC. 6. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic (ADM8696). 7. Write protection of CMOS RAM or EEPROM (ADM8697). CEIN LLIN CEOUT LOW LINE RESET RESET GENERATOR RESET OSC IN OSC SEL TIMEBASE FOR RESET AND WATCHDOG WATCHDOG TIMER WATCHDOG OUTPUT (WDO) WATCHDOG INPUT (WDI) POWER FAIL INPUT (PFI) 1.3V WATCHDOG TRANSITION DETECTOR ADM8697 POWER FAIL OUTPUT (PFO) The ADM8696/ADM8697 is fabricated using an advanced epitaxial CMOS process combining low power consumption (0.7 mW), extremely fast Chip Enable gating (2 ns) and high reliability. RESET assertion is guaranteed with VCC as low as 1 V. In addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased output current drive of up to 100 mA without the need for an external pass transistor. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 ull Operating Range, ADM8696/ADM8697–SPECIFICATIONS (V = Fotherwise noted.) V unless CC BATT = +2.8 V, TA = TMIN to TMAX Parameter VCC Operating Voltage Range VBATT Operating Voltage Range BATTERY BACKUP SWITCHING (ADM8696) VOUT Output Voltage VOUT in Battery Backup Mode Supply Current (Excludes IOUT) Supply Current in Battery Backup Mode Battery Standby Current (+ = Discharge, – = Charge) Battery Switchover Threshold VCC – VBATT Battery Switchover Hysteresis BATT ON Output Voltage BATT ON Output Short Circuit Current RESET AND WATCHDOG TIMER Low Line Threshold (LLIN) Reset Timeout Delay Watchdog Timeout Period, Internal Oscillator Watchdog Timeout Period, External Clock Minimum WDI Input Pulse Width Min 3.0 2.0 Typ Max 5.5 VCC – 0 3 Units V V V V V µA µA µA mV mV mV V mA µA V ms s ms Cycles Cycles ns ns ns mV V V V V V V V µA V V V µA µA V mV nA nA V V V µA V V V µA V V ns ns µA µA kHz kHz Test Conditions/Comments VCC – 0.005 VCC – 0.0025 VCC – 0.125 VCC – 0.2 VBATT – 0.005 VBATT – 0.002 115 200 0.4 1 –0.1 70 50 20 0.3 0.5 1.25 35 1.0 70 4032 960 50 100 30 2.5 1.3 50 1.6 100 4063 1011 25 1.35 70 2.25 140 4097 1025 +0.02 IOUT = 1 mA IOUT ≤ 100 mA IOUT = 250 µA, VCC < VBATT – 0.2 V IOUT = 100 mA VCC = 0 V, VBATT = 2.8 V 5.5 V > VCC > VBATT + 0.2 V Power-Up Power-Down ISINK = 3.2 mA BATT ON = VOUT = 2.4 V Sink Current BATT ON = VOUT, VCC = 0 V, Source Current RESET Output Voltage @ VCC = +1 V RESET, RESET Output Voltage 3.5 100 4 0.1 0.1 2.7 20 0.4 0.4 LOW LINE, WDO Output Voltage 3.5 Output Short Circuit Source Current WDI Input Threshold1 Logic Low Logic High WDI Input Current –10 POWER FAIL DETECTOR PFI Input Threshold PFI–LLIN Threshold Difference PFI Input Current LLIN Input Current PFO Output Voltage 1.2 –50 –25 –50 3.5 PFO Short Circuit Source Current CHIP ENABLE GATING (ADM8697) CEIN Threshold 3.0 CEIN Pull-Up Current CEOUT Output Voltage VCC – 0.5 CE Propagation Delay OSCILLATOR OSC IN Input Current OSC SEL Input Pull-Up Current OSC IN Frequency Range OSC IN Frequency with Ext. Capacitor 2 4 ±2 5 0 4 1.2 3 1 2.7 10 1 2.7 10 0.4 25 0.8 OSC SEL = HIGH Long Period Short Period Long Period Short Period VIL = 0.8, VIH = 3.75 V, VCC = 5 V VIL = 0.8, VIH = 3.5 V, VCC = 5 V VIL = 0.8, VIH = 2.6 V, VCC = 3 V ISINK = 10 µA, VCC = 1 V ISINK = 400 µA, VCC = 2 V, VBATT = 0 V ISINK = 3.2 mA, 3 V < VCC < 5.5 V ISOURCE = 1 µA, VCC = 5 V ISOURCE = 1 µA, VCC = 3 V ISINK = 3.2 mA, ISOURCE = 1 µA, VCC = 5 V ISOURCE = 1 µA, VCC = 3 V VCC = 5 V 3.5 1.2 1 –1 1.3 ± 15 ± 0.01 ± 0.01 10 VCC = 5 V VCC = 3 V WD1 = VOUT, (VCC) WD1 = 0 V 1.4 +50 +25 +50 0.4 25 0.8 ISINK = 3.2 mA ISOURCE = 1 µA ISOURCE = 1 µA, VCC = 3 V PFI = Low, PFO = 0 V VIL VIH VCC = 3 V ISINK = 3.2 mA ISOURCE = 800 µA VCC = 5.0 V VCC = 3.0 V 0.4 7 500 OSC SEL = 0 V OSC SEL = 0 V, COSC = 47 pF NOTE 1 WDI is a three-level input internally biased to 38% of V CC and has an input impedance of approximately 5 M Ω. Specifications subject to change without notice. –2– REV. 0 ADM8696/ADM8697 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . . 500 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM8696/ADM8697 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE PIN CONFIGURATIONS Model ADM8696AN ADM8696ARW ADM8696ARU ADM8697AN ADM8697ARW ADM8697ARU Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option* N-16 R-16 RU-16 N-16 R-16 RU-16 VBATT VOUT VCC GND BATT ON LOW LINE OSC IN OSC SEL 1 2 3 16 RESET 15 RESET 14 WDO ADM8696 4 5 6 7 8 TOP VIEW (Not to Scale) 13 LL IN 12 NC 11 WDI 10 PFO 9 PFI *N = Plastic DIP; R = Small Outline (Wide Body); RU = Thin Shrink Small Outline (TSSOP). TEST NC VCC LL IN GND LOW LINE OSC IN OSC SEL 1 2 3 4 5 6 7 8 16 RESET 15 RESET 14 WDO ADM8697 TOP VIEW (Not to Scale) 13 CEIN 12 CEOUT 11 WDI 10 PFO 9 PFI REV. 0 –3– ADM8696/ADM8697 PIN FUNCTION DESCRIPTION Mnemonic VCC VBATT VOUT Pin No. ADM8696 ADM8697 Function 3 1 2 3 — — Power Supply Input +3 V to +5 V. Backup Battery Input. Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. When VCC is higher than VBATT and LLIN is higher than the reset threshold, VCC is switched to VOUT. When VCC is lower than VBATT and LLIN is below the reset threshold, VBATT is switched to VOUT. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used. 0 V. Ground reference for all signals. Logic Output. RESET goes low whenever LLIN falls below 1.3 V and remains low for 50 ms after LLIN goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is enabled but not serviced within its timeout period. The RESET pulse width can be adjusted as shown in Table I. Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition at the WDI input. The watchdog timer is disabled when WDI is left floating or is driven to midsupply. Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1. Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The comparator is turned off and PFO goes low when VCC is below VBATT. Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used. Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when LLIN is above 1.3 V. If LLIN is below 1.3 V, CEOUT is forced high. Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT is internally switched to VCC. The output typically sinks 7 mA and can directly drive the base of an external PNP transistor to increase the output current above the 100 mA rating of VOUT. Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as LLIN rises above 1.3 V. Logic Output. RESET is an active high output. It is the inverse of RESET. Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull-up. See Table I and Figure 4. Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the reset delay and the watchdog timeout period. The timing can also be adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods. Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high when LOW LINE goes low. No Connect. It should be left open. Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V reference voltage. This input is normally used to monitor the power supply voltage. The output of the comparator generates a LOW LINE output signal. It also generates a RESET/RESET output. The comparator output also controls the battery switchover circuitry. This is a special test pin using during device manufacture. It should be connected to GND. GND RESET 4 15 5 15 WDI 11 11 PFI PFO 9 10 9 10 CEIN CEOUT BATT ON — — 5 13 12 — LOW LINE 6 RESET OSC SEL 16 8 6 16 8 OSC IN 7 7 WDO 14 14 NC LLIN 12 13 2 4 TEST — 1 –4– REV. 0 ADM8696/ADM8697 CIRCUIT INFORMATION Battery Switchover Section (ADM8696) Low Line RESET OUTPUT The battery switchover circuit is designed to switch over to battery backup in the event of a power failure. When LLIN is below the reset threshold and VCC is below VBATT, then VBATT is switched to VOUT. During normal operation, with VCC higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typical on resistance of 0.7 Ω and can supply up to 100 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 100 mA. If this is the case, then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used. If the continuous output current requirement at VOUT exceeds 100 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can directly drive the base of the external transistor. A 7 Ω MOSFET switch connects the VBATT input to VOUT during battery backup. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS circuitry. The supply current in battery backup is typically 0.4 µA. The ADM8696 operates with battery voltages from 2.0 V to VCC–0.3 V). High value capacitors, either standard electrolytic or the farad-size double layer capacitors, can also be used for short-term memory backup. A small charging current of typically 10 nA (0.1 µA max) flows out of the VBATT terminal. This current is useful for maintaining rechargeable batteries in a fully charged condition. This extends the life of the backup battery by compensating for its self-discharge current. Also note that this current poses no problem when lithium batteries are used for backup since the maximum charging current (0.1 µA) is safe for even the smallest lithium cells. If the battery switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. RESET is an active low output that provides a RESET signal to the microprocessor whenever the Low Line Input (LLIN) is below 1.3 V. The LLIN input is normally used to monitor the power supply voltage. An internal timer holds RESET low for 50 ms after the voltage on LLIN rises above 1.3 V. This is intended as a power-on RESET signal for the processor. It allows time for the power supply and microprocessor to stabilize. On power-down, the RESET output remains low, with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition. The LLIN comparator has approximately 12 mV of hysteresis for enhanced noise immunity. In addition to RESET, an active high RESET output is also available. This is the complement of RESET and is useful for processors requiring an active high RESET. V2 V1 V2 LLIN V1 RESET t1 t1 LOW LINE t1 = RESET TIME V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 Figure 2. Power-Fail Reset Timing Watchdog Timer RESET VCC VOUT VBATT GATE DRIVE The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the Watchdog Input (WDI) line. If this line is not toggled within the selected timeout period, a RESET pulse is generated. The ADM8696/ADM8697 may be configured for either a fixed “short” 100 ms or a “long” 1.6 second timeout period or for an adjustable timeout period. If the “short” period is selected, some systems may be unable to service the watchdog timer immediately after a reset, so a “long” timeout is automatically initiated directly after a reset is issued. The watchdog timer is restarted at the end of Reset, whether the Reset was caused by lack of activity on WDI or by LLIN falling below the reset threshold. The normal (short) timeout period becomes effective following the first transition of WDI after RESET has gone inactive. The watchdog timeout period restarts with each transition on the WDI pin. To ensure that the watchdog timer does not time out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum timeout period. If WDI remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 s). The watchdog monitor can be deactivated by floating the Watchdog Input (WDI) or by connecting it to midsupply. 100 mV BATT ON (ADM8691, ADM8693, ADM8695, ADM8696) INTERNAL SHUTDOWN SIGNAL WHEN VBATT > (VCC + 0.7V) 700 mV Figure 1. Battery Switchover Schematic REV. 0 –5– ADM8696/ADM8697 Table I. ADM8696, ADM8697 Reset Pulse Width and Watchdog Timeout Selections OSC SEL Low Low Floating or High Floating or High OSC IN External Clock Input External Capacitor Low Floating or High Normal Watchdog Timeout Period Immediately After Reset 4096 CLKS 1.6 s × C/47 pF 1.6 s 1.6 s Reset Active Period 512 CLKS 200 ms × C/47 pF 50 ms 50 ms 1024 CLKS 400 ms × C/47 pF 100 ms 1.6 s NOTE With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF). WDI 8 OSC SEL ADM869x 7 OSC IN WDO COSC t2 RESET t3 Figure 4b. External Capacitor t1 t1 t1 t1 = RESET TIME t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET NC 8 OSC SEL ADM869x NC 7 OSC IN Figure 3. Watchdog Timeout Period and Reset Active Time The watchdog timeout period defaults to 1.6 s and the reset pulse width defaults to 50 ms, but these times to be adjusted as shown in Table I. Figure 4 shows the various oscillator configurations that can be used to adjust the reset pulse width and watchdog timeout period. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods. In either case, immediately after a reset the timeout period is 1.6 s. This gives the microprocessor time to reinitialize the system. If OSC IN is low, the 100 ms watchdog period becomes effective after the first transition of WDI. The software should be written such that the I/O port driving WDI is left in its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 70 ms. Figure 4c. Internal Oscillator (1.6 s Watchdog) NC 8 OSC SEL ADM869x 7 OSC IN Figure 4d. Internal Oscillator (100 ms Watchdog) Watchdog Output (WDO) The Watchdog Output WDO provides a status output that goes low if the watchdog timer “times out” and remains low until set high by the next transition on the watchdog input. WDO is also set high when LLIN goes below the reset threshold. 8 OSC SEL ADM869x CLOCK 0 TO 500kHz 7 OSC IN Figure 4a. External Clock Source –6– REV. 0 ADM8696/ADM8697 CE Gating and RAM Write Protection (ADM8697) The ADM8697 contains memory protection circuitry that ensures the integrity of data in memory by preventing write operations when LLIN is below the threshold voltage. When LLIN is greater than 1.3 V, CEOUT is a buffered replica of CEIN, with a 2 ns propagation delay. When LLIN falls below the 1.3 V threshold, an internal gate forces CEOUT high, independent of CEIN. CEOUT typically drives the CE, CS or Write input of battery backed up CMOS RAM. This ensures the integrity of the data in memory by preventing write operations when VCC is at an invalid level. ADM8697 CEIN LLIN LOW = 0 LLIN OK = 1 CEOUT can be chosen such that the voltage at PFI falls below 1.3 V several milliseconds before the +5 V power supply falls below the reset threshold. PFO is normally used to interrupt the microprocessor so that data can be stored in RAM and the shutdown procedure executed before power is lost. INPUT POWER R1 ADM869x 1.3V PFO POWER FAIL OUTPUT R2 POWER FAIL INPUT Figure 7. Power Fail Comparator Table II. Input and Output Status In Battery Backup Mode Signal VOUT RESET RESET Status (ADM8696) VOUT is connected to VBATT via an internal PMOS switch. Logic low. Logic high. The open circuit output voltage is equal to VOUT. Logic low. (ADM8696) Logic high. The open circuit voltage is equal to VOUT. WDI is ignored. It is internally disconnected from the internal pull-up resistor and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. Logic high. The open circuit voltage is equal to VOUT. The Power Fail Comparator is turned off and has no effect on the Power Fail Output. Logic low. CEIN is ignored. It is internally disconnected from its internal pull-up and does not source or sink current as long as its input voltage is between GND and VOUT. The input voltage does not affect supply current. Logic high. The open circuit voltage is equal to VOUT. OSC IN is ignored. OSC SEL is ignored. Figure 5. Chip Enable Gating LLIN V2 V1 V2 V1 LOW LINE RESET t1 t1 BATT ON WDI LOW LINE CEIN WDO CEOUT PFI t1 = RESET TIME V1 = RESET VOLTAGE THRESHOLD LOW V2 = RESET VOLTAGE THRESHOLD HIGH HYSTERESIS = V2–V1 PFO CEIN Figure 6. Chip Enable Timing Power Fail Warning Comparator An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input (PFI) is compared to an internal +1.3 V reference. The Power Fail Output (PFO) goes low when the voltage at PFI is less than 1.3 V. Typically PFI is driven by an external voltage divider which senses either the unregulated dc input to the system’s 5 V regulator or the regulated 5 V output. The voltage divider ratio CEOUT OSC IN OSC SEL REV. 0 –7– ADM8696/ADM8697–Typical Performance Curves 5 53 VCC = +5V 4.99 4.98 4.97 RESET ACTIVE TIME – ms 10 20 30 40 50 60 IOUT – mA 70 80 90 100 52 VOUT – Volts 51 4.96 4.95 50 4.94 49 20 40 60 80 TEMPERATURE – °C 100 120 Figure 8. VOUT vs. IOUT Normal Operation 2.8 2.798 2.796 Figure 11. RESET Active Time vs. Temperature A4 100 90 3.36 V VOUT – Volts 2.794 2.792 2.79 2.788 2.786 150 10 0% 250 350 450 550 650 IOUT – µA 750 850 950 1050 1V 1V 500ms Figure 9. VOUT vs. IOUT Battery Backup 1.32 Figure 12. RESET Output Voltage vs. Supply Voltage 5.5 TA = +25°C 5.0 PFI INPUT THRESHOLD – V 1.31 VCC – Volts 1.30 1.29 20 40 60 80 TEMPERATURE – °C 100 120 4.5 4.0 3.5 3.0 2.5 2.0 10 100 1000 TIME DELAY – ms 10000 Figure 10. PFI Input Threshold vs. Temperature Figure 13. RESET Timeout Delay vs. VCC –8– REV. 0 ADM8696/ADM8697 APPLICATIONS INFORMATION Increasing the Drive Current (ADM8696) If the continuous output current requirements at VOUT exceeds 100 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output (ADM8696) can directly drive the base of the external transistor. +5V INPUT POWER PNP TRANSISTOR 0.1µF VCC VBATT BATTERY BATT ON VOUT 0.1µF This circuit is not entirely foolproof and it is possible a software fault could erroneously three-state the buffer. This would prevent the ADM869x from detecting that the microprocessor is no longer operating correctly. In most cases, a better method is to +7V TO +15V INPUT POWER 7805 +5V VCC R1 1.3V PFI R2 PFO R4 TO µP NMI ADM869x R3 ADM8696 R1 R1 VH = 1.3V 1+ ––– + ––– R3 R2 ( ) ) Figure 14. Increasing the Drive Current Using a Rechargeable Battery for Backup (ADM8696) R1 R1 (5V – 1.3V) VL = 1.3V 1+ ––– – ––––––––––––– 1.3V (R3 + R4 ) R2 ( If a capacitor or a rechargeable battery is used for backup, the charging resistor should be connected to VOUT since this eliminates the discharge path that would exist during power-down if the resistor is connected to VCC. I= VOUT – VBATT R ASSUMING R4 < < R3 THEN R1 HYSTERESIS VH – VL = 5V ––– R2 ( ) Figure 16. Adding Hysteresis to the Power Fail Comparator +5V INPUT POWER R 0.1µF VCC VBATT VOUT 0.1µF RECHARGABLE BATTERY ADM8696 extend the watchdog period rather than disabling the watchdog. This may be done under program control using the circuit shown in Figure 17b. When the control input is high, the OSC SEL pin is low and the watchdog timeout is set by the external capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of 100 s. When the control input is low, the OSC SEL pin is driven high, selecting the internal oscillator. The 100 ms or the 1.6 s period is chosen, depending on which diode in Figure 17b is used. With D1 inserted, the internal timeout is set at 100 ms while with D2 inserted the timeout is set at 1.6 s. WATCHDOG STROBE CONTROL INPUT WDI Figure 15. Rechargeable Battery Adding Hysteresis to the Power Fail Comparator ADM869x For increased noise immunity, hysteresis may be added to the power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added by connecting a resistor between the PFO output and the PFI input as shown in Figure 16. When PFO is low, resistor R3 sinks current from the summing junction at the PFI pin. When PFO is high, the series combination of R3 and R4 source current into the PFI summing junction. This results in differing trip levels for the comparator. Alternate Watchdog Input Drive Circuits Figure 17a. Programming the Watchdog Input CONTROL INPUT* D1 D2 OSC IN OSC SEL ADM869x The watchdog feature can be enabled and disabled under program control by driving WDI with a three-state buffer (Figure 17a). When three-stated, the WDI input will float, thereby disabling the watchdog timer. *LOW = INTERNAL TIMEOUT HIGH = EXTERNAL TIMEOUT Figure 17b. Programming the Watchdog Input REV. 0 –9– ADM8696/ADM8697 TYPICAL APPLICATIONS ADM8696 Figure 18 shows the ADM8696 in a typical power monitoring, battery backup application. VOUT powers the CMOS RAM. Under normal operating conditions with VCC present, VOUT is internally connected to VCC. If a power failure occurs, VCC will decay and VOUT will be switched to VBATT, thereby maintaining power for the CMOS RAM. Power Fail RESET Figure 18b shows a similar application for the ADM8696 but in this case the PFI input monitors the unregulated input to the 7805 voltage regulator. This gives an earlier warning of an impending power failure. It is useful with processors operating at low speeds or where there are a significant number of housekeeping tasks to be completed before the power is lost. INPUT POWER 7805 0.1µF VCC 3V BATTERY R1 VBATT 0.1µF BATT VOUT ON The VCC power supply is also monitored by the Low Line Input, LLIN. A RESET pulse is generated when LLIN falls below 1.3 V. RESET will remain low for 50 ms after LLIN returns above 1.3 V. This allows for a power-on reset and prevents repeated toggling of RESET if the VCC power supply is unstable. Resistors R3 and R4 should be chosen to give the desired VCC reset threshold. Watchdog Timer VCC CMOS RAM ADM8696 PFI R2 R3 NC GND WDI OSC IN OSC SEL LLIN R4 RESET LOW LINE WDO PFO RESET A0–A15 I/O LINE NMI RESET µP POWER The Watchdog Timer Input (WDI) monitors an I/O line from the µP system. This line must be toggled once every 1.6 s to verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program and may be tied up in an endless loop. If this happens, a reset pulse is generated to initialize the processor. If the watchdog timer is not needed the WDI input should be left floating. Power Fail Detector µP SYSTEM STATUS INDICATORS Figure 18b. ADM8696 Typical Application Circuit B The Power Fail Input, PFI, monitors the input power supply via a resistive divider network R1 and R2. This input is intended as an early warning power fail input. The voltage on the PFI input is compared with a precision 1.3 V internal reference. If the input voltage drops below 1.3 V, a power fail output (PFO) signal is generated. This warns of an impending power failure and may be used to interrupt the processor so that the system may be shut down in an orderly fashion. The resistors in the sensing network are ratioed to give the desired power fail threshold voltage VT. The threshold should be set at a higher voltage than the RESET threshold so there is sufficient time available to complete the shutdown procedure before the processor is RESET and power is lost. +5V R3 R1 VCC PFI RESET R4 R2 LLIN VOUT µP POWER CMOS RAM POWER This application also shows an optional external transistor that may be used to provide in excess of 100 mA current on VOUT. When VCC is higher than VBATT, the BATT ON output goes low, providing 25 mA of base drive for the external PNP transistor. The maximum current available is dependent on the power rating of the external transistor. RAM Write Protection The ADM8697 CEOUT line drives the Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as long as LLIN is above the reset threshold. If LLIN falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM during power-up, power-down, brownouts and momentary power interruptions. ADM8696 RESET VBATT GND PFO WDI µP SYSTEM µP RESET µP NMI I/O LINE + BATTERY Figure 18a. ADM8696 Typical Application Circuit A –10– REV. 0 ADM8696/ADM8697 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP (N-16) 0.840 (21.33) 0.745 (18.93) 16 1 9 8 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN PIN 1 0.210 (5.33) MAX 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) 16-Lead Thin Shrink Small Outline Package (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.256 (6.50) 0.246 (6.25) SEATING PLANE 8° 0° 0.028 (0.70) 0.020 (0.50) 16-Lead Wide Body SOIC (R-16) 0.413 (10.50) 16 9 0.299 (7.60) 1 8 0.419 (10.65) PIN 1 0.012 (0.3) 0.05 (1.27) BSC 0.019 (0.49) 0.014 (2.65) SEATING PLANE 0.030 (0.75) 0.013 (0.32) 0.042 (1.07) REV. 0 –11– –12– C2977–10–2/97 PRINTED IN U.S.A.