Continuous Rate 10 Mbps to 2.7 Gbps Clock
and Data Recovery ICs
ADN2817/ADN2818
Data Sheet
FEATURES
GENERAL DESCRIPTION
Serial data input: 10 Mbps to 2.7 Gbps
Exceeds ITU-T jitter specifications
Integrated limiting amplifier
5 mV p-p sensitivity (ADN2817 only)
Adjustable slice level: ±100 mV (ADN2817 only)
Proprietary dual-loop clock recovery architecture
Programmable LOS detect (ADN2817 only)
Integrated PRBS generator and detector
No reference clock required
Loss of lock indicator
Supports double data rate
BERMON or sample phase adjust options
Rate selectivity without the use of a reference clock
I2C interface to access optional features
Single-supply operation: 3.3 V
Low power
650 mW (ADN2817)
600 mW (ADN2818)
5 mm × 5 mm 32-lead LFCSP
The ADN2817/ADN2818 provide the receiver functions of
quantization, signal level detect, and clock and data recovery for
continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/
ADN2818 automatically lock to all data rates without the need for
an external reference clock or programming. All SONET jitter
requirements are exceeded, including jitter transfer, jitter generation,
and jitter tolerance. All specifications are quoted for −40°C to
+85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, and low power
fiber optic receiver.
The ADN2817/ADN2818 have many optional features available
through an I2C interface. For example, the user can read back
the data rate onto which the ADN2817 or ADN2818 is locked,
or the user can set the device to lock only to one particular data
rate if provisioning of data rates is required. A bit error rate
monitor (BERMON) circuit provides an estimate of the received
bit error rate (BER) without interruption of the data.
Alternatively, the user can adjust the data sampling phase to
optimize the received BER.
APPLICATIONS
SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates
Fibre Channel, 2× Fibre Channel, GbE, HDTV
WDM transponders
Regenerators/repeaters
Test equipment
The ADN2817/ADN2818 are available in a compact 5 mm ×
5 mm, 32-lead, lead frame chip scale package.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2
VCC VEE
ADN2817/ADN2818
SLICEP/
SLICEN
SLICE
ADJUST
(ADN2817
ONLY)
FREQ/
LOCK
DET
LOOP
FILTER
PIN
PHASE
SHIFTER
PHASE
DET
LOOP
FILTER
VCO
NIN
LOS
DETECT
(ADN2817
ONLY)
THRADJ
LOS
DATA
RETIMING
ΔФ
BERMON
DATAOUTP/
DATAOUTN
I2C
REGISTERS
CLKOUTP/ VBER BERMODE SCK
CLKOUTN
SDA
06001-001
VREF
Figure 1.
Rev. G
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Tel: 781.329.4700 ©2007–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADN2817/ADN2818
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Jitter Tolerance ............................................................................ 19
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 20
General Description ......................................................................... 1
Functional Description .................................................................. 22
Functional Block Diagram .............................................................. 1
Frequency Acquisition ............................................................... 22
Revision History ............................................................................... 3
Lock Detector Operation .......................................................... 22
Specifications..................................................................................... 4
Harmonic Detector .................................................................... 23
Jitter Specifications ....................................................................... 5
Limiting Amplifier (ADN2817 Only) ..................................... 23
Output and Timing Specifications ............................................. 6
Slice Level Adjust (ADN2817 Only) ........................................ 23
Bit Error Rate Monitor Specifications ....................................... 8
Loss of Signal (LOS) Detector (ADN2817 Only)................... 23
Timing Characteristics ................................................................ 9
Sample Phase Adjust .................................................................. 24
Absolute Maximum Ratings .......................................................... 10
BER Monitor ............................................................................... 24
Thermal Characteristics ............................................................ 10
Squelch Mode ............................................................................. 25
ESD Caution ................................................................................ 10
I2C Interface ................................................................................ 25
Pin Configuration and Function Descriptions ........................... 11
Reference Clock (Optional) ...................................................... 26
Typical Performance Characteristics ........................................... 12
Additional Features Available via the I2C Interface ............... 28
I2C-Interface Timing and Internal Register Description .......... 14
Applications Information .............................................................. 30
Terminology .................................................................................... 18
PCB Design Guidelines ............................................................. 30
Input Sensitivity and Input Overdrive ..................................... 18
DC-Coupled Application .......................................................... 32
Single-Ended vs. Differential .................................................... 18
Coarse Data Rate Readback Lookup Table ................................. 33
LOS Response Time ................................................................... 18
HI_CODE and LO_CODE Lookup Table .................................. 35
Jitter Specifications ......................................................................... 19
Outline Dimensions ....................................................................... 38
Jitter Generation ......................................................................... 19
Ordering Guide .......................................................................... 38
Jitter Transfer............................................................................... 19
Rev. G | Page 2 of 38
Data Sheet
ADN2817/ADN2818
REVISION HISTORY
6/2019—Rev. F to Rev. G
Deleted AN-941 References ......................................... Throughout
Changes to Ordering Guide ...........................................................38
Updated Outline Dimensions ........................................................38
12/2015—Rev. E to Rev. F
Changes to Figure 5.........................................................................11
Updated Outline Dimensions ........................................................38
Changes to Ordering Guide ...........................................................38
1/2013—Rev. D to Rev. E
Moved Revision History Section ..................................................... 3
Change to Table 8 ............................................................................15
Changes to Table 15 ........................................................................17
Changes to Rate Selectivity Section ..............................................28
1/2012—Rev. C to Rev. D
Changes to Figure 14 ......................................................................12
Updated Outline Dimensions ........................................................37
3/2010—Rev. B to Rev. C
Changes to Features Section and Applications Section ............... 1
Changes to Thermal Resistance Section ........................................ 9
Added Table 6; Renumbered Sequentially ..................................... 9
Changes to Table 7 ..........................................................................10
Changes to Table 8 ..........................................................................14
Changes to Table 14 ........................................................................15
Deleted Table 16; Renumbered Sequentially ...............................16
Changes to Table 16 ........................................................................16
Changes to I2C Interface Section................................................... 24
Changed fREF Ratio to DIV_FREF Ratio....................................... 25
Changes to Initiate Frequency Acquisition, Rate Selectivity,
Double Data Rate Mode, and PRBS Generator/Detector
Sections ............................................................................................. 27
Changes to Table 19 ........................................................................ 32
Changes to Table 20 ........................................................................ 34
2/2009—Rev. A to Rev. B
Updated Outline Dimensions........................................................ 37
Changes to Ordering Guide ........................................................... 37
8/2008—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1 ............................................................................................... 1
Added Bit Rate Monitor Specifications Section and Table 4;
Renumbered Sequentially ................................................................ 7
Changes to Figure 5 and Table 6 ................................................... 10
Changes to Table 7 and Table 8 ..................................................... 14
Changes to Table 14 ........................................................................ 15
Added Table 15 ................................................................................ 15
Added Table 16 ................................................................................ 16
Added Sample Phase Adjust Section and Bit Error Rate (BER)
Monitor Section ............................................................................... 23
Added Figure 32; Renumbered Sequentially ............................... 24
Changes to Figure 36 ...................................................................... 29
Added Exposed Pad Notation to Outline Dimensions .............. 37
7/2007—Revision 0: Initial Version
Rev. G | Page 3 of 38
ADN2817/ADN2818
Data Sheet
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range (See Figure 6)
Hysteresis (Electrical)
OC-48
OC-1
LOS Assert Time
LOS Deassert Time
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
OC-48
OC-12
10 Mbps
ACQUISITION TIME
Lock to Data Mode
OC-48
OC-12
OC-3
OC-1
10 Mbps
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Coarse Readback
Fine Readback
Test Conditions/Comments
Min
Typ
Max
Unit
At PIN or NIN, dc-coupled
PIN − NIN
DC-coupled (see Figure 40, Figure 41, and Figure 42)
223 − 1 PRBS, ac-coupled, 1 BER = 1 × 10−10
ADN2817
ADN2818
1.8
2.3
2.5
2.8
2.0
2.8
V
V
V
10
200
5
10
mV p-p
mV p-p
2700
Mbps
dB
Ω
pF
0.13
+0.95
0.95
V/V
V
V
mV
14.2
2.1
20.0
5.0
mV
mV
6.2
4.7
4.9
3.0
8.2
7.7
7.5
7.3
450
500
dB
dB
dB
dB
ns
ns
1000
250
ppm
ppm
1.0
1.0
500
µs
µs
µs
1.3
2.0
3.4
9.8
40.0
10.0
ms
ms
ms
ms
ms
ms
At 2.5 GHz
Differential
−15
100
0.65
ADN2817 only
SLICEP − SLICEN = ±0.5 V
SLICEP − SLICEN
DC level at SLICEP or SLICEN
0.10
−0.95
VEE
0.11
±1
ADN2817 only
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
RTHRESH = 0 Ω
RTHRESH = 10 kΩ
DC-coupled 2
DC-coupled2
With respect to nominal
With respect to nominal
See Table 19
In addition to REFCLK accuracy
Rev. G | Page 4 of 38
10
100
%
ppm
Data Sheet
Parameter
POWER SUPPLY
Voltage
Current
ADN2817
ADN2818
OPERATING TEMPERATURE RANGE
1
2
ADN2817/ADN2818
Test Conditions/Comments
Min
Typ
Max
Unit
3.0
3.3
3.6
V
210
180
247
217
+85
mA
mA
°C
−40
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the ADN2817
input stage.
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer Bandwidth
OC-48
OC-12
OC-3
Jitter Peaking
OC-48
OC-12
OC-3
Jitter Generation
OC-48
12 kHz to 5 MHz
OC-3
12 kHz to 1.3 MHz
OC-12
OC-3
Min
12 kHz to 20 MHz
OC-12
Jitter Tolerance
OC-48
1
Test Conditions/Comments
223 − 1 PRBS
600 Hz 1
6 kHz1
100 kHz
1 MHz1
20 MHz
30 Hz1
300 Hz1
25 kHz
250 kHz1
5 MHz
30 Hz1
300 Hz1
6500 Hz
65 kHz1
130 kHz
92.0
20.0
7.0
1.00
0.53
100.0
44.0
7.35
1.00
0.52
50.0
23.5
6.71
1.00
0.54
Jitter tolerance of the ADN2817/ADN2818 at these jitter frequencies is better than what the test equipment is able to measure.
Rev. G | Page 5 of 38
Typ
Max
Unit
548
93
30
839
137
40
kHz
kHz
kHz
0
0
0
0.03
0.03
0.03
dB
dB
dB
0.001
0.02
0.001
0.01
0.001
0.01
0.003
0.046
0.004
0.036
0.004
0.023
UI rms
UI p-p
UI rms
UI p-p
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
ADN2817/ADN2818
Data Sheet
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
CML OUPUT CHARACTERISTICS (CLKOUTP/CLKOUTN,
DATAOUTP/DATAOUTN)
Single-Ended Output Swing, VSE
Differential Output Swing, VDIFF
Output Voltage
High, VOH
Low, VOL
CML Outputs Timing
Rise Time
Fall Time
Setup Time, tS
Hold Time, tH
Setup Time, tDDRS
Hold Time, tDDRH
I2C INTERFACE DC CHARACTERISTICS
Input Voltage
High, VIH
Low, VIL
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
High, tHIGH
Low, tLOW
Start Condition
Hold Time, tHD;STA
Setup Time, tSU;STA
Data
Setup Time, tSU;DAT
Hold Time, tHD;DAT
SCK/SDA Rise/Fall Time, tR/tF
Stop Condition Setup Time, tSU;STO
Bus Free Time Between a Stop and a Start, tBUF
REFCLK CHARACTERISTICS
Input Voltage Range
VIL
VIH
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
Test Conditions/Comments
Min
Typ
Max
Unit
See Figure 3
See Figure 3
300
600
350
700
600
1200
mV
mV
VCC − 0.6
VCC − 0.35
VCC
VCC − 0.3
V
V
150
150
140
200
80
80
200
200
170
230
112
123
250
250
200
260
ps
ps
ps
ps
ps
ps
0.3 VCC
+10.0
0.4
V
V
µA
V
400
kHz
20% to 80%
80% to 20%
See Figure 2, OC-48
See Figure 2, OC-48
See Figure 4, OC-48
See Figure 4, OC-48
LVCMOS
0.7 VCC
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 22
−10.0
600
1300
ns
ns
600
600
ns
ns
100
300
20 + 0.1 Cb
600
1300
ns
ns
ns
ns
ns
300
Optional lock to REFCLK mode
At REFCLKP or REFCLKN
0
VCC
100
10
200
100
Rev. G | Page 6 of 38
V
V
mV p-p
MHz
ppm
Data Sheet
Parameter
LVTTL DC INPUT CHARACTERISTICS
Input Voltage
High, VIH
Low, VIL
Input Current
High
Low
LVTTL DC OUTPUT CHARACTERISTICS
Output Voltage
High
Low
ADN2817/ADN2818
Test Conditions/Comments
Min
Typ
Max
Unit
0.8
V
V
2.0
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
VOH, IOH = −2.0 mA
VOL, IOL = +2.0 mA
Rev. G | Page 7 of 38
+5
−5
2.4
0.4
µA
µA
V
V
ADN2817/ADN2818
Data Sheet
BIT ERROR RATE MONITOR SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 4.
Parameter
BERMON Extrapolation Mode
Final Computed BER Accuracy
Number of Bits (NUMBITS)
Pseudo BER (PBER) Measurement
Time
BER Range
Sample Phase Adjust Resolution
Sample Phase Adjust Accuracy
Sample Phase Adjust Range
Minimum Input Signal Level
Power Increase
BERMON Voltage Output Mode
BER Accuracy
NUMBITS
Measurement Time
VBER Voltage Range
Minimum Input Signal Level
Power Increase
Sample Phase Adjust Mode
Sample Phase Adjust Step Size
Sample Phase Adjust Accuracy
Sample Phase Adjust Range
Power Increase
Test Conditions/Comments
I2C-controlled eye profiling
Input BER range 1 × 10−3 to 1 × 10−12,
input deterministic jitter (DJ) < 0.4 UI,
DJ ceiling > 1 × 10−2; asymmetry < 0.1 UI;
requires external data processing algorithms
to implement Q factor extrapolation
Number of data bits to collect pseudo errors;
user programmable in increment factors of
23 over the range 218 to 239
Min
Typ
Max
±1
218
Decades
239
NUMBITS/
data rate
160
77
BER
Degrees
Degrees
UI
mV
mW
mW
±1
Decades
+1/−2
Decades
227
0.054
0.134
0.865
1.34
UI
sec
sec
sec
sec
V
mV
mW
6
1 × 10−2;
asymmetry = 0 UI; BER is read as a voltage on
the VBER pin, when the BER mode pin = VEE
Number of data bits to collect pseudo errors
2.5 Gbps
1 Gbps
155 Mbps
10 Mbps
Via 3 kΩ resistor to VEE
Differential peak to peak
BER voltage mode
Unit
Degrees
Degrees
UI
mW
Data Sheet
ADN2817/ADN2818
TIMING CHARACTERISTICS
CLKOUTP
tH
06001-002
tS
DATAOUTP/
DATAOUTN
Figure 2. Default Mode Output Timing
OUTP
VCML
VSE
OUTN
OUTP – OUTN
VDIFF
06001-003
VSE
0V
Figure 3. Single-Ended vs. Differential Output Specifications
tDDRS
tDDRH
DATAOUTP/
CLKOUTN
Figure 4. Double Data Rate Mode Output Timing
Rev. G | Page 9 of 38
06001-042
CLKOUTP/
CLKOUTN
ADN2817/ADN2818
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V,
CF = 0.47 µF, SLICEP = SLICEN = VEE, unless otherwise noted.
Thermal Resistance
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages, on a
4-layer board with the exposed paddle soldered to VEE.
Table 5.
Parameter
Supply Voltage (VCC)
Input Voltage (All Inputs)
Minimum
Maximum
Junction Temperature, Maximum
Storage Temperature Range
THERMAL CHARACTERISTICS
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6. Thermal Resistance
Package Type
32-Lead LFCSP
ESD CAUTION
Rev. G | Page 10 of 38
θJA
28
Unit
°C/W
Data Sheet
ADN2817/ADN2818
VBER
VCC
VEE
DATAOUTP
DATAOUTN
SQUELCH
CLKOUTP
CLKOUTN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADN2817/
ADN2818
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VCC
VEE
LOS
SDA
SCK
SADDR5
VCC
VEE
06001-004
THRADJ
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
LOL
9
10
11
12
13
14
15
16
BERMODE
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECTED TO VEE.
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
BERMODE
VCC
VREF
NIN
PIN
SLICEP
SLICEN
VEE
THRADJ
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
LOL
VEE
VCC
SADDR5
SCK
SDA
LOS
VEE
VCC
CLKOUTN
CLKOUTP
SQUELCH
DATAOUTN
DATAOUTP
VEE
VCC
VBER
EPAD
Type
Digital input
Power
Analog output
Analog input
Analog input
Analog input
Analog input
Power
Analog input
Digital input
Digital input
Power
Power
Analog output
Analog output
Digital output
Power
Power
Digital input
Digital input
Digital input
Digital output
Power
Power
Digital output
Digital output
Digital input
Digital output
Digital output
Power
Power
Analog output
Power
Description
Set this pin to logic low to enable analog voltage output mode for BER monitor.
Power for Input Stage, LOS.
Internal VREF Voltage. Decouple to ground with a 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
GND for the Limiting Amplifier, LOS.
LOS Threshold Setting Resistor.
Differential REFCLK Input. 10 MHz to 200 MHz.
Differential REFCLK Input. 10 MHz to 200 MHz.
VCO Power.
VCO Ground.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss of Lock Indicator. Active high, LVTTL.
FLL Detector Ground.
FLL Detector Power.
Slave Address Bit 5.
I2C Clock Input.
I2C Data Input.
Loss of Signal Detect Output. Active high, LVTTL.
Output Buffer, I2C Ground.
Output Buffer, I2C Power.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Disable Clock and Data Outputs. Active high, LVTTL.
Differential Recovered Data Output. CML.
Differential Recovered Data Output. CML.
Phase Detector, Phase Shifter Ground.
Phase Detector, Phase Shifter Power.
This pin represents BER when analog BERMON is enabled with 3 kΩ to VEE.
Exposed Paddle. The Exposed paddle on the bottom of the package must be connected to VEE.
Rev. G | Page 11 of 38
ADN2817/ADN2818
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.020
0.018
0.014
0.012
200mV/DIV
TRIP POINT (mV p-p)
0.016
0.010
0.008
0.006
06001-040
0.004
0
10k
1k
RTH (Ω)
100
10
1
100k
1M
06001-005
0.002
50ps/DIV
Figure 9. Output Eye, OC-48
Figure 6. LOS Comparator Trip Point Programming
5
100
JITTER AMPLITUDE (UI)
0
GAIN (dB)
SONET
–5
–10
ADN2817
10
1
–15
10k
100k
1M
JITTER FREQUENCY (Hz)
0.1
10
100
1k
10k
100k
1M
06001-039
1k
06001-032
–20
100
10M
06001-038
ADN2817
EQUIPMENT LIMIT
SONET GR-253 CORE 004
JITTER FREQUENCY (Hz)
Figure 7. Jitter Transfer, OC-1
Figure 10. Jitter Tolerance, OC-1
5
100
JITTER AMPLITUDE (UI)
SONET
ADN2817
–5
–10
10
1
–15
ADN2817
EQUIPMENT LIMIT
SONET GR-253 CORE 004
–20
100
1k
10k
100k
JITTER FREQUENCY (Hz)
1M
10M
06001-034
GAIN (dB)
0
Figure 8. Jitter Transfer, OC-3
0.1
10
100
1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 11. Jitter Tolerance, OC-3
Rev. G | Page 12 of 38
1M
Data Sheet
ADN2817/ADN2818
1000
5
0
JITTER AMPLITUDE (UI)
–5
ADN2817
–10
100
10
1
–15
1k
10k
100k
10M
1M
JITTER FREQUENCY (Hz)
0.1
10
06001-033
–20
100
1M
100k
10k
1k
10M
06001-037
ADN2817
EQUIPMENT LIMIT
SONET GR-253 CORE 004
100M
06001-036
GAIN (dB)
SONET
JITTER FREQUENCY (Hz)
Figure 12. Jitter Transfer, OC-12
Figure 15. Jitter Tolerance, OC-12
1000
5
JITTER AMPLITUDE (UI)
0
–5
ADN2817
–10
100
10
1
–15
ADN2817
EQUIPMENT LIMIT
SONET GR-253 CORE 004
100k
10M
1M
100M
JITTER FREQUENCY (Hz)
0.1
10
06001-035
–20
10k
100
1
0.65
0.1
1M
10M
0.01
0.60
0.001
BIT ERROR RATE
0.55
0.50
0.45
0.40
0.0001
0.00001
0.000001
0.0000001
CLKOUTP ADN2817
CLKOUTN ADN2817
600M
1.1G
0.00000001
1.6G
2.1G
2.6G
DATA RATE (Hz)
3.1G
06001-043
OUTPUT SWING (V)
100k
Figure 16. Jitter Tolerance, OC-48
0.70
0.30
100M
10k
JITTER FREQUENCY (Hz)
Figure 13. Jitter Transfer, OC-48
0.35
1k
0.000000001
1.0
1.5
2.0
2.5
3.0
3.5
INPUT LEVEL (mV)
Figure 17. Bit Error Rate vs. Input Level
Figure 14. Output Swing vs. Data Rate
Rev. G | Page 13 of 38
4.0
4.5
06001-041
GAIN (dB)
SONET
ADN2817/ADN2818
Data Sheet
I2C-INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
R/W
CTRL.
SLAVE ADDRESS [6:0]
A5
SET BY
PIN 19
0
0
0
0
0
X
06001-007
1
MSB = 1
0 = WR
1 = RD
S
SLAVE ADDR, LSB = 0 (WR)
A(S) SUB ADDR A(S) DATA A(S)
DATA A(S)
P
06001-008
Figure 18. Slave Address Configuration
Figure 19. I2C Write Data Transfer
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR
A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA
A(M)
DATA A(M) P
P = STOP BIT
A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(M) = ACKNOWLEDGE BY MASTER
06001-009
S
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
Figure 20. I2C Read Data Transfer
SDA
SLAVE ADDRESS
A6
SUB ADDRESS
A5
A7
STOP BIT
DATA
A0
D7
D0
SCK
S
WR
ACK
ACK
SLADDR[4:0]
ACK
SUB ADDR[6:1]
DATA[6:1]
Figure 21. I2C Data Transfer Timing
tF
tSU;DAT
tHD;STA
tBUF
SDA
tR
tR
tSU;STO
tF
tLOW
tHIGH
tHD;STA
S
tSU;STA
S
tHD;DAT
Figure 22. I2C Port Timing Diagram
Rev. G | Page 14 of 38
P
S
06001-011
SCK
P
06001-010
START BIT
Data Sheet
ADN2817/ADN2818
Table 8. Internal Register Map 1
Reg Name
FREQ0
FREQ1
FREQ2
Rate
MISC
R/W
R
R
R
R
R
Addr
0x00
0x01
0x02
0x03
0x04
CTRLA
W
0x08
CTRLA_RD
CTRLB
R
W
0x05
0x09
CTRLB_RD
CTRLC
R
W
0x06
0x11
CTRLD
W
CTRLE/BERCTLB 2
D7
MSB
MSB
0
D6
MSB
X
X
D5
LOS status
fREF range
D4
COARSE_RD[8:1]
LOL status Data rate
measurement
complete
Data rate/DIV_FREF ratio
Reset
MISC[4]
Initiate freq
acquisition
0
0
0
0
0
0x22
CDR
bypass
0x1F
0
Disable
CLKOUT
buffer
Enable
BERMON
0
W
Disable
DATAOUT
buffer
0
SEL_MODE
W
0x34
0
0
0
HI_CODE
LO_CODE
CODE_LSB
W
W
W
0x35
0x36
0x39
BERCTLA
W
0x1E
BERSTS
R
0x20
X
BER_RES
BER_DAC
Phase
R
R
W
0x21
0x24
0x37
X
0
1
2
0
0
D2
Static
LOL
Config
LOL
0
D3
BER
stdby
mode
0
0
Readback CTRLA
Reset
0
MISC[2]
Readback CTRLB
0
Config LOS
Initiate
PRBS
sequence
0
Limited
rate mode
D1
D0
LSB
LSB
LSB
X
COARSE_RD[0]
(LSB)
Measure
data rate
Lock to REFCLK
0
0
Squelch
0
mode
PRBS mode
PRBS/DDR enable and output mode
0
CLK
holdover
mode
0
HI_CODE[8:1]
LO_CODE[8:1]
0
0
HI_CODE[0]
LO_CODE[0]
(LSB)
(LSB)
BER timer (NUMBITS)
0
BER start
Error count byte select, for example, 011 = Byte 3
pulse
of 5 (NUMERRORS[39:0])
X
X
X
X
X
X
End of BER
measurement
(EOBM)
BER_RES[7:0], one byte of pseudo BER measurement result (NUMERRORS[39:0])
X
BER_DAC[5:0], input to BER DAC in analog BERMON mode
0
Phase[5:0], twos complement sample phase adjustment,
phase code range is from −30 decimal to +30 decimal,
which gives a sampling phase offset range from −0.5 UI to +0.5 UI;
for example, phase = 111010 is−6 decimal,
which gives a sampling phase offset of −6/+60 = −0.1 UI
X = don’t care.
Both CTRLE and BERCTLB registers are used, depending on the application.
Table 9. Miscellaneous Register, MISC
D7
X
D6
X
LOS Status
D5
0 = no loss of signal
1 = loss of signal
Static LOL
D4
0 = waiting for next LOL
1 = static LOL until reset
LOL Status
D3
0 = locked
1 = acquiring
Data Rate Measurement Complete
D2
0 = measuring data rate
1 = measurement complete
Rev. G | Page 15 of 38
D1
X
COARSE_RD[0] (LSB)
D0
COARSE_RD[0]
ADN2817/ADN2818
Data Sheet
Table 10. Control Register, CTRLA
D7
Set to 0
Set to 0
Set to 1
Set to 1
fREF Range
D6
Range
Set to 0 10 MHz to 25 MHz
Set to 1 25 MHz to 50 MHz
Set to 0 50 MHz to 100 MHz
Set to 1 100 MHz to 200 MHz
Data Rate/DIV_FREF Ratio
D5 D4 D3 D2 Ratio
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
n
2n
1
0
0
0
256
Measure Data Rate
D1
Set to 1 to measure data rate
Lock to REFCLK
D0
0 = lock to input data
1 = lock to reference clock
Table 11. Control Register, CTRLB
Config LOL
D7
0 = LOL pin normal
operation
1 = LOL pin is static LOL
Reset MISC[4]
D6
Write a 1 followed
by 0 to reset MISC[4]
Initiate Freq Acquisition
D5
Write a 1 followed
by 0 to initiate a
frequency acquisition
D4
Set
to 0
Reset MISC[2]
D3
Write a 1 followed
by 0 to reset MISC[2]
D2
Set
to 0
D1
Set
to 0
D0
Set
to 0
Table 12. Control Register, CTRLC
D7
Set to 0
D6
Set to 0
D5
Set to 0
D4
Set to 0
D3
Set to 0
Configure LOS
D2
0 = active high LOS
1 = active low LOS
Squelch Mode
D1
0 = squelch CLK and DATA
1 = squelch CLK or DATA
D0
Set to 0
Table 13. Control Register, CTRLD
CDR Bypass
D7
0 = CDR enabled
1 = CDR disabled
Disable
DATAOUT Buffer
D6
0 = data buffer enabled
1 = data buffer disabled
Disable
CLKOUT Buffer
D5
0 = CLK buffer enabled
1 = CLK buffer disabled
D4
Set to 0
Initiate PRBS
Sequence
D3
Write a 1 followed
by 0 to initiate a
PRBS generate
sequence
D2
0
0
1
D1
0
0
0
PRBS Mode
D0 Function
0
Power-down PRBS
1
Generate mode
0
Detect mode
Table 14. Control Registers, CTRLE/BERCTLB
D7
Set to 0
D6
Set to 0
Enable BERMON
D5
1 = BERMON
enabled
BER Stdby Mode
D4
1 = place BERMON in low
power standby mode
0 = BERMON
disabled
0 = BERMON ready
D3
Set to 0
Rev. G | Page 16 of 38
PRBS/DDR Enable and Output Mode
D2 D1 D0 Function
0
0
0
Normal data rate output mode
0
0
1
Offset decision circuit (ODC) output
mode
0
1
0
Enable DDR mode (double data rate
mode)
0
1
1
Offset decision circuit (ODC) output
in DDR mode
1
0
1
Enable PRBS detector/generator
All other combinations reserved
Data Sheet
ADN2817/ADN2818
Table 15. Mode Select Register, SEL_MODE
D7
Set to 0
D6
Set to 0
D5
Set to 0
D4
Set to 0
D3
Default 0
Limited rate enable = 1
D2
Set to 0
CLK Holdover Mode
D1
Set to 1 for clock holdover mode
D0
Set to 0
Table 16. BER Control Register, BERCTLA
D7
0
0
0
0
1
1
1
1
BER Timer (NUMBITS)
D6 D5 No. of Bits
0
0
218 bits
0
1
1
0
0
1
1
1
0
1
0
1
0
1
D4
Set to 0
BER Start Pulse
D3
Write a 1 followed by a 0 to initiate BER
measurement
221 bits
224 bits
227 bits
230 bits
233 bits
236 bits
239 bits
Error Count Byte Select (NUMERRORS[39:0])
D2
D1 D0 Byte Selection
0
0
0
Byte 0
0
0
0
1
Rev. G | Page 17 of 38
0
1
1
0
1
0
1
0
Byte 1
Byte 2
Byte 3
Byte 4
ADN2817/ADN2818
Data Sheet
TERMINOLOGY
10mV p-p
INPUT SENSITIVITY AND INPUT OVERDRIVE
OUTPUT
NOISE
1
0
VREF
PIN
+
QUANTIZER
–
50Ω
50Ω
VREF
2.5V
3kΩ
06001-013
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the logic
output of the quantizer and the analog voltage input is shown in
Figure 23. For sufficiently large positive input voltages, the output
is always Logic 1 and, similarly for negative inputs, the output is
always Logic 0. However, the transitions between Output Logic
Level 1 and Output Logic Level 0 are not at precisely defined
input voltage levels but occur over a range of input voltages. Within
this range of input voltages, the output may be either 1 or 0, or
it may even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage. Input
overdrive is the magnitude of signal required to guarantee the
correct logic level with 1 × 10−10 confidence level.
SCOPE
PROBE
Figure 24. Single-Ended Sensitivity Measurement
Differentially driving the ADN2817 (see Figure 25), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a singleended probe. A 5 mV p-p signal appears to drive the ADN2817
quantizer. However, the single-ended probe measures only half
the signal. The true quantizer input signal is twice this value
because the other quantizer input is a complementary signal to
the signal being observed.
5mV p-p
OFFSET
INPUT (V p-p)
SCOPE
PROBE
VREF
PIN
+
Figure 23. Input Sensitivity and Input Overdrive
QUANTIZER
NIN
SINGLE-ENDED vs. DIFFERENTIAL
AC coupling is typically used to drive the inputs to the quantizer.
The inputs are internally dc biased to a common-mode potential of
approximately 2.5 V. Driving the ADN2817/ADN2818 singleended and observing the quantizer input with an oscilloscope
probe at the point indicated in Figure 24 shows a binary signal
with an average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 24, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2817 quantizer typically has
5 mV p-p sensitivity. The ADN2818 does not have a limiting
amplifier at its input. The input sensitivity for the ADN2818 is
200 mV p-p.
–
50Ω
VREF
50Ω
VREF
5mV p-p
2.5V
3kΩ
06001-014
SENSITIVITY
(2× OVERDRIVE)
06001-012
OVERDRIVE
Figure 25. Differential Sensitivity Measurement
LOS RESPONSE TIME
The LOS response time is the delay between the removal of the
input signal and the indication of the loss of signal at the LOS
output, Pin 22. When the inputs are dc-coupled, the LOS assert
time of the ADN2817 is 450 ns typically and the deassert time is
500 ns typically. In practice, the time constant produced by the
ac coupling at the quantizer input and the 50 Ω on-chip input
termination determine the LOS response time.
Rev. G | Page 18 of 38
Data Sheet
ADN2817/ADN2818
JITTER SPECIFICATIONS
JITTER GENERATION
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter
has a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated must be less than 0.01 UI rms
and must be less than 0.1 UI p-p.
JITTER TRANSFER
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 26).
SLOPE = –20dB/DECADE
ACCEPTABLE
RANGE
06001-015
fC
JITTER FREQUENCY (kHz)
Figure 26. Jitter Transfer Curve
JITTER TOLERANCE
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating conditions
(see Figure 27).
15.00
Rev. G | Page 19 of 38
SLOPE = –20dB/DECADE
1.50
0.15
f0
f1
f2
f3
JITTER FREQUENCY (kHz)
Figure 27. SONET Jitter Tolerance Mask
f4
06001-016
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2817/ADN2818 performance with respect to those
specifications.
JITTER GAIN (dB)
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can cause
dynamic phase errors on the recovered clock sampling edge. Jitter
on the recovered clock causes jitter on the retimed data.
0.1
INPUT JITTER AMPLITUDE (UI p-p)
The ADN2817/ADN2818 CDR is designed to achieve the best
bit error rate (BER) performance and exceeds the jitter transfer,
generation, and tolerance specifications proposed for
SONET/SDH equipment defined in the Telcordia® Technologies
specification.
ADN2817/ADN2818
Data Sheet
THEORY OF OPERATION
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop is
caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 28 shows that
the jitter transfer function, Z(s)/X(s), is second-order low-pass,
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 29). This makes this circuit ideal for signal
regenerator applications, where jitter peaking in a cascade of
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
INPUT
DATA
X(s)
e(s)
d/sc
o/s
1/n
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
1
=
cn
n psh
X(s)
s2
+s
+1
do
o
TRACKING ERROR TRANSFER FUNCTION
06001-017
e(s)
s2
=
d psh do
X(s)
+
s2 + s
cn
c
Figure 28. ADN2817/ADN2818 PLL/DLL Architecture
JITTER PEAKING
IN ORDINARY PLL
ADN28xx
Z(s)
X(s)
o
n psh
d psh
c
FREQUENCY (kHz)
06001-018
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to a higher frequency
and increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while, simultaneously, the
delayed data loses phase. Because the loop filter is an integrator,
the static phase error is driven to zero.
psh
JITTER GAIN (dB)
The ADN2817/ADN2818 are delay- and phase-locked loop
circuits for clock recovery and data retiming from an NRZ
encoded data stream. The phase of the input data signal is tracked
by two separate feedback loops that share a common control
voltage. A high speed delay-locked loop path uses a voltage
controlled phase shifter to track the high frequency components
of input jitter. A separate phase control loop, composed of the
VCO, tracks the low frequency components of input jitter. The
initial frequency of the VCO is set by a third loop, which
compares the VCO frequency with the input data frequency
and sets the coarse tuning voltage. The jitter tracking phaselocked loop controls the VCO by the fine-tuning control.
Figure 29. ADN2817/ADN2818 Jitter Response vs. Conventional PLL
The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to track
large jitter amplitudes with small phase error. In this case, the
VCO is frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider tuning
range gives larger accommodation of low frequency jitter. The
internal loop control voltage remains small for small phase
errors, so the phase shifter remains close to the center of its
range and thus contributes little to the low frequency jitter
accommodation.
Rev. G | Page 20 of 38
Data Sheet
ADN2817/ADN2818
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or the other.
The size of the VCO tuning range, therefore, has only a small
effect on the jitter accommodation. The delay-locked loop control
voltage is now larger, and so the phase shifter takes on the
burden of tracking the input jitter. The phase shifter range, in
UI, can be seen as a broad plateau on the jitter tolerance curve.
The phase shifter has a minimum range of 2 UI at all data rates.
The gain of the loop integrator is small for high jitter frequencies,
so that larger phase differences are needed to make the loop
control voltage big enough to tune the range of the phase shifter.
Large phase errors at high jitter frequencies cannot be tolerated.
In this region, the gain of the integrator determines the jitter
accommodation. Because the gain of the loop integrator declines
linearly with frequency, jitter accommodation is lower with higher
jitter frequency. At the highest frequencies, the loop gain is very
small, and little tuning of the phase shifter can be expected. In this
case, jitter accommodation is determined by the eye opening of the
input data, the static phase error, and the residual loop jitter
generation. The jitter accommodation is roughly 0.5 UI in this
region. The corner frequency between the declining slope and
the flat region is the closed-loop bandwidth of the delay-locked
loop, which is roughly 3 MHz at OC-48.
Rev. G | Page 21 of 38
ADN2817/ADN2818
Data Sheet
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
Once LOL is deasserted, the frequency-locked loop is turned off.
The phase- and delay-locked loop (PLL/DLL) pulls in the VCO
frequency until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 µF ± 20%, X7R ceramic
chip capacitor with 300MΩ
INSULATION RESISTANCE
VCC
0.1µF
1nF
Figure 36. Typical ADN2817/ADN2818 Applications Circuit
Rev. G | Page 30 of 38
06001-025
50Ω
TIA
2
VCC
VCC
LOL
VCC
25
24
CF1
NIN
26
1
REFCLKP
0.1µF
27
CF2
VREF
28
VEE
1nF
29
VCC
VCC
0.1µF
30
REFCLKN
BERMODE
VEE
VCC
VBER
10kΩ
DATAOUTN
DATAOUTP
10kΩ
Data Sheet
ADN2817/ADN2818
Transmission Lines
Soldering Guidelines for Lead Frame Chip Scale Package
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP, REFCLKN, if using a high frequency reference clock,
such as 155 MHz). It is also necessary for the PIN/NIN input
traces to be matched in length, and the CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN output traces to be matched
in length to avoid skew between the differential traces.
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width. Center the land on the pad to ensure that the solder joint
size is maximized. The bottom of the lead frame chip scale package
has a central exposed pad. The pad on the printed circuit board
should be at least as large as this exposed pad. The user must
connect the exposed pad to VEE using plugged vias to prevent
solder from leaking through the vias during reflow. This ensures a
solid connection from the exposed pad to VEE.
All high speed CML outputs (CLKOUTP, CLKOUTN,
DATAOUTP, and DATAOUTN) require 100 Ω back
termination chip resistors connected between the output pin
and VCC. Place these resistors as close as possible to the output
pins. These 100 Ω resistors are in parallel with on-chip 100 Ω
termination resistors to create a 50 Ω back termination (see
Figure 37).
The high speed inputs (PIN and NIN) are internally terminated
with 50 Ω to an internal reference voltage (see Figure 38). A 0.1 µF
capacitor is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
100Ω
100Ω
100Ω
VTERM
100Ω
50Ω
0.1µF
For example, assuming that 2% droop can be tolerated, the
maximum differential droop is 4%. Normalizing to peak-topeak voltage,
50Ω
50Ω
VTERM
ADN2817/ADN2818
Droop = ∆ V = 0.04 V = 0.5 V p-p (1 − e–t/τ) ; therefore, τ = 12t
06001-026
0.1µF
where:
τ is the RC time constant (C is the ac coupling capacitor, and
R = 100 Ω seen by C).
t is the total discharge time, which is equal to nΤ.
n is the number of CIDs.
T is the bit period.
Figure 37. Typical ADN2817/ADN2818 Applications Circuit
ADN2817/ADN2818
VCC
CIN
TIA
TIA
PIN
50Ω
Calculate the capacitor value by combining the equations for τ and t.
C = 12nT/R
NIN
50Ω
CIN
50Ω
2.5V
VREF
3kΩ
06001-027
0.1µF
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2817/ADN2818 must
be chosen such that the device works properly over the full
range of data rates used in the application. When choosing the
capacitors, the time constant formed with the two 50 Ω resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can droop due to baseline wander (see Figure 39), causing
pattern dependent jitter (PDJ).
The user must determine how much droop is tolerable and choose
an ac coupling capacitor based on that amount of droop. The
amount of PDJ can then be approximated based on the capacitor
selection. The actual capacitor value selection may require some
trade-offs between droop and PDJ.
VCC
VCC
Choosing AC Coupling Capacitors
Figure 38. ADN2817/ADN2818 AC-Coupled Input Configuration
When the capacitor value is selected, approximate PDJ as
PDJps p-p = 0.5tr(1 − e(−nT/RC))/0.6
where:
PDJps p-p is the amount of pattern-dependent jitter allowed;
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