ADN4670

Programmable Low Voltage 1:10 LVDS Clock Driver ADN4670 FEATURES Low output skew 100 mV, this output sinks current. When the differential input voltage is between CLKx and CLKx < −100 mV, this output sources current. Noninverted Clock Output. When the differential input voltage is between CLKx and CLKx > 100 mV, this output sources current. When the differential input voltage is between CLKx and CLKx < −100 mV, this output sinks current. Power Supply Input. This part can be operated from 2.375 V to 2.625 V. Q9 to Q0 VDD Rev. 0 | Page 7 of 12 VSS Q9 Q9 Q8 Q8 Q7 Q7 VDD 9 10 11 12 13 14 15 16 ADN4670 THEORY OF OPERATION The ADN4670 is a clock driver/expander for low voltage differential signaling (LVDS). It takes a differential clock signal of typically 350 mV and expands it to 10 differential clock outputs with very low skew (typically < 30 ps). The device receives a differential current signal from a source such as a twisted pair cable, which develops a voltage of typically ±350 mV across a 100 Ω terminating resistor. This signal passes via a differential multiplexer to 10 drivers that each output a differential current signal. The device is programmable using a simple serial interface. One of two differential clock inputs (CLK0/CLK0 or CLK1/ CLK1), can be selected and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled. PROGRAMMING Three control inputs are provided for programming the ADN4670. EN is the enable input, which allows programming when high, SI is the serial data input, and CK is the serial clock input, which clocks data into the device on a low-to-high clock transition. Each of these inputs has an internal pull-up or pull-down resistor of 120 kΩ. EN and SI are pulled low if left open-circuit while CK is pulled high. The default condition if these inputs are left open-circuit is that all outputs are enabled, and the state of SI selects the inputs (0 = CLK0/CLK0 , 1 = CLK1/CLK1). This is the standard operating mode for which no programming of the device is required. Programming is enabled by taking EN high. The data on SI is then clocked into the device on each 0-to-1 transition of CK. Data on SI must be stable for the setup time (tSU) before the clock transition and remain stable for the hold time (tH) after the clock transition. To program the device, 11 bits of data are needed, starting with Bit 0, which enables or disables outputs Q9/Q9, through to Bit 10, which selects either CLK0/CLK0 or CLK1/CLK1 as the inputs. A 12th clock pulse is then required to transfer data from the shift register to the control register. A low-to-high transition on EN resets the control register and the next 12 CK pulses are programmed. LVDS RECIEVER INPUT TERMINATION Terminate the clock inputs with 100 Ω resistors from CLK0 to CLK0 and CLK1 to /CLK1, placed as close as possible to the input pins. FAIL-SAFE OPERATION In power-down mode (VDD = 0 V), the ADN4670 has fail-safe input and output pins. In power-on mode, fail-safe biasing can be achieved by connecting 10 kΩ pull-up resistors from CLK0 and CLK1 to VDD and 10 kΩ pull-down resistors from CLK0 and CLK1 to GND. Table 5. Control Logic Truth Table CK L L L L L L EN L L L L L L SI L L L H H H CLK0 L H Open X X X CLK0 H L Open X X X CLK1 X X X L H Open CLK1 X X X H L Open Q0 to Q9 L H L L H L Q0 to Q9 H L H H L H Table 6. State Machine Inputs EN L L H H L SI L H L H X CK X X ↑ ↑ X Output Default state with all outputs enabled, CLK0 selected, and the control register disabled All outputs enabled, CLK1 selected, and the control register disabled First stage stores low, other stage stores data of previous stage First stage stores high, other stage stores data of previous stage Reset the state machine, control register, and shift register Table 7. Serial Input Sequence Bit 10 CLK_SEL Bit 9 Q0 Bit 8 Q1 Bit 7 Q2 Bit 6 Q3 Bit 5 Q4 Bit 4 Q5 Bit 3 Q6 Bit 2 Q7 Bit 1 Q8 Bit 0 Q9 Table 8. Control Register Bit 10 L H X Bit[9:0] H H L Qx[9:0] CLK0 CLK1 Outputs disabled Rev. 0 | Page 8 of 12 ADN4670 OUTLINE DIMENSIONS PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.30 0.25 0.18 25 32 1 EXPOSED PAD PIN 1 INDICATOR 0.50 BSC 24 3.25 3.10 SQ 2.95 8 9 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 16 BOTTOM VIEW 0.25 MIN SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. Figure 5. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm× 5 mm Body, Very Very Thin Quad (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADN4670BCPZ ADN4670BCPZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 112408-A Package Option CP-32-7 CP-32-7 Z = RoHS Compliant Part. Rev. 0 | Page 9 of 12 ADN4670 NOTES Rev. 0 | Page 10 of 12 ADN4670 NOTES Rev. 0 | Page 11 of 12 ADN4670 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08870-0-4/10(0) Rev. 0 | Page 12 of 12