ADN8834ACPZ-R2

Data Sheet ADN8834 Ultracompact, 1.5 A Thermoelectric Cooler (TEC) Controller FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► FUNCTIONAL BLOCK DIAGRAM Patented high efficiency single inductor architecture Integrated low RDSON MOSFETs for the TEC controller TEC voltage and current operation monitoring No external sense resistor required Independent TEC heating and cooling current limit settings Programmable maximum TEC voltage 2.0 MHz PWM driver switching frequency External synchronization Two integrated, zero drift, rail-to-rail chopper amplifiers Capable of NTC or RTD thermal sensors 2.50 V reference output with 1% accuracy Temperature lock indicator Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a 24-lead, 4 mm × 4 mm LFCSP AEC-Q100 qualified for automotive applications Figure 1. APPLICATIONS TEC temperature control Optical modules ► Optical fiber amplifiers ► Optical networking systems ► Instruments requiring TEC temperature control ► ► GENERAL DESCRIPTION The ADN88341 is a monolithic TEC controller with an integrated TEC controller. It has a linear power stage, a pulse-width modulation (PWM) power stage, and two zero-drift, rail-to-rail operational amplifiers. The linear controller works with the PWM driver to control the internal power MOSFETs in an H-bridge configuration. By measuring the thermal sensor feedback voltage and using the integrated operational amplifiers as a proportional integral differential (PID) compensator to condition the signal, the ADN8834 drives current through a TEC to settle the temperature of a laser diode or a passive component attached to the TEC module to the programmed target temperature. The ADN8834 supports negative temperature coefficient (NTC) thermistors as well as positive temperature coefficient (PTC) resistive temperature detectors (RTD). The target temperature is set as an analog voltage input either from a digital-to-analog converter (DAC) or from an external resistor divider. that is used to bias a thermistor temperature sensing bridge as well as a voltage divider network to program the maximum TEC current and voltage limits for both the heating and cooling modes. With the zero drift chopper amplifiers, extremely good long-term temperature stability is maintained via an autonomous analog temperature control loop. Table 1. TEC Family Models Device No. MOSFET Thermal Loop Package ADN8831 ADN8833 Discrete Integrated Digital/analog Digital ADN8834 Integrated Digital/analog LFCSP (CP-32-7) WLCSP (CB-25-7), LFCSP (CP-24-15) WLCSP (CB-25-7), LFCSP (CP-24-15) The temperature control loop of the ADN8834 is stabilized by PID compensation utilizing the built in, zero drift chopper amplifiers. The internal 2.50 V reference voltage provides a 1% accurate output 1 Product is covered by U.S. Patent No. 6,486,643. Rev. C DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet ADN8834 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagram......................................1 General Description...............................................1 Specifications........................................................ 3 Absolute Maximum Ratings...................................7 Thermal Resistance........................................... 7 ESD Caution.......................................................7 Pin Configurations and Function Descriptions.......8 Typical Performance Characteristics..................... 9 Detailed Functional Block Diagram..................... 13 Theory of Operation.............................................14 Analog PID Control...........................................15 Digital PID Control............................................15 Powering the Controller....................................15 Enable and Shutdown ..................................... 16 Oscillator Clock Frequency.............................. 16 Temperature Lock Indicator (LFCSP Only)...... 16 Soft Start on Power-Up.................................... 16 TEC Voltage/Current Monitor........................... 17 Maximum TEC Voltage Limit............................ 17 Maximum TEC Current Limit............................ 17 Applications Information...................................... 19 Signal Flow.......................................................19 Thermistor Setup..............................................19 Thermistor Amplifier (Chopper 1)..................... 19 PID Compensation Amplifier (Chopper 2)........ 20 MOSFET Driver Amplifiers............................... 20 PWM Output Filter Requirements.................... 21 Input Capacitor Selection................................. 22 Power Dissipation.............................................22 PCB Layout Guidelines....................................... 24 Block Diagrams and Signal Flow......................24 Guidelines for Reducing Noise and Minimizing Power Loss...................................24 Example PCB Layout Using Two Layers..........25 Outline Dimensions............................................. 27 Ordering Guide.................................................27 Evaluation Boards............................................ 27 Automotive Products........................................ 28 REVISION HISTORY 3/2022—Rev. B to Rev. C Changes to Features Section.......................................................................................................................... 1 Changes to Figure 37, Figure 38, and Figure 39........................................................................................... 21 Updated Outline Dimensions......................................................................................................................... 27 Changes to Ordering Guide........................................................................................................................... 27 Added Automotive Products Section............................................................................................................. 28 analog.com Rev. C | 2 of 28 Data Sheet ADN8834 SPECIFICATIONS VIN = 2.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter POWER SUPPLY Driver Supply Voltage Controller Supply Voltage Supply Current Shutdown Current Undervoltage Lockout (UVLO) UVLO Hysteresis REFERENCE VOLTAGE LINEAR OUTPUT Output Voltage Low High Maximum Source Current Symbol VPVIN VVDD IVDD ISD VUVLO UVLOHYST VVREF PWM not switching EN/SY = AGND or VLIM/SD = AGND VVDD rising VLDR ILDR = 0 A ILDR_SOURCE ILDR_SINK On Resistance P-MOSFET RDS_PL(ON) N-MOSFET RDS_NL(ON) Hiccup Cycle PWM OUTPUT Output Voltage Low High Maximum Source Current ILDR_P_LKG ILDR_N_LKG ALDR ILDR_SH_GNDL ILDR_SH_PVIN(L) THICCUP VSFB Typ Max Unit 3.3 350 2.55 90 2.50 5.5 5.5 5 700 2.65 100 2.525 V V mA µA V mV V 1.5 1.2 V V A A A A 35 44 50 55 31 40 45 50 50 60 65 75 50 55 70 80 mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ 0.1 0.1 40 2.2 −2.2 15 10 10 µA µA V/V A A ms 2.7 2.7 IVREF = 0 mA to 10 mA 2.45 80 2.475 TJ = −40°C to +105°C TJ = −40°C to +125°C TJ = −40°C to +105°C TJ = −40°C to +125°C ILDR = 0.6 A WLCSP, VPVIN = 5.0 V WLCSP, VPVIN = 3.3 V LFCSP, VPVIN = 5.0 V LFCSP, VPVIN = 3.3 V WLCSP, VPVIN = 5.0 V WLCSP, VPVIN = 3.3 V LFCSP, VPVIN = 5.0 V LFCSP, VPVIN = 3.3 V 1.5 1.2 LDR short to PGNDL, enter hiccup LDR short to PVIN, enter hiccup ISFB = 0 A 1.5 1.2 V V V A A A A 65 80 80 95 60 mΩ mΩ mΩ mΩ mΩ 0.06 × VPVIN 0.93 × VPVIN ISW_SOURCE Maximum Sink Current ISW_SINK On Resistance P-MOSFET RDS_PS(ON) N-MOSFET RDS_NS(ON) analog.com Min 0 VPVIN Maximum Sink Current Leakage Current P-MOSFET N-MOSFET Linear Amplifier Gain LDR Short-Circuit Threshold Test Conditions/Comments TJ = −40°C to +105°C TJ = −40°C to +125°C TJ = −40°C to +105°C TJ = −40°C to +125°C ISW = 0.6 A WLCSP, VPVIN = 5.0 V WLCSP, VPVIN = 3.3 V LFCSP, VPVIN = 5.0 V LFCSP, VPVIN = 3.3 V WLCSP, VPVIN = 5.0 V 1.5 1.2 47 60 60 70 40 Rev. C | 3 of 28 Data Sheet ADN8834 SPECIFICATIONS Table 2. Parameter Leakage Current P-MOSFET N-MOSFET SW Node Rise Time1 PWM Duty Cycle2 SFB Input Bias Current PWM OSCILLATOR Internal Oscillator Frequency EN/SY Input Voltage Low High External Synchronization Frequency Synchronization Pulse Duty Cycle EN/SY Rising to PWM Rising Delay EN/SY to PWM Lock Time EN/SY Input Current Pull-Down Current ERROR/COMPENSATION AMPLIFIERS Input Offset Voltage Input Voltage Range Common-Mode Rejection Ratio (CMRR) Output Voltage High Symbol Typ Max Unit WLCSP, VPVIN = 3.3 V LFCSP, VPVIN = 5.0 V LFCSP, VPVIN = 3.3 V 45 45 55 65 75 85 mΩ mΩ mΩ ISW_P_LKG ISW_N_LKG tSW_R DSW ISFB 10 10 CSW = 1 nF 0.1 0.1 1 fOSC EN/SY high VEN/SY_ILOW VEN/SY_IHIGH fSYNC DSYNC tSYNC_PWM tSY_LOCK IEN/SY VOS1 VOS2 VCM1, VCM2 CMRR1, CMRR2 Test Conditions/Comments Min 93 2 2.0 2.15 MHz 0.8 V V MHz % ns Cycles µA µA 6 1.85 2.1 1.85 10 3.25 90 50 Number of SYNC cycles 0.3 0.3 VCM1 = 1.5 V, VOS1 = VIN1P − VIN1N VCM2 = 1.5 V, VOS2 = VIN2P − VIN2N 10 10 0 VCM1, VCM2 = 0.2 V to VVDD − 0.2 V VOH1, VOH2 10 0.5 0.5 100 100 VVDD 120 VVDD − 0.04 Low Power Supply Rejection Ratio (PSRR) Output Current Gain Bandwidth Product1 TEC CURRENT LIMIT ILIM Input Voltage Range Cooling VOL1, VOL2 PSRR1, PSRR2 IOUT1, IOUT2 GBW1, GBW2 VILIMC 1.3 Heating Current-Limit Threshold Cooling Heating ILIM Input Current Heating Cooling Cooling to Heating Current Detection Threshold TEC VOLTAGE LIMIT Voltage Limit Gain VLIM/SD Input Voltage Range1 VLIM/SD Input Current Cooling VILIMH 0.2 analog.com 1 µA µA ns % µA V 10 mV dB mA MHz VVREF − 0.2 1.2 V V 2.02 0.52 V V +0.2 42.5 µA µA mA 120 Sourcing and sinking VOUT1,VOUT2 = 0.5 V to VVDD − 1 V 5 2 VILIMC_TH VILIMH_TH VITEC = 0.5 V VITEC = 2 V 1.98 0.48 IILIMH IILIMC ICOOL_HEAT_TH Sourcing current −0.2 37.5 AVLIM VVLIM (VDRL − VSFB)/VVLIM IILIMC VOUT2 < VVREF/2 µV µV V dB 2.0 0.5 40 40 0.2 2 VVDD/2 V/V V −0.2 +0.2 µA Rev. C | 4 of 28 Data Sheet ADN8834 SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit Heating TEC CURRENT MEASUREMENT (WLCSP) Current Sense Gain IILIMH VOUT2 > VVREF/2, sinking current 8 10 12.2 µA RCS VPVIN = 3.3 V VPVIN = 5 V 700 mA ≤ ILDR ≤ 1.5 A, VPVIN = 3.3 V 800 mA ≤ ILDR ≤ 1.5 A, VPVIN = 5 V VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS V/A V/A % % V Current Measurement Accuracy ILDR_ERROR ITEC Voltage Accuracy VITEC_@_700_mA VITEC_@_−700_mA VITEC_@_800_mA VITEC_@_−800_mA TEC CURRENT MEASUREMENT (LFCSP) Current Sense Gain RCS Current Measurement Accuracy ILDR_ERROR ITEC Voltage Accuracy VITEC_@_700_mA VITEC_@_−700_mA ITEC Voltage Output Range VITEC_@_800_mA VITEC_@_−800_mA VITEC ITEC Bias Voltage Maximum ITEC Output Current TEC VOLTAGE MEASUREMENT Voltage Sense Gain Voltage Measurement Accuracy VITEC IITEC VTEC Output Voltage Range VTEC Bias Voltage Maximum VTEC Output Current TEMPERATURE GOOD (LFCSP ONLY) TMPGD Low Output Voltage TMPGD High Output Voltage TMPGD Output Low Impedance TMPGD Output High Impedance High Threshold Low Threshold INTERNAL SOFT START Soft Start Time VLIM/SD SHUTDOWN VLIM/SD Low Voltage Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold VVTEC VVTEC_B RVTEC analog.com AVTEC VVTEC_@_1_V VTMPGD_LO VTMPGD_HO RTMPGD_LOW RTMPGD_LOW VOUT1_THH VOUT1_THL tSS VPVIN = 3.3 V VPVIN = 5 V 700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V 800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS ITEC = 0 A ILDR = 0 A VLDR – VSFB = 1 V, VVREF/2 + AVTEC × (VLDR – VSFB) VLDR = VSFB No load No load IN2N tied to OUT2, VIN2P = 1.5 V IN2N tied to OUT2, VIN2P = 1.5 V 0.525 0.535 −10 −10 1.597 1.618 +10 +10 1.649 0.846 0.883 0.891 V 1.657 0.783 1.678 0.822 1.718 0.836 V V V/A V/A % % V 0.525 0.525 −15 −15 1.374 1.618 +15 +15 1.861 0.750 0.883 1.015 V 1.419 0.705 0 1.678 0.830 V V V 1.210 −2 1.250 1.921 0.955 VVREF − 0.05 1.285 +2 0.24 1.475 0.25 1.50 0.26 1.525 V/V V 0.005 1.225 −2 1.250 2.625 1.285 +2 V V mA 0.4 V V Ω Ω V V 2.0 1.40 25 50 1.54 1.46 150 VVLIM/SD_THL TSHDN_TH 1.56 ms 0.07 170 V mA V °C Rev. C | 5 of 28 Data Sheet ADN8834 SPECIFICATIONS Table 2. Parameter Thermal Shutdown Hysteresis 1 This specification is guaranteed by design. 2 This specification is guaranteed by characterization. analog.com Symbol TSHDN_HYS Test Conditions/Comments Min Typ 17 Max Unit °C Rev. C | 6 of 28 Data Sheet ADN8834 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating PVIN to PGNDL (WLCSP) PVIN to PGNDS (WLCSP) PVINL to PGNDL (LFCSP) PVINS to PGNDS (LFCSP) LDR to PGNDL (WLCSP) LDR to PGNDL (LFCSP) SW to PGNDS SFB to AGND AGND to PGNDL AGND to PGNDS VLIM/SD to AGND ILIM to AGND VREF to AGND VDD to AGND IN1P to AGND IN1N to AGND OUT1 to AGND IN2P to AGND IN2N to AGND OUT2 to AGND EN/SY to AGND ITEC to AGND VTEC to AGND Maximum Current VREF to AGND OUT1 to AGND OUT2 to AGND ITEC to AGND VTEC to AGND Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) −0.3 V to +5.75 V −0.3 V to +5.75 V −0.3 V to +5.75 V −0.3 V to +5.75 V −0.3 V to VPVIN −0.3 V to VPVINL −0.3 V to +5.75 V −0.3 V to VVDD −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to VVDD −0.3 V to VVDD −0.3 V to +3 V −0.3 V to +5.75 V −0.3 V to VVDD −0.3 V to VVDD −0.3 V to +5.75 V −0.3 V to VVDD −0.3 V to VVDD −0.3 V to +5.75 V −0.3 V to VVDD −0.3 V to +5.75 V −0.3 V to +5.75 V analog.com Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages, and is based on a 4-layer standard JEDEC board. Table 4. Package Type θJA θJC Unit 25-Ball WLCSP 24-Lead LFCSP 48 37 0.6 1.65 °C/W °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 20 mA 50 mA 50 mA 50 mA 50 mA 125°C −65°C to +150°C 260°C Rev. C | 7 of 28 Data Sheet ADN8834 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. LFCSP Pin Configuration (Top View) Figure 2. WLCSP Pin Configuration (Top View) Table 5. Pin Function Descriptions Pin No. WLCSP LFCSP Mnemonic Description A1, A2 N/A1 A3 A4 A5 B1, B2 B3 B4 B5 18, 19 20 21 23 24 17 22 1 3 PGNDL TMPGD OUT1 IN1P IN2P LDR IN1N IN2N VLIM/SD C1, C2 N/A1 N/A1 C3 C4 C5 D1, D2 D3 D4 N/A1 16 15 11 2 4 14 9 8 PVIN PVINL PVINS ITEC OUT2 ILIM SW VTEC EN/SY D5 E1, E2 E3 E4 E5 N/A1 5 12, 13 10 7 6 0 VDD PGNDS SFB AGND VREF EPAD Power Ground of the Linear TEC Controller. Temperature Good Output. Output of the Error Amplifier. Noninverting Input of the Error Amplifier. Noninverting Input of the Compensation Amplifier. Output of the Linear TEC Controller. Inverting Input of the Error Amplifier. Inverting Input of the Compensation Amplifier. Voltage Limit/Shutdown. This pin sets the cooling and heating TEC voltage limits. When this pin is pulled low, the device shuts down. Power Input for the TEC Controller. Power Input for the Linear TEC Driver. Power Input for the PWM TEC Driver. TEC Current Output. Output of the Compensation Amplifier. Current Limit. This pin sets the TEC cooling and heating current limits. Switch Node Output of the PWM TEC Controller. TEC Voltage Output. Enable/Synchronization. Set this pin high to enable the device. An external synchronization clock input can be applied to this pin. Power for the Controller Circuits. Power Ground of the PWM TEC Controller. Feedback of the PWM TEC Controller Output. Signal Ground. 2.5 V Reference Output. Exposed Pad. Solder to the analog ground plane on the board. 1 N/A means not applicable. analog.com Rev. C | 8 of 28 Data Sheet ADN8834 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Figure 4. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Cooling Mode with 2 Ω Load Figure 7. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in Heating Mode Figure 5. Efficiency vs. TEC Current at VIN = 3.3 V and 5 V in Heating Mode with 2 Ω Load Figure 8. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), Without Voltage and Current Limit in Cooling Mode Figure 6. Efficiency vs. TEC Current at VIN = 3.3 V with Different Loads in Cooling Mode Figure 9. Maximum TEC Current vs. Input Voltage at PVIN (VIN = 3.3 V), Without Voltage and Current Limit in Heating Mode analog.com Rev. C | 9 of 28 Data Sheet ADN8834 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10. Thermal Stability over Ambient Temperature at VIN = 3.3 V, VTEMPSET = 1 V Figure 13. VREF Load Regulation Figure 14. ITEC Current Reading Error vs. TEC Current in Cooling Mode Figure 11. Thermal Stability over Ambient Temperature at VIN = 3.3 V, VTEMPSET = 1.5 V Figure 15. ITEC Current Reading Error vs. TEC Current in Heating Mode Figure 12. VREF Error vs. Ambient Temperature analog.com Rev. C | 10 of 28 Data Sheet ADN8834 TYPICAL PERFORMANCE CHARACTERISTICS Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode Figure 19. Zero-Crossing TEC Current Zoom in from Heating to Cooling Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode Figure 20. Zero-Crossing TEC Current Zoom in from Cooling to Heating Figure 18. Cooling to Heating Transition Figure 21. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A analog.com Rev. C | 11 of 28 Data Sheet ADN8834 TYPICAL PERFORMANCE CHARACTERISTICS Figure 22. Typical Enable Waveforms in Heating Mode, VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Figure 23. Typical Switch and Voltage Ripple Waveforms in Cooling Mode VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Figure 24. Typical Switch and Voltage Ripple Waveforms in Heating Mode, VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A analog.com Rev. C | 12 of 28 Data Sheet ADN8834 DETAILED FUNCTIONAL BLOCK DIAGRAM Figure 25. Detailed Functional Block Diagram of the ADN8834 for the WLCSP analog.com Rev. C | 13 of 28 Data Sheet ADN8834 THEORY OF OPERATION The ADN8834 is a single chip TEC controller that sets and stabilizes a TEC temperature. A voltage applied to the input of the ADN8834 corresponds to the temperature setpoint of the target object attached to the TEC. The ADN8834 controls an internal FET H-bridge whereby the direction of the current fed through the TEC can be either positive (for cooling mode), to pump heat away from the object attached to the TEC, or negative (for heating mode), to pump heat into the object attached to the TEC. Temperature is measured with a thermal sensor attached to the target object and the sensed temperature (voltage) is fed back to the ADN8834 to complete a closed thermal control loop of the TEC. For the best overall stability, couple the thermal sensor close to the TEC. In most laser diode modules, a TEC and an NTC thermistor are already mounted in the same package to regulate the laser diode temperature. The TEC is differentially driven in an H-bridge configuration. The ADN8834 drives its internal MOSFET transistors to provide the TEC current. To provide good power efficiency and zero-crossing quality, only one side of the H-bridge uses a PWM driver. Only one inductor and one capacitor are required to filter out the switching frequency. The other side of the H-bridge uses a linear output without requiring any additional circuitry. This proprietary configuration allows the ADN8834 to provide efficiency of >90%. For most applications, a 1 µH inductor, a 10 μF capacitor, and a switching frequency of 2 MHz maintain less than 1% of the worst-case output voltage ripple across a TEC. The maximum voltage across the TEC and the current flowing through the TEC are set by using the VLIM/SD and ILIM pins. The maximum cooling and heating currents can be set independently to allow asymmetric heating and cooling limits. For additional details, see the Maximum TEC Voltage Limit section and the Maximum TEC Current Limit section. Figure 26. Typical Application Circuit with Analog PID Compensation in a Temperature Control Loop analog.com Rev. C | 14 of 28 Data Sheet ADN8834 THEORY OF OPERATION ANALOG PID CONTROL The ADN8834 integrates two self-correcting, auto-zeroing amplifiers (Chopper 1 and Chopper 2). The Chopper 1 amplifier takes a thermal sensor input and converts or regulates the input to a linear voltage output. The OUT1 voltage is proportional to the object temperature. The OUT1 voltage is fed into the compensation amplifier (Chopper 2) and is compared with a temperature setpoint voltage, which creates an error voltage that is proportional to the difference. For autonomous analog temperature control, Chopper 2 can be used to implement a PID network as shown in Figure 27 to set the overall stability and response of the thermal loop. Adjusting the PID network optimizes the step response of the TEC control loop. A compromised settling time and the maximum current ringing become available when this adjustment is done. To adjust the compensation network, see the PID Compensation Amplifier (Chopper 2) section. DIGITAL PID CONTROL The ADN8834 can also be configured for use in a software controlled PID loop. In this scenario, the Chopper 1 amplifier can either be left unused or configured as a thermistor input amplifier connected to an external temperature measurement analog-to-digital converter (ADC). For more information, see the Thermistor Amplifier (Chopper 1) section. If Chopper 1 is left unused, tie IN1N and IN1P to AGND. and short the IN2N and OUT2 pins together. See Figure 27 for an overview of how to configure the ADN8834 external circuitry for digital PID control. POWERING THE CONTROLLER The ADN8834 operates at an input voltage range of 2.7 V to 5.5 V that is applied to the VDD pin and the PVIN pin for the WLCSP (the PVINS pin and PVINL pin for the LFCSP. The VDD pin is the input power for the driver and internal reference. The PVIN input power pins are combined for both the linear and the switching driver. Apply the same input voltage to all power input pins: VDD and PVIN. In some circumstances, an RC low-pass filter can be added optionally between the PVIN for the WLCSP (PVINS and PVINL for the LFCSP) and VDD pins to prevent high frequency noise from entering VDD, as shown in Figure 27. The capacitor and resistor values are typically 10 Ω and 100 nF, respectively. When configuring power supply to the ADN8834, keep in mind that at high current loads, the input voltage may drop substantially due to a voltage drop on the wires between the front-end power supply and the PVIN pin for the WLCSP (PVINS and PVINL for the LFCSP). Leave a proper voltage margin when designing the front-end power supply to maintain the performance. Minimize the trace length from the power supply to the PVIN pin for the WLCSP (PVINS and PVINL for the LFCSP) to help mitigate the voltage drop. The Chopper 2 amplifier is used as a buffer for the external DAC, which controls the temperature setpoint. Connect the DAC to IN2P Figure 27. TEC Controller in a Digital Temperature Control Loop (WLCSP) analog.com Rev. C | 15 of 28 Data Sheet ADN8834 THEORY OF OPERATION ENABLE AND SHUTDOWN To enable the ADN8834, apply a logic high voltage to the EN/SY pin while the voltage at the VLIM/SD pin is above the maximum shutdown threshold of 0.07 V. If either the EN/SY pin voltage is set to logic low or the VLIM/SD voltage is below 0.07 V, the controller goes into an ultralow current state. The current drawn in shutdown mode is 350 µA typically. Most of the current is consumed by the VREF circuit block, which is always on even when the device is disabled or shut down. The device can also be enabled when an external synchronization clock signal is applied to the EN/SY pin, and the voltage at VLIM/SD input is above 0.07 V. Table 6 shows the combinations of the two input signals that are required to enable the ADN8834. by placing an inverter at one of the EN/SY pins, as shown in Figure 29. Table 6. Enable Pin Combinations EN/SY Input VLIM/SD Input Controller >2.1 V Switching between high >2.1 V and low 0.07 V Enabled Enabled No effect1 No effect1 ≤0.07 V Shutdown Shutdown Shutdown 1 No effect means this signal has no effect in shutting down or in enabling the device. OSCILLATOR CLOCK FREQUENCY The ADN8834 has an internal oscillator that generates a 2.0 MHz switching frequency for the PWM output stage. This oscillator is active when the enabled voltage at the EN/SY pin is set to a logic level higher than 2.1 V and the VLIM/SD pin voltage is greater than the shutdown threshold of 0.07 V. External Clock Operation The PWM switching frequency of the ADN8834 can be synchronized to an external clock from 1.85 MHz to 3.25 MHz, applied to the EN/SY input pin as shown on Figure 28. Figure 28. Synchronize to an External Clock Connecting Multiple ADN8834 Devices Multiple ADN8834 devices can be driven from a single master clock signal by connecting the external clock source to the EN/SY pin of each slave device. The input ripple can be greatly reduced by operating the ADN8834 devices 180° out of phase from each other analog.com Figure 29. Multiple ADN8834 Devices Driven from a Master Clock TEMPERATURE LOCK INDICATOR (LFCSP ONLY) The TMPGD outputs logic high when the temperature error amplifier output voltage, VOUT1, reaches the IN2P temperature setpoint (TEMPSET) voltage. The TMPGD has a detection range between 1.46 V and 1.54 V of VOUT1 and hysteresis. The TMPGD function allows direct interfacing either to the microcontrollers or to the supervisory circuitry. SOFT START ON POWER-UP The ADN8834 has an internal soft start circuit that generates a ramp with a typical 150 ms profile to minimize inrush current during power-up. The settling time and the final voltage across the TEC depends on the TEC voltage required by the control voltage of voltage loop. The higher the TEC voltage is, the longer it requires to be built up. When the ADN8834 is first powered up, the linear side discharges the output of any prebias voltage. As soon as the prebias is eliminated, the soft start cycle begins. During the soft start cycle, both the PWM and linear outputs track the internal soft start ramp until they reach midscale, where the control voltage, VC, is equal to the bias voltage, VB. From the midscale voltage, the PWM and linear outputs are then controlled by VC and diverge from each other until the required differential voltage is developed across the TEC or the differential voltage reaches the voltage limit. The voltage developed across the TEC depends on the control point at that moment in time. Figure 30 shows an example of the soft start in cooling mode. Note that, as both the LDR and SFB voltages increase with the soft start ramp and approach VB, the ramp slows down to avoid possible current overshoot at the point where the TEC voltage starts to build up. Rev. C | 16 of 28 Data Sheet ADN8834 THEORY OF OPERATION Figure 30. Soft Start Profile in Cooling Mode TEC VOLTAGE/CURRENT MONITOR The TEC real-time voltage and current are detectable at VTEC and ITEC, respectively. Voltage Monitor VTEC is an analog voltage output pin with a voltage proportional to the actual voltage across the TEC. A center VTEC voltage of 1.25 V corresponds to 0 V across the TEC. Convert the voltage at VTEC and the voltage across the TEC using the following equation: VVTEC = 1.25 V + 0.25 × (VLDR − VSFB) Current Monitor ITEC is an analog voltage output pin with a voltage proportional to the actual current through the TEC. A center ITEC voltage of 1.25 V corresponds to 0 A through the TEC. Convert the voltage at ITEC and the current through the TEC using the following equations: VITEC_COOLING = 1.25 V + ILDR × RCS where the current sense gain (RCS) is 0.525 V/A. VITEC_HEATING = 1.25 V − ILDR × RCS Figure 31. Using a Resistor Divider to Set the TEC Voltage Limit Calculate the cooling and heating limits using the following equations: VVLIM_COOLING = VREF × RV2/(RV1 +RV2) where VREF = 2.5 V. VVLIM_HEATING = VVLIM_COOLING − ISINK_VLIM × RV1||RV2 where ISINK_VLIM = 10 µA. VTEC_MAX_COOLING = VVLIM_COOLING × AVLIM where AVLIM = 2 V/V. VTEC_MAX_HEATING = VVLIM_HEATING × AVLIM MAXIMUM TEC CURRENT LIMIT To protect the TEC, separate maximum TEC current limits in cooling and heating directions are set by applying a voltage combination at the ILIM pin. MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Current Limit The maximum TEC voltage is set by applying a voltage divider at the VLIM/SD pin to protect the TEC. The voltage limiter operates bidirectionally and allows the cooling limit to be different from the heating limit. The internal current sink circuitry connected to ILIM draws a 40 µA current when the ADN8834 drives the TEC in a cooling direction, which allows a high cooling current. Use the following equations to calculate the maximum TEC currents: Using a Resistor Divider to Set the TEC Voltage Limit Separate voltage limits are set using a resistor divider. The internal current sink circuitry connected to VLIM/SD draws a current when the ADN8834 drives the TEC in a heating direction, which lowers the voltage at VLIM/SD. The current sink is not active when the TEC is driven in a cooling direction; therefore, the TEC heating voltage limit is always lower than the cooling voltage limit. VILIM_HEATING = VREF × RC2/(RC1 +RC2) where VREF = 2.5 V. VILIM_COOLING= VILIM_HEATING + ISINK_ILIM × RC1||RC2 where ISINK_ILIM = 40 µA. ITEC_MAX_COOLING = VILIM_COOLING − 1.25 V RCS ITEC_MAX_HEATING = 1.25 V − VILIM_HEATING RCS where RCS = 0.525 V/A. VILIM_HEATING must not exceed 1.2 V and VILIM_COOLING must be more than 1.3 V to leave proper margins between the heating and the cooling modes. analog.com Rev. C | 17 of 28 Data Sheet ADN8834 THEORY OF OPERATION Figure 32. Using a Resistor Divider to Set the TEC Current Limit analog.com Rev. C | 18 of 28 Data Sheet ADN8834 APPLICATIONS INFORMATION Figure 33. Signal Flow Block Diagram SIGNAL FLOW First, the resistance of the thermistor must be known, where The ADN8834 integrates two auto-zero amplifiers, defined as the Chopper 1 amplifier and the Chopper 2 amplifier. Both of the amplifiers can be used as standalone amplifiers; therefore, the implementation of temperature control can vary. Figure 33 shows the signal flow through the ADN8834, and a typical implementation of the temperature control loop using the Chopper 1 amplifier and the Chopper 2 amplifier. RLOW = RTH at TLOW RMID = RTH at TMID ► RHIGH = RTH at THIGH In Figure 33, the Chopper 1 and Chopper 2 amplifiers are configured as the thermistor input amplifier and the PID compensation amplifier, respectively. The thermistor input amplifier gains the thermistor voltage, then outputs to the PID compensation amplifier. The PID compensation amplifier then compensates a loop response over the frequency domain. RTH = RRexp β The output from the compensation loop at OUT2 is fed to the linear MOSFET gate driver. The voltage at LDR is fed with OUT2 into the PWM MOSFET gate driver. Including the internal transistors, the gain of the differential output section is fixed at 5. For details on the output drivers, see the MOSFET Driver Amplifiers section. THERMISTOR SETUP The thermistor has a nonlinear relationship to temperature; near optimal linearity over a specified temperature range can be achieved with the proper value of RX placed in series with the thermistor. analog.com ► ► TLOW and THIGH are the endpoints of the temperature range and TMID is the average. In some cases, with only the β constant available, calculate RTH using the following equation: 1 T − where: RTH is a resistance at T (K). RR is a resistance at TR (K). 1 TR Calculate RX using the following equation: RX = RLOWRMID + RMIDRHIGH − 2RLOWRHIGH RLOW + RHIGH − 2RMID THERMISTOR AMPLIFIER (CHOPPER 1) The Chopper 1 amplifier can be used as a thermistor input amplifier. In Figure 33, the output voltage is a function of the thermistor temperature. The voltage at OUT1 is expressed as: VOUT1 = RFB RTH + RX − RFB R +1 × VREF 2 (1) Rev. C | 19 of 28 Data Sheet ADN8834 APPLICATIONS INFORMATION where: RTH is a thermistor. RX is a compensation resistor. Calculate R using the following equation: R = RX + RTH_@_25°C VOUT1 is centered around VREF/2 at 25°C. An average temperatureto-voltage coefficient is −25 mV/°C at a range of 5°C to 45°C. sensitivity of the control loop, an additional pole is added at a higher frequency than that of the zeros. The bode plot of the magnitude is shown in Figure 36. Use the following equation to calculate the unity-gain crossover frequency of the feed-forward amplifier: f0dB = 1 2πRICI × RFB RTH + RX − RFB R × TECGAIN To ensure stability, the unity-gain crossover frequency must be lower than the thermal time constant of the TEC and thermistor. However, this thermal time constant is sometimes unspecified, making it difficult to characterize. There are many texts written on loop stabilization, and it is beyond the scope of this data sheet to discuss all methods and trade-offs for optimizing compensation networks. VOUT1 is a convenient measure to gauge the thermal instability of the system, which is also known as TEMPOUT. If the thermal loop is in steady state, the TEMPOUT voltage equals the TEMPSET voltage, meaning that the temperature of the controlled object equals the target temperature. Figure 34. VOUT1 vs. Temperature PID COMPENSATION AMPLIFIER (CHOPPER 2) Use the Chopper 2 amplifier as the PID compensation amplifier. The voltage at OUT1 feeds into the PID compensation amplifier. The frequency response of the PID compensation amplifier is dictated by the compensation network. Apply the temperature set voltage at IN2P. In Figure 39, the voltage at OUT2 is calculated using the following equation: VOUT2 = VTEMPSET − Z2 Z1 Figure 35. Implementing a PID Compensation Loop VOUT1 − VTEMPSET where: VTEMPSET is the control voltage input to the IN2P pin. Z1 is the combination of RI, RD, and CD (see Figure 35). Z2 is the combination of RP, CI, and CF (see Figure 35). The user sets the exact compensation network. This network varies from a simple integrator to proportional-integral (PI), PID (proportional-integral-derivative), or any other type of network. The user also determines the type of compensation and component values because they are dependent on the thermal response of the object and the TEC. One method to empirically determine these values is to input a step function to IN2P; thus changing the target temperature, and adjust the compensation network to minimize the settling time of the TEC temperature. A typical compensation network for temperature control of a laser module is a PID loop consisting of a very low frequency pole and two separate zeros at higher frequencies. Figure 35 shows a simple network for implementing PID compensation. To reduce the noise analog.com Figure 36. Bode Plot for PID Compensation MOSFET DRIVER AMPLIFIERS The ADN8834 has two separate MOSFET drivers: a switched output or pulse-width modulated (PWM) amplifier, and a high gain linear amplifier. Each amplifier has a pair of outputs that drive the gates of the internal MOSFETs, which, in turn, drive the TEC as shown in Figure 33. A voltage across the TEC is monitored via the SFB and LDR pins. Although both MOSFET drivers achieve the same result, to provide constant voltage and high current, their operation is different. The exact equations for the two outputs are Rev. C | 20 of 28 Data Sheet ADN8834 APPLICATIONS INFORMATION VLDR = VB − 40(VOUT2 − 1.25 V) VSFB = VLDR + 5(VOUT2 − 1.25 V) where: VOUT2 is the voltage at OUT2. VB is determined by VVDD as VB = 1.5 V for VVDD < 4.0 V VB = 2.5 V for VVDD > 4.0 V The compensation network that receives the temperature set voltage and the thermistor voltage fed by the input amplifier determines the voltage at OUT2. VLDR and VSFB have a low limit of 0 V and an upper limit of VVDD. Figure 37, Figure 38, and Figure 39 show the graphs of these equations. Figure 39. TEC Voltage vs. OUT2 Voltage PWM OUTPUT FILTER REQUIREMENTS A Type 3 compensator internally compensates the PWM amplifier. Because the poles and zeros of the compensator are designed and fixed by assuming the resonance frequency of the output LC tank is 50 kHz, the selection of the inductor and the capacitor must follow this guideline to ensure system stability. Inductor Selection Figure 37. LDR Voltage vs. OUT2 Voltage The inductor selection determines the inductor current ripple and loop dynamic response. Larger inductance results in smaller current ripple and slower transient response as smaller inductance results in the opposite performance. To optimize the performance, the trade-off must be made between transient response speed, efficiency, and component size. Calculate the inductor value with the following equation: L= VSW_OUT × VIN – VSW_OUT VIN × fSW × ΔIL where: VSW_OUT is the PWM amplifier output. fSW is the switching frequency (2 MHz by default). ∆IL is the inductor current ripple. A 1 µH inductor is typically recommended to allow reasonable output capacitor selection while maintaining a low inductor current ripple. If lower inductance is required, a minimum inductor value of 0.68 µH is suggested to ensure that the current ripple is set to a value between 30% and 40% of the maximum load current, which is 1.5 A. Figure 38. SFB Voltage vs. OUT2 Voltage analog.com Except for the inductor value, the equivalent dc resistance (DCR) inherent in the metal conductor is also a critical factor for inductor selection. The DCR accounts for most of the power loss on the inductor by DCR × IOUT2. Using an inductor with high DCR degrades the overall efficiency significantly. In addition, there is a conduct voltage drop across the inductor because of the DCR. When the PWM amplifier is sinking current in cooling mode, this voltage Rev. C | 21 of 28 Data Sheet ADN8834 APPLICATIONS INFORMATION drives the minimum voltage of the amplifier higher than 0.06 × VIN by at least tenth of millivolts. Similarly, the maximum PWM amplifier output voltage is lower than 0.93 × VIN. This voltage drop is proportional to the value of the DCR and it reduces the output voltage range at the TEC. When selecting an inductor, ensure that the saturation current rating is higher than the maximum current peak to prevent saturation. In general, ceramic multilayer inductors are suitable for low current applications due to small size and low DCR. When the noise level is critical, use a shielded ferrite inductor to reduce the electromagnetic interference (EMI). Value Toko 1.0 µH ± 20%, 2.6 A (typical) Taiyo Yuden 1.0 µH ± 20%, 2.2 A (typical) Murata 1.0 µH ± 20%, 2.3 A (typical) Device No. Footprint DFE201612R-H-1R0M 2.0 × 1.6 MAKK2016T1R0M 2.0 × 1.6 LQM2MPN1R0MGH 2.0 × 1.6 The output capacitor selection determines the output voltage ripple, transient response, as well as the loop dynamic response of the PWM amplifier output. Use the following equation to select the capacitor: VSW_OUT × VIN – VSW_OUT 2 × ΔVOUT Table 8. Recommended Capacitors Value Murata 10 µF ± 10%, 10 V Murata 10 µF ± 20%, 10 V Taiyo Yuden 10 µF ± 20%, 10 V Device No. Footprint (mm) ZRB18AD71A106KE01L 1.6 × 0.8 GRM188D71A106MA73 1.6 × 0.8 LMK107BC6106MA-T 1.6 × 0.8 INPUT CAPACITOR SELECTION On the PVIN pin, the amplifiers require an input capacitor to decouple the noise and to provide the transient current to maintain a stable input and output voltage. A 10 µF ceramic capacitor rated at 10 V is the minimum recommended value. Increasing the capacitance reduces the switching ripple that couples into the power supply but increases the capacitor size. Because the current at the input terminal of the PWM amplifier is discontinuous, a capacitor analog.com This section provides guidelines to calculate the power dissipation of the ADN8834. Approximate the total power dissipation in the device by where: PLOSS is the total power dissipation in the ADN8834. PLINEAR is the power dissipation in the linear regulator. The PWM power stage is configured as a buck regulator and its dominant power dissipation (PPWM) includes power switch conduction losses (PCOND), switching losses (PSW), and transition losses (PTRAN). Other sources of power dissipation are usually less significant at the high output currents of the application thermal limit and can be neglected in approximation. Use the following equation to estimate the power dissipation of the buck regulator: PLOSS = PCOND + PSW + PTRAN VIN × 8 × L × fSW Note that the voltage caused by the product of current ripple, ΔIL, and the capacitor equivalent series resistance (ESR) also add up to the total output voltage ripple. Selecting a capacitor with low ESR can increase overall regulation and efficiency performance. Vendor POWER DISSIPATION PWM Regulator Power Dissipation Capacitor Selection C= In most applications, a decoupling capacitor is used in parallel with the input capacitor. The decoupling capacitor is usually a 100 nF ceramic capacitor with very low ESR and ESL, which provides better noise rejection at high frequency bands. PLOSS = PPWM + PLINEAR Table 7. Recommended Inductors Vendor with low effective series inductance (ESL) is preferred to reduce voltage spikes. Conduction Loss (PCOND) The conduction loss consists of two parts: inductor conduction loss (PCOND_L) and power switch conduction loss (PCOND_S). PCOND = PCOND_L + PCOND_S Inductor conduction loss is proportional to the DCR of the output inductor, L. Using an inductor with low DCR enhances the overall efficiency performance. Estimate inductor conduction loss by PCOND_L = DCR × IOUT2 Power switch conduction losses are caused by the flow of the output current through both the high-side and low-side power switches, each of which has its own internal on resistance (RDSON). Use the following equation to estimate the amount of power switch conduction loss: PCOND_S = (RDSON_HS × D + RDSON_LS × (1 − D)) × IOUT2 where: RDSON_HS is the on resistance of the high-side MOSFET. D is the duty cycle (D = VOUT/VIN). RDSON_LS is the on resistance of the low-side MOSFET. Rev. C | 22 of 28 Data Sheet ADN8834 APPLICATIONS INFORMATION Switching Loss (PSW) Switching losses are associated with the current drawn by the controller to turn the power devices on and off at the switching frequency. Each time a power device gate is turned on or off, the controller transfers a charge from the input supply to the gate, and then from the gate to ground. Use the following equation to estimate the switching loss: PSW = (CGATE_HS + CGATE_LS) × VIN2 × fSW where: CGATE_HS is the gate capacitance of the high-side MOSFET. CGATE_LS is the gate capacitance of the low-side MOSFET. fSW is the switching frequency. For the ADN8834, the total of (CGATE_HS + CGATE_LS) is approximately 1 nF. Transition Loss (PTRAN) Transition losses occur because the high-side MOSFET cannot turn on or off instantaneously. During a switch node transition, the MOSFET provides all the inductor current. The source-to-drain voltage of the MOSFET is half the input voltage, resulting in power loss. Transition losses increase with both load and input voltage and occur twice for each switching cycle. Use the following equation to estimate the transition loss: PTRAN = 0.5 × VIN × IOUT × (tR + tF) × fSW where: tR is the rise time of the switch node. tF is the fall time of the switch node. For the ADN8834, tR and tF are both approximately 1 ns. Linear Regulator Power Dissipation The power dissipation of the linear regulator is given by the following equation: PLINEAR = [(VIN − VOUT) × IOUT] + (VIN × IGND) where: VIN and VOUT are the input and output voltages of the linear regulator. IOUT is the load current of the linear regulator. IGND is the ground current of the linear regulator. Power dissipation due to the ground current is generally small and can be ignored for the purposes of this calculation. analog.com Rev. C | 23 of 28 Data Sheet ADN8834 PCB LAYOUT GUIDELINES Figure 40. System Block Diagram BLOCK DIAGRAMS AND SIGNAL FLOW The ADN8834 integrates analog signal conditioning blocks, a load protection block, and a TEC controller power stage all in a single IC. To achieve the best possible circuit performance, attention must be paid to keep noise of the power stage from contaminating the sensitive analog conditioning and protection circuits. In addition, the layout of the power stage must be performed such that the IR losses are minimized to obtain the best possible electrical efficiency. The system block diagram of the ADN8834 is shown in Figure 40. GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS Each printed circuit board (PCB) layout is unique because of the physical constraints defined by the mechanical aspects of a given design. In addition, several other circuits work in conjunction with the TEC controller; these circuits have their own layout requirements, so there are always compromises that must be made for a given system. However, to minimize noise and keep power losses to a minimum during the PCB layout process, observe the following guidelines. General PCB Layout Guidelines Switching noise can interfere with other signals in the system; therefore, the switching signal traces must be placed away from the power stage to minimize the effect. If possible, place the ground plate between the small signal layer and power stage layer as a shield. AGND to PGNDS using only a single point connection. This ensures that the switching currents of the power stage do not flow into the sensitive AGND node. PWM Power Stage Layout Guidelines The PWM power stage consists of a MOSFET pair that forms a switch mode output that switches current from PVIN to the load via an LC filter. The ripple voltage on the PVIN pin is caused by the discontinuous current switched by the PWM side MOSFETs. This rapid switching causes voltage ripple to form at the PVIN input, which must be filtered using a bypass capacitor. Place a 10 µF capacitor as close as possible to the PVIN pin to connect PVIN to PGNDS. Because the 10 µF capacitor is sometimes bulky and has higher ESR and ESL, a 100 nF decoupling capacitor is usually used in parallel with it, placed between PVIN and PGNDS. Because the decoupling is part of the pulsating current loop, which carries high di/dt signals, the traces must be short and wide to minimize the parasitic inductance. As a result, this capacitor is usually placed on the same side of the board as the ADN8834 to ensure short connections. If the layout requires that a 10 µF capacitor be on the opposite side of the PCB, use multiple vias to reduce via impedance. The layout around the SW node is also critical because it switches between PVIN and ground rapidly, which makes this node a strong EMI source. Keep the copper area that connects the SW node to the inductor small to minimize parasitic capacitance between the SW node and other signal traces. This helps minimize noise on the SW node due to excessive charge injection. However, in high current applications, the copper area may be increased reasonably to provide heat sink and to sustain high current flow. Supply voltage drop on traces is also an important consideration because it determines the voltage headroom of the TEC controller at high currents. For example, if the supply voltage from the frontend system is 3.3 V, and the voltage drop on the traces is 0.5 V, PVIN sees only 2.8 V, which limits the maximum voltage of the linear regulator as well as the maximum voltage across the TEC. To mitigate the voltage waste on traces and impedance interconnection, place the ADN8834 and the input decoupling components close to the supply voltage terminal. This placement not only improves the system efficiency but also provides better regulation performance at the output. The linear power stage consists of a MOSFET pair that forms a linear amplifier, which operates in linear mode for very low output currents, and changes to fully enhanced mode for greater output currents. To prevent noise signal from circulating through ground plates, reference all of the sensitive analog signals to AGND and connect Because the linear power stage does not switch currents rapidly like the PWM power stage, it does not generate noise currents. analog.com Connect the ground side of the capacitor in the LC filter as close as possible to PGNDS to minimize the ESL in the return path. Linear Power Stage Layout Guidelines Rev. C | 24 of 28 Data Sheet ADN8834 PCB LAYOUT GUIDELINES However, the linear power stage still requires a minimum amount of bypass capacitance to decouple its input. Place a 100 nF capacitor that connects from PVIN to PGNDL as close as possible to the PVIN pin. Placing the Thermistor Amplifier and PID Components The thermistor conditioning and PID compensation amplifiers work with very small signals and have gain; therefore, attention must be paid when placing the external components with these circuits. Place the thermistor conditioning and PID circuit components close to each other near the inputs of Chopper 1 and Chopper 2. Avoid crossing paths between the amplifier circuits and the power stages to prevent noise pickup on the sensitive nodes. Always reference the thermistor to AGND to have the cleanest connection to the amplifier input and to avoid any noise or offset build up. EXAMPLE PCB LAYOUT USING TWO LAYERS Figure 41, Figure 42, and Figure 43 show an example ADN8834 PCB layout that uses two layers. This layout example achieves a small solution size of approximately 20 mm2 with all of the conditioning circuitry and PID included. Using more layers and blinds via allows the solution size to be reduced even further because more of the discrete components can relocate to the bottom side of the PCB. Figure 41. Example PCB Layout Using Two Layers (Top and Bottom Layers) analog.com Rev. C | 25 of 28 Data Sheet ADN8834 PCB LAYOUT GUIDELINES Figure 42. Example PCB Layout Using Two Layers (Top Layer Only) Figure 43. Example PCB Layout Using Two Layers (Bottom Layer Only) analog.com Rev. C | 26 of 28 Data Sheet ADN8834 OUTLINE DIMENSIONS Figure 44. 25-Ball Wafer Level Chip Scale Package [WLCSP] (CB-25-7) Dimensions shown in millimeters Figure 45. 24-Lead Lead-frame Chip Scale Package [LFCSP] 4 mm × 4 mm and 0.75 mm Package Height (CP-24-15) Dimensions shown in millimeters Updated: February 22, 2022 ORDERING GUIDE Model1, 2 Temperature Range Package Description Packing Quantity Package Option ADN8834ACBZ-R7 ADN8834ACPZ-R2 ADN8834ACPZ-R7 ADN8834WACPZ-R7 -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 25-Ball WLCSP (2.54mm x 2.54mm) 24-Lead LFCSP (4mm x 4mm w/ EP) 24-Lead LFCSP (4mm x 4mm w/ EP) 24-Lead LFCSP (4mm x 4mm w/ EP) Reel, 1500 Reel, 250 Reel, 1500 Reel, 1500 CB-25-7 CP-24-15 CP-24-15 CP-24-15 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. EVALUATION BOARDS Model1 Description ADN8834CB-EVALZ ADN8834CP-EVALZ ADN8834MB‑EVALZ 25-Ball WLCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit 24-Lead LFCSP Evaluation Board: ±1.5 A TEC Current Limit, 3 V TEC Voltage Limit Mother Evaluation Board of the ADN8834 for PID Tuning 1 Z = RoHS Compliant Part. analog.com Rev. C | 27 of 28 Data Sheet ADN8834 OUTLINE DIMENSIONS AUTOMOTIVE PRODUCTS The ADN8834W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©2015-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. C | 28 of 28