4 A, Low VIN, Low Noise,
CMOS Linear Regulator
ADP1764
Data Sheet
TYPICAL APPLICATION CIRCUITS
APPLICATIONS
Regulation to noise sensitive applications such as radio
frequency (RF) transceivers, analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) circuits,
phase-locked loops (PLLs), voltage controlled oscillators
(VCOs) and clocking integrated circuits
Field-programmable gate array (FPGA) and digital signal
processor (DSP) supplies
Medical and healthcare
Industrial and instrumentation
ADP1764
VIN = 1.8V
CIN
22µF
RPULL-UP
100kΩ
PG
VIN
VOUT
EN
PG
VADJ
REFCAP
VREG
CREG
1µF
CREF
1µF
GND
ADP1764
VIN = 1.8V
CIN
22µF
RPULL-UP
100kΩ
PG
VIN
VOUT
SENSE
EN
PG
SS
CSS
10nF
COUT
22µF
ON
OFF
VADJ
REFCAP
VREG
CREG
1µF
VOUT = 1.5V
GND
CREF
1µF
RADJ
10kΩ
Figure 2. Adjustable Output Operation
The ADP1764 is available in fixed output voltages ranging from
0.55 V to 1.5 V. The output voltage (VOUT) of the adjustable
output model can be set from 0.5 V to 1.5 V through an
external resistor connected between VADJ and ground.
The ADP1764 has an externally programmable soft start time by
connecting a capacitor to the SS pin. Short-circuit and thermal
overload protection circuits prevent damage in adverse conditions.
The ADP1764 is available in a small, 16-lead LFCSP package for
the smallest footprint solution to meet a variety of applications.
Table 1. Related Devices
The ADP1764 is a low noise, low dropout (LDO) linear
regulator. It is designed to operate from a single input supply
with an input voltage as low as 1.10 V without the requirement
of an external bias supply to increase efficiency and provide up
to 4 A of output current (IOUT).
ADP1761
Input
Voltage
1.10 V to 1.98 V
Maximum
Current
1A
ADP1762
1.10 V to 1.98 V
2A
ADP1763
1.10 V to 1.98 V
3A
The low 47 mV typical dropout voltage at a 4 A load allows the
ADP1764 to operate with a small headroom while maintaining
regulation and providing better efficiency.
ADP1740/
ADP1741
ADP1752/
ADP1753
ADP1754/
ADP1755
1.6 V to 3.6 V
2A
1.6 V to 3.6 V
0.8 A
1.6 V to 3.6 V
1.2 A
Model
Rev. A
ON
OFF
Figure 1. Fixed Output Operation
GENERAL DESCRIPTION
The ADP1764 is optimized for stable operation with small 22 μF
ceramic output capacitors. The ADP1764 delivers optimal transient
performance with minimal printed circuit board (PCB) area.
COUT
22µF
SENSE
SS
CSS
10nF
VOUT = 1.5V
14939-002
4 A maximum output current
Low input voltage supply range
VIN = 1.10 V to 1.98 V, no external bias supply required
Fixed output voltage range (VOUT_FIXED): 0.55 V to 1.5 V
Adjustable output voltage range (VOUT_ADJ): 0.5 V to 1.5 V
Ultralow noise: 2 μV rms, 100 Hz to 100 kHz
Noise spectral density: 5 nV/√Hz at 10 kHz; 4 nV/√Hz at 100 kHz
Low dropout voltage: 47 mV typical at 4 A load
Operating supply current: 5 mA typical at no load
±1.5% fixed output voltage accuracy over line, load, and
temperature
Excellent power supply rejection ratio (PSRR) performance
69 dB typical at 10 kHz at 4 A load
46 dB typical at 100 kHz at 4 A load
Excellent load/line transient response
Soft start to reduce inrush current
Optimized for small 22 μF ceramic capacitors
Current-limit and thermal overload protection
Power-good indicator
Precision enable
16-lead, 3 mm × 3 mm LFCSP package
14939-001
FEATURES
Fixed/
Adjustable
Fixed/
adjustable
Fixed/
adjustable
Fixed/
adjustable
Fixed/
adjustable
Fixed/
adjustable
Fixed/
adjustable
Package
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
16-lead
LFCSP
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©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADP1764
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start Function ..................................................................... 13
Applications ....................................................................................... 1
Adjustable Output Voltage ........................................................ 14
General Description ......................................................................... 1
Enable Feature ............................................................................ 14
Typical Application Circuits............................................................ 1
Power-Good (PG) Feature ........................................................ 14
Revision History ............................................................................... 2
Applications Information .............................................................. 15
Specifications..................................................................................... 3
Capacitor Selection .................................................................... 15
Input and Output Capacitor: Recommended Specifications.. 4
Undervoltage Lockout ............................................................... 16
Absolute Maximum Ratings............................................................ 5
Current-Limit and Thermal Overload Protection ................. 16
Thermal Data ................................................................................ 5
Thermal Resistance/Parameter................................................... 5
Paralleling ADP1764 Devices for High Current
Applications ................................................................................ 16
ESD Caution .................................................................................. 5
Thermal Considerations............................................................ 17
Pin Configuration and Function Descriptions ............................. 6
PCB Layout Considerations ...................................................... 19
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 20
Theory of Operation ...................................................................... 13
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/2017—Rev. 0 to Rev. A
Changes to Thermal Data and Table 5........................................... 5
Changed Thermal Resistance Section to Thermal
Resistance/Parameter Section ......................................................... 5
Changes to Typical Performance Characteristics Section........... 7
Changes to Table 7, Figure 50 through Figure 52, and Figure 50
Caption through Figure 52 Caption ............................................. 17
Changes to Figure 53 though Figure 55 and Figure 53 Caption
through Figure 55 Caption ............................................................ 18
1/2017—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
ADP1764
SPECIFICATIONS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, IOUT = 100 mA, CIN = 22 µF, COUT = 22 µF, CREF = 1 µF, CREG = 1 µF, TA = 25°C, and
minimum and maximum limits at TJ = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE SUPPLY RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND_SD
NOISE 1
Output Noise
Noise Spectral Density
POWER SUPPLY REJECTION RATIO1
OUTNOISE
OUTNSD
PSRR
OUTPUT VOLTAGE RANGE
Fixed
Adjustable
FIXED OUTPUT VOLTAGE ACCURACY
VOUT_FIXED
VOUT_ADJ
VOUT
ADJUSTABLE PIN CURRENT
IADJ
ADJUSTABLE OUTPUT VOLTAGE
GAIN FACTOR
AD
REGULATION
Line
∆VOUT/∆VIN
Load 2
DROPOUT VOLTAGE 3
∆VOUT/∆IOUT
VDROPOUT
START-UP TIME1, 4
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD1, 5
tSTARTUP
IREF
ILIMIT
Test Conditions/Comments
TJ = −40°C to +125°C
IOUT = 0 µA
IOUT = 100 mA
IOUT = 4 A
EN = GND
TJ = −40°C to +85°C
TJ = 85°C to 125°C
Min
1.10
5
5
11
4
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, to
1.98 V
IOUT = 100 mA to 4 A
IOUT = 3 A, VOUT = 1.2 V
IOUT = 4 A, VOUT = 1.2 V
CSS = 10 nF, VOUT = 1 V
1.1 V ≤ VIN ≤ 1.98 V
Rev. A | Page 3 of 20
Max
1.98
17
18
23
200
900
10 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
100 Hz to 100 kHz, VIN = 1.1 V, VOUT = 0.9 V
10 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
100 Hz to 100 kHz, VIN = 1.5 V, VOUT = 1.3 V
10 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
100 Hz to 100 kHz, VIN = 1.7 V, VOUT = 1.5 V
VOUT = 0.55 V to 1.5 V, IOUT = 100 mA
At 10 kHz
At 100 kHz
IOUT = 4 A, modulated VIN
10 kHz, VOUT = 1.3 V, VIN = 1.7 V
100 kHz, VOUT = 1.3 V, VIN = 1.7 V
1 MHz, VOUT = 1.3 V, VIN = 1.7 V
10 kHz, VOUT = 0.9 V, VIN = 1.1 V
100 kHz, VOUT = 0.9 V, VIN = 1.1 V
1 MHz, VOUT = 0.9 V, VIN = 1.1 V
TJ = 25°C
IOUT = 100 mA, TA = 25°C
100 mA < IOUT < 4 A, TJ = 0°C to 85°C
100 mA < IOUT < 4 A, TJ = 0°C to 125°C
TJ = 25°C, VADJ = 0.5 V
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, to
1.98 V
VADJ = 0.5 V; VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever
is greater, to 1.98 V
TJ = 25°C
TJ = −40°C to +125°C
Typ
0.55
0.5
−0.75
−1.2
−1.5
49.5
49.0
Unit
V
mA
mA
mA
µA
µA
µA
3
2
3
2
3
2
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
5
4
nV/√Hz
nV/√Hz
69
46
35
67
45
36
dB
dB
dB
dB
dB
dB
50.0
50.0
1.5
1.5
+0.75
+1.2
+1.5
50.7
51.2
V
V
%
%
%
µA
µA
2.99
2.96
3.02
−0.10
+0.10
%/V
0.3
65
75
%/A
mV
mV
ms
µA
A
8
5.5
0.15
40
47
1
10
6.5
12
7.0
ADP1764
Parameter
THERMAL SHUTDOWN1
Threshold
Hysteresis
POWER-GOOD (PG) OUTPUT
Output Voltage Threshold
Falling
Rising
Output Voltage Low
Leakage Current
Delay
PRECISION EN INPUT
Logic Input Voltage
High
Low
Input Logic Hysteresis
Input Leakage Current
Input Delay Time
UNDERVOLTAGE LOCKOUT
Input Voltage
Rising
Falling
Hysteresis
Data Sheet
Symbol
Test Conditions/Comments
TSSD
TSSD_HYS
TJ rising
152
16
°C
°C
PGFALL
PGRISE
PGLOW
IPG_LKG
PGDELAY
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V
1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA
1.1 V ≤ VIN ≤ 1.98 V
ENRISING to PGRISING
1.1 V ≤ VIN ≤ 1.98 V
−6.2
−3.5
%
%
V
µA
ms
ENHIGH
ENLOW
ENHYS
IEN_LKG
tEN_DLY
UVLO
UVLORISE
UVLOFALL
UVLOHYS
Min
0.01
0.75
0.60
0.55
VEN = VIN or GND
From EN rising from 0 V to VIN to 0.1 × VOUT
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Typ
0.85
Max
0.3
1
0.65
0.60
50
0.01
100
0.69
0.65
1.00
0.93
70
1.06
1
Unit
V
V
mV
µA
µs
V
V
mV
Guaranteed by characterization but not production tested.
Based on an endpoint calculation using 100 mA and 4 A loads.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4
Start-up time is the time from the rising edge of VEN to VOUT being at 90% of its nominal value.
5
Current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output voltage
is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
1
2
3
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
CAPACITANCE 1
Input
Output
Regulator
Reference
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
CIN, COUT
CREG
CREF
1
Symbol
CIN
COUT
CREG
CREF
RESR
Test Conditions/Comments
TA = −40°C to +125°C
Min
Typ
14.5
14.5
0.7
0.07
22
22
1
1
Max
Unit
µF
µF
µF
µF
TA = −40°C to +125°C
0.2
0.5
2
Ω
Ω
Ω
The minimum input and output capacitance must be >14.5 µF over the full range of the operating conditions. Consider the full range of the operating conditions in
the application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 20
Data Sheet
ADP1764
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to GND
EN to GND
VOUT to GND
SENSE to GND
VREG to GND
REFCAP to GND
VADJ to GND
SS to GND
PG to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +2.16 V
−0.3 V to +3.96 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +3.96 V
−65°C to +150°C
−40°C to +125°C
125°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP1764 can be damaged when the junction
temperature limits are exceeded. The use of appropriate thermal
management techniques is recommended to ensure that the
maximum junction temperature does not exceed the limits shown
in Table 4.
Use the following equation to calculate the junction temperature
(TJ) from the board temperature (TBOARD) or package top
temperature (TTOP):
ΨJB of the package is based on modeling and calculation using a
4-layer board. JESD51-12, Guidelines for Reporting and Using
Electronic Package Thermal Information, states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications.
THERMAL RESISTANCE/PARAMETER
Values shown in Table 5 are calculated in compliance with
JEDEC standards for thermal reporting. θJA is the natural
convection junction to ambient thermal resistance measured in a
one cubic foot sealed enclosure. θJC is the junction to case thermal
resistance. θJB is the junction to board thermal resistance. ΨJB is
the junction to board thermal characterization parameter. ΨJT is
the junction to top thermal characterization parameter.
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. Thermal
resistance/parameter values may vary, depending on the PCB
material, layout, and environmental conditions.
Table 5. Thermal Resistance/Parameter
Package
Type
CP-16-48 1
1
θJA
40.65
θJC
7.47
θJB
17.38
ΨJB
12.9
ΨJT
0.85
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board for θJA, θJC, θJB, ΨJB, ΨJT, and a JEDEC 1S0P thermal test board for θJC
with four thermal vias. See JEDEC JESD51-12.
ESD CAUTION
TJ = TBOARD + (PD × ΨJB)
TJ = TTOP + (PD × ΨJT)
ΨJB is the junction to board thermal characterization parameter
and ΨJT is the junction to top thermal characterization
parameter with units of °C/W.
Rev. A | Page 5 of 20
ADP1764
Data Sheet
13 SENSE
14 SS
16 EN
15 PG
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN 1
12 VOUT
VIN 2
ADP1764
11 VOUT
VIN 3
TOP VIEW
(Not to Scale)
10 VOUT
9
NOTES
1. THE EXPOSED PAD IS ELECTRICALLY
CONNECTED TO GND. IT IS RECOMMENDED
THAT THIS PAD BE CONNECTED TO A GROUND
PLANE ON THE PCB. THE EXPOSED PAD IS
ON THE BOTTOM OF THE PACKAGE.
14939-003
GND 7
VOUT
VADJ 8
VREG 6
REFCAP 5
VIN 4
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1 to 4
Mnemonic
VIN
5
REFCAP
6
VREG
7
8
GND
VADJ
9 to 12
VOUT
13
SENSE
14
15
SS
PG
16
EN
EP
Description
Regulator Input Supply. Bypass VIN to GND with a 22 µF or greater capacitor. Note that all four VIN pins must be
connected to the source supply.
Reference Filter Capacitor. Connect a 1 µF capacitor from the REFCAP pin to ground. Do not connect a load from
this pin to ground.
Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 1 µF or greater capacitor. Do not connect a
load from this pin to ground.
Ground.
Adjustable Voltage Pin for the Adjustable Output Option. Connect a 10 kΩ external resistor between the VADJ pin
and ground to set the output voltage to 1.5 V. For the fixed output option, leave this pin floating.
Regulated Output Voltage. Bypass VOUT to GND with a 22 µF or greater capacitor. Note that all four VOUT pins
must be connected to the load.
Sense Input. The SENSE pin measures the actual output voltage at the load and feeds it to the error amplifier.
Connect SENSE as close to the load as possible to minimize the effect of IR drop between VOUT and the load.
Soft Start Pin. A capacitor connected to this pin determines the soft start time.
Power-Good Output. This open-drain output requires an external pull-up resistor. If the device is in shutdown
mode, current-limit mode, or thermal shutdown mode, or if the VOUT voltage falls below 90% of the nominal
output voltage, the PG pin immediately transitions to low.
Enable Input. Drive the EN pin high to turn on the regulator. Drive the EN pin low to turn off the regulator. For
automatic startup, connect the EN pin to the VIN pin.
Exposed Pad. The exposed pad is electrically connected to GND. It is recommended that this pad be connected to
a ground plane on the PCB. The exposed pad is on the bottom of the package.
Rev. A | Page 6 of 20
Data Sheet
ADP1764
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.2 V or VIN = 1.1 V, whichever is greater, VOUT = 1.3 V, IOUT = 100 mA, TA = 25°C, unless otherwise noted.
24
1.312
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
1.310
1.308
20
18
1.306
16
1.304
14
IGND (mA)
VOUT (V)
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
22
1.302
1.300
12
10
8
1.298
6
1.296
4
1.294
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 4. Output Voltage (VOUT) vs. Temperature, VOUT = 1.3 V
14939-007
2
14939-004
1.292
–40
Figure 7. Ground Current (IGND) vs. Temperature, VOUT = 1.3 V
24
1.304
22
1.303
20
18
1.302
16
IGND (mA)
VOUT (V)
1.301
1.300
14
12
10
1.299
8
6
1.298
4
1.297
10
LOAD CURRENT (A)
0
0.1
14939-005
1
Figure 5. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.3 V
1.303
10
Figure 8. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.3 V
1.305
1.304
1
LOAD CURRENT (A)
14939-008
2
1.296
0.1
24
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
22
20
18
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
16
IGND (mA)
1.301
14
12
10
1.300
8
1.299
6
4
1.298
1.58
1.66
1.74
1.82
1.90
1.98
VIN (V)
Figure 6. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 1.3 V
0
1.5
1.6
1.7
1.8
1.9
2.0
VIN (V)
Figure 9. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 1.3 V
Rev. A | Page 7 of 20
14939-009
2
1.297
1.50
14939-006
VOUT (V)
1.302
ADP1764
Data Sheet
0.906
24
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
0.904
0.902
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
20
18
0.900
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
16
0.898
IGND (mA)
VOUT (V)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
22
0.896
0.894
14
12
10
8
0.892
6
0.890
4
0.888
–20
0
20
40
60
80
100
120
140
0
–40
TEMPERATURE (°C)
0.904
24
0.903
22
40
60
80
100
120
140
20
0.901
18
0.900
16
IGND (mA)
0.899
0.898
0.897
0.896
0.895
14
12
10
8
0.894
6
0.893
4
0.892
1
10
LOAD CURRENT (A)
0
0.1
14939-011
0.890
0.1
1
10
LOAD CURRENT (A)
Figure 11. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 0.9 V
14939-014
2
0.891
Figure 14. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 0.9 V
24
0.904
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
0.903
0.902
0.901
0.900
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
22
20
18
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
1.3
1.4
16
IGND (mA)
0.899
0.898
0.897
0.896
0.895
14
12
10
8
0.894
6
0.893
4
0.892
2
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
VIN (V)
14939-012
0.891
Figure 12. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = 0.9 V
0
1.1
1.2
1.5
1.6
1.7
1.8
1.9
2.0
VIN (V)
Figure 15. Ground Current (IGND) vs. Input Voltage (VIN), VOUT = 0.9 V
Rev. A | Page 8 of 20
14939-015
VOUT (V)
20
Figure 13. Ground Current (IGND) vs. Temperature, VOUT = 0.9 V
0.902
VOUT (V)
0
TEMPERATURE (°C)
Figure 10. Output Voltage (VOUT) vs. Temperature, VOUT = 0.9 V
0.890
1.1
–20
14939-013
2
14939-010
0.886
–40
Data Sheet
ADP1764
1000
24
VIN = 1.10V
VIN = 1.30V
VIN = 1.50V
VIN = 1.70V
VIN = 1.90V
VIN = 1.98V
100
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
22
20
18
IGND_SD (µA)
16
14
IGND (mA)
10
1
12
10
8
6
0.1
4
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0
1.1
14939-016
–20
1.2
1.3
1.4
1.5
VIN (V)
Figure 16. Shutdown Current (IGND_SD) vs. Temperature at
Various Input Voltages (VIN), VOUT = 0.9 V
14939-019
2
0.01
–40
Figure 19. Ground Current (IGND) vs. Input Voltage (VIN) in Dropout,
VOUT = 1.3 V
0.10
T
0.09
SLEW RATE = 4A/µs
0.08
IOUT
VDROPOUT (V)
0.07
3
0.06
0.05
VOUT
0.04
1
0.03
0.02
1
10
LOAD CURRENT (A)
Figure 17. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 1.3 V
B
W
B
W
CH1 50mV
CH3 2A
5GS/s
4.00µs
CH3
1M points T
11.04000µs
2.44A
14939-020
0
0.1
14939-017
0.01
Figure 20. Load Transient Response, COUT = 22 μF, VIN = 1.8 V, VOUT = 1.3 V
1.32
T
1.31
1.30
SLEW RATE = 4A/µs
1.29
IOUT
3
1.27
1.26
VOUT
1.25
1
1.23
ILOAD = 0.1A
ILOAD = 1.0A
ILOAD = 2.0A
ILOAD = 3.0A
ILOAD = 4.0A
1.22
1.21
1.20
1.25
1.30
1.35
1.40
1.45
1.50
VIN (V)
Figure 18. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
VOUT = 1.3 V
CH1 50mV
CH3 2A
B
W
B
W
5GS/s
4.00µs
CH3
1M points T
11.16000µs
2.44A
14939-021
1.24
14939-018
VOUT (V)
1.28
Figure 21. Load Transient Response, COUT = 47 μF, VIN = 1.8 V, VOUT = 1.3 V
Rev. A | Page 9 of 20
ADP1764
Data Sheet
T
T
SLEW RATE = 4A/µs
VIN
IOUT
3
VOUT
2
1
1
5GS/s
4.00µs
CH3
1M points T
11.24000µs
2.48A
CH1 2mV
CH3 500mV
Figure 22. Load Transient Response, COUT = 22 μF, VIN = 1.4 V, VOUT = 0.9 V
B
W
B
W
5GS/s
4.00µs
CH2
1M points T
9.020000µs
1.53V
14939-025
B
W
B
W
CH1 50mV
CH3 2A
14939-022
VOUT
Figure 25. Line Transient Response, Load Current = 4 A,
VIN = 1.3 V to 1.7 V Step, VOUT = 0.9 V
4.0
T
3.5
10Hz TO 100kHz
100Hz TO 100kHz
SLEW RATE = 4A/µs
OUTPUT NOISE (µV rms)
IOUT
3
VOUT
1
3.0
2.5
2.0
1.5
1.0
B
W
B
W
5GS/s
4.00µs
CH3
1M points T
11.32000µs
2.48A
0
0.1
1
10
LOAD CURRENT (A)
14939-026
CH1 50mV
CH3 2A
14939-023
0.5
Figure 26. Output Noise vs. Load Current (ILOAD)
Figure 23. Load Transient Response, COUT = 47 μF, VIN = 1.4 V, VOUT = 0.9 V
4.0
T
3.5
OUTPUT NOISE (µV rms)
VIN
2
1
10Hz TO 100kHz
100Hz TO 100kHz
3.0
2.5
2.0
1.5
1.0
VOUT
B
W
B
W
5GSPS
4.00µs
CH2
1M POINTS T
9.020000µs
1.86V
0
0.5
14939-024
CH1 2mV
CH2 500mV
0.7
0.9
1.1
1.3
OUTPUT VOLTAGE (V)
Figure 27. Output Noise vs. Output Voltage (VOUT)
Figure 24. Line Transient Response, Load Current = 4 A,
VIN = 1.6 V to 1.98 V Step, VOUT = 1.3 V
Rev. A | Page 10 of 20
1.5
14939-027
0.5
Data Sheet
ADP1764
1k
1k
100
10
1
0.1
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
100
10
1
0.1
10
Figure 28. Noise Spectral Density vs. Frequency
at Various Output Voltages (VOUT), 0.1 Hz to 1 MHz
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 31. Noise Spectral Density vs. Frequency
at Various Load Current (IOUT), 10 Hz to 10 MHz
1k
–10
VOUT = 0.5V
VOUT = 0.9V
VOUT = 1.3V
VOUT = 1.5V
VIN = 1.5V
VIN = 1.6V
VIN = 1.7V
VIN = 1.8V
VIN = 1.9V
–20
–30
100
–40
PSRR (dB)
NOISE SPECTRAL DENSITY (nV/√Hz)
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
14939-031
10k
NOISE SPECTRAL DENSITY (nV√Hz)
VOUT = 0.5V
VOUT = 0.9V
VOUT = 1.3V
VOUT = 1.5V
14939-028
NOISE SPECTRAL DENSITY (nV/√Hz)
100k
10
–50
–60
–70
–80
1
–90
100
1k
100k
10k
1M
10M
FREQUENCY (Hz)
–110
14939-029
0.1
10
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages (VIN), VOUT = 1.3 V, Load = 4 A
Figure 29. Noise Spectral Density vs. Frequency
at Various Output Voltages (VOUT), 10 Hz to 10 MHz
–10
100k
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
10k
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–20
–30
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
–40
PSRR (dB)
1k
100
10
–50
–60
–70
–80
–90
1
0.1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 30. Noise Spectral Density vs. Frequency
at Various Load Current (IOUT), 0.1 Hz to 1 MHz
–110
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 33. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads (ILOAD), VOUT = 1.3 V, VIN = 1.7 V
Rev. A | Page 11 of 20
14939-033
–100
14939-030
NOISE SPECTRAL DENSITY (nV/√Hz)
10
14939-032
–100
ADP1764
Data Sheet
–10
–10
VIN = 1.1V
VIN = 1.2V
VIN = 1.3V
VIN = 1.4V
VIN = 1.5V
–20
–30
–40
–40
–50
–50
PSRR (dB)
–60
–70
–70
–80
–80
–90
–90
–100
–100
1
1k
100
10
10k
100k
1M
10M
FREQUENCY (Hz)
–110
0.2
14939-034
–110
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Input Voltages (VIN), VOUT = 0.9 V, Load = 4 A
FREQUENCY = 10Hz
FREQUENCY = 100Hz
FREQUENCY = 1kHz
FREQUENCY = 10kHz
FREQUENCY = 100kHz
FREQUENCY = 1MHz
FREQUENCY = 10MHz
0.3
0.4
0.5
0.6
HEADROOM (V)
Figure 36. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Various Frequencies, VOUT = 0.9 V, Load = 4 A
–10
0
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–20
–30
= 0.1A
= 1.0A
= 2.0A
= 3.0A
= 4.0A
–10
–20
–30
–40
–40
PSRR (dB)
–50
–60
–70
–50
–60
–70
–80
–80
–90
–90
–100
–100
–110
–110
0.2
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency at
Various Loads (ILOAD), VOUT = 0.9 V, VIN = 1.3 V
14939-035
PSRR (dB)
–60
FREQUENCY =
FREQUENCY =
FREQUENCY =
FREQUENCY =
FREQUENCY =
FREQUENCY =
FREQUENCY =
0.3
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
0.4
HEADROOM (V)
0.5
0.6
14939-037
PSRR (dB)
–30
14939-036
–20
Figure 37. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage at
Various Frequencies, VOUT = 1.3 V, Load = 4 A
Rev. A | Page 12 of 20
Data Sheet
ADP1764
THEORY OF OPERATION
The ADP1764 is a low dropout (LDO), low noise linear regulator
that uses an advanced proprietary architecture to achieve high
efficiency regulation. It also provides high PSRR and excellent line
and load transient response using a small 22 µF ceramic output
capacitor. The device operates from a 1.10 V to 1.98 V input rail
to provide up to 4 A of output current. The supply current in
shutdown mode is less than 4 µA.
ADP1764
tSTARTUP_ADJ = tDELAY + VADJ × (CSS/ISS)
PG
REFERENCE,
BIAS
GND
SENSE
For applications that require a controlled startup, the ADP1764
provides a programmable soft start function. The programmable
soft start is useful for reducing inrush current upon startup and
for providing voltage sequencing. To implement soft start, connect
a small ceramic capacitor from SS to GND. At startup, a 10 µA
current source charges this capacitor. The voltage at SS limits
the ADP1764 start-up output voltage, providing a smooth ramp up
to the nominal output voltage. To calculate the start-up time for
the fixed output (tSTARTUP_FIXED) and adjustable (tSTARTUP_ADJ) output,
use the following equations:
tSTARTUP_FIXED = tDELAY + VREF × (CSS/ISS)
(1)
SS BLOCK
SS
REFCAP
Figure 38. Functional Block Diagram, Fixed Output
where:
tDELAY is a fixed delay of 100 µs.
VREF is a 0.5 V internal reference for the fixed output model option.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (10 µA).
VADJ is the voltage at the VADJ pin, equal to RADJ × IADJ.
ADP1764
VIN
VREG
VOUT
INTERNAL
BIAS SUPPLY
SHORT-CIRCUIT,
THERMAL
PROTECTION
SENSE
VOUT (V)
IADJ
EN
VADJ
PG
SS BLOCK
SS
REFCAP
14939-039
GND
The ADP1764 is available in output voltages ranging from 0.55 V
to 1.5 V for a fixed output. Contact your local Analog Devices, Inc.,
sales representative for other fixed voltage options. The adjustable
output option can be set from 0.5 V to 1.5 V. The ADP1764 uses
the EN pin to enable and disable the VOUT pin under normal
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–1.0
EN
CSS = 0nF
CSS = 10nF
CSS = 22nF
–0.5
0
0.5
1.0
1.5
2.0
2.5
TIME (ms)
Figure 40. Fixed VOUT Ramp-Up with External Soft Start Capacitor (VOUT, EN) vs. Time
VOUT (V)
Figure 39. Functional Block Diagram, Adjustable Output
Internally, the ADP1764 consists of a reference, an error amplifier,
and a pass device. The output current is delivered via the pass
device, which is controlled by the error amplifier, forming a
negative feedback system that ideally drives the feedback voltage
to equal the reference voltage. If the feedback voltage is lower than
the reference voltage, the negative feedback drives more current,
increasing the output voltage. If the feedback voltage is higher than
the reference voltage, the negative feedback drives less current,
decreasing the output voltage.
(2)
14939-040
EN
INTERNAL
BIAS SUPPLY
14939-038
VREG
VOUT
SHORT-CIRCUIT,
THERMAL
PROTECTION
SOFT START FUNCTION
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–1.0
EN
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
–0.5
0
0.5
1.0
TIME (ms)
=
=
=
=
=
=
1.5
0.5V;
0.5V;
0.5V;
1.5V;
1.5V;
1.5V;
CSS
CSS
CSS
CSS
CSS
CSS
2.0
=
=
=
=
=
=
0nF
10nF
22nF
0nF
10nF
22nF
2.5
14939-041
VIN
operating conditions. When EN is high, VOUT turns on. When
EN is low, VOUT turns off. For automatic startup, tie EN to VIN.
Figure 41. Adjustable VOUT Ramp-Up with External Soft Start Capacitor
(VOUT, EN) vs. Time
Rev. A | Page 13 of 20
ADP1764
Data Sheet
ADJUSTABLE OUTPUT VOLTAGE
POWER-GOOD (PG) FEATURE
The output voltage of the ADP1764 can be set over a 0.5 V to
1.5 V range. Connect a resistor (RADJ) from the VADJ pin to
ground to set the output voltage. To calculate the output voltage
(VOUT), use the following equation:
The ADP1764 provides a power-good pin (PG) to indicate the
status of the output. This open-drain output requires an external
pull-up resistor that can be connected to VIN or VOUT. If the
device is in shutdown mode, current-limit mode, or thermal
shutdown, or if it falls below 90% of the nominal output voltage,
PG immediately transitions low. During soft start, the rising
threshold of the power-good signal is 96.5% of the nominal
output voltage.
VOUT = AD × (RADJ × IADJ)
(3)
where:
AD is the gain factor with a typical value of 2.99 between the
VADJ pin and VOUT pin.
IADJ is the 50 μA constant current out of the VADJ pin.
ENABLE FEATURE
The ADP1764 uses the EN pin to enable and disable the VOUT
pins under normal operating conditions. As shown in Figure 42,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
T
The open-drain output is held low when the ADP1764 has
sufficient input voltage to turn on the internal PG transistor. An
optional soft start delay can be detected. The PG transistor is
terminated via a pull-up resistor to VIN or VOUT.
Power-good accuracy is 93.8% of the nominal regulator output
voltage when this voltage is rising, with a 96.5% trip point when
this voltage is falling.
Regulator input voltage brownouts or glitches trigger a power
no good if VOUT falls below 93.8%.
A normal power-down triggers a power good when VOUT is
at 96.5%.
VOUT
T
EN
EN
1
VOUT
2
1
100kSPS
10.00ms
CH1
10k POINTS T
121.9200ms
1.21V
PG
Figure 42. Typical EN Pin Operation
2
As shown in Figure 43, the EN pin has built in hysteresis. This
hysteresis prevents on/off oscillations that can occur due to noise
on the EN pin as it passes through the threshold points.
1.4
CH1 1V CH3 1V
CH2 1V
5.00MSPS 200µs
CH2
10k POINTS T
–70.00000µs
1.30V
14939-044
CH1 200mV
CH2 200mV
14939-042
3
Figure 44. VOUT vs. Typical PG Voltage Behavior, VIN Rising (VOUT = 1.3 V)
1.3
T
1.2
EN
1.1
1.0
1
0.8
VOUT
0.7
0.6
0.5
3
0.4
0.2
0.1
0
0.59
0.60
0.61
0.62
0.63
0.64
EN THRESHOLD (V)
2
0.65
Figure 43. Output Voltage vs. EN Threshold, VOUT = 1.3 V
0.66
PG
CH1 1V BW
CH2 1V BW
CH3 1V BW
200µs
500MSPS
1M POINTS
T
CH2
700mV
–5.20000µs
14939-045
TA = +125°C
TA = +85°C
TA = +25°C
TA = 0°C
TA = –40°C
0.3
14939-043
VOUT (V)
0.9
Figure 45. VOUT vs. Typical PG Voltage Behavior, VIN Falling (VOUT = 1.3 V)
Rev. A | Page 14 of 20
Data Sheet
ADP1764
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Input and Output Capacitor Properties
Output Capacitor
Use any good quality ceramic capacitors with the ADP1764 as
long as they meet the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
are not recommended, due to their poor temperature and dc bias
characteristics.
The ADP1764 is designed for operation with small, space-saving
ceramic capacitors, but it can function with most commonly used
capacitors as long as care is taken with the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 22 μF
capacitance with an ESR of 50 mΩ or less is recommended to
ensure the stability of the ADP1764. Transient response to changes
in load current is also affected by output capacitance. Using a larger
value of output capacitance improves the transient response of the
ADP1764 to large changes in load current. Figure 46 and Figure 47
show the transient responses for output capacitance values of 22 μF
and 47 μF, respectively.
T
SLEW RATE = 5A/µs
IOUT
3
Figure 48 shows the capacitance vs. dc bias voltage characteristics
of a C2012X5R1A226K125AB, 0805 case, 22 μF, 10 V, X5R
capacitor. The voltage stability of a capacitor is strongly influenced
by the capacitor size and voltage rating. In general, a capacitor
in a larger package or with a higher voltage rating exhibits
improved stability. The temperature variation of the X5R
dielectric is about ±15% over the −55°C to +85°C temperature
range and is not a function of package size or voltage rating.
25
VOUT
5GSPS
4.00µs
CH3
1M POINTS T
11.04000µs
2.44A
14939-046
B
W
B
W
CH1 50mV
CH3 2A
CAPACITANCE, NOMINAL (µF)
1
Figure 46. Output Transient Response, COUT = 22 μF, VOUT = 1.3 V
20
15
10
5
0
SLEW RATE = 5A/µs
IOUT
0
2
4
6
8
DC BIAS VOLTAGE (V)
3
10
14939-048
T
Figure 48. Capacitance vs. DC Bias Voltage
Use Equation 4 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage.
VOUT
1
CEFF = COUT × (1 − TEMPCO) × (1 − TOL)
B
W
B
W
5GSPS
4.00µs
CH3
1M POINTS T
11.16000µs
2.44A
where:
CEFF is the effective capacitance at the operating voltage.
COUT is the output capacitor.
TEMPCO is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
14939-047
CH1 50mV
CH3 2A
(4)
Figure 47. Output Transient Response, COUT = 47 μF, VOUT = 1.3 V
Input Bypass Capacitor
Connecting a 22 μF capacitor from the VIN pin to the GND pin
to the ground plane reduces the circuit sensitivity to the PCB
layout, especially when long input traces or high source impedances are encountered. If an output capacitance greater than 22 μF
is required, it is recommended to increase the input capacitor to
match it.
In this example, the worst case temperature coefficient
(TEMPCO) over −55°C to +125°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and COUT = 19.48 μF at 1.0 V, as shown in Figure 48.
Substituting these values in Equation 4 yields
Rev. A | Page 15 of 20
CEFF = 19.48 μF × (1 − 0.15) × (1 − 0.1) = 14.9 μF
ADP1764
Data Sheet
output and reducing the output current to zero. As the junction
temperature cools and drops below 136°C, the output turns on
and conducts 6.5 A into the short, again causing the junction
temperature to rise above 152°C. This thermal oscillation between
136°C and 152°C causes a current oscillation between 6.5 A and
0 A that continues as long as the short remains at the output.
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP1764, it is imperative
to evaluate the effects of dc bias, temperature, and tolerances on
the behavior of the capacitors for each application.
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that junction temperatures do not exceed 125°C.
UNDERVOLTAGE LOCKOUT
The ADP1764 has an internal undervoltage lockout (UVLO)
circuit that disables all inputs and the output when the input
voltage is less than approximately 1.06 V. The UVLO ensures that
the ADP1764 inputs and output behave in a predictable manner
during power-up.
PARALLELING ADP1764 DEVICES FOR HIGH
CURRENT APPLICATIONS
In applications where high output current is required while
maintaining low noise and high PSRR performance, connect two
ADP1764 devices in parallel to handle loads up to 7 A.
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1764 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP1764 is designed to reach the current limit
when the output load reaches 6.5 A (typical). When the output
load exceeds 6.5 A, the output voltage is reduced to maintain a
constant current limit.
When paralleling the ADP1764, the two outputs must be of the
same voltage setting to maintain good current sharing between
the two LDOs. To improve current sharing accuracy, add identical
ballast resistors (RBALLAST) at the output of each regulator, as shown
in Figure 49. Note that large ballast resistors improve current
sharing accuracy, but degrade the load regulation performance
and increase the losses along the power line. Therefore, it is best
to keep the ballast resistors at a minimum. In addition, tie the
VADJ, SS, and REFCAP pins of the LDO regulators together to
minimize error between the two outputs.
Thermal overload protection is included that limits the junction
temperature to a maximum of 152°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation) when the junction temperature begins to rise above 152°C,
the output turns off, reducing the output current to zero. When the
junction temperature drops below 136°C (typical), the output turns
on again, and the output current is restored to its nominal value.
Use Equation 5 to calculate the output of the two paralleled
ADP1764 LDOs.
VOUT = 2 × AD × (RADJ × IADJ)
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP1764 reaches the current limit so that
only 6.5 A is conducted into the short. If self-heating of the
junction becomes great enough to cause its temperature to rise
above 152°C, thermal shutdown activates, turning off the
where:
AD is the gain factor with a typical value of 2.99 between the
VADJ pin and VOUT pin.
IADJ is the 50 μA constant current out of the VADJ pin.
ADP1764
CIN
22µF
VIN
VOUT
SS
VADJ
REFCAP
VREG
CREG
1µF
GND
ADP1764
CIN
22µF
VIN
VOUT
RADJ
4.02kΩ
CREF
1µF
RBALLAST = 5mΩ
COUT
22µF
SENSE
EN
PG
SS
VADJ
VREG
CREG
1µF
ENABLE
EN
PG
VOUT = 1.2V/7A
COUT
22µF
SENSE
RPULLUP
100kΩ
CSS
1nF
RBALLAST = 5mΩ
REFCAP
GND
CREF
1µF
14939-049
VIN = 1.5V
Figure 49. Two ADP1764 Devices Connected in Parallel to Achieve Higher Current Output
Rev. A | Page 16 of 20
(5)
Data Sheet
ADP1764
To guarantee reliable operation, the junction temperature of the
ADP1764 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include board temperature, power
dissipation in the power device, and thermal characterization
parameter between the junction and board (ΨJB). The ΨJB
parameter is dependent on the package assembly compounds and
the PCB copper area. Table 7 shows the typical ΨJB values for the
16-lead LFCSP package for various PCB copper areas.
Table 7. Typical Non-JEDEC ΨJB Values
ΨJB (°C/W) at 2W
71.05
18.9
13.45
13.15
60
40
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VIN – VOUT (V)
Figure 50. 1000 mm2 of PCB Copper, TB = 25°C
140
TJ MAX
120
0.1A
1.0A
2.0A
3.0A
4.0A
100
80
60
40
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VIN – VOUT (V)
14939-051
0
Figure 51. 500 mm2 of PCB Copper, TB = 25°C
140
(6)
TJ MAX
(7)
JUNCTION TEMPERATURE (°C)
120
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
0.1A
1.0A
2.0A
3.0A
4.0A
100
80
60
40
20
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TB + (((VIN − VOUT) × ILOAD) × ΨJB)
80
20
where:
TB is the board temperature.
PD is the power dissipation in the die, given by
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND)
100
20
Calculate the junction temperatures of the ADP1764 by
TJ = TB + (PD × ΨJB)
0.1A
1.0A
2.0A
3.0A
4.0A
(8)
As shown in Equation 8, for a given board temperature, inputto-output voltage differential, and continuous load current,
a minimum copper area requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C.
Rev. A | Page 17 of 20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
VIN – VOUT (V)
Figure 52. 100 mm2 of PCB Copper, TB = 25°C
1.4
14939-052
PCB Copper Area (mm )
25
100
500
1000
2
TJ MAX
120
14939-050
When the junction temperature exceeds 152°C, the regulator
enters thermal shutdown. The regulator recovers only after the
junction temperature decreases below 136°C to prevent any
permanent damage. Therefore, thermal analysis for the chosen
application is important to guarantee reliable performance over
all conditions. The junction temperature of the die is the sum of
the board temperature and the temperature rise of the package
due to the power dissipation, as shown in Equation 6.
140
JUNCTION TEMPERATURE (°C)
In applications with a low input-to-output voltage differential,
the ADP1764 does not dissipate much heat. However, in
applications with high ambient temperature and/or high input
voltage, the heat dissipated in the package may become large
enough to cause the junction temperature of the die to exceed
the maximum junction temperature of 125°C.
Figure 50 to Figure 55 show the junction temperature calculations
for the different board temperatures, power dissipation, and
areas of the PCB copper.
JUNCTION TEMPERATURE (°C)
THERMAL CONSIDERATIONS
ADP1764
Data Sheet
140
140
TJ MAX
TJ MAX
120
100
80
60
40
100
80
60
40
0.1A
1.0A
2.0A
3.0A
4.0A
20
20
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VIN – VOUT (V)
0
14939-053
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VIN – VOUT (V)
Figure 53. 1000 mm2 of PCB Copper, TB = 50°C, LFCSP
14939-055
0.1A
1.0A
2.0A
3.0A
4.0A
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
120
Figure 55. 100 mm2 of PCB Copper, TB = 50°C, LFCSP
140
TJ MAX
0.1A
1.0A
2.0A
3.0A
4.0A
100
TADP1764 = 109°C
80
60
40
20
0
0.2
0.4
0.6
0.8
1.0
1.2
VIN – VOUT (V)
Figure 54. 500 mm2 of PCB Copper, TB = 50°C, LFCSP
1.4
14939-056
TB = 91.7°C
0
14939-054
JUNCTION TEMPERATURE (°C)
120
Figure 56. Thermal Image of the ADP1764 Evaluation Board at ILOAD = 4 A,
VIN = 1.5 V, VOUT = 1.3 V, TB = 91.7°C
Figure 56 shows a thermal image of the ADP1764 evaluation
board operating at a 4 A current load. The total power dissipation
on the ADP1764 is 744 mW, which makes the temperature on
the surface of the device higher by 17.3°C than the temperature
of the evaluation board.
Rev. A | Page 18 of 20
Data Sheet
ADP1764
PCB LAYOUT CONSIDERATIONS
14939-058
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Place the soft start capacitor (CSS) as
close as possible to the SS pin. Place the reference capacitor
(CREF) and regulator capacitor (CREG) as close as possible to the
REFCAP pin and VREG pin, respectively. Connect the load as
close as possible to the VOUT and SENSE pins.
14939-057
Figure 58. Typical Board Layout, Top Side
14939-059
Figure 57. Evaluation Board
Figure 59. Typical Board Layout, Bottom Side
Rev. A | Page 19 of 20
ADP1764
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.50
BSC
13
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
1
12
1.80
1.70 SQ
1.60
EXPOSED
PAD
9
*0.40
TOP VIEW
0.80
0.75
0.70
4
5
8
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PKG-005014
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
0.35
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4
WITH EXCEPTION TO LEAD LENGHT.
10-04-2016-A
PIN 1
INDICATOR
0.28
0.23
0.18
Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADP1764ACPZ0.85-R7
ADP1764ACPZ-0.9-R7
ADP1764ACPZ0.95-R7
ADP1764ACPZ-1.0-R7
ADP1764ACPZ-1.1-R7
ADP1764ACPZ-1.2-R7
ADP1764ACPZ1.25-R7
ADP1764ACPZ-1.3-R7
ADP1764ACPZ-1.5-R7
ADP1764ACPZ-R7
ADP1764-1.0-EVALZ
ADP1764-ADJ-EVALZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
0.85
0.9
0.95
1.0
1.1
1.2
1.25
1.3
1.5
Adjustable
1.0
1.0
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
Evaluation Board (Fixed)
Evaluation Board (Adjustable)
Package Option
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
CP-16-48
Branding
LUW
LUX
LUY
LUZ
LV0
LV1
LV2
LV3
LV4
LUV
Z = RoHS Compliant Part.
For additional voltage options, contact a local Analog Devices sales or distribution representative. Additional voltage options are available by special order and
include the following: 0.55 V, 0.6 V, 0.65 V, 0.7 V, 0.75 V, 0.8 V, 1.05 V, 1.15 V, 1.35 V, 1.4 V, and 1.45 V.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14939-0-6/17(A)
Rev. A | Page 20 of 20
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