FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 2.3 V to 6.5 V
Fixed and adjustable output voltage options
Fixed output voltage pair options: 1.2 V/1.8 V, 1.2 V/3.3 V,
1.8 V/3.3 V
Adjustable output voltage range: 0.8 V to 6 V
Minimum guaranteed continuous output current: 800 mA
Up to 94% efficiency
Low quiescent current of 15 µA for both channels in power
saving mode (PSM)
Low shutdown current: 0.1 μA (typical)
100% duty cycle for low dropout operation
SYNC pin switching frequency options
2 MHz fixed pulse-width modulation (PWM) mode
2 MHz PSM/PWM automatic transitioning mode
External clock synchronization from 1.5 MHz to 2.5 MHz
Enable input with precision thresholds for each output
180° phase shifted PWM outputs for minimum VIN ripple
Current-limit and thermal shutdown (TSD) protection
Quick output discharge (QOD)
10-lead, 3 mm × 3 mm × 0.75 mm LFCSP package
APPLICATIONS
Portable and battery-powered equipment
Automatic meter readers (WSN)
Point of sales and transaction processing instruments
Mobile phones
Digital cameras and audio devices
Medical instruments
Medium format display tablets and pads
GENERAL DESCRIPTION
The ADP2230 includes two high efficiency, low quiescent current,
800 mA, step-down, dc-to-dc converters in a small, 10-lead,
3 mm × 3 mm, LFCSP package. The total solution requires only
five tiny external components. When the ADP2230 is used with
three 0603 capacitors and two 2 mm × 2 mm inductors, the
total solution size is about 48 mm2, resulting in the smallest
footprint solution to meet a variety of portable applications.
The ADP2230 buck regulator uses a proprietary, high speed,
current mode, constant frequency, PWM control scheme for
excellent stability and transient response. The buck outputs
operate out of phase to reduce the input current ripple.
To ensure the longest battery life in portable applications, the
ADP2230 has a power saving variable frequency mode that
reduces the switching frequency under light load conditions.
Rev. A
ADP2230
VIN
CIN
10µF
2
VIN1
9
VIN2
L1
2.2µH
VOUT1
SW1 1
COUT1
10µF
FB1 3
ON
OFF
ON
OFF
4
EN1
7
EN2
L2
2.2µH
SW2 10
VOUT2
PWM
6
SYNC
FB2 8
AGND
PGND
(EPAD)
5
11
PSM/PWM
COUT2
10µF
10705-001
Data Sheet
Dual 2 MHz, 800 mA, Synchronous, Low
Quiescent Current Buck Regulator
ADP2230
Figure 1. Fixed Output Voltage Typical Application Circuit
During logic controlled shutdown, the input is disconnected
from the output, and it draws less than 0.1 μA from the input
source. The ADP2230 operates from input voltages from 2.3 V
to 6.5 V, allowing the use of multiple alkaline, NiMH, or lithium
cells and other standard power sources.
The ADP2230 offers multiple options for setting the operating
frequency. To maximize light load efficiency, the ADP2230 can
operate at a reduced switching frequency in PSM and switch
automatically to PWM as the load increases. The ADP2230 can
be forced to operate at 2 MHz in PWM only mode when noise
considerations are more important than efficiency. The
ADP2230 can also be synchronized with a 1.5 MHz to 2.5 MHz
external clock via the SYNC pin. When using the external clock
synchronization control, both buck outputs operate in phase
with the applied clock signal.
The ADP2230 includes an internal power switch, synchronous
rectifier, and compensation to minimize external part count
and maximize efficiency. Other key protection features include
undervoltage lockout to prevent deep battery discharge, internal
soft start to prevent input current overshoot at startup, and an
integrated, switched resistor, QOD function that automatically
discharges the output when the device is disabled. Short-circuit
protection and thermal overload protection circuits prevent
damage in adverse conditions.
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ADP2230
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Applications ....................................................................................... 1
Overview ..................................................................................... 12
General Description ......................................................................... 1
Operating Conditions ................................................................ 12
Typical Application Circuit ............................................................. 1
SYNC Pin Control Schemes...................................................... 13
Revision History ............................................................................... 2
Features Descriptions ................................................................ 13
Specifications..................................................................................... 3
Applications Information .............................................................. 15
Recommended Component Specifications ............................... 4
Setting the Output Voltage ........................................................ 15
Absolute Maximum Ratings ............................................................ 5
Selecting the Inductor ................................................................ 15
Thermal Data ................................................................................ 5
Selecting the Input and Output Capacitors ............................ 16
Thermal Resistance ...................................................................... 5
PCB Layout Considerations .......................................................... 17
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 18
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 18
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
11/14—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 18
10/14—Revision 0: Initial Version
Rev. A | Page 2 of 18
Data Sheet
ADP2230
SPECIFICATIONS
VIN = VENx = 5.0 V, VOUT = 3.3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter
SUPPLY
Input Voltage Range
Quiescent Current
Standby Current
Shutdown Current
Undervoltage Lockout
VIN Rising Threshold
VIN Falling Threshold
Soft Start Time
FIXED AND ADJUSTABLE OUTPUT
Load Regulation PWM
Line Regulation
PSM Rising Threshold
PSM Hysteresis
FIXED OUTPUT VOLTAGE
Fixed VOUT Accuracy
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 3.3 V
Fixed VOUT FB Pin Current1
ADJUSTABLE OUTPUT VOLTAGE
Feedback Voltage
Adjustable VOUT Range
Adjustable VOUT FB Pin Current
SWITCHING CHARACERISTICS
On Resistance
P-Channel
N-Channel
Current Limit
P-Channel
N-Channel
P-Channel Leakage Current
Minimum On Time
SWx Node Discharge Resistor
Phase Shift Between SW1 and SW2
OSCILLATOR
Fixed PWM Oscillator Frequency
External Clock Synchronization
Range
External Clock Duty Cycle Range
SYNC Pin
High Threshold
Low Threshold
Leakage Current
Symbol
VIN
IQ
ISD
Test Conditions/Comments
Min
Typ
2.3
VSYNC = GND, no load, device not switching
One channel enabled
Both channels enabled
VENx = 1 V
VENx = GND, TJ = −40°C to +85°C
8
15
55
0.1
1.96
185
tSS
2.23
2.05
270
Max
Unit
6.5
V
23
34
μA
μA
μA
μA
2.5
2.28
395
V
V
μs
∆VOUT/∆IOUT
IOUT = 0 mA to 800 mA
0.1
%/A
∆VOUT/∆VIN
VIN = 2.3 V to 6.5 V, VOUT = 1.2 V, IOUT = 500 mA
VIN = 5 V, VOUT = 3.3 V
0.1
230
25
%/V
mA
mA
VIN = 5 V, no load
VOUT_1.2V
VOUT_1.8V
VOUT_3.3V
IFB_FIXED
VFB
VOUT_ADJ
IFB_ADJ
VFB = 1.2 V
1.168
1.748
3.202
1.1
1.2
1.8
3.3
2.0
1.220
1.851
3.363
2.8
V
V
V
μA
0.774
0.8
0.8
10
0.818
6
150
V
V
nA
230
180
325
275
mΩ
mΩ
930
300
1300
500
3
35
250
180
1475
625
2
65
340
mA
mA
μA
ns
Ω
Degrees
1600
1.5
2000
2300
2.5
kHz
MHz
85
%
0.4
1
V
V
μA
VFB = 0.8 V
VIN = 5 V, ISW = 400 mA
RDSON_P
RDSON_N
VIN = 5 V, VSW = GND, TJ = −40°C to +85°C
tON-MIN
VSYNC = GND or VSYNC = VIN (no external clock)
fSW_FIXED
fSW_RANGE
VSYNC = GND or VSYNC = VIN
20
1.3
VSYNC = GND or VSYNC = VIN
Rev. A | Page 3 of 18
0.01
ADP2230
Parameter
ENABLE STANDBY LOGIC LEVELS
High
Low
Hysteresis
ENABLE PRECISION LOGIC LEVELS
Operating Maximum
EN1
EN2
High
Low
ENx Pin Leakage Current
THERMAL SHUTDOWN
Threshold
Hysteresis
1
Data Sheet
Symbol
Test Conditions/Comments
2.3 V ≤ VIN ≤ 6.5 V
Min
Typ
Max
Unit
0.4
V
V
mV
1.15
200
2.3 V ≤ VIN ≤ 6.5 V
VEN1
VEN2
ENx pin rising
ENx pin falling
VENx = VIN or GND
1.2
1.1
0.01
1
TJ rising
5.5
6.5
1.255
1
V
V
V
V
µA
°C
°C
150
15
The fixed VOUT feedback pin current is the internal feedback voltage, 0.8 V (typical), divided by the bottom feedback resistor, typically 400 kΩ.
RECOMMENDED COMPONENT SPECIFICATIONS
TA = −40°C to +125°C
Table 2.
Parameter
INPUT AND OUTPUT CAPACITANCE2
Capacitor Equivalent Series Resistance (ESR)
INDUCTANCE
Symbol
CIN, COUT
ESRCIN, ESRCOUT
L
Min1
7
0.001
1.5
Typ
10
Max
0.01
2.2
Unit
µF
Ω
μH
Minimum values represent the minimum effective values of the components under the application operating conditions. To achieve the minimum effective values,
components specified as 2.2 µH inductors and 10 µF capacitors are recommended.
2
Ensure that the minimum input and output capacitance is greater than 7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended.
1
Rev. A | Page 4 of 18
Data Sheet
ADP2230
ABSOLUTE MAXIMUM RATINGS
The specified values of θJA are based on a 4-layer, 4 in. × 3 in.
circuit board. See JEDEC JESD51-7, High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages, for
detailed information on board construction. For more
information, see AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
Table 3.
Parameter
VINx, FBx, EN2, SYNC to AGND, PGND
EN1
SWx to AGND, PGND
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to +6 V
−0.3 V to VINx
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL DATA
Exceeding the junction temperature (TJ) limit can cause damage
to the ADP2230. Monitoring ambient temperature does not
guarantee that TJ is within the specified temperature limits. The
maximum ambient temperature may require derating in
applications with high power dissipation and poor thermal
resistance.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation of the device, and the
junction-to-ambient thermal resistance (θJA) of the package.
Maximum TJ is calculated from the ambient temperature (TA)
and power dissipation (PD) using the formula
TJ = TA + (PD × θJA)
(1)
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12,
Guidelines for Reporting and Using Electronic Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the
component power flowing through multiple thermal paths
rather than a single path as in junction-to-board thermal
resistance (θJB). Therefore, ΨJB thermal paths include convection
from the top of the package as well as radiation from the
package, factors that make ΨJB more useful in real-world
applications. Maximum TJ is calculated from the board
temperature (TB) and PD using the formula
TJ = TB + (PD × ΨJB)
(2)
For more information regarding ΨJB, see JESD51-12 and
JESD51-8, Integrated Circuit Thermal Test Method
Environmental Conditions—Junction-to-Board.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is,
a device soldered in a circuit board for surface-mount packages.
θJC is a parameter for surface-mount packages with top mounted
heat sinks.
Table 4. Thermal Resistance
Package Type
10-Lead, 3 mm × 3mm LFCSP
ESD CAUTION
θJA of the package is based on modeling and calculation using a
4-layer board. θJA is highly dependent on the application and
board layout. In applications where high maximum power
dissipation exists, close attention to thermal board design is
required. The value of θJA can vary, depending on PCB material,
layout, and environmental conditions.
Rev. A | Page 5 of 18
θJA
44.6
θJC
5.45
Unit
°C/W
ADP2230
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SW1 1
FB1 3
ADP2230
TOP VIEW
EN1 4
AGND 5
11
PGND
9
VIN2
8
FB2
7
EN2
6
SYNC
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF
THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS
ELECTRICALLY CONNECTED TO PGND
INSIDE THE PACKAGE. THE EXPOSED
PAD MUST BE CONNECTED TO THE
GROUND PLANE ON THE BOARD FOR
PROPER OPERATION.
10705-002
10 SW2
VIN1 2
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
SW1
VIN1
FB1
EN1
AGND
SYNC
7
8
9
10
11
EN2
FB2
VIN2
SW2
EPAD
Description
Connection from MOSFET Power Switches to the Inductor for Buck 1.
Analog and Power Voltage Input for Buck 1. Connect VIN1 to VIN2.
Output Voltage Feedback for Buck 1.
Precision Enable for Buck 1. Do not leave the EN1 pin floating.
Analog Ground.
Frequency Synchronization. Drive SYNC high to force the device to operate in 2 MHz fixed PWM mode. Drive SYNC
low to force the device to operate in 2 MHz PSM/PWM automatic transitioning mode. Apply an external clock
between 1.5 MHz and 2.5 MHz to the SYNC pin to synchronize the ADP2230 switching to the applied external
clock. Do not leave the SYNC pin floating.
Precision Enable for Buck 2. Do not leave the EN2 pin floating.
Output Voltage Feedback for Buck 2.
Analog and Power Voltage Input for Buck 2. Connect VIN2 to VIN1.
Connection from MOSFET Power Switches to the Inductor for Buck 2.
Exposed Pad, Power Ground (PGND). The exposed pad on the bottom of the LFCSP package enhances thermal
performance and is electrically connected to PGND inside the package. The exposed pad must be connected to the
ground plane on the board for proper operation.
Rev. A | Page 6 of 18
Data Sheet
ADP2230
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VENx = 5.0 V, CIN1 = CIN2 = COUT1 = COUT2 = 10 µF (GRM21BR61C106KE15), L1 = L2 = 2.2 μH (XFL3012-222MEB), typical values are
at TA = 25°C, and minimum/maximum limits are guaranteed for TJ = −40°C to +125°C, unless otherwise noted. All limits at temperature
extremes are guaranteed via correlation using standard statistical quality control (SQC).
1.220
90
OUTPUT VOLTAGE (V)
PWM MODE
70
60
VIN = 2.5V
VIN = 3.5V
VIN = 4.5V
VIN = 5.5V
VIN = 6.5V
40
0.1
1
10
100
1.205
1.200
1.195
PWM MODE
1.190
1.185
1.180
1.175
1000
LOAD CURRENT (mA)
1.170
10705-103
50
1
AUTO MODE
3.35
3.34
OUTPUT VOLTAGE (V)
90
EFFICIENCY (%)
85
80
75
PWM MODE
70
65
3.33
AUTO MODE
3.32
3.31
3.30
3.29
3.28
60
VIN = 4.5V
VIN = 5.5V
VIN = 6.5V
1
10
100
1000
LOAD CURRENT (mA)
3.26
0.1
1
10
1000
Figure 7. Load Regulation, VOUT = 3.3 V
280
1.45
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
260
1.40
LOAD CURRENT (mA)
240
1.35
1.30
1.25
220
200
180
160
VOUT = 1.2V RISING
VOUT = 1.8V RISING
VOUT = 3.3V RISING
VOUT = 1.2V FALLING
VOUT = 1.8V FALLING
VOUT = 3.3V FALLING
140
3.3
4.3
INPUT VOLTAGE (V)
5.3
6.3
10705-105
120
1.20
2.3
100
LOAD CURRENT (mA)
Figure 4. Efficiency vs. Load Current, VOUT = 3.3 V, Different Input Voltages
TYPICAL MAXIMUM CONTINUOUS
OUTPUT CURRENT (A)
PWM MODE
3.27
10705-104
55
50
0.1
VIN = 4.5V
VIN = 5.5V
VIN = 6.5V
VOUT = 3.3V
fSW = 2MHz
10705-107
95
1000
100
Figure 6. Load Regulation, VOUT = 1.2 V
3.36
VOUT = 3.3V
fSW = 2MHz
10
LOAD CURRENT (mA)
Figure 3. Efficiency vs. Load Current, VOUT = 1.2 V, Different Input Voltages
100
VIN = 2.5V
VIN = 3.5V
VIN = 4.5V
VIN = 5.5V
VIN = 6.5V
AUTO MODE
1.210
80
EFFICIENCY (%)
VOUT = 1.2V
fSW = 2MHz
1.215
AUTO MODE
10705-106
VOUT = 1.2V
fSW = 2MHz
100
2.3
3.0
3.7
4.4
5.1
5.8
6.5
INPUT VOLTAGE (V)
Figure 5. Typical Maximum Continuous Output Current vs. Input Voltage
Rev. A | Page 7 of 18
Figure 8. PSM to PWM Mode Transition Threshold vs. Input Voltage
10705-011
100
ADP2230
1.24
Data Sheet
600
VOUT = 1.2V
fSW = 2MHz
500
OUTPUT VOLTAGE (V)
1.22
PMOS RDSON
400
1.20
1.18
300
200
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 500mA
IOUT = 800mA
4.3
5.3
6.3
INPUT VOLTAGE (V)
0
2.3
6.3
1.60
1.55
PMOS CURRENT LIMIT (A)
3.31
3.3
3.29
3.28
IOUT = 1mA
IOUT = 10mA
IOUT = 100mA
IOUT = 500mA
IOUT = 800mA
3.26
4.6
5.1
5.6
6.1
INPUT VOLTAGE (V)
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
1.50
1.45
1.40
1.35
1.30
1.25
1.20
2.3
10705-114
3.27
4.1
5.3
Figure 12. PMOS Drain-to-Source On Resistance (RDSON)
VOUT = 3.3V
fSW = 2MHz
3.6
4.3
INPUT VOLTAGE (V)
Figure 9. Line Regulation, VOUT = 1.2 V, Different Loads
3.32
3.3
10705-021
3.3
3.3
4.3
5.3
10705-117
1.14
2.3
100
10705-113
1.16
OUTPUT VOLTAGE (V)
TA = –40°C
TA = +25°C
TA = +125°C
6.3
INPUT VOLTAGE (V)
Figure 13. PMOS Current Limit vs. Input Voltage, Different Output Voltages
Figure 10. Line Regulation, VOUT = 3.3 V, Different Loads
600
TA = –40°C
TA = +25°C
TA = +125°C
500
LOAD CURRENT (50mA/DIV)
400
NMOS RDSON
4
300
OUTPUT VOLTAGE (50mA/DIV)
AC-COUPLED
200
1
3.3
4.3
5.3
6.3
INPUT VOLTAGE (V)
Figure 11. NMOS Drain-to-Source On Resistance (RDSON)
TIME (40µs/DIV)
10705-027
0
2.3
10705-022
100
Figure 14. Load Transient Response, VOUT = 1.2 V, Auto Mode, 10 mA to 110 mA
Rev. A | Page 8 of 18
Data Sheet
ADP2230
LOAD CURRENT (100mA/DIV)
LOAD CURRENT (100mA/DIV)
4
4
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
OUTPUT VOLTAGE (100mV/DIV)
AC-COUPLED
1
TIME (40µs/DIV)
Figure 15. Load Transient Response, VOUT = 1.2 V, Auto Mode, 50 mA to 250 mA
10705-031
TIME (40µs/DIV)
10705-028
1
Figure 18. Load Transient Response, VOUT = 1.8 V, Auto Mode, 50 mA to 250 mA
LOAD CURRENT (200mA/DIV)
LOAD CURRENT (200mA/DIV)
4
4
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
OUTPUT VOLTAGE (100mV/DIV)
AC-COUPLED
10705-029
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 16. Load Transient Response, VOUT = 1.2 V, Auto Mode, 200 mA to 600 mA
10705-032
1
1
Figure 19. Load Transient Response, VOUT = 1.8 V, Auto Mode, 200 mA to 600 mA
LOAD CURRENT (50mA/DIV)
LOAD CURRENT (50mA/DIV)
4
4
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
10705-030
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 17. Load Transient Response, VOUT = 1.8 V, Auto Mode, 10 mA to 110 mA
10705-033
1
1
Figure 20. Load Transient Response, VOUT = 3.3 V, Auto Mode, 10 mA to 110 mA
Rev. A | Page 9 of 18
ADP2230
Data Sheet
LOAD CURRENT (100mA/DIV)
LOAD CURRENT (100mA/DIV)
4
4
OUTPUT VOLTAGE (100mV/DIV)
AC-COUPLED
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
1
TIME (40µs/DIV)
Figure 21. Load Transient Response, VOUT = 3.3 V, Auto Mode, 50 mA to 250 mA
10705-037
TIME (40µs/DIV)
10705-034
1
Figure 24. Load Transient Response, VOUT = 1.8 V, PWM Mode, 50 mA to 250 mA
LOAD CURRENT (200mA/DIV)
LOAD CURRENT (100mA/DIV)
4
4
OUTPUT VOLTAGE (100mV/DIV)
AC-COUPLED
OUTPUT VOLTAGE (100mV/DIV)
AC-COUPLED
10705-035
TIME (40µs/DIV)
TIME (40µs/DIV)
Figure 22. Load Transient Response, VOUT = 3.3 V, Auto Mode, 200 mA to 600 mA
10705-038
1
1
Figure 25. Load Transient Response, VOUT = 1.8 V, PWM Mode, 200 mA to 600 mA
ENx PIN (5V/DIV)
LOAD CURRENT (50mA/DIV)
1
OUTPUT VOLTAGE (5V/DIV)
2
4
SWx PIN (5V/DIV)
OUTPUT VOLTAGE (20mV/DIV)
AC-COUPLED
3
INDUCTOR CURRENT (200mA/DIV)
TIME (40µs/DIV)
10705-036
4
TIME (40µs/DIV)
Figure 26. Startup, VOUT = 3.3 V, No Load
Figure 23. Load Transient Response, VOUT = 1.8 V, PWM Mode, 10 mA to 110 mA
Rev. A | Page 10 of 18
10705-039
1
Data Sheet
ADP2230
ENx PIN (5V/DIV)
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
1
1
OUTPUT VOLTAGE (5V/DIV)
2
SWx PIN (2V/DIV)
SWx PIN (5V/DIV)
3
3
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (200mA/DIV)
TIME (2µs/DIV)
Figure 27. Startup, VOUT = 3.3 V, 800 mA
1
10705-133
TIME (40µs/DIV)
10705-040
4
4
Figure 29. Typical PSM Operation, VOUT = 3.3 V, ILOAD = 50 mA, 150 mA
VOUT1 = 1.2V (2V/DIV)
OUTPUT VOLTAGE (50mV/DIV)
AC-COUPLED
VOUT2 = 3.3V SHORTED TO GROUND
(2V/DIV)
1
2
SWx PIN (2V/DIV)
SWx PIN (2V/DIV)
3
3
INDUCTOR CURRENT (500mA/DIV)
TIME (400ns/DIV)
4
TIME (2µs/DIV)
Figure 28. Short-Circuit Response
10705-134
4
10705-041
INDUCTOR CURRENT (200mA/DIV)
Figure 30. Typical PWM Operation, VOUT = 3.3 V, ILOAD = 400 mA
Rev. A | Page 11 of 18
ADP2230
Data Sheet
THEORY OF OPERATION
VIN1
VIN2
RDS ON × Kr
RDS ON × Kr
SLOPE COMP
1.2V
1.0V
SLOPE COMP
P_ILIMIT
P_ILIMIT
PRECISION
EN1
PRECISION
EN1
STANDBY
1.2A
VIN
1.2A
VIN
1.0V
EN2
EN1
IMIN
IMIN
PWM
PWM
N_I LIMIT
N_ILIMIT
CONTROL
LOGIC
CONTROL
LOGIC
–0.5A – (PWM)
–0.5A – (PWM)
SW1
1.2V
STANDBY
0A – (PSM)
PSM
SW2
0A – (PSM)
PSM
VIN
VIN
0.808V
0.808V
0.8V
0.8V
PGND
OSCILLATOR
FIXED
VOUT
ONLY
FIXED
VOUT
ONLY
FB2
FB1
0.8V
gM
VCOMP
V TO I
ICOMP
ICOMP
VCOMP
V TO I
gM
0.8V
SOFT
START
SOFT
START
AGND
VIN
UVLO
2.25V
150°C
135°C
THSD
10705-003
SYNC
H = PWM ONLY
L = PWM/PSM
Figure 31. Internal Block Diagram
OVERVIEW
The ADP2230 contains two, high efficiency, step-down, dc-todc converters that use a proprietary, high speed, current mode,
constant frequency, PWM control scheme for excellent stability
and transient response. To ensure long battery life, the
ADP2230 also has a PSM mode that reduces the switching
frequency under light load conditions. The architecture ensures
smooth transitions between PWM mode and PSM, and
maintains high efficiencies at light loads.
The ADP2230 operates with an input voltage between 2.3 V and
6.5 V and buck to output voltages between 0.8 V and 6 V.
The ADP2230 buck outputs operate out of phase to reduce the
input current ripple. All versions include an internal power
switch, synchronous rectifier, and internal compensation for
minimal external part count. The ADP2230 also includes
internal protection features such as precision enable, soft start,
UVLO, TSD, and short-circuit protection.
The ADP2230 also includes an integrated, 200 Ω, switched
resistor, quick output discharge (QOD) function that
automatically discharges the output when the device is disabled.
The following sections describe the operating conditions, the
modes of operation, and the features of the ADP2230.
OPERATING CONDITIONS
Input Voltage
The ADP2230 operates with an input voltage between 2.3 V and
6.5 V. The VIN1 and VIN2 pins cannot be controlled separately.
VIN1 and VIN2 must be tied together and powered from a
single source.
Output Voltage
The ADP2230 step-down, dc-to-dc converter is available with
adjustable output voltages that can be set between 0.8 V and
6 V. The ADP2230 is also available in three fixed output voltage
pair options: 1.2 V/1.8 V, 1.2 V/3.3 V, or 1.8 V/3.3 V. For
additional output voltage options, contact a local sales or
distribution representative.
Rev. A | Page 12 of 18
Data Sheet
ADP2230
SYNC PIN CONTROL SCHEMES
External Clock Synchronization
There are three possible switching control schemes for the
ADP2230 that can be selected using the SYNC pin: PWM
mode, PSM/PWM automatic transitioning mode, and external
clock synchronization. In PWM mode and PSM/PWM
automatic transitioning mode, the two bucks operate 180° out
of phase. When using the external clock synchronization
control scheme, the two bucks operate in phase.
When a 1.5 MHz to 2.5 MHz external clock is applied to the
SYNC pin, the ADP2230 automatically detects the rising edge
of the first clock and synchronizes to the external clock. If the
device is synchronized to an external clock, the two bucks
operate in phase, PSM is disabled, and the device is forced to
operate in PWM mode only.
PWM Mode
Precision Enable
When the SYNC pin is fixed high (VSYNC ≥ 1.3 V), the ADP2230
operates in the fixed 2 MHz PWM mode. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted to regulate the output voltage. The
switching frequency is 2 MHz, typical, over all input, output,
and load conditions.
The ADP2230 has two enable inputs, EN1 and EN2, that allow
each of the buck outputs to be enabled and shut down independently. The enable circuits of the ADP2230 minimize the
input current during shutdown and simultaneously provide
precision enable thresholds. When the enable input voltages are
below 0.4 V, the regulators are in shutdown mode. When both
buck converters are in shutdown mode, the supply current is
0.1 μA (typical). As the enable input voltages rise above the
standby enable threshold of 1.15 V (minimum), the internal
bias currents and voltages are activated, turning on the
precision enable circuitry. This allows the precision enable
circuitry to accurately detect when the ENx pin voltage exceeds
the precision enable rising threshold of 1.2 V (maximum).
At the start of each oscillator cycle in PWM, the P-channel
MOSFET switch is turned on, putting a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current level that turns
off the P-channel MOSFET switch and turns on the N-channel
MOSFET synchronous rectifier. This puts a negative voltage
across the inductor, causing the inductor current to decrease.
The synchronous rectifier stays on until the next clock cycle.
PSM/PWM Automatic Transitioning Mode
When the SYNC pin is fixed low (VSYNC ≤ 0.4 V), the ADP2230
is able to automatically transition between PWM mode and
PSM to maintain the highest efficiency. The ADP2230 operates
in fixed frequency PWM mode for medium to high load
currents. If the load current falls below the PSM/PWM
threshold level, the converter smoothly transitions to the
reduced frequency PSM. The PSM/PWM threshold varies with
the operating conditions. The PSM/PWM transition level for
various operating conditions is shown in Figure 8. The two
buck converters operate independently and can have different
PSM/PWM current thresholds for the same output voltage.
When the device enters PSM, the ADP2230 switches only when
necessary to maintain the output voltage within regulation.
When the output voltage falls below the lower regulation
threshold, the ADP2230 enters PWM mode for a few oscillator
cycles until the output voltage reaches the upper regulation
threshold. When it reaches the upper threshold, the ADP2230
enters sleep mode and waits for the output voltage to fall below
the lower regulation threshold. During the wait time between
the bursts, both power switches are off to minimize quiescent
current, and the output capacitor supplies the entire load
current. Due to the PSM architecture, the output voltage ripple
in this mode is larger than the ripple in the PWM mode of
operation. Figure 29 shows the typical operation in PSM mode.
FEATURES DESCRIPTIONS
Due to device constraints, EN1 and EN2 have different
operating maximums. EN2 has a 6.5 V operating maximum and
can be directly connected to VINx for any application. EN1 has
a 5.5 V operating maximum and cannot be directly connected
to VINx for applications where VIN is greater than 5.5 V.
Connect a resistor divider from VINx to EN1 to reduce the
voltage applied to the EN1 pin to 5.5 V or less.
Quick Output Discharge
The ADP2230 includes an internal, 200 Ω discharge resistor on
the SWx pin that forces the output voltage to zero when the
buck is disabled. This ensures that the output of the buck is
always in a well defined state.
Output Short-Circuit Protection
The ADP2230 includes frequency foldback to prevent output
current runaway on a hard short. When the voltage at the
feedback pin (FBx) falls below 0.3 V, indicating the possibility of
a hard short at the output, the switching frequency is reduced to
half of the internal oscillator frequency. The reduction in the
switching frequency provides more time for the inductor to
discharge, preventing a runaway of output current.
Undervoltage Lockout
To protect against battery discharge, an undervoltage lockout
(UVLO) circuit is incorporated into the ADP2230. When the
input voltage drops below the UVLO threshold, the ADP2230
shuts down, and both power switches and both synchronous
rectifiers turn off. If EN1 and EN2 are logic high, when the
input voltage rises above the UVLO threshold, the soft start
periods are initiated and the two buck converters are enabled.
Rev. A | Page 13 of 18
ADP2230
Data Sheet
Thermal Shutdown
In the event that the junction temperature of the ADP2230 rises
above 150°C, the thermal shutdown protection circuit turns off
the regulator. Extreme junction temperature can be the result of
high current operation, poor circuit board design, and/or high
ambient temperature. A 15°C hysteresis is included in the
protection circuit so that when a thermal shutdown occurs, the
device does not return to normal operation until the on-chip
temperature drops below 135°C. Upon exiting thermal shutdown,
the soft start sequences are initiated.
Soft Start
The ADP2230 has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter. Typical soft start time is
350 μs. The ADP2230 is also capable of starting up into a
precharged output capacitor. If soft start is invoked when the
output capacitor charge is greater than zero, the device delays
the start of switching until the internal soft start ramp reaches
the corresponding FB voltage. This feature prevents discharging
the output capacitor at the beginning of soft start.
Current Limit
The ADP2230 has protection circuitry that limits the direction
and amount of current that flows through the power switch and
synchronous rectifier, cycle by cycle. The positive current limit
of 1300 mA ( typical) on the power switch limits the amount of
current that can flow from the input to the output. In PWM, the
ADP2230 also has a negative current limit of 500 mA (typical),
on the synchronous rectifier that prevents the inductor current
from reversing direction and flowing out of the load.
100% Duty Cycle
The ADP2230 enters and exits 100% duty cycle smoothly. The
control loop seeks the next clock cycle while the high-side
switch is engaged. When this occurs, the clock signal is masked,
and the PMOS remains on. When the input voltage increases,
the internal VCOMP node decreases its signal to the control loop;
thus, the device stops skipping clock cycles and exits 100% duty
cycle.
Rev. A | Page 14 of 18
Data Sheet
ADP2230
APPLICATIONS INFORMATION
The ADP2230 is designed with a high 1.5 MHz to 2.5 MHz
operating frequency that enables the use of small chip inductors
and capacitors that are ideal for use in applications with solution
size constraints. The external component selection for the
ADP2230 application circuit is also driven by the input and
output operating requirements. Compatible components for the
application circuits in Figure 32 and Figure 33 are identified
using the recommended inductors in Table 6 and selection
guides in the following sections.
ADP2230/
ADP2231
VIN = 6.0V
CIN
10µF
2
VIN1
9
VIN2
OFF
ON
OFF
4
EN1
7
EN2
Use the following equation to determine R1 and R2 for the
desired VOUT:
R1
VOUT 1
VFB
R2
(3)
where VFB = 0.8 V, typical.
L1
2.2µH
VOUT1 = 1.2V
SW1 1
SELECTING THE INDUCTOR
The ADP2230 is designed for optimal performance with 2.2 μH
inductors that have favorable saturation currents and lower dc
resistances (DCR) for their given physical size. Other inductor
values are not recommended.
COUT1
10µF
FB1 3
ON
The ADP2230 is available with adjustable output voltage pairs
and can be configured for output voltages between 0.8 V and
6 V. The output voltage is set by a resistor voltage divider, R1FBx,
from the output voltage (VOUT) to the 0.8 V feedback input at FBx
and R2FBx from FBx to ground (see Figure 33).
L2
2.2µH
VOUT2 = 1.8V
SW2 10
PWM
6
FB2 8
SYNC
AGND
PGND
(EPAD)
5
11
COUT2
10µF
10705-004
PSM/PWM
Figure 32. Typical Application Circuit Fixed Output Voltage
ADP2230/
ADP2231
VIN = 6.0V
CIN
10µF
2
VIN1
9
VIN2
VOUT1 = 3.3V
R1FB1
FB1 3
ON
OFF
ON
OFF
4
EN1
7
EN2
The saturation current of the selected inductor must be greater
than the maximum peak inductor current, IPK, of the application. The maximum peak inductor current is the maximum
load current plus half the inductor ripple current determined by
the following equation:
L1
2.2µH
SW1 1
R2FB1
COUT1
10µF
L2
2.2µH
I
I PK I LOAD ( MAX ) L
2
where ΔIL is the ripple current of the inductor.
VOUT2 = 1.8V
SW2 10
R1FB2
PWM
6
SYNC
PSM/PWM
AGND
R2FB2
COUT2
10µF
11
10705-005
5
FB2 8
PGND
(EPAD)
To ensure stable and efficient performance with the ADP2230,
select a compatible inductor with a sufficient current rating,
saturation current, and low DCR. The specifications and value
of the selected inductor affect efficiency, output ripple, transient
response, and the transition level between PSM/PWM.
Suggested inductors are shown in Table 6.
The ripple current can be calculated as follows:
I L
Figure 33. Typical Application Circuit Adjustable Output Voltage
SETTING THE OUTPUT VOLTAGE
The ADP2230 is available with 1.2 V/1.8 V, 1.2 V/3.3 V, or
1.8 V/3.3 V fixed output voltage pairs. For these options, the
output voltage is set by an internal resistive feedback divider,
and no external resistors are necessary to set the output, as
shown in Figure 32.
(4)
V
VOUT
1 OUT
f SW L
VIN
(5)
where:
fSW is the switching frequency in MHz (2 MHz, typical).
L is the inductor value.
The largest ripple current, ΔIL, occurs at the maximum input
voltage.
Rev. A | Page 15 of 18
ADP2230
Data Sheet
Table 6. Suggested Inductors
Manufacturer
TDK
Murata
Wurth
Taiyo Yuden
Toko
Coilcraft
1
Part Number
MLP2016S2R2M
MLP2520S2R2S
VLF252012MT-2R2M
VLF302510MT-2R2M
VLF302515MT-2R2M
LQM2HPN2R2MG0
LQH32PN2R2NNC
74479787222
7440430022
BRC2012T2R2MD
MDT2520-CR2R2M
DEM2810C (1224AS-H-2R2M)
DEM2815C (1226AS-H-2R2M)
XPL2010-222
XFL3010-222
XFL3012-222
Inductance
(µH)
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 30%
2.2 ± 20%
2.2 ± 30%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
2.2 ± 20%
DCR (mΩ)
Typ
110
110
57
70
42
80
64
80
23
110
90
85
43
156
111
81
Current
Rating (A)
1.20
1.20
1.67
1.23
2.71
1.30
1.85
1.50
2.50
1.00
1.35
1.10
1.40
0.96
1.0
1.40
Saturation
Current (A)
N/A
1.20
1.04
1.37
1.57
N/A
N/A
0.70
2.35
1.10
N/A
1.40
2.20
0.94
0.94
1.00
Size (L × W × H) (mm)
2.00 × 1.60 × 1.00
2.50 × 2.00 × 1.00
2.50 × 2.00 × 1.00
3.00 × 2.50 × 1.00
3.00 × 2.50 × 1.40
2.50 × 2.00 × 0.90
3.20 × 2.50 × 1.55
2.50 × 2.00 × 1.00
4.80 × 48.0 × 2.80
2.00 × 1.25 × 1.40
2.50 × 2.00 × 1.00
3.20 × 3.00 × 1.00
3.20 × 3.00 × 1.50
1.90 × 2.00 × 1.00
3.00 × 3.00 × 1.00
3.00 × 3.00 × 1.30
Package
0806
1008
1008
N/A
N/A
1008
1210
1008
N/A
0805
1008
N/A
N/A
N/A
N/A
1212
N/A means not applicable.
SELECTING THE INPUT AND OUTPUT CAPACITORS
The ADP2230 is designed for optimal performance with 10 µF
capacitors. Use any size, good quality, low ESR, X5R or X7R
ceramic capacitors with the ADP2230, as long as they meet
the capacitance and voltage requirements of the application.
Capacitors less than 10 µF are not recommended.
Input Capacitor
The ADP2230 is designed to operate with a single 10 µF input
capacitor (CIN). The input capacitor must be able to support the
maximum input operating voltage and the maximum rms input
current.
Place the input capacitor as close as possible to the VINx pins
to reduce input voltage ripple. Select an input capacitor capable
of withstanding the rms input current for the maximum
continuous load current in the application using the following
equation:
I RMS ≈ I OUT ( MAX ) ×
VOUT × (VIN − VOUT )
VIN
(6)
The input capacitor reduces the input voltage ripple caused by
the switch currents on the VINx pin and reduces the circuit
sensitivity to the PCB layout, especially when long input traces or
high source impedance are encountered.
Output Capacitor
The ADP2230 requires two 10 µF capacitors, COUT1 and COUT2,
with one capacitor on each buck output. The output capacitor
selection affects both the output voltage ripple (ΔVOUT) and the
stability of the control loop.
The ADP2230 is designed for operation with small, space
saving ceramic capacitors, but function with most commonly
used capacitors as long as care is taken to calculate the effective
ESR value. Capacitors with low ESR values produce the lowest
output voltage ripple. A capacitor with an ESR between 0.001 Ω
and 0.01 Ω is recommended to ensure stability of the ADP2230.
To determine the maximum ESR for a given ΔVOUT, use the
following equation:
ESRCOUT ( MAX ) <
∆VOUT
∆I L
(7)
where ΔVOUT is the peak-to-peak output voltage ripple as
calculated in Equation 8.
The overall output voltage ripple is the sum of the voltage spike
caused by the output capacitor ESR plus the voltage ripple caused
by charging and discharging the output capacitor. The output
voltage ripple is determined by the following equation:
ΔVOUT ≈ ΔIL × (ESRCOUT + 1/(8 × COUT × fSW))
(8)
where:
ESRCOUT is the ESR of the chosen capacitor.
ΔIL is the ripple current of the inductor calculated in Equation 7.
The largest voltage ripple occurs at the highest input voltage.
At light load currents, if SYNC is set low, the converter operates
in PSM, and the output voltage ripple increases.
To improve the transient response of the ADP2230, increase the
value of COUT. Capacitors less than 10 µF are not recommended.
Rev. A | Page 16 of 18
Data Sheet
ADP2230
PCB LAYOUT CONSIDERATIONS
For high efficiency, good regulation, and stability with the
ADP2230, a well designed PCB is required. Poor layout can
affect the ADP2230 buck performance, causing electromagnetic
interference (EMI), poor electromagnetic compatibility (EMC),
ground bounce, and voltage losses.
Improve heat dissipation from the package by increasing
the amount of copper attached to the pins of the ADP2230.
Keep the low ESR input and output capacitors, CIN and
COUT, and the inductors, L1 and L2, as close as possible to
the ADP2230. Avoid long trace lengths from the device to
the capacitors that add series inductance and may cause
instability or increased ripple.
Route the output voltage path away from the inductor and
SWx node to minimize noise and magnetic interference.
Keep high current traces as short and as wide as possible.
Avoid routing high impedance traces near any node
connected to SWx or near the inductor to prevent radiated
noise injection.
Use a ground plane with several vias connected to the
component side ground to reduce noise interference on
sensitive circuit nodes.
The use of 0402 or 0603 capacitors achieves the smallest
possible footprint solution where board area is limited.
Figure 34. PCB Layout, Top
10705-008
10705-009
Use the following guidelines when designing PCBs:
Figure 35. PCB Layout, Bottom
Rev. A | Page 17 of 18
ADP2230
Data Sheet
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 36. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP2230ACPZ-1218R7
ADP2230ACPZ-1233R7
ADP2230ACPZ-1833R7
ADP2230ACPZ-R7
ADP2230CP-EVALZ
1
2
Buck 1
Output
Voltage (V)2
1.2
1.2
1.8
Adjustable
Buck 2
Output
Voltage (V)2
1.8
3.3
3.3
Adjustable
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Z = RoHS Compliant Part.
For additional output voltage options, contact a local sales or distribution representative.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10705-0-11/14(A)
Rev. A | Page 18 of 18
Package Description
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead LFCSP_WD
Evaluation Board with Adjustable
Output Voltage Option
Package
Option
CP-10-9
CP-10-9
CP-10-9
CP-10-9
Branding
LJ3
LM3
LMK
LMQ
工商网监
湘ICP备2023018690号
