FEATURES
Input voltage: 4.5 V to 20 V
Integrated 44 mΩ high-side MOSFET
0.6 V ± 1% reference voltage over temperature
Continuous output current: 6 A
Programmable switching frequency: 250 kHz to 1.4 MHz
Synchronizes to external clock: 250 kHz to 1.4 MHz
180° out-of-phase synchronization
Programmable UVLO
Power-good output
External compensation
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
TYPICAL APPLICATIONS CIRCUIT
VIN
1
2
CIN
3
4
5
ROSC
6
7
CSS
8
PVIN
BST
PVIN
SW
UVLO
LD
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
L
CBST
15
VOUT
14
COUT
FET
13
12
CVREG
11
10
RTOP
9
RBOT
CC_EA
RC_EA
CCP_EA
Figure 1.
APPLICATIONS
100
95
90
85
EFFICIENCY (%)
Communication infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load application
SW
ADP2381
PGOOD
16
10209-001
Data Sheet
20 V, 6 A Synchronous Step-Down
Regulator with Low-Side Driver
ADP2381
80
75
70
65
60
50
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
10209-002
VOUT = 3.3V
VOUT = 5V
VOUT = 1.2V
55
Figure 2. ADP2381 Efficiency vs. Output Current, VIN = 12 V, fSW = 250 kHz
GENERAL DESCRIPTION
The ADP2381 is a current mode control, synchronous, stepdown, dc-to-dc regulator. It integrates a 44 mΩ power MOSFET
and a low-side driver to provide a high efficiency solution. The
ADP2381 runs from an input voltage of 4.5 V to 20 V and can
deliver 6 A of output current. The output voltage can be
adjusted to 0.6 V to 90% of the input voltage. The switching
frequency of the ADP2381 can be programmed from
250 kHz to 1.4 MHz or fixed at 290 kHz or 550 kHz. The
synchronization function allows the switching frequency to be
synchronized to an external clock to minimize system noise.
External compensation and an adjustable soft start provide
design flexibility. The power-good output provides simple and
reliable power sequencing. Additional features include
programmable undervoltage lockout (UVLO), overvoltage
protection (OVP), overcurrent protection (OCP), and thermal
shutdown (TSD).
The ADP2381 operates over the −40°C to +125°C junction
temperature range and is available in a 16-lead TSSOP_EP
package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
ADP2381
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Applications ....................................................................................... 1
Input Capacitor Selection .......................................................... 15
Typical Applications Circuit............................................................ 1
Output Voltage Setting .............................................................. 15
General Description ......................................................................... 1
Voltage Conversion Limitations ............................................... 15
Revision History ............................................................................... 2
Inductor Selection ...................................................................... 15
Specifications..................................................................................... 3
Output Capacitor Selection....................................................... 17
Absolute Maximum Ratings ............................................................ 5
Low-Side Power Device Selection ............................................ 17
Thermal Information ................................................................... 5
Programming Input Voltage UVLO ........................................ 18
ESD Caution .................................................................................. 5
Compensation Design ............................................................... 18
Pin Configuration and Function Description .............................. 6
ADIsimPower Design Tool ....................................................... 19
Typical Performance Characteristics ............................................. 7
Design Example .............................................................................. 20
Functional Block Diagram ............................................................ 12
Output Voltage Setting .............................................................. 20
Theory of Operation ...................................................................... 13
Frequency Setting ....................................................................... 20
Control Scheme .......................................................................... 13
Inductor Selection ...................................................................... 20
Internal Regulator (VREG) ....................................................... 13
Output Capacitor Selection....................................................... 20
Bootstrap Circuitry .................................................................... 13
Low-Side MOSFET Selection ................................................... 21
Low-Side Driver.......................................................................... 13
Compensation Components ..................................................... 21
Oscillator ..................................................................................... 13
Soft Start Time Program ........................................................... 21
Synchronization .......................................................................... 13
Input Capacitor Selection .......................................................... 21
Enable and Soft Start .................................................................. 13
Schematic for Design Example ................................................. 21
Power Good ................................................................................. 14
External Components Recommendation .................................... 23
Peak Current Limit and Short-Circuit Protection ................. 14
Circuit Board Layout Recommendations ................................... 25
Overvoltage Protection (OVP) ................................................. 14
Typical Application Circuits ......................................................... 27
Undervoltage Lockout (UVLO) ................................................ 14
Outline Dimensions ....................................................................... 28
Thermal Shutdown ..................................................................... 14
Ordering Guide .......................................................................... 28
REVISION HISTORY
3/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
ADP2381
SPECIFICATIONS
VIN = 12 V, TJ = −40°C to +125°C for min/max specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
FB
FB Regulation Voltage
Symbol
VPVIN
IQ
ISHDN
VFB
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
Regulator Current Limit
SW
High-Side On Resistance 1
High-Side Peak Current Limit
Negative Current-Limit Threshold Voltage 2
SW Minimum On Time
SW Minimum Off Time
LOW-SIDE DRIVER (LD)
Rising Time2
Falling Time2
Sourcing Resistor
Sinking Resistor
BST
Bootstrap Voltage
OSCILLATOR (RT PIN)
Switching Frequency
IFB
Switching Frequency Range
SYNC
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
EN/SS
Enable Threshold
Internal Soft Start
SS Pin Pull-Up Current
fSW
Test Conditions/Comments
No switching
EN/SS = GND
PVIN rising
PVIN falling
0°C < TJ < 85°C
−40°C < TJ < +125°C
gm
ISOURCE
ISINK
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
Min
4.5
2
80
3.7
V
mA
µA
V
V
V
V
µA
360
40
40
500
60
60
620
80
80
µS
µA
µA
7.6
8
350
100
8.4
V
mV
mA
44
9.6
20
120
200
70
11.5
135
170
300
mΩ
A
mV
ns
ns
20
10
4
2
6
3.5
ns
ns
Ω
Ω
4.5
5
5.7
V
210
400
425
250
290
550
500
360
690
570
1400
kHz
kHz
kHz
kHz
1400
kHz
ns
ns
V
V
tMIN_ON
tMIN_OFF
CDL = 2.2 nF; see Figure 17
CDL = 2.2 nF; see Figure 20
RT pin connected to GND
RT pin open
ROSC = 100 kΩ
20
3.5
170
4.5
0.606
0.609
0.1
7.7
fSW
Unit
0.6
0.6
0.01
VBST − VSW = 5 V
VBOOT
2.8
130
4.3
3.9
Max
0.594
0.591
65
tR
tF
Typ
250
100
100
1.3
0.4
0.5
ISS_UP
2.6
Rev. 0 | Page 3 of 28
1500
3.3
4
V
Clock cycles
µA
ADP2381
Parameter
POWER GOOD (PGOOD)
PGOOD Range
PGOOD Deglitch Time
PGOOD Leakage Current
PGOOD Output Low Voltage
UVLO
Rising Threshold
Falling Threshold
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Data Sheet
Symbol
Test Conditions/Comments
Min
FB rising threshold
FB falling threshold
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
IPGOOD = 1 mA
Typ
95
90
1024
16
0.01
125
1.02
1.2
1.1
150
25
Pin-to-pin measurement.
Guaranteed by design.
Rev. 0 | Page 4 of 28
Max
Unit
0.1
200
%
%
Clock cycles
Clock cycles
µA
mV
1.28
V
V
°C
°C
Data Sheet
ADP2381
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN, PGOOD
SW
BST
UVLO, FB, EN/SS, COMP, SYNC, RT
VREG, LD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
THERMAL INFORMATION
Table 3. Thermal Resistance
Package Type
16-lead TSSOP_EP
θJA
39.48
Unit
°C/W
θJA is specified for the worst-case conditions, that is, a device
soldered in circuit board (4-layer, JEDEC standard board) for
surface-mount packages.
ESD CAUTION
Rev. 0 | Page 5 of 28
ADP2381
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTION
PVIN
1
16 BST
PVIN
2
15 SW
UVLO
3
PGOOD
4
RT
5
SYNC
6
11 PGND
EN/SS
7
10 GND
COMP
8
TOP VIEW
(Not to Scale)
14 SW
13 LD
12 VREG
9
FB
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO AN EXTERNAL GROUND PLANE UNDERNEATH
THE IC FOR THERMAL DISSIPATION.
10209-003
ADP2381
Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No.
1, 2
Mnemonic
PVIN
3
4
5
UVLO
PGOOD
RT
6
SYNC
7
EN/SS
8
9
10
11
12
13
14, 15
16
17
COMP
FB
GND
PGND
VREG
LD
SW
BST
EPAD
Description
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and
PGND.
Undervoltage Lockout Pin. An external resistor divider can be used to set the turn-on threshold.
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency
between 250 kHz and 1.4 MHz. If the RT pin is connected to GND, the switching frequency is set to 290
kHz. If the RT pin is open, the switching frequency is set to 550 kHz.
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
between 250 kHz and 1.4 MHz (see the Oscillator section and the Synchronization section for details).
Enable Pin (EN). When this pin voltage falls below 0.5 V, the regulator is disabled.
Soft Start (SS). This pin can also be used to set the soft start time.
Connect a capacitor from SS to GND to program the slow soft start time. If this pin is open, the regulator
is enabled and uses the internal soft start.
Error Amplifier Output. Connect an RC network from COMP to FB.
Feedback Voltage Sense Input. Connect to a resistor divider from VOUT.
Analog Ground. Connect to the ground plane.
Power Ground. Connect to the source of the synchronous N-channel MOSFET.
Internal 8 V Regulator Output. Place a 1 µF ceramic capacitor between this pin and GND.
Low-Side Gate Driver Output. Connect this pin to the gate of the synchronous N-MOSFET.
Switch Node Output. Connect this pin to the output inductor.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF ceramic capacitor between SW and BST.
The exposed pad should be soldered to an external ground plane underneath the IC for thermal
dissipation.
Rev. 0 | Page 6 of 28
Data Sheet
ADP2381
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
85
85
EFFICIENCY (%)
80
75
70
75
70
65
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
50
0
1
2
3
4
5
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS6298
55
6
OUTPUT CURRENT (A)
50
0
100
100
95
95
90
90
85
85
EFFICIENCY (%)
EFFICIENCY (%)
3
4
5
80
75
70
80
75
70
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
65
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
INDUCTOR: FDVE1040-3R3M
MOSFET: FDS6298
55
60
50
0
1
2
3
4
5
INDUCTOR: 744 333 0100
MOSFET: FDS6298
55
6
OUTPUT CURRENT (A)
50
10209-005
60
0
150
3.00
QUIESCENT CURRENT (mA)
3.20
140
130
120
110
TJ = –40°C
TJ = +25°C
TJ = +125°C
12
14
16
VIN (V)
18
20
4
5
6
2.80
2.60
2.40
2.20
TJ = –40°C
TJ = +25°C
TJ = +125°C
1.80
10209-006
10
3
2.00
90
8
2
Figure 8. Efficiency at VIN = 5 V, fSW = 500 kHz
160
6
1
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 500 kHz
100
6
Figure 7. Efficiency at VIN = 12 V, fSW = 250 kHz
65
SHUTDOWN CURRENT (μA)
2
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 500 kHz
4
1
10209-008
INDUCTOR: FDVE1040-2R2M
MOSFET: FDS6298
55
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
60
10209-004
60
10209-007
65
80
4
6
8
10
12
14
16
VIN (V)
Figure 6. Shutdown Current vs. VIN
Figure 9. Quiescent Current vs. VIN
Rev. 0 | Page 7 of 28
18
20
10209-009
EFFICIENCY (%)
Operating conditions: TA = 25oC, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 2 × 100 µF, fSW = 500 kHz, unless otherwise noted.
ADP2381
Data Sheet
1.30
4.5
4.4
1.25
UVLO PIN THRESHOLD (V)
PVIN UVLO THRESHOLD (V)
RISING
4.3
4.2
4.1
4.0
FALLING
3.9
3.8
RISING
1.20
1.15
FALLING
1.10
1.05
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
1.00
–40
10209-010
3.6
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. PVIN UVLO Threshold vs. Temperature
10209-013
3.7
Figure 13. UVLO Pin Threshold vs. Temperature
3.30
606
3.25
FEEDBACK VOLTAGE (mV)
SS PULL-UP CURRENT (µA)
604
3.20
3.15
3.10
3.05
3.00
602
600
598
596
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
594
–40
10209-011
2.90
–40
–20
0
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
Figure 11. SS Pin Pull-Up Current vs. Temperature
10209-014
2.95
Figure 14. FB Voltage vs. Temperature
530
8.4
8.3
520
VREG VOLTAGE (V)
ROSC = 100kΩ
500
490
8.1
8.0
7.9
7.8
480
470
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
7.6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 12. Frequency vs. Temperature
Figure 15. VREG Voltage vs. Temperature
Rev. 0 | Page 8 of 28
10209-015
7.7
10209-012
FREQUENCY (kHz)
8.2
510
Data Sheet
ADP2381
11.0
50
40
20
–40
–20
0
20
40
60
80
100
10.0
9.5
9.0
8.5
8.0
–40
10209-016
30
10.5
120
TEMPERATURE (°C)
–20
0
20
40
60
80
120
100
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
SW
SW
1
1
LD
LD
2
CH1 5.00V
CH2 5.00V
M20.0ns
T 46.60%
A CH2
3.70V
10209-017
2
CH1 5.00V
Figure 17. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
CH2 5.00V
M20.0ns
T 43.80%
A CH2
3.70V
10209-020
MOSFET RDSON (mΩ)
60
10209-019
PEAK CURRENT LIMIT THRESHOLD (A)
70
Figure 20. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
VOUT (AC)
1
EN/SS
3
IL
1
SW
VOUT
PGOOD
2
4
CH1 10mV
B
W
CH2 10V
CH4 2A Ω
M2.00µs
T 50.00%
A CH2
6.00V
10209-018
4
IOUT
CH1 2.00V BW CH2 5.00V
CH3 5.00V
CH4 5.00A Ω
Figure 18. Working Mode Waveform
M2.00ms
T 50.00%
A CH2
Figure 21. Soft Start with Full Load
Rev. 0 | Page 9 of 28
5.80V
10209-021
2
ADP2381
Data Sheet
SYNC
EN/SS
3
3
1
VOUT
SW
PGOOD
2
2.00V
CH3 5.00V BW
Figure 22. Precharged Output
CH2 10.0V
M1.00µs
T 50.00%
A CH2
7.00V
10209-025
A CH2
13.5V
10209-026
CH1 2.00V BW CH2 5.00V
M2.00ms
CH3 5.00V
CH4 5.00A Ω T 49.60%
10209-022
4
2
IL
Figure 25. External Synchronization
VOUT (AC)
VOUT (AC)
1
1
VIN
SW
IOUT
3
IL
2
CH1 100mV
B
W
CH4 2.00A Ω
M200µs
T 70.20%
A CH4
2.52 A
10209-023
4
Figure 23. Load Transient Response, 1 A to 5 A
CH1 20.0mV
CH3 5.00V
B
W
B
W
CH2 10.0V BW M1.00ms A CH3
T 20.20%
Figure 26. Line Transient Response, VIN from 10 V to 16 V, IOUT = 6 A
VOUT
VOUT
1
1
SW
SW
2
2
IL
IL
4
M10.00ms
T 30.40%
A CH1
1.96V
CH1 2.00V BW CH2 10.0V
CH4 5.00A Ω
Figure 24. Output Short Entry
M10.00ms
T 60.40%
A CH1
Figure 27. Output Short Recovery
Rev. 0 | Page 10 of 28
1.96V
10209-027
CH1 2.00V BW CH2 10.0V
CH4 5.00A Ω
10209-024
4
ADP2381
7
6
6
5
5
4
3
2
1
0
25
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
40
4
3
2
1
55
70
85
100
AMBIENT TEMPERATURE (°C)
0
25
VOUT = 1V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
40
55
70
85
100
AMBIENT TEMPERATURE (°C)
Figure 28. Load Current vs. Ambient Temperature, VIN = 12 V,
fSW = 500 kHz
Figure 29. Load Current vs. Ambient Temperature, VIN = 12 V,
fSW = 250 kHz
Rev. 0 | Page 11 of 28
10209-029
LOAD CURRENT (A)
7
10209-028
LOAD CURRENT (A)
Data Sheet
ADP2381
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
VREG
ADP2381
CLK
RT
BIAS AND DRIVER
REGULATOR
OSCILLATOR
SYNC
PVIN
SLOPE RAMP
UVLO
PVIN
320kΩ
UVLO
BOOST
REGULATOR
+
125kΩ
1.2V
+
ACS
–
–
SLOPE RAMP
Σ
IMAX
+
OCP
–
HICCUP
MODE
COMP
BST
ISS
0.6V
+
EN/SS
+
FB
–
0.7V
+
CMP
–
AMP
–
NFET
DRIVER
SW
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
OVP
+
VREG
CLK
0.54V
LD
DRIVER
–
PGND
+
PGOOD
GND
+
Figure 30. Functional Block Diagram
Rev. 0 | Page 12 of 28
10209-030
NEGATIVE
CURRENT LIMIT
CMP
–
DEGLITCH
Data Sheet
ADP2381
THEORY OF OPERATION
CONTROL SCHEME
The ADP2381 uses fixed frequency, peak current-mode PWM
control architecture. At the start of each oscillator cycle, the
high-side N-MOSFET is turned on, putting a positive voltage
across the inductor. Current in the inductor increases until
the current sense signal crosses the peak inductor current threshold that turns off the high-side N-MOSFET and turns on the
low-side N-MOSFET. This puts a negative voltage across the
inductor, causing the inductor current to decrease. The lowside N-MOSFET stays on for the rest of the cycle.
INTERNAL REGULATOR (VREG)
The internal regulator provides a stable supply for the internal
circuits and provides bias voltage for the low-side gate driver.
Placing a 1 µF ceramic capacitor between VREG and GND is
recommended. The internal regulator also includes a currentlimit circuit to protect the circuit if the maximum external
load is added.
BOOTSTRAP CIRCUITRY
The ADP2381 has integrated the boot regulator to provide the
gate drive voltage for the high-side N-MOSFET. It generates a
5 V bootstrap voltage between BST and SW by differential
sensing.
1400
1200
600
400
200
0
20
60
100
140
180
220
ROSC (kΩ)
260
300
Figure 31. Switching Frequency vs. ROSC
SYNCHRONIZATION
To synchronize the ADP2381, connect an external clock to the
SYNC pin. The frequency of the external clock can be in the
range of 250 kHz to 1.4 MHz. During synchronization, the
switching rising edge runs 180° out of phase with the external
clock rising edge.
When the ADP2381 is being synchronized, connect a resistor
from the RT pin to GND to program the internal oscillator to
run at 90% to 110% of the external synchronization clock.
ENABLE AND SOFT START
When the voltage of the EN/SS pin exceeds 0.5 V, the ADP2381
starts operation.
LOW-SIDE DRIVER
The LD pin provides the gate driver for the low-side N-channel
MOSFET. Internal circuitry monitors the external MOSFET to
ensure break-before-make switching to prevent cross
conduction.
OSCILLATOR
The ADP2381 switching frequency is controlled by the RT pin.
If the RT pin is connected to GND, the switching frequency is
set to 290 kHz. If the RT pin is open, the switching frequency is
set to 550 kHz. A resistor connected from RT to GND can
program the switching frequency according to the following
equation:
57,600
ROSC [kΩ] + 15
800
The ADP2381 has an internal digital soft start. The internal soft
start time can be calculated by using the following equation:
It is recommended to place a 0.1 µF, X7R or X5R ceramic
capacitor between the BST pin and the SW pin.
f SW [kHz] =
1000
10209-031
The ADP2381 can operate with an input voltage from 4.5 V to
20 V and regulate the output voltage down to 0.6 V. Additional
features for design flexibility include programmable switching
frequency, soft start, external compensation, and power-good pin.
A 100 kΩ resistor sets the frequency to 500 kHz, and a 215 kΩ
resistor sets the frequency to 250 kHz. Figure 31 shows the typical
relationship between fSW and ROSC.
SWITCHING FREQUENCY (kHz)
The ADP2381 is a synchronous, step-down, dc-to-dc regulator.
It uses current-mode architecture with an integrated high-side
power switch and a low-side driver. It targets high performance
applications that require high efficiency and design flexibility.
t SS _ INT =
1500
(ms)
f SW [kHz]
A slow soft start time can be programmed by the EN/SS pin.
Place a capacitor between the EN/SS pin and GND. An internal
current charges this capacitor to establish the soft start ramp.
The soft start time can be calculated by using the following
equation:
t SS _ EXT =
0.6 V × CSS
I SS _UP
where:
CSS is the soft start capacitance.
ISS_UP is the soft start pull-up current (3.3 µA).
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the EN/SS voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
Rev. 0 | Page 13 of 28
ADP2381
Data Sheet
If the output voltage is charged prior to turn-on, the ADP2381
prevents the low-side MOSFET from turning on, which
discharges the output voltage until the soft start voltage exceeds
the voltage on the FB pin.
When the regulator is disabled or a current fault happens, the
soft start capacitor is discharged, and the internal digital soft
start is reset to 0 V.
POWER GOOD
The power-good (PGOOD) pin is an active high, open-drain
output that requires a pull-up resistor. A logic high indicates
that the voltage at the FB pin (and, therefore, the output
voltage) is above 95% of the reference voltage and there is a
1024 cycle waiting period before PGOOD is pulled high. A logic
low indicates that the voltage at the FB pin is below 90% of the
reference voltage and there is a 16-cycle waiting period before
PGOOD is pulled low.
PEAK CURRENT LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2381 has a peak current-limit protection circuit to
prevent current runaway. During soft start, the ADP2381 uses
frequency foldback to prevent output current runaway. The
switching frequency is reduced according to the voltage on the
FB pin, which allows more time for the inductor to discharge.
The correlation between the switching frequency and FB pin
voltage is shown in Table 5.
The ADP2381 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the
sink current-limit threshold, which is typically 20 mV, the lowside MOSFET turns off immediately for the rest of this cycle.
Both high-side and low-side MOSFETs turn off until the next
clock cycle.
In some cases, the input voltage (PVIN) ramp rate is too slow or
the output capacitor is too large to support the setting regulation
voltage during the soft start, causing the regulator to enter
hiccup mode. To avoid such cases, use a resistor divider at the
UVLO pin to program the UVLO input voltage, or use a longer
soft start time.
OVERVOLTAGE PROTECTION (OVP)
The ADP2381 provides an overvoltage protection feature to
protect the system against an output shorting to a higher voltage
supply or a strong load transient occurring. If the feedback
voltage increases to 0.7 V, the internal high-side MOSFET and
low-side driver are turned off until the voltage at FB decreases to
0.63 V. At that time, the ADP2381 resumes normal operation.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO pin enable threshold is 1.2 V with 100 mV
hysteresis.
The ADP2381 has an internal voltage divider consisting of two
resistors from PVIN to GND, 320 kΩ for the high-side resistor
and 125 kΩ for the low-side resistor. An external resistor divider
from PVIN to GND can be used to override the internal resistor
divider.
Table 5. Switching Frequency and FB Pin Voltage
FB Pin Voltage
VFB ≥ 0.4 V
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
restart. If the current limit fault is cleared, the regulator resumes
normal operation. Otherwise, it reenters hiccup mode.
Switching Frequency
fSW
fSW/2
fSW/4
For heavy load protection, the ADP2381 uses hiccup mode for
overcurrent protection. When the inductor peak current reaches
the current-limit value, the high-side MOSFET turns off and
the low-side driver turns on until the next cycle, while the
overcurrent counter increments. If the overcurrent counter
reaches 10, or the FB pin voltage falls to ≤0.4 V after the soft
start, the regulator enters hiccup mode. The high-side MOSFET
and low-side MOSFET are both turned off. The regulator
remains in this mode for 4096 clock cycles and then attempts to
THERMAL SHUTDOWN
In the event that the ADP2381 junction temperatures rise above
150°C, the thermal shutdown circuit turns off the regulator.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, and/or high ambient
temperature. A 25°C hysteresis is included so that when thermal
shutdown occurs, the ADP2381 does not return to operation
until the on-chip temperature drops below 125°C. Upon
recovery, soft start is initiated prior to normal operation.
Rev. 0 | Page 14 of 28
Data Sheet
ADP2381
APPLICATIONS INFORMATION
INPUT CAPACITOR SELECTION
The input decoupling capacitor is used to attenuate high
frequency noise on the input. This capacitor should be a
ceramic capacitor in the range of 10 µF to 47 µF. It should be
placed close to the PVIN pin. The loop composed by this input
capacitor, high-side NFET, and low-side NFET must be kept as
small as possible.
The voltage rating of the input capacitor must be greater than
the maximum input voltage. The rms current rating of the input
capacitor should be larger than the following equation:
OUTPUT VOLTAGE SETTING
The output voltage of ADP2381 can be set by an external
resistive divider using the following equation:
VOUT_MAX = DMAX × VIN
As Equation 1 to Equation 3 show, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
INDUCTOR SELECTION
Table 6. Resistor Divider for Different Output Voltages
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor leads to a faster transient response, but it
degrades efficiency due to larger inductor ripple current,
whereas using a large inductor value leads to smaller ripple
current and better efficiency, but it results in a slower transient
response.
RBOT, ±1% (kΩ)
15
10
10
10
15
2.21
3
As a guideline, the inductor ripple current, ΔIL, is typically set
to 1/3 of the maximum load current. The inductor can be
calculated using the following equation:
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2381 is typically 120 ns. The
minimum output voltage at a given input voltage and frequency
can be calculated using the following equation:
VOUT_MIN = VIN × tMIN_ON × fSW – (RDSON_HS – RDSON_LS) × IOUT_MIN
× tMIN_ON × fSW – (RDSON_LS + RL) × IOUT_MIN
(1)
where:
VOUT_MIN is the minimum output voltage.
tMIN_ON is the minimum on time.
fSW is the switching frequency.
RDSON_HS is the high-side MOSFET on resistance.
RDSON_LS is the low-side MOSFET on resistance.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
(3)
where DMAX is the maximum duty.
Table 6 gives the recommended resistor divider values for
various output voltage options.
RTOP, ±1% (kΩ)
10
10
15
20
47.5
10
22
VOUT_MAX = VIN × (1 – tMIN_OFF × fSW) – (RDSON_HS – RDSON_LS) ×
IOUT_MAX × (1 – tMIN_OFF × fSW) – (RDSON_LS + RL) × IOUT_MAX
(2)
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated by using the
following equation:
To limit output voltage accuracy degradation due to FB bias
current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ.
VOUT (V)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
The maximum output voltage limited by the minimum off time
at a given input voltage and frequency can be calculated using
the following equation:
where:
VOUT_MAX is the maximum output voltage.
tMIN_OFF is the minimum off time.
IOUT_MAX is the maximum output current.
I C IN _ RMS = I OUT × D × (1 − D )
R
VOUT = 0.6 × 1 + TOP
RBOT
The maximum output voltage for a given input voltage and
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is
typically 200 ns, and the maximum duty cycle of the ADP2381
is typically 90%.
L=
(V
IN
− VOUT )
∆I L × f SW
×D
where:
VIN is the input voltage.
VOUT is the output voltage.
ΔIL is the inductor current ripple.
fSW is the switching frequency.
D is the duty cycle.
D=
VOUT
VIN
The ADP2381 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when
the duty cycle is larger than 50%. The internal slope
compensation limits the minimum inductor value.
Rev. 0 | Page 15 of 28
ADP2381
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by the following equation:
VOUT × (1 − D )
quick saturation characteristic, the saturation current rating of
the inductor should be higher than the current-limit threshold of
the switch to prevent the inductor from becoming saturated.
The rms current of the inductor can be calculated by
2 × f SW
The inductor peak current is calculated using the following
equation:
I PEAK = I OUT +
2
I RMS = I OUT
+
∆I L
2
∆I L2
12
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
The saturation current of the inductor must be larger than the
peak inductor current. For the ferrite core inductors with a
Table 7. Recommended Inductors
Vendor
Toko
Vishay
Wurth Elektronik
Part No.
FDVE0630-R47M
FDVE0630-R75M
FDVE0630-1R0M
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
IHLP3232DZ-R47M-11
IHLP3232DZ-R68M-11
IHLP3232DZ-1R0M-11
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
744 325 120
744 325 180
744 325 240
744 325 330
744 325 420
Value (µH)
0.47
0.75
1.0
1.5
2.2
3.3
4.7
0.47
0.68
1.0
1.5
2.2
3.3
4.7
1.2
1.8
2.4
3.3
4.2
Rev. 0 | Page 16 of 28
ISAT (A)
15.6
10.9
9.5
13.7
11.4
9.8
8.2
14
14.5
12
27.5
25.6
18.6
17
25
18
17
15
14
IRMS (A)
14.1
10.7
9.5
14.6
11.6
9.0
8.0
25
22.2
18.2
15
12
10
9.5
20
16
14
12
11
DCR (mΩ)
3.7
6.2
8.5
4.6
6.8
10.1
13.8
2.38
3.22
4.63
5.8
9
14.4
16.5
1.8
3.5
4.75
5.9
7.1
Data Sheet
ADP2381
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
performance.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output ripple
voltage and the loop dynamics of the regulator.
During a load step transient on the output, for example, when
the load is suddenly increased, the output capacitor supplies the
load until the control loop has a chance to ramp up the inductor
current, which causes the output to undershoot. The output
capacitance required to satisfy the voltage droop requirement
can be calculated using the following equation:
COUT _UV =
KUV × ∆I STEP × L
2 × (VIN − VOUT ) × ∆VOUT _UV
2
I C OUT _ RMS =
LOW-SIDE POWER DEVICE SELECTION
The selected MOSFET must meet the following requirements:
•
Another case occurs when a load is suddenly removed from the
output. The energy stored in the inductor rushes into the
capacitor, which causes the output to overshoot. The output
capacitance required to meet the overshoot requirement can be
calculated using the following equation:
K OV × ∆I STEP 2 × L
(VOUT + ∆VOUT _ OV )2 − VOUT 2
•
•
•
where:
KOV is a factor typically of 2.
ΔVOUT_OV is the allowable undershoot on the output voltage.
The output ripple is determined by the ESR and the capacitance. Use the following equation to select a capacitor that can
meet the output ripple requirements:
COUT _ RIPPLE =
RESR =
8 × f SW
∆I L
12
The ADP2381 has an integrated low-side MOSFET driver that
drives the low-side NFET. The selection of the low-side NFET
affects the dc-to-dc regulator performance.
where:
KUV is a factor typically of 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
COUT _ OV =
The selected output capacitor voltage rating should be greater
than the output voltage. The rms current rating of the output
capacitor should be larger than the following equation:
Drain-source voltage (VDS) must be higher than
1.2 × VIN.
Drain current (ID) must be greater than 1.2 × ILIMIT_MAX,
which is the selected maximum current-limit threshold.
The ADP2381 low-side gate drive voltage is 8 V. Make sure
that the selected MOSFET can fully turn on at 8 V. Total
gate charge (Qg at 8 V) must be less than 50 nC. Lower Qg
characteristics constitute higher efficiency.
The low-side MOSFET carries the inductor current when
the high-side MOSFET is turned off. For low duty cycle
application, the low-side MOSFET carries the output
current during most of the period. To achieve higher
efficiency, it is important to select a low on-resistance
MOSFET. The power conduction loss of the low-side
MOSFET can be calculated by using the following
equation:
PFET_LOW = IOUT2 × RDSON × (1 – D)
∆I L
× ∆VOUT _ RIPPLE
•
∆VOUT _ RIPPLE
∆I L
where:
ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR is the equivalent series resistance of the output capacitor.
where RDSON is the on resistance of the low-side MOSFET.
Make sure that the MOSFET can handle the thermal
dissipation due to the power loss.
Some recommended MOSFETs are listed in Table 8.
Table 8. Recommended MOSFETs
Vendor
Fairchild
Fairchild
Fairchild
Vishay
AOS
AOS
Part No.
FDS6298
FDS8880
FDM7578
SiA430DJ
AON7402
AO4884L
VDS (V)
30
30
25
20
30
40
ID (A)
13
10.7
14
10.8
39
10
Rev. 0 | Page 17 of 28
RDSON (mΩ)
12
12
8
18.5
15
16
Qg (nC)
10
12
8
5.3
7.1
13.6
ADP2381
Data Sheet
PROGRAMMING INPUT VOLTAGE UVLO
fZ =
The internal voltage divider from PVIN to GND sets the default
start/stop values of the input voltage to achieve undervoltage
lockout (UVLO) performance. The default rising/falling
threshold of PVIN and UVLO are listed in Table 9. These
default values can be replaced by using an external voltage
divider to achieve a more accurate externally adjustable UVLO,
as shown in Figure 32. Lower values of the external resistors are
recommended to obtain a high accuracy UVLO threshold
because the values of the internal 320 kΩ and 125 kΩ resistors
may vary by as much as 20%.
Table 9. Default Rising/Falling Voltage Threshold
Pin
PVIN
UVLO
Rising Threshold (V)
4.28
1.2
Falling Threshold (V)
3.92
1.1
ADP2381
VIN
PVIN
320kΩ
R1
2 × π × RESR × COUT
1
2 × π × (R + RESR ) × COUT
fP =
where:
AVI = 8.7 A/V.
R is the load resistance.
COUT is the output capacitance.
RESR is the equivalent series resistance of the output capacitor.
The external voltage loop is compensated by a transconductance amplifier with a simple external RC network placed either
between COMP and GND or between COMP and FB, as shown
in Figure 33 and Figure 34, respectively.
Compensation Network Between COMP and GND
Figure 33 shows the simplified peak current mode control small
signal circuit with a compensation network placed between
COMP and GND.
VOUT
UVLO
125kΩ
R2
1
VOUT
ADP2381
RTOP
COMP VCOMP
10209-032
FB
RBOT
Figure 32. External Programmable UVLO
(V
IN _ RISING
− 1.2 V ) × R2
1.2 V
R2
R
RC
–
CCP
RESR
CC
GND
Figure 33. Small Signal Circuit with Compensation Network Between COMP
and GND
TV (s) =
+ 1.1 V
where VIN_FALLING is the falling threshold of VIN.
R BOT
−gm
×
×
R BOT + RTOP CC + CCP
1 + RC × C C × s
R ×C ×C
s × 1 + C C CP × s
CC + CCP
× GVD (s)
Use the following design guidelines to select the RC, CC, and CCP
compensation components:
COMPENSATION DESIGN
The ADP2381 uses a peak current-mode control architecture
for excellent load and line transient response. For peak currentmode control, the power stage can be simplified as a voltage
controlled current source, supplying current to the output
capacitor and load resistor. It consists of one domain pole and
one zero contributed by the output capacitor ESR.
•
•
Determine the cross frequency, fC. Generally, fc is between
fSW/12 and fSW/6.
RC can be calculated by
RC =
The control to output transfer function is given by the following
equation:
s
1 +
×
× fZ
2
π
V ( s)
GVD (s) = OUT
= AVI × R ×
s
VCOMP (s)
1+
2 ×π × f P
COUT
The closed-loop transfer function is as follows:
The falling threshold of VIN can be determined by the
following equation:
VIN _ FALLING =
AVI
The RC and CC compensation components contribute a zero,
and the optional CCP and RC contribute an optional pole.
where VIN_RISING is the rising threshold of VIN.
1.1 V × R1
+
10209-033
A 1 kΩ resistor for R2 is an appropriate choice. Use the
following equation to obtain the value of R1 for a chosen input
voltage rising threshold:
R1 =
–
gm
+
•
VREF × g m × AVI
where:
VREF = 0.6 V.
gm = 500 µS.
Place the compensation zero at the domain pole, fP. CC can
be determined by:
CC =
Rev. 0 | Page 18 of 28
2 × π ×VOUT × COUT × fC
(R + RESR ) × COUT
RC
Data Sheet
•
ADP2381
CCP is optional, and it can be used to cancel the zero caused
by the ESR of the output capacitors.
CCP =
RESR × COUT
where:
r0 is the equivalent output impedance of the trans-conductance
amplifier, 40 MΩ.
RTOP // RBOT =
RC
Compensation Network Between COMP and FB
RTOP RBOT
RTOP + RBOT
Solve the preceding equations to obtain:
The compensation RC network can also be placed between
COMP and FB, as shown in Figure 34.
CC _ EA = B × g m −
CCP_EA
RC_EA
RC _ EA =
CC_EA
VOUT
CCP _ EA =
ADP2381
COMP
FB
RBOT
B + RC CC
VOUT
RTOP
–
gm
+
+
AVI
COUT
RESR
B=
10209-034
GND
Figure 34. Small Signal Circuit with Compensation Network Between COMP
and FB
When connecting the compensation network as shown in
Figure 34, it should have the same pole and zero as in Figure 33
to maintain the same compensation performance.
Assuming that the compensation networks of Figure 33 and
Figure 34 have the same pole and zero,
gm
r0 RC CC CCP = r0 RC _ EACC _ EACCP _ EA +
r0 RC CC CCP
( B + RC CC )(r0 + A)
A = (RTOP // R BOT )(1 + g m × r0 )
R
CCP _ EA + CC _ EA
CC _ EA
where:
VCOMP
–
RC CC = RC _ EACC _ EA /
r0 RC CC CCP
( B + RC CC )(r0 + A)
r0 (CCP + CC )
1 + g m ( A + r0 )
ADIsimPower DESIGN TOOL
The ADP2381 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about the ADIsimPower design tools, visit
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
RC _ EACC _ EACCP _ EA (RTOP // RBOT )(1 + g m × r0 )
r0 (CCP + CC ) + RC CC =
r0 (CCP _ EA + CC _ EA ) + RC _ EACC _ EA +
(CCP _ EA + CC _ EA )(RTOP // RBOT )(1 + g m × r0 )
Rev. 0 | Page 19 of 28
ADP2381
Data Sheet
DESIGN EXAMPLE
This section provides the procedures of selecting the external
components based on the example specifications listed in Table 10.
The schematic of this design example is shown in Figure 36.
This results in IPEAK = 7.09 A.
The rms current flowing through the inductor can be calculated
by the following equation:
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter
Input Voltage
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
I RMS I OUT 2
Specification
VIN = 12.0 V ± 10%
VOUT = 3.3 V
IOUT = 6 A
∆VOUT_RIPPLE = 33 mV
±5%, 1 A to 5 A, 2 A/μs
fSW = 500 kHz
This results in IRMS = 6.03 A.
According to the calculated rms and peak inductor current
values, select an inductor with a minimum rms current rating of
6.03 A and a minimum saturation current rating of 7.09 A.
OUTPUT VOLTAGE SETTING
Choose a 10 kΩ resistor as the top feedback resistor (RTOP) and
calculate the bottom feedback resistor (RBOT) by using the
following equation:
0.6
RBOT RTOP
V
OUT 0.6
To protect the inductor from reaching its saturation limit, the
inductor should be rated for at least 9.6 A saturation current for
reliable operation.
Based on these requirements, select a 2.2 μH inductor, such as
the FDVE1040-2R2M from Toko, which has 6.8 mΩ DCR and
11.4 A saturation current.
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple requirement and the load transient response.
To set the output voltage to 3.3 V, the resistors values are
RTOP = 10 kΩ, RBOT = 2.21 kΩ.
To meet the output voltage ripple requirement, use the
following equation to calculate the ESR and capacitance of the
output capacitor:
FREQUENCY SETTING
Connect a 100 kΩ resistor from RT pin to GND to set the
switching frequency at 500 kHz.
COUT _ RIPPLE
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ΔIL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
L
(VIN VOUT ) D
I L
This results in COUT_RIPPLE = 16.5 μF and RESR = 15.1 mΩ.
COUT _UV
K OV I STEP 2 L
(VOUT VOUT _ OV )2 VOUT 2
KUV I STEP 2 L
2 (VIN VOUT ) VOUT _UV
VOUT D
where:
KOV = KUV = 2, the coefficients for estimation purposes.
ΔISTEP = 4 A, the load transient step.
ΔVOUT_OV = 5%VOUT, the overshoot voltage.
ΔVOUT_UV = 5%VOUT, the undershoot voltage.
L f SW
This results in COUT_OV = 63.1 μF and COUT_UV = 24.5 μF.
The peak-to-peak inductor ripple current can be calculated by
the following equation:
IN
VOUT _ RIPPLE
COUT _ OV
This results in L = 2.659 μH. Choose the standard inductor
value of 2.2 μH.
V
RESR
I L
8 f SW VOUT _ RIPPLE
To meet the ±5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
I L f SW
where:
VIN = 12 V.
VOUT = 3.3 V.
D = VOUT/VIN = 0.275.
ΔIL = 1.8A.
fSW = 500 kHz.
I L
I L 2
12
This results in ΔIL = 2.18 A.
The peak inductor current can be calculated using the following
equation:
I PEAK I OUT
I L
2
According to the preceding calculation, the output capacitance
must be larger than 63 μF, and the ESR of the output capacitor
must be smaller than 15 mΩ. It is recommended that one 100
μF, X5R, 6.3 V ceramic capacitor and one 47 μF, X5R, 6.3 V
ceramic capacitor be used, such as the GRM32ER60J107ME20
and GRM32ER60J476ME20 from Murata with an ESR = 2 mΩ.
Rev. 0 | Page 20 of 28
Data Sheet
ADP2381
LOW-SIDE MOSFET SELECTION
This results in
Choose the standard values for RC_EA = 73.2 kΩ, CC_EA = 820 pF,
and CCP_EA = 2.2 pF.
Figure 35 shows the bode plot at 6 A. The cross frequency is
kHz, and the phase margin is 61°.
For a better load transient and stability performance, set the
cross frequency, fC, at fSW/10. In this case, fC = 1/500 kHz =
50 kHz.
CC _ EA
r0 RC CC CCP
= B × gm −
B
RC CC )(r0 + A)
+
(
RC _ EA =
CCP _ EA
B + RC CC
MAGNITUDE (dB)
COMPENSATION COMPONENTS
CC _ EA
r0 RC CC CCP
=
( B + RC CC )(r0 + A)
144
36
108
24
72
12
36
0
0
–12
–36
–24
–72
–36
–108
–48
–144
–180
10k
100k
1M
FREEQUENCY (Hz)
RC =
2 × π × VOUT × COUT × f C
VREF × g m × AVI
0.6 V × 500 μS × 8.7 A /V
CC =
Figure 35. Bode Plot at 6 A
=
2 × π × 3.3V × 94 μF × 50 kHz
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
= 37.3 kΩ
(R + RESR ) × COUT
=
RC
(3.3 V / 6 A + 0.002 Ω) × 94 μF
37.3 kΩ
CCP =
RESR × COUT
RC
=
CSS =
= 1.39 nF
0.002 Ω × 94 μF
37.3 kΩ
1 + g m ( A + r0 )
=
40 MΩ ×(5.04 pF + 1.39 nF)
1 + 500μS × (3.62 × 107 + 40 MΩ)
0.6
=
4 ms × 3.3 μA
0.6 V
= 22 nF
INPUT CAPACITOR SELECTION
A minimum 10 μF ceramic capacitor is required to be placed
near the PVIN pin. In this application, one 10 μF, X5R, 25 V
ceramic capacitor is recommended.
10 kΩ × 2.21 kΩ
RTOP R BOT
(1 + g m × r0 ) =
×
10 kΩ + 2.21 kΩ
RTOP + R BOT
r0 (CCP + CC )
t SS _ EXT × I SS _UP
Choose a standard component value, CSS = 22 nF.
= 5.04 pF
(1 + 500 μS × 40 MΩ) = 3.62 ×107
B=
180
48
–60
1k
where:
A=
60
PHASE (dB)
It is recommended that a 30 V, N-channel MOSFET, such as the
FDS6298 from Fairchild, be used. The RDSON of the FDS6298 at
a 4.5 V driver voltage is 9.4 mΩ, and the total gate charge at 5 V
is 10 nC.
RC_EA = 73.3 kΩ.
CC_EA = 727.6 pF.
CCP_EA = 2.56 pF.
10209-035
A low RDSON N-channel MOSFET is selected as a high efficiency
solution. The breakdown voltage of the MOSFET must be
higher than 1.2 × VIN, and the drain current must be larger than
1.2 × ILIMIT.
SCHEMATIC OF DESIGN EXAMPLE
=
See Figure 36 for a schematic of the design example.
1.46 × 10 −6
Rev. 0 | Page 21 of 28
ADP2381
Data Sheet
CIN
10µF
25V
1
2
3
ROSC
100kΩ
4
5
6
7
CSS
22nF
8
BST
PVIN
SW
PVIN
UVLO
SW
ADP2381
LD
PGOOD
RT
VREG
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
820pF
16
15
CBST
0.1µF
L1
2.2µH
14
M1
FDS6298
13
12
11
VOUT = 3.3V
COUT1
100µF
6.3V
COUT2
47µF
6.3V
CVREG
1µF
10
9
RC_EA
73.2kΩ
RTOP
10kΩ
1%
RBOT
2.21kΩ
1%
10209-036
VIN = 12V
CCP_EA
2.2pF
Figure 36. Schematic of Design Example
Rev. 0 | Page 22 of 28
Data Sheet
ADP2381
EXTERNAL COMPONENTS RECOMMENDATION
Table 11. Recommended External Components for Typical Applications with Compensation Network Between COMP and GND, 6
A Output Current
fSW (kHz)
250
500
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
2.2
2.2
3.3
3.3
4.7
4.7
6.8
1.5
2.2
2.2
2.2
3.3
2.2
1
1.5
1.5
2.2
2.2
3.3
1
1
1
1
1.5
1
1
1
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
COUT (µF) 1
680 + 470
680 + 2 × 100
680 + 2 × 100
680
470
3 × 100
2 × 100
680 + 2 × 100
680 + 2 × 100
680
470
3 × 100
3 × 100
470
470
3 × 100
3 × 100
2 × 100
100
680
470
3 × 100
2 × 100
2 × 100
100 + 47
2 × 100
100
100
100
3 × 100
2 × 100
2 × 100
100 + 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
20
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
15
2.21
3
15
10
10
10
15
2.21
RC (kΩ)
68
56
71.5
71.5
69.8
36
36
47
56
59
47
28
36
62
82
39
56
47
36
75
62
33
25.5
36
36
51
36
47
73.2
43
34.8
43
39
36
47
CC (pF)
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
680
680
680
680
680
680
680
680
680
680
CCP (pF)
150
130
100
91
62
10
6.8
150
130
100
91
10
10
68
56
10
6.8
4.7
3.3
82
68
10
8.2
6.8
4.7
4.7
3.3
2.2
1.8
8.2
6.8
6.8
4.7
3.3
2.2
680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 23 of 28
ADP2381
Data Sheet
Table 12. Recommended External Components for Typical Applications with Compensation Network between COMP and FB, 6 A
Output Current
fSW (kHz)
250
500
1000
1
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
12
12
5
5
5
5
5
5
12
12
12
12
5
5
5
5
5
5
VOUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
1
1.2
1.5
1.8
2.5
3.3
L (µH)
2.2
2.2
3.3
3.3
4.7
4.7
6.8
1.5
2.2
2.2
2.2
3.3
2.2
1
1.5
1.5
2.2
2.2
3.3
1
1
1
1
1.5
1
1
1
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
COUT (µF) 1
680 + 470
680 + 2 × 100
680 + 2 × 100
680
470
3 × 100
2 × 100
680 + 2 × 100
680 + 2 × 100
680
470
3 × 100
3 × 100
470
470
3 × 100
3 × 100
2 × 100
100
680
470
3 × 100
2 × 100
2 × 100
100 + 47
2 × 100
100
100
100
3 × 100
2 × 100
2 × 100
100 + 47
100
100
RTOP (kΩ)
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
20
47.5
10
22
10
10
15
20
47.5
10
RBOT (kΩ)
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
15
2.21
3
15
10
10
10
15
2.21
RC_EA (kΩ)
270
200
287
316
470
71.5
86.6
191
200
240
220
187
71.5
220
330
169
360
93.1
86.6
330
220
130
100
220
71.5
232
240
93.1
169
178
120
178
169
240
93.1
CC_EA (pF)
750
820
680
680
470
1500
1200
750
820
680
680
390
1500
390
390
330
220
680
620
390
390
330
330
220
680
160
100
390
330
180
220
180
160
100
390
CCP_EA (pF)
39
39
22
22
10
4.7
2.2
39
39
22
22
2.2
4.7
22
15
2.2
1
2.2
1.5
22
22
2.2
2.2
1
2.2
1
1
1
1
2.2
2.2
1
1
1
1
680 μF: 4V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 24 of 28
Data Sheet
ADP2381
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential for obtaining the best
performance from the ADP2381. Poor printed circuit board
(PCB) layout degrades the output regulation as well as the
electromagnetic interface (EMI) and electromagnetic
compatibility (EMC) performance. Figure 38 shows a PCB
layout example. For optimum layout, use the following
guidelines:
•
•
Use separate analog ground and power ground planes.
Connect the ground reference of sensitive analog circuitry,
such as output voltage divider components, to analog
ground. In addition, connect the ground reference of
power components, such as input and output capacitors
and a low-side MOSFET, to power ground. Connect both
ground planes to the exposed pad of the ADP2381.
Place the input capacitor, inductor, low-side MOSFET,
output capacitor as close to the IC as possible and use short
traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the
input capacitor through the inductor, the output capacitor,
and the power ground plane back to the input capacitor as
short as possible. To accomplish this, ensure that the input
and output capacitors share a common power ground
VIN
1
2
CIN
3
4
5
ROSC
6
7
CSS
8
•
•
PVIN
BST
PVIN
SW
UVLO
SW
ADP2381
LD
PGOOD
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
16
15
CBST
L
14
COUT
FET
13
12
VOUT
CVREG
11
10
RTOP
9
RBOT
CC_EA
RC_EA
CCP_EA
Figure 37. High Current Path in the PCB Circuit
Rev. 0 | Page 25 of 28
10209-037
•
•
plane. In addition, ensure that the high current path from
the power ground plane through the external MOSFET,
inductor, and output capacitor back to the power ground
plane is as short as possible by tying the MOSFET source
node to the PGND plane as close as possible to the input
and output capacitors.
Make the low-side driver path from the LD pin of the
ADP2381 to the external MOSFET gate node and back to
the PGND pin of the ADP2381 as short as possible, and
use a wide trace for better noise immunity.
Connect the exposed pad of the ADP2381 to a large copper
plane to maximize its power dissipation capability for
better thermal dissipation.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Try to
minimize the length of the trace that connects the top of
the feedback resistor divider to the output while keeping
the trace away from the high current traces and the
switching node to avoid noise pickup. To further reduce
noise pickup, place an analog ground plane on either side
of the FB trace and ensure that the trace is as short as
possible to reduce parasitic capacitance pickup.
ADP2381
Data Sheet
PVIN
POWER GROUND PLANE
Input
Bulk Cap
Bottom Layer
Trace
Output
Capacitor
Input
Bypass
Cap
Pull Up
BST
PVIN
SW
UVLO
SW
CBST
INDUCTOR
VOUT
SW
LD
RT
VREG
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
Copper Plane
LOW-SIDE
MOSFET
PVIN
PGOOD
VIA
CVREG
RC_EA
CSS
RTOP
ROSC
10209-038
CCP_EA
RBOT
ANALOG GROUND PLANE
Figure 38. Recommended PCB Layout
Rev. 0 | Page 26 of 28
Data Sheet
ADP2381
TYPICAL APPLICATION CIRCUITS
VIN = 12V
1
CIN
10µF
25V
2
3
PVIN
SW
SW
ADP2381
LD
PGOOD
5
VREG
RT
6
7
CSS
22nF
BST
UVLO
4
ROSC
100kΩ
PVIN
8
SYNC
PGND
EN/SS
GND
COMP
FB
16
L1
1µH
CBST
0.1µF
15
VOUT = 1.2V
COUT
470µF
6.3V
14
M1
FDS6298
13
12
11
CVREG
1µF
RTOP
10kΩ
1%
10
9
RBOT
10kΩ
1%
RC
62kΩ
CCP
68pF
10209-039
CC
1.5nF
Figure 39. Compensation Network Between COMP and GND, VIN = 12 V, VOUT = 1.2 V, IOUT = 6 A, fSW = 500 kHz
CIN
10µF
25V
1
R1
7.32kΩ
1%
2
3
R2
1kΩ R
OSC
1% 100kΩ
4
5
6
7
CSS
22nF
8
PVIN
BST
PVIN
SW
UVLO
16
15
12
VREG
RT
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
330pF
M1
FDS6298
13
LD
PGOOD
VOUT = 1.8V
COUT1
100µF
6.3V
14
SW
ADP2381
L1
1.5µH
CBST
0.1µF
11
COUT2
100µF
6.3V
COUT3
100µF
6.3V
CVREG
1µF
RTOP
20kΩ
1%
10
9
RBOT
10kΩ
1%
RC_EA
169kΩ
10209-040
VIN = 12V
CCP_EA
2.2pF
Figure 40. Programming Input Voltage UVLO Rising Threshold at 10 V, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 500 kHz
CIN
10µF
25V
1
2
3
ROSC
82kΩ
4
5
6
7
8
BST
PVIN
SW
PVIN
UVLO
SW
ADP2381
LD
PGOOD
RT
VREG
SYNC
PGND
EN/SS
GND
COMP
FB
CC_EA
620pF
16
15
CBST
0.1µF
L1
3.3µH
14
M1
FDS6298
13
12
11
VOUT = 5V
COUT
100µF
6.3V
CVREG
1µF
10
9
RC_EA
86.6kΩ
CCP_EA
1.5pF
RTOP
22kΩ
1%
RSOT
3kΩ
1%
10209-041
VIN = 12V
Figure 41. Using Internal Soft Start, Programming Switching Frequency at 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 6 A, fSW = 600 kHz
Rev. 0 | Page 27 of 28
ADP2381
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
3.40
2.68
9
16
16
9
4.50
4.40
4.30
2.46
1.75
EXPOSED
PAD
1
6.40 BSC
8
1
BOTTOM VIEW
TOP VIEW
0.95
0.90
0.85
1.10 MAX
SEATING
PLANE
0.30
0.19
0.65 BSC
0.20
0.09
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.25
0.15 MAX
0.05 MIN
COPLANARITY
0.076
8°
0°
0.70
0.60
0.50
08-03-2010-A
8
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 42. 16-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP2381AREZ-R7
ADP2381AREZ
ADP2381-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP_EP
16-Lead TSSOP_EP
Evaluation Board
Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10209-0-3/12(0)
Rev. 0 | Page 28 of 28
Package Option
RE-16-4
RE-16-4
Packing
Reel
Tube
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