ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
UG-758
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the ADP5070/ADP5071 DC-to-DC Switching Regulators/Converters
FEATURES
GENERAL DESCRIPTION
Input voltage range: 3 V to 13.2 V
Output current:
ADP5070: up to 480 mA (VPOS), up to 140 mA (VNEG),
depending on VIN
ADP5071: up to 1020 mA (VPOS), up to 320 mA (VNEG),
depending on VIN
Output voltage: ±15 V
Output voltage with low dropout (LDO) regulators: ±12 V
The ADP5070CP-EVALZ and ADP5071CP-EVALZ evaluation
boards demonstrate the functionality of the ADP5070 and
ADP5071 dc-to-dc converters, respectively.
EVALUATION KIT CONTENTS
ADP5070CP-EVALZ or ADP5071CP-EVALZ evaluation board
ADDITIONAL EQUIPMENT NEEDED
DC power supply
Multimeters for voltage and current measurements
Electronic or resistive loads
Use either board to evaluate simple device measurements, such
as line regulation, load regulation, and efficiency. Device features
can be demonstrated, such as selectable operating frequency,
soft start, sequencing, and slew rate control. The ADP7142 and
ADP7182 LDO regulators are also available on the boards as an
option for enhanced low noise output.
For more details about the dc-to-dc converters, refer to the
ADP5070 and ADP5071 data sheets. For further information on
the LDO regulators, refer to the ADP7142 and ADP7182 data
sheets. Use these data sheets in conjunction with this user guide.
12653-001
EVALUATION BOARD PHOTOGRAPH
Figure 1. ADP5070CP-EVALZ/ADP5071CP-EVALZ LFCSP Evaluation Board
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. A | Page 1 of 12
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ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Voltage Measurements ........................................................6
Evaluation Kit Contents ................................................................... 1
Line Regulation..............................................................................6
Additional Equipment Needed ....................................................... 1
Load Regulation ............................................................................7
General Description ......................................................................... 1
Efficiency ........................................................................................7
Evaluation Board Photograph......................................................... 1
Evaluation Board Schematics...........................................................8
Revision History ............................................................................... 2
Ordering Information .......................................................................9
Evaluation Board Hardware ............................................................ 3
Bill of Materials ..............................................................................9
Evaluation Board Configurations .............................................. 3
REVISION HISTORY
4/2018—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Added Figure 5 and Figure 6, Changes to Table 1 ........................ 5
Changes to Evaluation Board Configurations Section ................ 3
Changes to Output Voltage Measurements Section ..................... 6
Changes to Efficiency Section, Figure 9, Figure 10 ...................... 7
Changes to Figure 13 and Figure 14 ............................................... 8
Changes to Table 4 .......................................................................... 12
3/2015—Revision 0: Initial Version
Rev. A | Page 2 of 13
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
UG-758
EVALUATION BOARD HARDWARE
EVALUATION BOARD CONFIGURATIONS
The evaluation boards are configured to provide a ±15 V output
from a 3 V to 13.2 V input. The optional LDO regulators are
configured for a 12 V output (ADP7142) and a −12 V output
(ADP7182).
Table 2 and Table 3 list the components for the ADP5070 and
ADP5071 boards, respectively.
Table 4 lists the components common to both designs, including
the ADP7142 and ADP7182 LDO regulators.
The boards allow the end user to customize the design; refer to
the ADP5070 and ADP5071 data sheets or to the ADIsimPower
tools to obtain alternative component values. If the design is
customized, it is possible to obtain more than 70 V between the
positive and negative terminals on the boards. Proper design
customization can achieve an output current of more than 1 A for
the boost regulator and more than 300 mA for the inverting
regulator. It is the responsibility of the end user to ensure the
boards are suitable for such a design and to take appropriate
safety precautions.
Figure 2 outlines the board features available to the user.
Figure 3 and Figure 4 highlight the ADP5070/ADP5071 and
supporting components, including locations for optional components if the user wants to modify the design. Figure 5 and
Figure 6 show the maximum output current for this design of
the evaluation board.
ADP5070/ADP5071
POSITIVE LDO VIN;
INSERT JUMPER TO CONNECT
TO ADP5070/ADP5071 OUTPU T;
LOWER PIN IS VIN
+
OUTPUT
GND –
NEGATIVE LDO VIN;
INSERT JUMPER TO CONNECT
TO ADP5070/ADP5071 OUTPU T;
LOWER PIN IS VIN
NEGATIVE LDO OUTPUT
POSITIVE LDO OUTPUT
ADP7182 NEGATIVE LDO;
OPTIONAL FOR LOW NOISE
APPLICATIONS;
CONNECT LN_VIN TO USE
ADP7142 POSITIVE LDO;
OPTIONAL FOR LOW
NOISE APPLICATIONS;
CONNECT LP_VIN TO USE
NEGATIVE LDO EXTERNAL ENABLE;
AN EXTERNAL ENABLE CAN BE
CONNECTED TO LN_EN IF
J_LN_EN IS REMOVED
POSITIVE LDO
EXTERNAL ENABLE;
AN EXTERNAL ENABLE
CAN BE CONNECTED TO
LP_EN IF J_LP_EN
IS REMOVED
ADP5070/ADP5071
POWER INPUT
SWITCHING FREQUENCY;
EXTERNAL CLOCK CAN
BE CONNECTED TO
CENTER PIN
(5.5V MAXIMUM)
SEQUENCING;
SEQUENCED = AGND
SIMULTANEOUS = VREG
MANUAL = NO CONNECT
SLEW RATE;
SLOW = AGND
NORMAL = VREG
FAST = NO
CONNECT
POSITIVE AND NEGATIVE ENABLES;
ADP5070/ADP5071
OUTPUT ENABLES CAN BE
CONNECTED EXTERNALLY TO
CENTER PIN (5.5V MAXIMUM)
SOFT START;
RSS CONTROLS RATE
REMOVE JUMPER TO
DISCONNECT RESISTOR
Figure 2. Outline of ADP5070/ADP5071 Evaluation Board Features
Rev. A | Page 3 of 12
12653-002
ENABLE PROTECTION;
IN COMBINATION WITH R7,
R8 AND CR1 PROVIDE
SUITABLE ENABLE VOLTAGE
ACROSS V IN RANGE TO ON
POSITION ON EN HEADERS;
DISCONNECT V_EN AND
POWER ENABLES
EXTERNALLY FOR EFFICIENCY
MEASUREMENT
UG-758
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
BOOST OUTPUT
CAPACITOR
(1210)
INVERTER OUTPUT
CAPACITOR
(1210)
INVERTER INDUCTOR
(COILCRAFT XAL40xx)
INVERTER DIODE
(POWERDI123)
BOOST DIODE
(POWERDI123)
INPUT CAPACITOR
(1206)
ADP5070/ADP5071
(20-LEAD LFCSP)
BOOST INDUCTOR
(COILCRAFT XAL40xx)
BOOST
COMPENSATION
RESISTOR AND
CAPACITOR (0603)
INVERTER
COMPENSATION
RESISTOR AND
CAPACITOR (0603)
INVERTER
FEEDBACK
RESISTORS (0805)
RFT2 = TOP
RFB2 = BOTTOM
12653-003
VREG AND VREF
INTERNAL SUPPLY
DECOUPLING
CAPACITORS
(0805)
BOOST FEEDBACK
RESISTORS (0805)
RFT1 = TOP
RFB1 = BOTTOM
Figure 3. ADP5070/ADP5071 Top Component Detail
OPTIONAL ADDITIONAL
OUTPUT CAPACITORS
COMPENSATION MODE
CONNECT THE CENTER TERMINAL OF JP5 AND JP6 TOWARD THE
CENTER OF THE BOARD (DOTTED PIN) FOR TYPE 2 COMPENSATION.
FIT ADDITIONAL COMPONENTS AND CONNECT TOWARD THE EDGE
OF THE BOARD FOR TYPE 3.
Figure 4. Bottom of Evaluation Printed Circuit Board (PCB) Showing Locations for Optional Components
Rev. A | Page 4 of 12
12653-004
TYPE 3
COMPENSATION
COMPONENTS
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
ADP5070,
ADP5070,
ADP5071,
ADP5071,
MAXIMUM OUTPUT CURRENT (A)
1.2
1.1
0.40
fSW = 1.2MHz, 6.8µH
fSW = 2.4MHz, 6.8µH
fSW = 1.2MHz, 4.7µH
fSW = 2.4MHz, 4.7µH
ADP5070,
ADP5070,
ADP5071,
ADP5071,
0.35
MAXIMUM OUTPUT CURRENT (A)
1.3
UG-758
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
fSW = 1.2MHz, 15µH
fSW = 2.4MHz, 15µH
fSW = 1.2MHz, 6.8µH
fSW = 2.4MHz, 6.8µH
0.30
0.25
0.20
0.15
0.10
0.05
3
4
5
6
7
8
9
10
11
12
INPUT VOLTAGE (V)
13
14
0
12653-105
0
3
4
5
6
7
8
9
10
INPUT VOLTAGE (V)
Figure 5. Boost Regulator Maximum Output Current (A) vs. Input Voltage (V)
11
12
13
14
12653-106
0.1
Figure 6. Inverting Regulator Maximum Output Current (A) vs. Input Voltage (V)
Table 1. Evaluation Board Function Descriptions
Jumper/Connector
Mnemonic
VIN
POS
NEG
V_EN
EN1
EN2
SYNC/FREQ
SEQ
SLEW
SS
LDO POS
LP_VIN
LP_EN
LDO NEG
LN_VIN
LN_EN
Description
Power supply to the ADP5070/ADP5071. In the default configuration, this ranges from 3 V to 5.5 V.
Output from boost regulator of the ADP5070/ADP5071. 15 V in default configuration.
Output from inverting regulator of the ADP5070/ADP5071. −15 V in default configuration.
Provides a clamped enable voltage to allow the boards to operate using input voltages greater than 5.5 V without
damaging the EN1 and EN2 pins. For efficiency measurements, remove this jumper and provide an enable signal
from an external supply.
Boost regulator precision enable. The voltage in the EN1 pin is compared to an internal precision reference to
enable the boost regulator output. Connect the EN1 jumper to the on position to turn on the boost regulator.
Connect this jumper to the off position or remove this jumper to turn the regulator off (an internal pulldown is
present in the ADP5070/ADP5071). Connect an external enable voltage below the lesser of 5.5 V and VIN to the
center pin during efficiency measurement and remove the V_EN jumper.
Inverting regulator precision enable. The voltage in the EN2 pin is compared to an internal precision reference to
enable the inverting regulator output. Connect the EN2 jumper to the on position to turn on the inverting
regulator. Connect this jumper to the off position or remove this jumper to turn the regulator off (an internal
pulldown is present in the ADP5070/ADP5071). Connect an external enable voltage below the lesser of 5.5 V and
VIN to the center pin during efficiency measurement and remove the V_EN jumper.
Synchronization input and frequency setting. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high.
To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency,
connect the SYNC/FREQ pin to an external clock (5.5 V maximum).
Start-up sequence control. For manual VPOS/VNEG startup using an individual precision enabling pin, leave the SEQ
pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to VREG (use the EN1
pin to enable internal references early, if required). For a sequenced startup, pull the SEQ pin low. Use either EN1
or EN2 to enable VPOS or VNEG and the corresponding supply is the first in sequence; hold the other enable pin low.
Driver stage slew rate control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew
rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the
slowest slew rate (best noise performance), connect the SLEW pin to AGND.
Soft start programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start
time, connect the SS jumper. The SS jumper connects the RSS resistor between the SS pin and AGND.
Positive output of the ADP7142 LDO regulator. Connect LP_VIN to use the external positive LDO regulator. Set to
12 V in the default configuration.
Connects the positive output of the ADP5070/ADP5071 to the ADP7142 LDO regulator.
Use as an external enable for the ADP7142 LDO regulator if J_LP_EN is removed.
Negative output of the ADP7182 LDO regulator. Connect LN_VIN to use the external negative LDO regulator. Set
to −12 V in the default configuration.
Connects the negative output of the ADP5070/ADP5071 to the ADP7182 LDO regulator.
Use as an external enable for the ADP7182 LDO regulator if J_LN_EN is removed.
Rev. A | Page 5 of 12
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ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
OUTPUT VOLTAGE MEASUREMENTS
2.
3.
4.
5.
6.
Connect the negative (−) terminal of the voltage source to
the GND terminal of the power input connector on the
right side of the evaluation board.
Connect the positive (+) terminal of the voltage source to
the VIN terminal of the power input connector on the
right side of the evaluation board.
Connect a load between the POS or NEG terminal and
GND terminal at the output connector (center top of the
PCB).
Connect the voltmeter across the selected output terminal
and ground in parallel with the load resistor.
Turn the voltage source on. If the EN1 or EN2 jumper is in
the on position, the respective boost or inverting regulator
powers up.
Disconnect the SEQ jumper.
If the load current is large, the user must connect the voltmeter as
close as possible to the output capacitor to reduce the effects of
voltage drops due to PCB trace impedance.
0.5
VOUT ACCURACY
FBx VOLTAGE ACCURACY
0.3
0.1
–0.1
–0.3
–0.5
0
5
10
15
20
VIN (V)
12653-005
1.
Figure 7. Boost Regulator Line Regulation, VPOS = 15 V, fSW = 1.2 MHz,
15 mA Load, TA = 25°C (Nominal Defined as Average Value Within a Range of
10% to 90% VIN)
0.5
If long power leads are used from the power supply, especially at
higher loads, connect a large capacitor (10,000 μF or more)
across the VIN terminals to prevent losses from lead inductance.
Measure the input voltage at these terminals or use a power
supply with a 4-wire supply and sense arrangement.
VOUT ACCURACY
VREF ACCURACY
FBx VOLTAGE ACCURACY
0.3
0.1
–0.1
–0.3
–0.5
0
5
10
VIN (V)
15
20
12653-006
Follow these steps to connect to a voltage source and voltmeter:
For line regulation measurements, monitor the regulator
output while its input is varied. For good line regulation, the
output must change as little as possible with varying input
levels. It is possible to repeat this measurement under different
load conditions. During line regulation tests, keep the power
supply leads short and remove any additional input capacitor.
Figure 7 and Figure 8 show the typical line regulation performance
of the ADP5070/ADP5071 at both the output and feedback pins.
VARIATION FROM NOMINAL (%)
Ensure that the resistor has an adequate power rating to handle
the expected power dissipation. Use an electronic load as an
alternative. Ensure that the voltage source supplies enough
current for the expected load levels, taking into account the
device efficiency.
LINE REGULATION
VARIATION FROM NOMINAL (%)
For basic output voltage accuracy measurements, connect the
evaluation board to a voltage source and a voltmeter. Use a
resistor as the load for the regulator.
Figure 8. Inverting Regulator Line Regulation, VNEG = −15 V, fSW = 1.2 MHz,
15 mA Load, TA = 25°C (Nominal Defined as Average Value Within a Range of
10% to 90% VIN)
Rev. A | Page 6 of 12
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
UG-758
LOAD REGULATION
EFFICIENCY
For load regulation measurements, monitor the regulator output
while the load is varied. For good load regulation, the output
must change as little as possible with varying loads. The input
voltage must be held constant during this measurement. Figure 9
and Figure 10 show the typical load regulation performance of the
ADP5070/ADP5071 at both the output and feedback pins. Keep
power leads short during this test and use a power supply with
remote sense.
For efficiency measurements, monitor the regulator input and
output while the load is varied. The input voltage must be held
constant during this measurement. Keep power leads short during
this test and use a power supply with remote sense. Connect
ammeters in series with the input and output. Connect voltmeters
to the PCB side of the ammeter and measure the voltage across the
input and output terminals. For the best results, measure the
voltage across the input and output capacitors. If possible, particularly at low current, trigger the meters simultaneously and set
the meters to average readings for a period of a few hundred
milliseconds or more. Averaging the readings removes the
switching ripple and skip mode effects. Figure 11 and Figure 12
show typical efficiency curves using 5 V and 12 V inputs.
LOAD REGULATION (% CHANGE IN VFB1)
1.2MHz
2.4MHz
100
90
80
12653-007
EFFICIENCY (%)
70
40
30
Figure 9. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V (Nominal
Defined as Average Value Within a Range of 65% to 75% Maximum Load)
20
VIN = 5V, fSW = 1.2MHz
VIN = 5V, fSW = 2.4MHz
VIN = 12V, fSW = 1.2MHz
VIN = 12V, fSW = 2.4MHz
10
0.50
1.2MHz
2.4MHz
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
0.30
Figure 11. Boost Regulator Efficiency vs. Load Current, VPOS = 15 V, TA = 25°C
100
0.10
90
80
VIN = 5V, fSW = 1.2MHz
VIN = 5V, fSW = 2.4MHz
VIN = 12V, fSW = 1.2MHz
VIN = 12V, fSW = 2.4MHz
–0.10
EFFICIENCY (%)
70
–0.30
0
0.05
LOAD (A)
0.10
60
50
40
30
20
Figure 10. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V (Nominal
Defined as Average Value Within a Range of 65% to 75% Maximum Load)
10
0
0.001
0.01
0.1
LOAD CURRENT (A)
1
12653-112
–0.50
12653-008
LOAD REGULATION (% VARIATION IN VREF TO VFB2)
50
12653-111
LOAD (A)
60
Figure 12. Inverting Regulator Efficiency vs. Load Current, VNEG = −15 V, TA = 25°C
Rev. A | Page 7 of 12
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ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
EVALUATION BOARD SCHEMATICS
ADP5070_VOUT
1
2
3
OUTPUT SCREW TERMINALS
MC000045
VNEG
VPOS
DC - DC CONVERTER
DNI
COUT2B
DNI PGND
COUT1B
COMP1
STAR AT CVIN1 CAP
COUT2
COUT1
10UF
10UF
D2
DFLS240-7
D1
DFLS240-7
PGND
15UH
CHF3
TBD0402
DNI
AGND
RC1
RC2
12K
10K
CHF4
TBD0402
DNI
CVREG
GND
AGND
VREF
FB2
1UF
1
A
2
COM
3
B
PAD
20
19
18
17
16
EN1
SS
EN2
COMP2
COMP1
RFB1
137K
B
COM
A
SW1
SW2
1UF
VREG
CVREF
JP5
JP6
3PIN_SOLDER_JUMPER
3PIN_SOLDER_JUMPER
RFB2
118K
RFT2
CFF1
TBD0402
FB2
FB1
PGND
15
PVIN1
14
VREG
13
AGND
12
VREF
11
FB2
6
COMP1
7
EN1
8
SS
9
EN2
10
COMP2
RFF1
TBD0402
DNI
CTB0308/2
10UF
1
2
3
RFT1
2.43MEG
1
2
U1
INBK 1
INBK
2
SYNC/FREQ
3
SEQ
4
SLEW
5
FB1
FB1
SYNC
SEQ
SLEW
CC2
0.068UF
CC1
0.047UF
VIN
VIN
CIN1
PAD
SW1
PGND
SW2
PVIN2
PVINSYS
L1
6.8UH
2.32MEG
ADP5070ACPZ-R7
RFF2
TBD0402
DNI
CFF2
TBD0402
DNI
PGND
VNEG ENABLE
VPOS ENABLE
V_EN
VREG
1
2
EN2
SYNC
SEQ
1
2
3
SEQ
3
22-03-2031
SOFT START TIME
RESISTOR VALUES TBD
VREG
EN2
1
2
3
SYNC SELECT
SEQUENCE SELECT
V_EN
EN1
EN1
GND
L2
GND
DNI
COMP2
TBD1210
TBD1210
22-03-2031
SS
1
2
2
3
RSS
49.9K
22-03-2031
69157-102HLF
REMOVE JUMPER FOR DEFAULT
VIN
22-03-2031
SS
1
SYNC
GND
GND
V_EN
GND
GND
GND
1
2
69157-102HLF
R7
SLEW RATE SELECT
14.3K
VREG
V_EN
SLEW
1
2
3
SLEW
CR1
MMSZ5233BS-7-F
22-03-2031
12653-113
R8
11K
GND
GND
Figure 13. Evaluation Board Schematic for the ADP5070/ADP5071
NEGATIVE SUPPLY LDO - 12V OUT
LN_VIN
2.2UF
CIN4
COUT4
2.2UF
GND
U3
VNEG
1
J_LN_EN
4
VIN
LDO_NEG
EN
ADJ
LN_EN
VOUT
5
1
2
GND
1
ADP7182AUJZ
0.1UF
3
2
CNR4
1
2
MC000044
GND
RNR4
619
GND
Figure 14. Evaluation Board Schematic for the Optional LDO Regulators (LFCSP Package Version)
Rev. A | Page 8 of 12
12653-114
RFB4
69157-102
RFT4
2
52.3K
LN_VIN
5.9K
1
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
UG-758
ORDERING INFORMATION
BILL OF MATERIALS
Table 2. Evaluation Board Components—ADP5070 Version
Component
U1
COUT1
COUT2
L1
L2
D1
Package
LFCSP
1210
1210
XAL40xx
XAL40xx
PowerDi123
Description
ADP5070 LFCSP
VOUT1 capacitor
VOUT2 capacitor
VOUT1 inductor
VOUT2 inductor
VOUT1 diode
Value
ADP5070
10 μF
10 μF
6.8 μH
15 μH
Schottky
D2
PowerDi123
VOUT2 diode
Schottky
CC1
603
47 nF
10%
10 V
CC2
603
68 nF
10%
10 V
RC1
603
12 kΩ
1%
RC2
603
10 kΩ
1%
RFT1
805
2.43 MΩ
1%
RFB1
805
137 kΩ
1%
RFT2
805
2.32 MΩ
1%
RFB2
805
118 kΩ
1%
CIN1
CVREG
CVREF
JP5
1206
805
805
10 μF
1 μF
1 μF
Bridge dot
side
Bridge dot
side
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
10%
10%
10%
COUT1B
1210
Boost regulator
compensation
capacitor
Inverting regulator
compensation
capacitor
Boost regulator
compensation resistor
Inverting regulator
compensation resistor
VOUT1 top feedback
resistor
VOUT1 bottom feedback
resistor
VOUT2 top feedback
resistor
VOUT2 bottom feedback
resistor
CIN capacitor
VREG capacitor
VREF capacitor
Solder jumper
Compensation 1
Solder jumper
Compensation 2
VOUT1 capacitor
COUT2B
1210
VOUT2 capacitor
CHF3
603
CHF4
603
CFF1
603
CFF2
603
RFF1
805
Compensation 1 high
frequency capacitor
Compensation 2 high
frequency capacitor
Feedforward
Capacitor 1
Feedforward
Capacitor 2
Feedforward Resistor 1
RFF2
805
Feedforward Resistor 2
JP6
Tolerance
Voltage
Part Number
10%
10%
20%
20%
50 V
50 V
40 V
GRM32ER71H106KA12L
GRM32ER71H106KA12L
XAL4030-682ME
XAL4030-153ME
DFLS240
40 V
DFLS240
10%
10%
10%
10%
10%
10%
1%
1%
Rev. A | Page 9 of 12
25 V
10 V
10 V
TMK316B7106KL-TD
GRM188R71A105KA61D
GRM188R71A105KA61D
Manufacturer
Analog Devices, Inc.
Murata
Murata
Coilcraft
Coilcraft
Diodes
Incorporated
Diodes
Incorporated
Taiyo Yuden
Murata
Murata
UG-758
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
Table 3. Evaluation Board Components—ADP5071 Version
Component
U1
COUT1
COUT2
L1
L2
D1
Package
LFCSP
1210
1210
XAL40xx
XAL40xx
PowerDi123
Description
ADP5071 LFCSP
VOUT1 capacitor
VOUT2 capacitor
VOUT1 inductor
VOUT2 inductor
VOUT1 diode
Value
ADP5071
10 μF
10 μF
4.7 μH
6.8 μH
Schottky
D2
PowerDi123
VOUT2 diode
Schottky
CC1
603
47 nF
10%
10 V
CC2
603
47 nF
10%
10 V
RC1
603
5.6 kΩ
1%
RC2
603
6.8 kΩ
1%
RFT1
805
2.43 MΩ
1%
RFB1
805
137 kΩ
1%
RFT2
805
2.32 MΩ
1%
RFB2
805
118 kΩ
1%
CIN1
CVREG
CVREF
JP5
1206
805
805
10 μF
1 μF
1 μF
Bridge dot
side
Bridge dot
side
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
Not
installed
10%
10%
10%
COUT1B
1210
Compensation 1
capacitor
Compensation 2
capacitor
Compensation 1 zero
resistor
Compensation 2 zero
resistor
VOUT1 top feedback
resistor
VOUT1 bottom feedback
resistor
VOUT2 top feedback
resistor
VOUT2 bottom feedback
resistor
CIN capacitor
VREG capacitor
VREF capacitor
Solder jumper
Compensation 1
Solder jumper
Compensation 2
VOUT1 capacitor
COUT2B
1210
VOUT2 capacitor
CHF3
603
CHF4
603
CFF1
603
CFF2
603
RFF1
805
Compensation 1 high
frequency capacitor
Compensation 2 high
frequency capacitor
Feedforward
Capacitor 1
Feedforward
Capacitor 2
Feedforward Resistor 1
RFF2
805
Feedforward Resistor 2
JP6
Tolerance
Voltage
Part Number
10%
10%
20%
20%
50 V
50 V
40 V
GRM32ER71H106KA12L
GRM32ER71H106KA12L
XAL4030-472ME
XAL4030-682ME
DFLS240
40 V
DFLS240
10%
10%
10%
10%
10%
10%
1%
1%
Rev. A | Page 10 of 12
25 V
10 V
10 V
TMK316B7106KL-TD
GRM188R71A105KA61D
GRM188R71A105KA61D
Manufacturer
Analog Devices
Murata
Murata
Coilcraft
Coilcraft
Diodes
Incorporated
Diodes
Incorporated
Taiyo Yuden
Murata
Murata
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
UG-758
Table 4. Evaluation Board Components—LDO Regulators and Miscellaneous Components
Component
U3
Package
LFCSP
Description
ADP7142 positive LDO
Value
ADP7142
Tolerance
Voltage
Part Number
ADP7142
Manufacturer
Analog
Devices
CIN4
0805
2.2 μF
10%
25 V
COUT3
0805
2.2 μF
10%
25 V
RFT3
0603
90.9 kΩ
1%
RFB3
0603
10 kΩ
1%
CNR3
0603
100 nF
10%
RNR3
0603
1 kΩ
1%
CSS3
0805
1 nF
10%
J_LP_EN
U2
0603
LFCSP
Positive LDO input
capacitor
Positive LDO output
capacitor
Positive LDO top
feedback resistor
Positive LDO bottom
feedback resistor
Positive LDO noise
reduction capacitor
Positive LDO noise
reduction resistor
Positive LDO soft start
capacitor
Enable jumper
ADP7182 negative LDO
Any
Any
ADP7182
Analog
Devices
CIN3
0805
2.2 μF
10%
25 V
COUT4
0805
2.2 μF
10%
25 V
RFT4
0603
5.9 kΩ
RFB4
0603
CNR4
0603
RNR4
0603
J_LN_EN
RSS
CR1
0603
0603
SOD123
Negative LDO input
capacitor
Negative LDO output
capacitor
Negative LDO top
feedback resistor
Negative LDO bottom
feedback resistor
Negative LDO noise
reduction capacitor
Negative LDO noise
reduction resistor
Enable jumper
Soft start resistor
Enable Zener diode
1%
Any
Any
52.3 kΩ
1%
Any
Any
100 nF
10%
Any
Any
619 Ω
1%
Any
Any
0 Ω link
49.9 kΩ
MMSZ5233B-7-F
1%
Any
MMSZ5233B-7-F
Any
Any
Any
Any
Diodes
Incorporated
Any
Any
Any
R7
R8
SYNC/FREQ, SEQ,
SLEW, EN1, EN2
LP_VIN, LN_VIN, SS
0603
0603
2.54 mm
Enable divider resistor
Enable divider resistor
Option headers
14.3 kΩ
11 kΩ
3-pin header
2.54 mm
Option headers
2-pin header
Any
Any
25 V
25 V
0 Ω link
ADP7182
Rev. A | Page 11 of 12
25 V
6V
1%
1%
UG-758
ADP5070CP-EVALZ/ADP5071CP-EVALZ User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
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not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
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AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
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registered trademarks are the property of their respective owners.
UG12653-0-4/18(A)
Rev. A | Page 12 of 12
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