Backlight Driver with I/O Expander
ADP5520
Data Sheet
FEATURES
TYPICAL OPERATING CIRCUIT
1µF
VBAT
1µF
4.7µH
1 PGND
2.2kΩ
2.2kΩ
10kΩ
2
22
23
SW
BST
BL_SNK
CAP_OUT 20
21 VBAT
I/O RAIL
10kΩ
1µF
16 VDDIO
GND 19
GND 18
ADP5520
5 SCL
GND 24
4 SDA
100nF
3 INT
CMP_IN 17
15 RST
6
I/O
13
7
8
9
10
11
12
A
B
C
D
E
F
G
H
ILED
VBAT
14
VBAT
Figure 1.
APPLICATIONS
Display backlight driver for phones that require slider or flip
keypad functions with single or multiple LED indicators
GENERAL DESCRIPTION
The ADP5520 is a versatile single-chip, white LED backlight
driver with a user configurable I/O expander. This device fits
handset applications where the flip or slider section of the phone
requires backlighting, I/O signaling and detecting, auxiliary LED
lighting, and keypad functions. By incorporating an I2Ccompatible serial interface and a single line interrupt, the
ADP5520 significantly reduces the total number of lines
required to interface with the baseband processor across the
hinge flex.
Rev. B
The ADP5520 can detect ambient light levels and adjust the
backlight brightness accordingly, resulting in extended battery
operation.
Once configured, the ADP5520 is capable of controlling the
flip/slider backlight intensity, on/off timing, dimming, and
fading without the intervention of the main processor, which
results in valuable battery power saving.
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Tel: 781.329.4700 ©2008–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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07445-001
R3 R2 R1 R0 C0 C1 C2 C3
I/O
Efficient asynchronous boost converter for driving up to
6 white LEDs
2.7 V to 5.5 V input voltage range
128 programmable backlight LED current levels (30 mA
maximum)
Ambient light sensing with autonomous backlight
adjustment
Programmable backlight fade-in/fade-out times
Programmable backlight dim and off times
8 configurable GPIO pins (input, output, up to 4 × 4 keypad)
Up to 3 auxiliary LED current sinks (1 dedicated, 2 configurable)
64 programmable auxiliary LED current levels (14 mA
maximum)
Programmable auxiliary LED fade-in/fade-out times
Programmable auxiliary LED on and off times (allows
blinking)
I2C-compatible serial interface
Interrupt line for signaling an external processor (INT)
Hard reset (RST)
Current limit protection
Thermal overload protection
Available in small 4.0 mm × 4.0 mm, 24-lead LFCSP package
ADP5520
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Advanced Fading (Square) ........................................................ 13
Applications ....................................................................................... 1
Advanced Fading (Cubic 1 and Cubic 2) ................................ 14
Typical Operating Circuit ................................................................ 1
Ambient Light Sensing .............................................................. 14
General Description ......................................................................... 1
Automatic Backlight Adjustment ............................................. 15
Revision History ............................................................................... 2
I/O Expansion Pins (GPIOs) .................................................... 15
Specifications..................................................................................... 3
I/O Expansion Pins (Keypad Matrix) ...................................... 15
I C Timing Specifications ............................................................ 4
Absolute Maximum Ratings............................................................ 5
I/O Expansion Pins and ILED Pin (Auxiliary LED Current
Sinks)............................................................................................ 17
Thermal Resistance ...................................................................... 5
Interrupt Output (INT) ............................................................. 19
ESD Caution .................................................................................. 5
Reset Input (RST) ....................................................................... 19
Pin Configuration and Function Descriptions ............................. 6
Communication Interface ............................................................. 20
Typical Performance Characteristics ............................................. 6
Register Map ................................................................................... 21
Theory of Operation ........................................................................ 9
Detailed Register Descriptions ..................................................... 22
Backlight Drive and Control ....................................................... 9
Applications Information .............................................................. 34
Backlight Operating Levels ....................................................... 10
Converter Topology ................................................................... 34
Backlight Maximum and Dim Settings ................................... 10
PCB Layout ................................................................................. 35
Backlight Turn On/Off/Dim ..................................................... 11
Example Circuits ............................................................................ 36
Automatic Dim and Turn Off Timers ..................................... 11
Outline Dimensions ....................................................................... 38
Linear Backlight Fade In and Fade Out ................................... 12
Ordering Guide .......................................................................... 38
2
Fade Override ............................................................................. 13
REVISION HISTORY
10/2017—Rev. A to Rev. B
Changed nINT, nRST, and nSTNBY to INT, RST, and
STNBY ............................................................................ Throughout
Change to Package Type Column, Table 4 .................................... 5
Changes to Figure 3 and Table 5 ..................................................... 6
Updated Outline Dimensions ....................................................... 38
Changes to Ordering Guide .......................................................... 38
1/2010—Rev. 0 to Rev. A
Changes to Table 1.............................................................................3
Changes to Table 5.............................................................................6
Changes to Figure 32...................................................................... 14
Updated Outline Dimensions ....................................................... 38
Changes to Ordering Guide .......................................................... 38
7/2008—Revision 0: Initial Version
Rev. B | Page 2 of 38
Data Sheet
ADP5520
SPECIFICATIONS
VBAT = 2.7 V to 4.8 V, TJ = −40°C to +125°C, unless otherwise noted. 1
Table 1.
Parameter
SUPPLY VOLTAGE
VBAT Input Voltage Range
VDDIO Input Voltage Range
Undervoltage Lockout Threshold
SW leakage
SUPPLY CURRENT
Shutdown Current 3
Standby Current 4
BACKLIGHT LED DRIVER (SW, BST)
Current Limit (Peak Inductor Current)
Switch On Resistance
Overvoltage Limit
Boost Startup Time
BACKLIGHT LED CURRENT SINK (BL_SNK)
Full-Scale Backlight Current
Backlight Current Ramp Rate
AMBIENT LIGHT SENSOR (CMP_IN)
Full-Scale Current
INPUT LOGIC LEVELS (SCL, SDA, RST, C0, C1, C2, C3, R0, R1, R2, R3) 5
Logic Low Input Voltage
Logic High Input Voltage
Input Leakage Current
Symbol
VBAT
VVDDIO
UVLOVBAT
UVLOVBAT
UVLOVDDIO
UVLOVDDIO
SWLEAKAGE
ISD
ISTNBY
Conditions
VBAT falling
VBAT rising
VDDIO falling
VDDIO rising
2.7
1.7
1.7
1.7 V ≤ VDDIO ≤ 3.3 V2
1.7 V ≤ VDDIO ≤ 3.3 V2
1.7 V ≤ VDDIO ≤ 3.3 V2
INPUT LOGIC DEBOUNCE (RST, C0, C1, C2, C3, R0, R1, R2, R3) 6
PUSH-PULL OUTPUT LOGIC LEVELS (C0, C1, C2, C3, R0, R1, R2, R3) 7
Logic Low Output Voltage
Logic High Output Voltage
VOL
VOH
ISINK = 1 mA
ISOURCE = 1 mA
VOL
VOH-LEAKAGE
ISINK = 1 mA
1.7 V ≤ VDDIO ≤ 3.3 V2
LEDLEAKAGE
LEDFULLSCALE
Sink disabled
Applied pin voltage = 1 V
TS
TSHYS
TJ rising
TJ falling
Max
Unit
5.5
3.3 2
2.1
2.4
1.3
1.4
0.1
1.62
1
0.1
25
1
45
μA
μA
450
100
24.5
600
200
27
1
750
400
29.5
mA
mΩ
V
ms
26
30
0.3
32
mA
mA/ms
0.7
1
1.2
mA
0.3 × VDDIO
V
V
µA
µs
1.1
Fade timers disabled
BLFULLSCALE
Typ
V
V
V
V
V
V
μA
VDDIO = 0 V
1.7 V ≤ VDDIO ≤ 3.3 V2,
STNBY = 0
VIL
VIH
VI-LEAKAGE
VIL-DBNC
OPEN-DRAIN OUTPUT LOGIC LEVELS (INT), SDA)
Logic Low Output Voltage
Logic High Leakage Current
AUX LED CURRENT SINK (ILED, C3, R3) 8
Leakage
Full-scale Current Sink
GPIO PULL-UP RESISTANCE (C0, C1, C2, C3, R0, R1, R2, R3) 9
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Min
2.7
0.7 × VDDIO
50
0.1
75
1
100
0.4
V
V
0.1
0.4
1
V
µA
0.1
14
65
1
16.5
80
µA
mA
kΩ
VDDIO − 0.2
10.5
50
150
10
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25⁰C, VBAT = 3.6 V.
3.3 V or VBAT, whichever is smaller.
3
Internal LDO powered down, digital blocks inactive, I2C inactive, boost inactive.
4
Internal LDO powered up, digital blocks active, I2C active, boost inactive.
5
C0, C1, C2, C3, R0, R1, R2, and R3 are configured as digital inputs.
6
C0, C1, C2, C3, R0, R1, R2, and R3 are configured as digital inputs, with debounce enabled.
7
C0, C1, C2, C3, R0, R1, R2, and R3 are configured as digital outputs.
8
C3 and R3 are configured as digital inputs with pull-up.
9
C0, C1, C2, C3, R0, R1, R2, and R3 are configured as digital inputs with pull-up.
1
2
Rev. B | Page 3 of 38
°C
°C
ADP5520
Data Sheet
I2C TIMING SPECIFICATIONS
Table 2.
Parameter
Delay from Reset Deassertion to I2C Access
fSCL
tHIGH
tLOW
tSU, DAT
tHD, DAT
tSU, STA
tHD, STA
tBUF
tSU, STO
tR
tF
tSP
CB 1
Min
60
SCL clock frequency
SCL high time
SCL low time
Data setup time
Data hold time
Setup time for repeated start
Hold time for start/repeated start
Bus free time for stop and start condition
Setup time for stop condition
Rise time for SCL and SDA
Fall time for SCL and SDA
Pulse width of suppressed spike
Capacitive load for each bus line
Max
Unit
μs
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
μs
pF
400
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20 + 0.1 CB
20 + 0.1 CB
0
0.9
300
300
50
400
CB is the total capacitance of one bus line in picofarads.
SDA
tLOW
tR
tF
tSU, DAT
tF
tHD, STA
tSP
tBUF
tR
SCL
S
tHD, DAT
tHIGH
tSU, STA
Sr
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
tSU, STO
P
S
07445-002
1
Description
Figure 2. I2C Interface Timing Diagram
Rev. B | Page 4 of 38
Data Sheet
ADP5520
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
VBAT to GND
VDDIO to GND
SW, BST to GND
ILED, R0, R1, R2, R3, C0, C1, C2, C3, CMP_IN,
SCL, SDA, INT, RST, CAP_OUT, BL_SNK
to GND
PGND to GND
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
1
Rating
−0.3 V to +6 V
−0.3 V to VBAT
−0.3 V to +30 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +85°C1
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
24-Lead LFCSP (CP-24-14)
ESD CAUTION
In applications where high power dissipation and poor thermal resistance
are present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (TA(MAX)) is dependent on the maximum
operating junction temperature (TJ(MAXOP) = 125°C), the maximum power
dissipation of the device (PD(MAX)), and the junction-to-ambient thermal
resistance of the part/package in the application (θJA), using the following
equation: TA(MAX) = TJ(MAXOP) − (θJA × PD(MAX)).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to GND.
Rev. B | Page 5 of 38
θJA
50
Unit
°C/W
ADP5520
Data Sheet
20 CAP_OUT
19 GND
22 BST
21 VBAT
24 GND
18 GND
PGND 1
SW 2
17 CMP_IN
INT 3
ADP5520
SDA 4
TOP VIEW
(Not to Scale)
SCL 5
16 VDDIO
15 RST
14 ILED
R2 6
C2 11
C3 12
C0 9
C1 10
R1 7
R0 8
13 R3
NOTES
1. EXPOSED PAD MUST BE CONNECTED
TO GROUND.
07445-003
PIN 1
INDICATOR
23 BL_SNK
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mnemonic
PGND
SW
INT
SDA
SCL
R2
R1
R0
C0
C1
C2
C3
R3
ILED
RST
16
VDDIO
17
18
19
20
CMP_IN
GND
GND
CAP_OUT
21
22
23
24
VBAT
BST
BL_SNK
GND
EPAD
Description
Power Switch Output to Ground.
Power Switch Input.
Processor Interrupt. This pin is active low, and open drain, Pull up to VDDIO.
I2C-Compatible Serial Data Line. Open drain requires external pull-up to VDDIO.
I2C-Compatible Serial Clock Line. Open drain requires external pull-up to VDDIO.
Row 2 when configured in a keypad matrix, D2 when configured as an I/O.
Row 1 when configured in a keypad matrix, D1 when configured as an I/O.
Row 0 when configured in a keypad matrix, D0 when configured as an I/O.
Column 0 when configured in a keypad matrix, D4 when configured as an I/O.
Column 1 when configured in a keypad matrix, D5 when configured as an I/O.
Column 2 when configured in a keypad matrix, D6 when configured as an I/O.
Column 3 when configured in a keypad matrix, D7 when configured as an I/O, LED 2 when configured as a current sink.
Row 3 when configured in a keypad matrix, D3 when configured as an I/O, LED 3 when configured as a current sink.
LED 1 Current Sink.
Reset Input, Active Low. This input signal resets the device to the power-up default conditions. Must be driven low
for 75 µs (typical) to be valid.
Supply Voltage for the I/O Pins. Voltage is 1.7 V to 3.3 V (or VBAT, whichever is smaller). If VDDIO = 0, the device goes
into full shutdown mode.
Input for Ambient Light Sensing.
Ground.
Ground.
Capacitor for Internal 2.7 V LDO. A 1 μF capacitor must be connected between this pin and GND. Do not use this
pin to supply external loads.
Main Supply Voltage for the IC (2.7 V to 5.5 V).
Overvoltage Monitor Input for the Boost Converter.
Backlight Current Sink.
Ground.
Exposed Pad. Exposed pad must be connected to ground.
Rev. B | Page 6 of 38
Data Sheet
ADP5520
TYPICAL PERFORMANCE CHARACTERISTICS
VBAT = 3.6 V, TA = 25°C, unless otherwise noted. Inductor = LPS4012-472MLB. Schottky rectifier = MBR140SFT1G.
48
90
STANDBY SUPPLY CURRENT (µA)
85
80
EFFICIENCY (%)
75
70
65
60
6 LEDs,
6 LEDs,
6 LEDs,
6 LEDs,
55
50
VBAT
VBAT
VBAT
VBAT
= 3.0V
= 3.6V
= 4.2V
= 5.5V
TEMP = –40°C
40
TEMP = +25°C
32
24
16
TEMP = +85°C
8
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28
BACKLIGHT CURRENT (mA)
30
0
2.5
07445-047
40
Figure 4. Efficiency vs. Backlight Current (6 LEDS)
4.0
4.5
VBAT (V)
5.0
5.5
6.0
80
75
70
65
6 LEDs, VBAT = 3.6V
5 LEDs, VBAT = 3.6V
4 LEDs, VBAT = 3.6V
60
55
50
45
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28
BACKLIGHT CURRENT (mA)
30
Figure 5. Efficiency vs. Backlight Current (4, 5, and 6 LEDS)
80
75
6 LEDs, VBAT = 4.2V
6 LEDs, VBAT = 4.2V,
AUTOLOAD-ENABLED
60
55
50
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28
BACKLIGHT CURRENT (mA)
30
07445-049
45
40
8
6
4
2
0.5
1.0
1.5
2.0
AUX LED PIN VOLTAGE (V)
2.5
3.0
Figure 8. Typical Auxiliary LED Pin (R3, C3, or ILED), Full-Scale Sink Current vs.
Applied Pin Voltage
85
65
10
0
90
70
12
0
07445-048
40
14
07445-051
AUX LED FULL-SCALE SINK CURRENT (mA)
16
85
EFFICIENCY (%)
3.5
Figure 7. Standby Supply Current vs. VBAT
90
EFFICIENCY (%)
3.0
07445-050
45
Figure 6. Efficiency vs. Backlight Current (Autoload On/Off)
Rev. B | Page 7 of 38
ADP5520
Data Sheet
SW
SW
1
1
INDUCTOR CURRENT
INDUCTOR CURRENT
2
2
BST
BST
3
4
CH1 20.0V
CH3 10.0V
CH2 500mA
CH4 1.0V
TIME (4µs/DIV)
BL_SNK
4
CH1 20.0V
CH3 10.0V
Figure 9. Boost Operation (Backlight = 30 mA)
CH2 500mA
CH4 1.0V
TIME (4µs/DIV)
07445-054
BL_SNK
07445-052
3
Figure 11. Boost Operation (Backlight = 2 mA)
SW
SW
1
1
INDUCTOR CURRENT
INDUCTOR CURRENT
2
2
BST
BST
BL_SNK
3
3
CH2 500mA
CH4 1.0V
TIME (4µs/DIV)
4
07445-053
CH1 20.0V
CH3 10.0V
CH1 10.0V
CH3 10.0V
Figure 10. Boost Operation (Backlight = 15 mA)
CH2 500mA
CH4 1.0V
TIME (1ms/DIV)
Figure 12. Boost Startup
Rev. B | Page 8 of 38
07445-055
BL_SNK
4
Data Sheet
ADP5520
THEORY OF OPERATION
1µF
VBAT
1µF
4.7µH
SW
BST
2
BL_SNK
22
23
27V
I-LIMIT
FB
AUTO
LOAD
0.65V
OVP
BACKLIGHT
CURRENT
CONTROL
BOOST
CONTROL
PGND
1
VBAT
THERMAL S/D
IN
21
VDDIO 16
POR
EN
LDO
VBAT
OUT
CAP_OUT
STATE MACHINE
LIGHT
SENSOR
20
1µF
17
CMP_IN
2.7V
REGISTER MAP
BIAS/CLOCK
100nF
INTERRUPT/RESET
CONTROL
SCL 5
SDA 4
LED
CURRENT
CONTROL
INTERFACE
INT 3
RST 15
18
19
24
6
7
8
9
10
11
GND GND GND R2 R1 R0 C0 C1 C2
13
12
14
C3 ILED
R3
07445-004
I/O CONFIG
GPIO/KEYPAD
ADP5520
Figure 13. Internal Block Diagram
The ADP5520 is a backlight white LED driver with an I/O port
expander. It is ideal for cell phone designs and other portable
devices, where keypad and/or extended I/O functionality is
needed. Programmable fade-in, fade-out, dim, and off timers
provide the backlight with flexible control features. Using an
external photodiode, the ADP5520 can perform ambient light
sensing, and adjust the backlight brightness according to
varying lighting conditions.
The I/O port expander has eight configurable GPIO pins. The
I/Os can be configured as a keypad matrix, digital inputs, or
digital outputs. Additionally, two of the I/Os (R3 and C3) can be
configured as current sink lines and, paired with a dedicated
sink line (ILED), can be used to drive up to three auxiliary LEDs.
Programmable fading is also available for auxiliary LEDs.
Once programmed through its I2C-compatible interface, the
ADP5520 can run autonomously. An interrupt line (INT) is
available to alert an external microprocessor of the status of its
I/Os, keypad presses and releases, ambient light sensor comparator
states, and overvoltage conditions.
BACKLIGHT DRIVE AND CONTROL
White LEDs are common in backlighting the displays of modern
portable devices such as cell phones. White LEDs require a high
forward voltage, VF, before they conduct current and emit light.
Display panels, depending on their size, can be backlit with
single or multiple white LEDs. In panels that require multiple
LEDs, the LEDs are commonly connected in a series string to
achieve uniform brightness in each LED by passing a common
current through all of them. The LED string needs to be biased
with a voltage greater than the sum of the VF of each LED
before it conducts.
The ADP5520 is an asynchronous boost converter capable of
driving an LED string with 24.5 V (minimum). For detailed
information about the boost device, see the Applications
Information section. With sufficient forward voltage created,
the ADP5520 controls the current (and thus the brightness)
of the LED string via an adjustable internal current sink. An
internal state machine, in conjunction with programmable
timers, dynamically adjusts the current sink between 0 mA
and 30 mA to achieve impressive backlight control features.
Rev. B | Page 9 of 38
ADP5520
Data Sheet
BACKLIGHT MAXIMUM AND DIM SETTINGS
BST
The backlight maximum and dim current settings are determined by a 7-bit code programmed by the user into the registers
listed in the Backlight Operating Levels section. This 7-bit
resolution allows the user to set the backlight to 1 of 128
different levels between 0 mA and 30 mA. The ADP5520 can
implement two distinct algorithms to achieve a linear and a
nonlinear relationship between input code and backlight
current. The BL_LAW bits in Register 0x02 are used to swap
between algorithms.
BL_SNK
DAYLIGHT_MAX
DAYLIGHT_DIM
BL_VALUE
OFFICE_MAX
MUX
OFFICE_DIM
BL_EN
DARK_MAX
DARK_DIM
BL_OFFT
BL_DIMT
BL_LVL
DIM_EN
COUNTERS
AND
CONTROL
LOGIC
BL_LAW
BL_FI
CLOCK
GENERATOR
07445-005
BL_FO
By default, the ADP5520 uses a linear algorithm (BL_LAW =
00), where backlight current increases linearly for a corresponding increase of input code. Backlight current (in mA) is determined
by the following equation:
Backlight Current = Code × (Fullscale_Current/127)
Figure 14. Backlight Brightness Control
BACKLIGHT OPERATING LEVELS
Backlight brightness control can operate in three distinct levels:
daylight (L1), office (L2), and dark (L3). The BL_LVL bits in
Register 0x02 control the level in which the backlight operates.
The BL_LVL bits can be changed manually, or if in automatic
mode, by the ambient light sensor (see the Ambient Light Sensing
section). By default, the backlight operates at daylight level
(BL_LVL = 00), where the maximum brightness is set using
Register 0x05 (DAYLIGHT_MAX). A daylight dim setting can
also be set using Register 0x06 (DAYLIGHT_DIM). When operating at office level (BL_LVL = 01), the backlight maximum and
dim brightness settings are set by Register 0x07 (OFFICE_MAX)
and Register 0x08 (OFFICE_DIM). When operating at dark
level (BL_LVL = 10), the backlight maximum and dim brightness
settings are set by Register 0x09 (DARK_MAX) and Register 0x0A
(DARK_DIM).
DAYLIGHT (L1)
OFFICE (L2)
where:
Code is the input code programmed by the user.
Fullscale_Current is the maximum sink current allowed
(typically 30 mA).
The ADP5520 can also implement a nonlinear (square approximation) relationship between input code and backlight current level.
In this case (BL_LAW = 01), the backlight current (in mA) is
determined by the following equation:
Fullscale _ Current
Backlight Current = Code ×
127
DARK (L3)
DAYLIGHT_MAX
BACKLIGHT CURRENT
2
(2)
Figure 16 shows the backlight current level vs. input code for
both the linear and square law algorithms.
30
25
BACKLIGHT CURRENT (mA)
30mA
(1)
OFFICE_MAX
DARK_MAX
DAYLIGHT_DIM
OFFICE_DIM
20
15
LINEAR
10
SQUARE
5
BACKLIGHT OPERATING LEVELS
Figure 15. Backlight Operating Levels
0
0
32
64
SINK CODE
96
Figure 16. Backlight Current vs. Sink Code
Rev. B | Page 10 of 38
128
07445-007
0
07445-006
DARK_DIM
Data Sheet
ADP5520
BACKLIGHT TURN ON/OFF/DIM
AUTOMATIC DIM AND TURN OFF TIMERS
With the device in operating mode (STNBY = 1), the backlight
can be turned on using the BL_EN bit in Register 0x00. Before
turning on the backlight, choose which level (daylight (L1),
office (L2), or dark (L3)) to operate in, and ensure that maximum
and dim settings are programmed for that level. The backlight
turns on when BL_EN = 1. The backlight turns off when
BL_EN = 0.
The user can program the backlight to dim automatically by
using the BL_DIMT timer in Register 0x03. The dim timer has
15 settings ranging from 10 sec to 2 min. Program the dim
timer before turning on the backlight. If BL_EN = 1, the
backlight turns on to its maximum setting, and the dim timer
starts counting. When the dim timer expires, the internal state
machine sets DIM_EN = 1, and the backlight goes to its dim
setting.
BACKLIGHT
CURRENT
BACKLIGHT
CURRENT
MAX
DIM TIMER
RUNNING
DIM TIMER
RUNNING
MAX
BL_EN = 1
07445-008
DIM
BL_EN = 0
Figure 17. Backlight Turn On/Off
DIM_EN = 0 DIM_EN = 1
OR
BL_EN = 1
BL_EN = 0
07445-010
BL_EN = 1 DIM_EN = 1
While the backlight is on (BL_EN = 1), the user can make it
change to a dim setting by programming DIM_EN = 1 in
Register 0x00. If DIM_EN = 0, the backlight reverts to its
maximum setting.
SET BY USER
SET BY INTERNAL STATEMACHINE
Figure 19. Dim Timer
If the user clears the DIM_EN bit (or reasserts the BL_EN bit),
the backlight reverts to its maximum setting and the dim timer
begins counting again. When the dim timer expires, the internal
state machine again sets DIM_EN = 1, and the backlight goes to
its dim setting. Reasserting BL_EN at any point during the dim
timer countdown causes the timer to reset and begin counting
again. The backlight can be turned off at any point during the
dim timer countdown by clearing BL_EN.
MAX
BL_EN = 1
DIM_EN = 1
DIM_EN = 0
BL_EN = 0
07445-009
DIM
Figure 18. Backlight Turn On/Dim/Off
The maximum and dim settings can be set between 0 mA and
30 mA; therefore, it is possible to program a dim setting that is
greater than a maximum setting. For normal expected operation,
ensure that the dim setting is programmed to be less than the
maximum setting.
The user can also program the backlight to turn off automatically by using the BL_OFFT timer in Register 0x03. The off
timer has 15 settings ranging from 10 sec to 2 min. Program the
off timer before turning on the backlight. If BL_EN = 1, the
backlight turns on to its maximum setting, and the off timer
starts counting. When the off timer expires, the internal state
machine clears the BL_EN bit, and the backlight turns off.
It is also possible to activate the backlight automatically when a
key press is detected. With the row and column pins configured as
a keypad matrix, and the KP_BL_EN bit asserted in Register 0x02,
the internal state machine asserts BL_EN and turns on the backlight if a key is pressed. See the I/O Expansion Pins (Keypad
Matrix) section for more information on using keypad
functionality.
BACKLIGHT
CURRENT
OFF TIMER
RUNNING
MAX
BL_EN = 1 BL_EN = 0
SET BY USER
SET BY INTERNAL STATE MACHINE
Figure 20. Off Timer
Rev. B | Page 11 of 38
07445-011
BACKLIGHT
CURRENT
ADP5520
Data Sheet
Reasserting BL_EN at any point during the off timer countdown
causes the timer to reset and begin counting again. The backlight
can be turned off at any point during the off timer countdown
by clearing BL_EN.
The dim timer and off timer can be used together for sequential
maximum-to-dim-to-off functionality. With both the dim and
off timers programmed, if BL_EN is asserted, the backlight turns
on to its maximum setting. When the dim timer expires, the
backlight changes to its dim setting. When the off timer expires,
the backlight turns off.
The time programmed in BL_FI represents the time it takes the
backlight current to go from 0 mA to 30 mA. Fading between
intermediate settings is shorter.
The BL_FO timer in Register 0x04 can be used for smooth fadeout transitions from high to low backlight settings such as
maximum-to-dim and dim-to-off. The BL_FO timer can be
programmed to one of 15 settings ranging from 0.3 sec to 5.5 sec.
Program the BL_FO timer before asserting BL_EN.
30.0
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
27.5
BACKLIGHT CURRENT (mA)
25.0
BACKLIGHT
CURRENT
DIM TIMER
RUNNING
MAX
OFF TIMER
RUNNING
DIM
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
0
DIM_EN = 1
BL_EN = 0
0
0.5
1.0
07445-012
BL_EN = 1
SET BY USER
SET BY INTERNAL STATE MACHINE
1.5
2.0 2.5 3.0 3.5
FADE-OUT TIME (s)
4.0
4.5
5.0
5.5
07445-014
2.5
Figure 23. Linear Fade-out Times
LINEAR BACKLIGHT FADE IN AND FADE OUT
The time programmed in BL_FO represents the time it takes
the backlight current to go from 30 mA to 0 mA. Fading
between intermediate settings is shorter.
To counteract the abrupt visual effect of near instant turn-on
and turn-off of the backlight, the ADP5520 contains timers to
facilitate the smooth fading between off, on, and dim states. By
default (BL_LAW = 00), the ADP5520 implements a fading
scheme using the linear backlight code algorithm (see Equation 1).
Figure 24 shows the fade timers in use. With BL_FI and BL_FO
programmed, if BL_EN is asserted, then the backlight fades in
to its maximum setting. If DIM_EN is asserted, then the backlight
fades out to its dim setting. If BL_EN is cleared, the backlight
fades out to off.
Figure 21. Dim and Off Timers Used Together
The BL_FI timer in Register 0x04 can be used for smooth fade-in
transitions from low to high backlight settings, such as off-to-dim,
off-to-maximum, and dim-to-maximum. The BL_FI timer can be
programmed to one of 15 settings ranging from 0.3 sec to 5.5 sec.
Program the BL_FI timer before asserting BL_EN.
BACKLIGHT
CURRENT
FADE-IN
OFF-TO-MAX
FADE-OUT
FADE-IN
FADE-IN
FADE-OUT
MAX
FADE-OUT
DIM-TO-OFF
30.0
27.5
FADE-OUT
MAX-TO-DIM
DIM
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0
0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-IN TIME (s)
4.0
Figure 22. Linear Fade-In Times
4.5
5.0
5.5
BL_EN = 1 DIM_EN = 1 BL_EN = 0
BL_EN = 0
BL_EN = 1
BL_EN = 0
BL_EN = 1
SET BY USER
07445-015
22.5
Figure 24. Backlight Turn On/Off/Dim with Fade Timers
07445-013
BACKLIGHT CURRENT (mA)
25.0
During any point in a fade-out, if BL_EN is asserted, then the
backlight stops at its current fade-out position and begins
fading in.
The fade-in and fade-out timers can be used independently of each
other, that is, fade-in can be enabled while fade-out is disabled.
The fade timers can also be used with the off and dim timers.
Rev. B | Page 12 of 38
Data Sheet
ADP5520
Figure 25 shows the fade timers used with the dim and off timers.
Although the default linear fade algorithm gives a smooth increase
and decrease in backlight current, the resulting increase and
decrease in brightness still appears visually abrupt. For example,
for a given fade-in time, the eye can notice an initial increase in
brightness as backlight current is increased, but cannot perceive
much more of an increase in brightness as backlight current is
increased to maximum.
DIM TIMER
RUNNING
FADE-OUT
FADE-IN
MAX
OFF TIMER
RUNNING
BL_EN = 1
DIM_EN = 1
BL_EN = 0
DIM_EN = 0
SET BY USER
SET BY INTERNAL STATE MACHINE
07445-016
FADE-OUT
DIM
ADVANCED FADING (SQUARE)
The reason for this is that the eye, like all human senses, perceives
changes in light when the brightness of the light source is changed
logarithmically (Weber-Fechner law). To achieve a more natural
fading experience to the user, the fade timers can be used in
conjunction with the square law approximation backlight codes
(see Equation 2) by setting BL_LAW = 01.
Figure 25. Fade/Dim/Off Timers Used Together
30.0
27.5
FADE OVERRIDE
BACKLIGHT
CURRENT
FADE-IN
OVERRIDDEN
FADE-OUT
OVERRIDDEN
BACKLIGHT CURRENT (mA)
25.0
A fade override feature allows the BL_FI and BL_FO timers to
be overridden if the BL_EN bit is reasserted (either by the user
or due to a key press) during a fade-in or fade-out period, and
sets the backlight to its maximum setting. Fade override can be
activated by setting the FOVR bit in Register 0x02.
22.5
20.0
17.5
15.0
10.0
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
7.5
5.0
2.5
MAX
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
12.5
0
0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-IN TIME (s)
4.0
4.5
5.0
5.5
07445-018
BACKLIGHT
CURRENT
Figure 27. Square Law Fade-In Times
30.0
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
27.5
BL_EN = 1
(REASSERTED BY
USER OR A KEY PRESS)
BL_EN = 0
BL_EN = 1
(REASSERTED BY
USER OR A KEY PRESS)
SET BY USER
Figure 26. Fade Override
22.5
20.0
17.5
15.0
12.5
10.0
7.5
5.0
2.5
0
0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-OUT TIME (s)
4.0
Figure 28. Square Law Fade-Out Times
Rev. B | Page 13 of 38
4.5
5.0
5.5
07445-019
BL_EN = 0
07445-017
BL_EN = 1
BACKLIGHT CURRENT (mA)
25.0
ADP5520
Data Sheet
ADVANCED FADING (CUBIC 1 AND CUBIC 2)
AMBIENT LIGHT SENSING
Two additional advanced techniques are available for fading the
backlight brightness levels, Cubic 1 (BL_LAW = 10) and Cubic 2
(BL_LAW = 11). Referring to the backlight brightness control
block diagram shown in Figure 14, linear and square fading is
implemented by ramping the 128 linear/square algorithm codes
at a fixed frequency over the duration of a given fade-in/fadeout time.
The ADP5520 can be used in conjunction with an external
photosensor to detect when ambient light conditions have
dropped below programmable set points. An ADC samples the
output of the external photosensor. The ADC result is fed into
two programmable trip comparators. The ADC has an input
range of 0 μA to 1000 μA (typical).
L2_EN
Cubic fading is implemented by reusing the square algorithm
codes, but by ramping them with a clock source whose frequency
output increases as the sink current code increases (see Figure 29).
Cubic 1 and Cubic 2 differ by having separate frequency vs.
code characteristics.
BST
L2_TRIP
L2_HYS
PHOTO
SENSOR
OUTPUT
BL_SNK
L2_OUT
FILTER
SETTINGS
ADC
L3_TRIP
L3_HYS
L3_OUT
DAYLIGHT_DIM
OFFICE_MAX
OFFICE_DIM
BL_VALUE
L3_EN
MUX
Figure 31. Ambient Light Sensing and Trip Comparators
BL_EN
DARK_MAX
DARK_DIM
BL_OFFT
BL_DIMT
BL_LVL
DIM_EN
COUNTERS
AND
CONTROL
LOGIC
BL_LAW
BL_FI
CLOCK
GENERATOR
07445-020
BL_FO
Figure 29. Backlight Brightness Control (Cubic)
Figure 30 shows a comparison of fade law techniques. Cubic
fades complete faster than linear or square fades for a given fade
time setting. Cubic 1 completes approximately 30% faster, and
Cubic 2 completes approximately 10% faster than an equivalent
linear or square fade time.
With four fade laws and 15 fade time settings, users have tremendous flexibility to find the right fade experience for their application.
30
The Level 2 (office) light sensor comparator, L2_CMPR, is used
to detect when the photosensor output has dropped below the
programmable L2_TRIP point. If this event occurs, the
L2_OUT status signal is set. L2_CMPR contains programmable
hysteresis, meaning that the photosensor output must rise above
L2_TRIP + L2_HYS before L2_OUT is cleared. L2_CMPR is
enabled in Register 0x0C via the L2_EN bit. The L2_TRIP and
L2_HYS values of L2_CMPR can be set between 0 μA and 1000 μA
(typical) in steps of 4 μA (typical).
L3_CMPR is used to detect when the photosensor output
has dropped below the programmable L3_TRIP point. If this
event occurs, the L3_OUT status signal is set. L3_CMPR contains
programmable hysteresis, meaning that the photosensor output
must rise above L3_TRIP + L3_HYS before L3_OUT is cleared.
L3_CMPR is enabled in Register 0x0C via the L3_EN bit. The
L3_TRIP and L3_HYS values of L3_CMPR can be set between 0
μA and 127 μA (typical) in steps of 0.5 μA (typical).
L2_TRIP
25
CUBIC 1
L2_HYS
20
L3_TRIP
15
LINEAR
L3_HYS
10
1
CUBIC 2
5
0
10
ADC RANGE (µA)
100
1000
07445-023
SQUARE
Figure 32. Comparator Ranges
0
0.2
0.4
0.6
UNIT FADE TIME
0.8
Figure 30. Fade Law Comparison Over a Unit Fade Time
1.0
07445-021
BACKLIGHT CURRENT (mA)
07445-022
DAYLIGHT_MAX
The L2_CMPR and L3_CMPR comparators can be enabled
independently of each other. The ADC and comparators run
continuously when L2_EN and/or L3_EN are set, during
automatic backlight adjustment mode. A single conversion
Rev. B | Page 14 of 38
Data Sheet
ADP5520
takes 80 ms (typical). Filter times of between 80 ms and 10 sec
can be programmed for the comparators before they change state.
VDDIO
It is also possible to use the light sensor comparators in a single
shot mode. After the single shot measurement is completed, the
internal state machine clears the FORCE_RD bit.
The ambient light sensor comparators can be used to automatically transition the backlight between one of its three operating
levels. To enable this mode, the BL_AUTO_ADJ bit is set in
Register 0x02.
Once enabled, the internal state machine takes control of the
BL_LVL bits and changes them based on the L2_OUT and
L3_OUT status bits. The L2_OUT status bit indicates that ambient
light conditions have dropped below the L2_TRIP point and the
backlight must be moved to its office (L2) level. The L3_OUT
status bit indicates that ambient light conditions have dropped
below the L3_TRIP point and the backlight must be moved
to its dark (L3) level. Table 6 shows the relationship between
backlight operation and the ambient light sensor comparator
outputs.
The L3_OUT status bit has greater priority, so the backlight
operates at L3 (dark) even if L2_OUT is set.
Table 6. Comparator Output Truth Table (X = Don’t Care)
BL_AUTO_ADJ
0
L3_OUT
X
L2_OUT
X
1
0
0
1
0
1
1
1
0
1
1
1
Backlight Operation
BL_LVL can be manually
set by the user
BL_LVL = 00, backlight
operates at L1 (daylight)
BL_LVL = 01, backlight
operates at L2 (office)
BL_LVL = 10, backlight
operates at L3 (dark)
BL_LVL = 10, backlight
operates at L3 (dark)
I/O EXPANSION PINS (GPIOs)
The eight I/O expansion pins (R0, R1, R2, R3, C0, C1, C2, and
C3) can be configured as general-purpose digital inputs, digital
inputs with pull-up, or digital outputs. Two of the I/O pins (R3
and C3) are LED current sinks by default. To use them as GPIOs,
set Bit 4 and Bit 5 in Register 0x11. Register 0x17 to Register 0x1F
are used to configure the I/O pins in GPIO mode. Figure 33
shows the typical makeup of a GPIO block, where Rx/Cx
represents any one of the eight I/O lines.
Dx_IN
DEBOUNCE
VDDIO
GPIO (Rx/Cx)
Dx_OUT
Dx_DIR
Figure 33. Typical GPIO Block
When configured as an output, a digital buffer drives the GPIO
Rx and Cx pins to 0 V for a Logic 0 and to the VDDIO rail for a
Logic 1. Output data for each I/O is set using Register 0x1A.
Each I/O has a pull-up resistor that can be enabled when used
as an input. This can be useful for interfacing to an external
signal that has only pull-down capabilities. Pull-ups can be
enabled and disabled using Register 0x1F.
Each I/O has a debounce circuit that effectively filters out glitches
and pulses less than 75 µs (typical) to prevent false triggering
when configured as an input. By default, debounce is enabled
but can be disabled using Register 0x1E.
I/Os configured as inputs store the digital state sensed at each
pin in Register 0x19. Interrupts can be generated by digital
inputs if enabled in Register 0x1B. The input interrupt level
can be selected using Register 0x1D. Interrupts generated are
stored in Register 0x1C. The master GPI_INT bit is set if any
interrupt bits are set in Register 0x1C, and the INT pin is
asserted.
To deassert the INT pin and clear the GPI_INT bit, the 0x1C
register must be cleared by reading it twice (assuming the interrupt
condition has gone away), and then a 1 must be written to the
GPI_INT bit in Register 0x00. Figure 34 shows the interrupt
generation scheme, where Dx represents any one of the eight
digital input lines.
REG
0x19
Dx_IN
REG Dx_ILVL
0x1D
REG
Dx_IN_IEN
0x1B
INTERRUPT
CONDITION
DECODE
AND
REG 0x1C
READ TWICE
TO CLEAR
REG 0x00
WRITE 1
TO CLEAR
Dx_IN_ISTAT
GPI_INT
INT
DRIVE
Figure 34. GPIO Interrupt generation
I/O EXPANSION PINS (KEYPAD MATRIX)
The eight I/O expansion pins (R0, R1, R2, R3, C0, C1, C2, and
C3) can be configured to decode a keypad matrix, consisting of
up to 16 switches (4 × 4 matrix). See the Example Circuits
section for other possible matrix configurations.
Two of the I/O pins (R3 and C3) are LED current sinks by
default. To use them as keypad decoders, set Bit 4 and Bit 5 in
Register 0x11. The R0, R1, R2, and R3 I/O pins make up the
rows of the keypad matrix. The C0, C1, C2, and C3 I/O pins
make up the columns of the keypad matrix.
Rev. B | Page 15 of 38
07445-025
AUTOMATIC BACKLIGHT ADJUSTMENT
Dx_IN_DBNC
07445-024
The interrupt flag, CMPR_INT, is set in Register 0x00 if either
of the L2_OUT or L3_OUT status bits change state, meaning
interrupts can be generated if ambient light conditions transition
between any of the programmed trip points. CMPR_INT can
cause the INT pin to be asserted if the CMPR_IEN bit is set in
Register 0x00. The CMPR_INT flag can be cleared only by
writing a 1 to it.
Dx_PULL
ADP5520
Data Sheet
To configure the device for key scanning and decoding, the R0,
R1, R2, and R3 pull-ups must be enabled in Register 0x1F. Key
scanning and decoding is then enabled by programming the
row and column bits in Register 0x17. The row pull-ups must
be enabled before enabling key scanning.
If the A button is released, the switch opens the connection
between R0 and C0, and R0 is pulled up high. The key scanner
requires that the key be released for two scan cycles. Because the
release of a key is not necessarily in sync with the key scanning
sampling period, it may take between 25 ms and 50 ms for a key
to register as being released. Once the key is registered as being
released, the key scanner returns to idle mode.
Figure 35 shows the row and column pins connected to a typical
4 × 4, 16-switch keypad matrix. When key scanning is idle, the
row pins are pulled high and the column pins are pulled low.
The key scanner operates by checking if the row pins are low. If
the A button in the matrix is pressed, the switch connects R0 to
C0. The key scan circuit senses that the R0 pin has been pulled low
and begins a key scan cycle. To prevent glitches or narrow press
times registering as valid key presses, the key scanner requires
the key to be pressed for two scan cycles. The key scanner has a
sampling period of 25 ms, so the key must be pressed and held
for at least 25 ms to register as being pressed. If the key is continuously pressed, the key scanner continues to sample every 25 ms.
C0
2
nINT
CH1 2.0V
CH3 2.0V
KEYPAD
SCAN
AND
DECODE
C2
C3
R0
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
R1
R2
Key press/release status and interrupt information is recorded
in Register 0x20 through Register 0x25. When a key is pressed,
an interrupt is generated and stored. Key press interrupts for A
through H are stored in Register 0x20, and key press interrupts for
I through P are stored in Register 0x21. The master KP_INT flag is
set if any interrupt bits are set in Register 0x20 or Register 0x21.
The INT pin is asserted if KP_INT is set and if KP_IEN is
enabled in Register 0x01.
R3
4 × 4 KEYPAD MATRIX
Figure 35. Keypad Decode Configuration
R0
To deassert the INT pin and clear the KP_INT flag, Register 0x20
and Register 0x21 must be cleared by reading them once, and
then a 1 must be written to the KP_INT bit in Register 0x00.
Figure 38 shows the interrupt generation scheme, where
KP_x_ISTAT represents any one of the 16 key press interrupt
status bits.
1
READ ONCE
TO CLEAR
REGISTERS
KP_x_ISTAT
0x20 AND 0x21
2
C0
REG 0x00
WRITE 1
TO CLEAR
KP_INT
AND
REG 0x01
KP_IEN
INT
DRIVE
07445-027
C1
TIME (10ms/DIV)
Figure 37. Key Press (R0, C0)
07445-026
C0
CH2 2.0V
07445-057
D3_PULL
D2_PULL
D1_PULL
3
D0_PULL
VDDIO
R0
1
Figure 38. Key Press Interrupt Generation
INT
It is possible to clear key press interrupts (KP_INT = 1) and
deassert INT while a key is still pressed.
CH1 2.0V
CH3 2.0V
CH2 2.0V
TIME (10ms/DIV)
Figure 36. Key Press(R0,C0)
07445-056
3
When a key is released, an interrupt is also generated and
stored. Key release interrupts for A through H are stored in
Register 0x22, and key release interrupts for I through P are
stored in Register 0x23. The master KR_INT flag is set if any
interrupt bits are set in Register 0x22 or Register 0x23. The
INT pin is asserted if KR_INT is set and if KR_IEN is enabled
in Register 0x01.
Rev. B | Page 16 of 38
Data Sheet
ADP5520
To deassert the INT pin and clear the KR_INT flag, Register 0x22
and Register 0x23 must be cleared by reading them once, and then
a 1 must be written to the KR_INT bit in Register 0x00. Figure 39
shows the interrupt generation scheme, where KR_x_ISTAT
represents any one of the 16-key release interrupt status bits.
REGISTERS
KP_x_ISTAT
0x22 AND 0x23
REG 0x00
WRITE 1
TO CLEAR
KR_INT
AND
REG 0x01
KP_IEN
INT
DRIVE
07445-028
READ ONCE
TO CLEAR
Figure 39. Key Release Interrupt Generation
The backlight can be programmed to turn on as a consequence
of a key press, using the KP_BL_EN bit in Register 0x02. To
enable this feature, observe the following sequence:
1.
2.
3.
4.
Enable the row pull-ups using Register 0x1F.
Enable key scanning on rows and columns using
Register 0x17.
Enable backlight turn-on due to key press by setting
KP_BL_EN in Register 0x02.
Set device to operating mode (STNBY = 1) in Register 0x00.
When a key is pressed, the backlight turns on. If the off timer is
programmed, the backlight turns off, or the user can turn off
the backlight by clearing BL_EN.
If the user wants the backlight to turn on again with a subsequent key press, the KP_INT and KR_INT bits in Register 0x00
must be cleared.
I/O EXPANSION PINS AND ILED PIN (AUXILIARY
LED CURRENT SINKS)
The ILED pin and two of the I/O expansion pins (R3 and C3)
can be used as auxiliary LED current sinks. Each LED current
sink is programmable up to 14 mA (typical) and can be
independently turned on and off.
The ILED pin is the current sink for LED 1. Its sink current can
be set using LED1_CURRENT in Register 0x14. The LED 1
sink can be enabled with LED1_EN in Register 0x11.
The C3 pin is the current sink for LED 2. Its sink current can be
set using LED2_CURRENT in Register 0x15. The LED 2 sink
can be enabled with LED2_EN in Register 0x11.
The R3 pin is the current sink for LED 3. Its sink current can be
set using LED3_CURRENT in Register 0x16. The LED 3 sink
can be enabled with LED3_EN in Register 0x11.
The LEDx_CURRENT registers are six bits wide, allowing the
user to set the LED sink current to one of 64 different levels
between 0 mA and 14 mA. The ADP5520 can implement two
distinct algorithms, to achieve a linear and a nonlinear
relationship between input code and sink current.
By default, the ADP5520 uses a linear algorithm (LED_LAW = 0),
where the LED sink current increases linearly for a corresponding
increase of input code. LED sink current (in milliamps) is determined by the following equation:
LED Sink Current = Code × (Fullscale_Current/63)
where:
Code is the input code programmed by the user.
Fullscale_Current is the maximum sink current allowed
(typically 14 mA).
LED1_EN
LED1_OFFT
LED 1
DIGITAL
COUNTERS
AND
CONTROL
R3
C3
ILED
LED1_CURRENT
VBAT
VBAT
VBAT
LED2_EN
LED2_CURRENT
LED2_OFFT
LED 2
DIGITAL
COUNTERS
AND
CONTROL
LED3_EN
LED3_CURRENT
LED3_OFFT
LED 3
DIGITAL
COUNTERS
AND
CONTROL
LED_ONT
LED_FI
07445-029
LED_FO
LED_LAW
Figure 40. LED Current Sinks
Rev. B | Page 17 of 38
(3)
ADP5520
Data Sheet
The ADP5520 can also implement a nonlinear (square approximation) relationship between input code and LED sink current
level. In this case (LED_LAW = 1), the LED sink current (in
milliamps) is determined by the following equation:
2
(4)
Figure 41 shows the auxiliary LED sink current levels vs. input
code for both the linear and square law algorithms.
10
8
6
4
14
2
12
0
1.0
1.5
2.0 2.5 3.0 3.5
FADE-OUT TIME (s)
4.0
4.5
5.0
5.5
To achieve a more natural fading experience to the eye, the fade
timers can be used in conjunction with the square law approximation codes (see Equation 4) by setting LED_LAW = 1.
6
SQUARE
14
2
12
32
CODE
48
64
Figure 41. LED Sink Current vs. Code
Similar to the backlight current sink, the ADP5520 contains
timers to facilitate the smooth fading between off and on states
of the LED current sinks. All three LED sinks share a common
fade-in (LED_FI) timer as well as a common fade-out (LED_FO)
timer. The fade-in and fade-out timers are located in Register 0x13,
and can be programmed to one of 15 settings ranging from 0.3 sec
to 5.5 sec. Fade-in times represent the time it takes to fade from
0 mA to 14 mA. Fade-out times represent the time it takes to
fade from 14 mA to 0 mA. Fading between intermediate settings
is shorter. Program the fade timers before asserting LEDx_EN.
By default (LED_LAW = 0), the ADP5520 implements a fading
scheme using the linear algorithm (see Equation 3).
14
12
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
8
6
4
2
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-IN TIME (s)
4.0
4.5
5.0
6
4
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2
0
0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-IN TIME (s)
4.0
4.5
5.0
5.5
Figure 44. Square Law Fade-In Times
14
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
12
10
8
6
4
0
0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
FADE-OUT TIME (s)
4.0
4.5
Figure 45. Square Law Fade-Out Times
0
0
8
2
5.5
07445-031
10
10
Figure 42. Linear Fade-In Times
Rev. B | Page 18 of 38
5.0
5.5
07445-034
16
LED SINK CURRENT (mA)
0
LED SINK CURRENT (mA)
4
07445-033
LINEAR
0
LED SINK CURRENT (mA)
0.5
Figure 43. Linear Fade-Out Times
8
07445-030
LED SINK CURRENT (mA)
0
10
07445-032
Fullscale _ Current
63
0.3 SEC
0.6 SEC
0.9 SEC
1.2 SEC
1.5 SEC
1.8 SEC
2.1 SEC
2.4 SEC
2.7 SEC
3.0 SEC
3.5 SEC
4.0 SEC
4.5 SEC
5.0 SEC
5.5 SEC
12
LED SINK CURRENT (mA)
LED Sink Current = Code ×
14
Data Sheet
ADP5520
INTERRUPT OUTPUT (INT)
The ADP5520 can generate interrupts to an external processor
via its interrupt output, INT. INT is an active low open-drain
pin that must be pulled up to VDDIO. INT can be asserted by
one of several internal blocks, as shown in Figure 47.
VDDIO
ALS COMPARATOR INTERRUPTS
GPIO INTERRUPTS
KEY PRESS INTERRUPTS
Program all fade, on, and off timers before enabling any of the
LED current sinks. If LEDx is on during a blink cycle and
LEDx_EN is cleared, it turns off (or fades to off if fade-out is
enabled). If LEDx is off during a blink cycle and LEDx_EN is
cleared, then it stays off.
LEDx
CURRENT
OR
INT
KEY RELEASE INTERRUPTS
OVERVOLTAGE INTERRUPT
07445-036
The LED current sinks have additional timers to facilitate
blinking functions. A shared on timer (LED_ONT) used in
conjunction with three off timers (LED1_OFFT, LED2_OFFT,
and LED3_OFFT) allow the LED current sinks to be configured
in various blinking modes. The on timer can be set to four
different settings: 0.2 sec, 0.6 sec, 0.8 sec, and 1.2 sec. The off
timers have four different settings: disabled, 0.6 sec, 0.8 sec, and
1.2 sec. Blink mode is activated by setting the off timers to any
setting other than disabled.
Figure 47. INT Pin Drive
RESET INPUT (RST)
ON TIME
FADE-IN
ON TIME
FADE-OUT FADE-IN
The ADP5520 can be restored to a power-on reset state if the
RST pin is held low. RST contains a debounce circuit, so the pin
must be held low for greater than 75 μs (typical) before a reset
occurs.
FADE-OUT
MAX
LEDx_EN = 1
SET BY USER
OFF
TIME
07445-035
OFF
TIME
Figure 46. LEDx Blink Mode with Fading
Rev. B | Page 19 of 38
ADP5520
Data Sheet
COMMUNICATION INTERFACE
Figure 49 shows a typical read sequence for reading back an
internal register.
Communication to the ADP5520 is done via its I2C-compatible
serial interface. Figure 48 shows a typical write sequence for
programming an internal register.
5.
6.
7.
8.
0 = WRITE
ST
SP
1
1
0
0
1
CHIP ADDRESS
0
0
0
0
REGISTER ADDRESS
0
ADP5520 RECEIVES DATA
07445-037
0
ADP5520 ACK
Figure 48. I2C Write Sequence
0 = WRITE
1 = READ
ST
0
1
1
0
0
1
CHIP ADDRESS
0
0
0
0
REGISTER ADDRESS
SP
0
1
1
0
0
1
CHIP ADDRESS
Figure 49. I2C Read Sequence
Rev. B | Page 20 of 38
0
0
1
ADP5520 SENDS DATA
07445-038
ST
NO ACK
7.
4.
ADP5520 ACK
5.
6.
3.
ADP5520 ACK
4.
The cycle begins with a start condition, followed by the
chip write address (0x64).
The ADP5520 acknowledges the chip write address byte by
pulling the data line low.
The address of the register from which data is to be read is
sent next.
The ADP5520 acknowledges the register address byte by
pulling the data line low.
The cycle continues with a repeat start, followed by the
chip read address (0x65).
The ADP5520 acknowledges the chip read address byte by
pulling the data line low.
The ADP5520 places the contents of the previously
addressed register on the bus for readback.
There is a no acknowledge following the readback data
byte, and the cycle is completed with a stop condition.
2.
ADP5520 ACK
3.
ADP5520 ACK
2.
1.
The cycle begins with a start condition, followed by the
chip write address (0x64).
The ADP5520 acknowledges the chip write address byte by
pulling the data line low.
The address of the register to which data is to be written is
sent next.
The ADP5520 acknowledges the register address byte by
pulling the data line low.
The data byte to be written is sent next.
The ADP5520 acknowledges the data byte by pulling the
data line low.
A stop condition completes the sequence.
ADP5520 ACK
1.
Data Sheet
ADP5520
REGISTER MAP
All registers are 0 on reset. Unused bits are read as 0.
Table 7.
Register
Address
0x00
Register Name
MODE_STATUS
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
INTERRUPT_ENABLE
BL_CONTROL
BL_TIME
BL_FADE
DAYLIGHT_MAX
DAYLIGHT_DIM
OFFICE_MAX
OFFICE_DIM
DARK_MAX
DARK_DIM
BL_VALUE
ALS_CMPR_CFG
L2_TRIP
L2_HYS
L3_TRIP
L3_HYS
LED_CONTROL
LED_TIME
LED_FADE
LED1_CURRENT
LED2_CURRENT
LED3_CURRENT
GPIO_CFG_1
GPIO_CFG_2
GPIO_IN
GPIO_OUT
GPIO_INT_EN
GPIO_INT_STAT
GPIO_INT_LVL
GPIO_DEBOUNCE
GPIO_PULLUP
KP_INT_STAT_1
KP_INT_STAT_2
KR_INT_STAT_1
KR_INT_STAT_2
KEY_STAT_1
KEY_STAT_2
Register Description
Sets device operating mode. Contains enables for backlight on/dim. Contains top-level interrupt
status bits.
Contains enables for allowing interrupts to assert INT.
Sets parameters relating to backlight control.
Contains backlight off and dim timers.
Contains backlight fade-in and fade-out timers.
Sets daylight (L1) maximum current.
Sets daylight (L1) dim current.
Sets office (L2) maximum current.
Sets office (L2) dim current.
Sets dark (L3) maximum current.
Sets dark (L3) dim current.
Read-only register of what the backlight is presently set to.
Sets enables and filters for ambient light sensor comparators. Contains comparator output status bits.
Sets the light sensor comparator (L2_CMPR) threshold point.
Sets the light sensor comparator (L2_CMPR hysteresis.
Sets the light sensor comparator (L3_CMPR) threshold point.
Sets the light sensor comparator (L3_CMPR) hysteresis.
Contains enables and configuration for the three auxiliary LED current sinks.
Contains the on and off timers for the three auxiliary LED current sinks.
Contains the fade-in and fade-out timers for the three auxiliary LED current sinks.
Sets the LED 1 (ILED) sink current.
Sets the LED 2 (C3) sink current.
Sets the LED 3 (R3) sink current.
Configuration for I/O pins. (GPIOs or keypad matrix)
Configuration for I/O pins. (GPIO direction, input or output)
Read-only register. Reflects the logic state of GPIO inputs.
Sets GPIO output logic drive level.
GPIO input interrupt enable.
GPIO input interrupt status.
Configures the GPIO input interrupt level that causes an interrupt (active high or low).
GPIO input debounce enable/disable.
GPIO pull-up enable/disable.
Read only register. Contains interrupt status information for key presses on Key A through Key H.
Read-only register. Contains interrupt status information for key presses on Key I through Key P.
Read-only register. Contains interrupt status information for key releases on Key A through Key H.
Read-only register. Contains interrupt status information for key releases on Key I through Key P.
Read-only register. Reflects the present state of Key A through Key H.
Read-only register. Reflects the present state of Key I through Key P.
Rev. B | Page 21 of 38
ADP5520
Data Sheet
DETAILED REGISTER DESCRIPTIONS
If one of the interrupt bits in Table 8 is cleared and there is a pending interrupt, INT deasserts for 50 μs and reasserts, but the status of the
pending interrupt stays set.
Table 8. Register 0x00, Device Mode and Status (MODE_STATUS)
Bit
7
Mnemonic
STNBY
R/W
R/W
6
BL_EN
R/W
5
DIM_EN
4
OVP_INT
3
CMPR_INT
2
GPI_INT
1
KR_INT
0
KP_INT
R/W
Description
0 = device is in standby mode. If 1.8 V ≤ VDDIO ≤ 3.3 V, then I2C, GPIO, and key scanning
functions are available.
1 = device is in operating mode. Additional functions, such as backlight driver, auxiliary
LED sinks, and ambient light sensor functions, can be enabled.
0 = backlight driver is disabled.
1 = backlight driver is enabled.
0 = dim mode is disabled.
1 = dim mode is enabled. Dim mode can be enabled in two ways. One is by manually
setting this bit, in which case the backlight stays at a dim level until this bit is manually
cleared. The second method is by setting the BL_DIMT timer, in which case an internal
state machine sets this bit when the timer expires.
0 = no overvoltage protection (OVP) condition.
1 = OVP condition detected. Once set, this bit can be cleared by writing a 1 to it.
0 = no ambient light sensor comparators have triggered.
1 = One of the ambient light sensor comparators has triggered. Once set, this bit can be
cleared by writing a 1 to it.
0 = no GPIO input interrupt detected.
1 = GPIO input interrupt condition has occurred. To clear this interrupt bit, the GPIO
interrupt status (Register 0x1C) must be cleared first. Then this bit can be cleared by
writing a 1 to it.
0 = no key release interrupt present.
1 = key release detected. To clear this interrupt bit, Key Release Interrupt Status 1
(Register 0x22) and Key Release Interrupt Status 2 (Register 0x23) must be cleared first.
Then this bit can be cleared by writing a 1 to it.
0 = no key press interrupt present.
1 = key press detected. To clear this interrupt bit, Key Press Interrupt Status 1 (Register
0x20) and Key Press Interrupt Status 2 (Register 0x21) must be cleared first. Then this bit
can be cleared by writing a 1 to it.
Table 9. Register 0x01, Interrupt Enable (INTERRUPT_ENABLE)
Bit
[7:5]
4
Mnemonic
R/W
AUTO_LD_EN
R/W
3
CMPR_IEN
R/W
2
OVP_IEN
R/W
1
KR_IEN
R/W
0
KP_IEN
R/W
Description
Unused.
0 = autoload disabled.
1 = autoload enabled. A 1 mA dummy load turns on when the backlight code is less than 8
(linear law) or less than Code 32 (square law).
0 = ambient light sensor comparators interrupt disabled.
1 = ambient light sensor comparators interrupt enabled.
0 = OVP interrupt disabled.
1 = OVP interrupt enabled.
0 = key release interrupt disabled.
1 = key release interrupt enabled.
0 = key press interrupt disabled.
1 = key press interrupt enabled.
Rev. B | Page 22 of 38
Data Sheet
ADP5520
Table 10. Register 0x02, Backlight Control (BL_CONTROL)
Bit
[7:6]
Mnemonic
BL_LVL
R/W
R/W
[5:4]
BL_LAW
R/W
3
BL_AUTO_ADJ
R/W
2
OVP_EN
R/W
1
FOVR
R/W
0
KP_BL_EN
R/W
Description
Brightness level control for the backlight.
00 = daylight (L1).
01 = office (L2).
10 = dark (L3).
See the description for the BL_AUTO_ADJ bit.
Backlight fade-on/fade-off transfer characteristic.
00 = linear.
01 = square.
10 = Cubic 1.
11 = Cubic 2.
0 = ambient light sensor comparators have no effect on the backlight operating level. The user
can manually adjust backlight operating level using the BL_LVL bits.
1 = ambient light sensor comparators automatically adjust the backlight operating level. The
internal state machine takes control of the BL_LVL bits.
0 = backlight ramp-down during OVP disabled.
1 = backlight ramp-down during OVP enabled.
0 = backlight fade override disabled.
1 = backlight fade override enabled.
0 = key press has no effect on the backlight.
1 = key press causes internal state machine to assert BL_EN and turn on the backlight. If this
function is used, assert this bit before asserting STNBY = 1.
Table 11. Register 0x03, Backlight Off and Dim Timers (BL_TIME)
Bit
[7:4]
Mnemonic
BL_OFFT
R/W
R/W
[3:0]
BL_DIMT
R/W
Description
Backlight off timer (set this timer before BL_EN is set).
0000 = timer disabled.
0001 = 10 sec.
0010 = 15 sec.
0011 = 20 sec.
0100 = 25 sec.
0101 = 30 sec.
0110 = 35 sec.
0111 = 40 sec.
1000 = 50 sec.
1001 = 60 sec.
1010 = 70 sec.
1011 = 80 sec.
1100 = 90 sec.
1101 = 100 sec.
1110 = 110 sec.
1111 = 120 sec.
Backlight dim timer (set this timer before BL_EN is set).
0000 = timer disabled.
0001 = 10 sec.
0010 = 15 sec.
0011 = 20 sec.
0100 = 25 sec.
0101 = 30 sec.
0110 = 35 sec.
0111 = 40 sec.
1000 = 50 sec.
1001 = 60 sec.
Rev. B | Page 23 of 38
ADP5520
Bit
Mnemonic
Data Sheet
R/W
Description
1010 = 70 sec.
1011 = 80 sec.
1100 = 90 sec.
1101 = 100 sec.
1110 = 110 sec.
1111 = 120 sec.
Table 12. Register 0x04, Backlight Fade-In and Fade-Out Timers (BL_FADE)
Bit
[7:4]
Mnemonic
BL_FO
R/W
R/W
[3:0]
BL_FI
R/W
Description
Backlight fade-out timer (set this timer before BL_EN is set).
0000 = timer disabled.
0001 = 0.3 sec.
0010 = 0.6 sec.
0011 = 0.9 sec.
0100 = 1.2 sec.
0101 = 1.5 sec.
0110 = 1.8 sec.
0111 = 2.1 sec.
1000 = 2.4 sec.
1001 = 2.7 sec.
1010 = 3.0 sec.
1011 = 3.5 sec.
1100 = 4.0 sec.
1101 = 4.5 sec.
1110 = 5.0 sec.
1111 = 5.5 sec.
Backlight fade-in timer (set this timer before BL_EN is set).
0000 = timer disabled.
0001 = 0.3 sec.
0010 = 0.6 sec.
0011 = 0.9 sec.
0100 = 1.2 sec.
0101 = 1.5 sec.
0110 = 1.8 sec.
0111 = 2.1 sec.
1000 = 2.4 sec.
1001 = 2.7 sec.
1010 = 3.0 sec.
1011 = 3.5 sec.
1100 = 4.0 sec.
1101 = 4.5 sec.
1110 = 5.0 sec.
1111 = 5.5 sec.
Table 13. Register 0x05, Level 1 (Daylight) Maximum Current (DAYLIGHT_MAX)
Bit
7
[6:0]
Mnemonic
R/W
DAYLIGHT_MAX
R/W
Description
Unused.
Maximum current setting for the backlight when BL_LVL is at Level 1 (daylight). See Figure 16 for
backlight current vs. sink code relationship.
Rev. B | Page 24 of 38
Data Sheet
ADP5520
Table 14. Register 0x06, Level 1 (Daylight) Dim Current (DAYLIGHT_DIM)
Bit
7
[6:0]
Mnemonic
R/W
DAYLIGHT_DIM
R/W
Description
Unused.
Dim current setting for the backlight when BL_LVL is at Level 1 (daylight). See Figure 16 for
backlight current vs. sink code relationship.
Table 15. Register 0x07, Level 2 (Office) Maximum Current (OFFICE_MAX)
Bit
7
[6:0]
Mnemonic
R/W
OFFICE_MAX
R/W
Description
Unused.
Maximum current setting for the backlight when BL_LVL is at Level 2 (office). See Figure 16 for
backlight current vs. sink code relationship.
Table 16. Register 0x08, Level 2 (Office) Dim Current (OFFICE_DIM)
Bit
7
[6:0]
Mnemonic
R/W
OFFICE_DIM
R/W
Description
Unused.
Dim current setting for the backlight when BL_LVL is at Level 2 (office). See Figure 16 for
backlight current vs. sink code relationship.
Table 17. Register 0x09, Level 3 (Dark) Maximum Current (DARK_MAX)
Bit
7
6 to 0
Mnemonic
R/W
DARK_MAX
R/W
Description
Unused.
Maximum current setting for the backlight when BL_LVL is at Level 3 (dark). See Figure 16 for
backlight current vs. sink code relationship.
Table 18. Register 0x0A, Level 3 (Dark) Dim Current (DARK_DIM)
Bit
7
[6:0]
Mnemonic
R/W
DARK_DIM
R/W
Description
Unused.
Dim current setting for the backlight when BL_LVL is at Level 3 (dark). See Figure 16 for
backlight current vs. sink code relationship.
Table 19. Register 0x0B, Backlight Current Value (BL_VALUE)
Bit
7
[6:0]
Mnemonic
R/W
BL_VALUE
R
Description
Unused.
Read-only register. Contains the present value to which the backlight is programmed.
Table 20. Register 0x0C, Light Sensor Comparator Configuration (ALS_CMPR_CFG)
Bit
[7:5]
Mnemonic
FILT
R/W
R/W
4
FORCE_RD
R/W
3
L3_OUT
R
2
L2_OUT
R
1
L3_EN
R/W
Description
Light sensor filter time.
000 = 0.08 sec.
001 = 0.16 sec.
010 = 0.32 sec.
011 = 0.64 sec.
100 = 1.28 sec.
101 = 2.56 sec.
110 = 5.12 sec.
111 = 10.24 sec.
Forces the light sensor comparator to perform a single conversion. This bit is cleared by the
internal state machine when the conversion is complete.
0 = ambient light is greater than Level 3 (dark).
1 = L3_CMPR comparator has detected a change in ambient light from Level 2 (office) to Level 3
(dark).
0 = ambient light is greater than Level 2 (office).
1 = L2_CMPR comparator has detected a change in ambient light from Level 1 (daylight) to
Level 2 (office).
0 = disable Comparator L3_CMPR.
1 = enable Comparator L3_CMPR. If automatic backlight adjustment is required, BL_AUTO_ADJ
must be set also.
Rev. B | Page 25 of 38
ADP5520
Bit
0
Mnemonic
L2_EN
Data Sheet
R/W
R/W
Description
0 = disable Comparator L2_CMPR.
1 = enable Comparator L2_CMPR. If automatic backlight adjustment is required, BL_AUTO_ADJ
must be set also.
Table 21. Register 0x0D, Level 2 (Office) Comparator Trip Point (L2_TRIP)
Bit
[7:0]
Mnemonic
L2_TRIP
R/W
R/W
Description
Sets the trip value for Comparator L2_CMPR. If ambient light levels fall below this trip point,
L2_OUT is set. Each code is equal to 4 μA (typical). Full scale is 1000 μA (typical).
Table 22. Register 0x0E, Level 2 (Office) Comparator Hysteresis (L2_HYS)
Bit
[7:0]
Mnemonic
L2_HYS
R/W
R/W
Description
Sets the hysteresis value for Comparator L2_CMPR. If ambient light levels increase above L2_TRIP +
L2_HYS, then L2_OUT is cleared. Each code is equal to 4 μA (typical). Full scale is 1000 μA (typical).
Table 23. Register 0x0F, Level 3 (Dark) Comparator Trip Point (L3_TRIP)
Bit
[7:0]
Mnemonic
L3_TRIP
R/W
R/W
Description
Sets the trip value for Comparator L3_CMPR. If ambient light levels fall below this trip point,
L3_OUT is set. Each code is equal to 0.5 μA (typical). Full scale is 127 μA (typical).
Table 24. Register 0x10, Level 3 (Dark) Comparator Hysteresis (L3_HYS)
Bit
[7:0]
Mnemonic
L3_HYS
R/W
R/W
Description
Sets the hysteresis value for Comparator L3_CMPR. If ambient light levels increase above L3_TRIP +
L3_HYS, then L3_OUT is cleared. Each code is equal to 0.5 μA (typical). Full scale is 127 μA (typical).
Table 25. Register 0x11, LED Control (LED_CONTROL)
Bit
[7:6]
5
Mnemonic
R/W
R3_MODE
R/W
4
C3_MODE
R/W
3
LED_LAW
R/W
2
LED3_EN
1
LED2_EN
0
LED1_EN
Description
Unused.
0 = R3 is configured as a current sink (LED 3).
1 = R3 is configured as a GPIO (D3).
0 = C3 is configured as a current sink (LED 2).
1 = C3 is configured as a GPIO (D7).
LED current sink fade-on/fade-off transfer characteristic.
0 = linear.
1 = square.
0 = LED 3 is disabled.
1 = LED 3 is enabled.
0 = LED 2 is disabled.
1 = LED 2 is enabled.
0 = LED 1 is disabled.
1 = LED 1 is enabled.
Table 26. Register 0x12, Auxiliary LED On and Off Timers (LED_TIME)
Bit
[7:6]
Mnemonic
LED_ONT
R/W
R/W
[5:4]
LED3_OFFT
R/W
Description
Sets the LED on time when used in conjunction with the LEDx_OFFT timer to perform LED
blinking. All three LED sinks share this common timer.
00 = 0.2 sec.
01 = 0.6 sec.
10 = 0.8 sec.
11 = 1.2 sec.
Sets the LED 3 off time when used in conjunction with the LED_ONT timer to perform LED
blinking. LED 3 stays on continuously if the timer is disabled.
00 = LED 3 timer disabled.
01 = 0.6 sec.
10 = 0.8 sec.
11 = 1.2 sec.
Rev. B | Page 26 of 38
Data Sheet
ADP5520
Bit
[3:2]
Mnemonic
LED2_OFFT
R/W
R/W
[1:0]
LED1_OFFT
R/W
Description
Sets the LED 2 off time when used in conjunction with the LED_ONT timer to perform LED
blinking. LED 2 stays on continuously if the timer is disabled.
00 = LED 2 timer disabled.
01 = 0.6 sec.
10 = 0.8 sec.
11 = 1.2 sec.
Sets the LED 1 off time when used in conjunction with the LED _ONT timer to perform LED
blinking. LED 1 stays on continuously if the timer is disabled.
00 = LED 1 timer disabled.
01 = 0.6 sec.
10 = 0.8 sec.
11 = 1.2 sec.
Table 27. Register 0x13, LED Fade-In and Fade-Out Timers (LED_FADE)
Bit
[7:4]
Mnemonic
LED_FO
R/W
R/W
[3:0]
LED_FI
R/W
Description
LED fade-out timer (set this timer before LED x_EN is enabled).
0000 = timer disabled.
0001 = 0.3 sec.
0010 = 0.6 sec.
0011 = 0.9 sec.
0100 = 1.2 sec.
0101 = 1.5 sec.
0110 = 1.8 sec.
0111 = 2.1 sec.
1000 = 2.4 sec.
1001 = 2.7 sec.
1010 = 3.0 sec.
1011 = 3.5 sec.
1100 = 4.0 sec.
1101 = 4.5 sec.
1110 = 5.0 sec.
1111 = 5.5 sec.
LED fade-in timer (set this timer before LED x_EN is enabled).
0000 = timer disabled.
0001 = 0.3 sec.
0010 = 0.6 sec.
0011 = 0.9 sec.
0100 = 1.2 sec.
0101 = 1.5 sec.
0110 = 1.8 sec.
0111 = 2.1 sec.
1000 = 2.4 sec.
1001 = 2.7 sec.
1010 = 3.0 sec.
1011 = 3.5 sec.
1100 = 4.0 sec.
1101 = 4.5 sec.
1110 = 5.0 sec.
1111 = 5.5 sec.
Rev. B | Page 27 of 38
ADP5520
Data Sheet
Table 28. Register 0x14, LED 1 Sink Current (LED1_CURRENT)
Bit
[7:6]
[5:0]
Mnemonic
R/W
LED1_CURRENT
R/W
Description
Unused.
Sink current setting for LED 1. See Figure 41 for LED sink current vs. code relationship.
Table 29. Register 0x15, LED 2 Sink Current (LED2_CURRENT)
Bit
[7:6]
[5:0]
Mnemonic
R/W
LED2_CURRENT
R/W
Description
Unused.
Sink current setting for LED 2. See Figure 41 for LED sink current vs. code relationship.
Table 30. Register 0x16, LED 3 Sink Current (LED3_CURRENT)
Bit
[7:6]
[5:0]
Mnemonic
R/W
LED3_CURRENT
R/W
Description
Unused.
Sink current setting for LED 3. See Figure 41 for LED sink current vs. code relationship.
Table 31. Register 0x17, GPIO Configuration 1 (Pin Configuration) (GPIO_CFG_1)
Bit
7
Mnemonic
C3_CONFIG
R/W
R/W
6
C2_CONFIG
R/W
5
C1_CONFIG
R/W
4
C0_CONFIG
R/W
3
R3_CONFIG
R/W
2
R2_CONFIG
R/W
1
R1_CONFIG
R/W
0
R0_CONFIG
R/W
Description
0 = C3 is configured as a GPIO (D7).
1 = C3 is configured as a keypad column (Column 3). Ensure that C3_MODE = 1 when C3 is to be
used as a GPIO or a keypad column.
0 = C2 is configured as a GPIO (D6).
1 = C2 is configured as a keypad column (Column 2).
0 = C1 is configured as a GPIO (D5).
1 = C1 is configured as a keypad column (Column 1).
0 = C0 is configured as a GPIO (D4).
1 = C0 is configured as a keypad column (Column 0).
0 = R3 is configured as a GPIO (D3).
1 = R3 is configured as a keypad row (Row 3). Ensure that R3_MODE = 1 when R3 is to be used as a
GPIO or a keypad row.
0 = R2 is configured as a GPIO (D2).
1 = R2 is configured as a keypad row (Row 2).
0 = R1 is configured as a GPIO (D1).
1 = R1 is configured as a keypad row (Row 1).
0 = R0 is configured as a GPIO (D0).
1 = R0 is configured as a keypad row (Row 0).
Table 32. Register 0x18, GPIO Configuration 2 (GPIO Direction) (GPIO_CFG_2)
Bit
7
Mnemonic
D7_DIR
R/W
R/W
6
D6_DIR
R/W
5
D5_DIR
R/W
4
D4_DIR
R/W
3
D3_DIR
R/W
2
D2_DIR
R/W
1
D1_DIR
R/W
0
D0_DIR
R/W
Description
0 = D7 is configured as an input.
1 = D7 is configured as an output.
0 = D6 is configured as an input.
1 = D6 is configured as an output.
0 = D5 is configured as an input.
1 = D5 is configured as an output.
0 = D4 is configured as an input.
1 = D4 is configured as an output.
0 = D3 is configured as an input.
1 = D3 is configured as an output.
0 = D2 is configured as an input.
1 = D2 is configured as an output.
0 = D1 is configured as an input.
1 = D1 is configured as an output.
0 = D0 is configured as an input.
1 = D0 is configured as an output.
Rev. B | Page 28 of 38
Data Sheet
ADP5520
Table 33. Register 0x19, GPIO Input Status (GPIO_IN)
Bit
7
Mnemonic
D7_IN
R/W
R
6
D6_IN
R
5
D5_IN
R
4
D4_IN
R
3
D3_IN
R
2
D2_IN
R
1
D1_IN
R
0
D0_IN
R
Description
0 = D7 input is low.
1 = D7 input is high.
0 = D6 input is low.
1 = D6 input is high.
0 = D5 input is low.
1 = D5 input is high.
0 = D4 input is low.
1 = D4 input is high.
0 = D3 input is low.
1 = D3 input is high.
0 = D2 input is low.
1 = D2 input is high.
0 = D1 input is low.
1 = D1 input is high.
0 = D0 input is low.
1 = D0 input is high.
Table 34. Register 0x1A, GPIO Output Drive (GPIO_OUT)
Bit
7
Mnemonic
D7_OUT
R/W
R/W
6
D6_OUT
R/W
5
D5_OUT
R/W
4
D4_OUT
R/W
3
D3_OUT
R/W
2
D2_OUT
R/W
1
D1_OUT
R/W
0
D0_OUT
R/W
Description
0 = D7 output is driven low.
1 = D7 output is driven high.
0 = D6 output is driven low.
1 = D6 output is driven high.
0 = D5 output is driven low.
1 = D5 output is driven high.
0 = D4 output is driven low.
1 = D4 output is driven high.
0 = D3 output is driven low.
1 = D3 output is driven high.
0 = D2 output is driven low.
1 = D2 output is driven high.
0 = D1 output is driven low.
1 = D1 output is driven high.
0 = D0 output is driven low.
1 = D0 output is driven high.
Table 35. Register 0x1B, GPIO Interrupt Enable (GPIO_INT_EN)
Bit
7
Mnemonic
D7_IN_IEN
R/W
R/W
6
D6_IN_IEN
R/W
5
D5_IN_IEN
R/W
4
D4_IN_IEN
R/W
3
D3_IN_IEN
R/W
2
D2_IN_IEN
R/W
Description
0 = prevents D7 input from generating interrupts on INT.
1 = allows D7 input to generate interrupts on INT.
0 = prevents D6 input from generating interrupts on INT.
1 = allows D6 input to generate interrupts on INT.
0 = prevents D5 input from generating interrupts on INT.
1 = allows D5 input to generate interrupts on INT.
0 = prevents D4 input from generating interrupts on INT.
1 = allows D4 input to generate interrupts on INT.
0 = prevents D3 input from generating interrupts on INT.
1 = allows D3 input to generate interrupts on INT.
0 = prevents D2 input from generating interrupts on INT.
1 = allows D2 input to generate interrupts on INT.
Rev. B | Page 29 of 38
ADP5520
Data Sheet
Bit
1
Mnemonic
D1_IN_IEN
R/W
R/W
0
D0_IN_IEN
R/W
Description
0 = prevents D1 input from generating interrupts on INT.
1 = allows D1 input to generate interrupts on INT.
0 = prevents D0 input from generating interrupts on INT.
1 = allows D0 input to generate interrupts on INT.
Table 36. Register 0x1C, GPIO Interrupt Status (GPIO_INT_STAT)
Bit
7
Mnemonic
D7_IN_ISTAT
R/W
R
6
D6_IN_ISTAT
R
5
D5_IN_ISTAT
R
4
D4_IN_ISTAT
R
3
D3_IN_ISTAT
R
2
D2_IN_ISTAT
R
1
D1_IN_ISTAT
R
0
D0_IN_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt condition detected on D7_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D6_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D5_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D4_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D3_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D2_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D1_IN. Bit cleared when read twice.
0 = no interrupt detected.
1 = interrupt condition detected on D0_IN. Bit cleared when read twice.
Table 37. Register 0x1D, GPIO Interrupt Level Configuration (GPIO_INT_LVL)
Bit
7
Mnemonic
D7_ILVL
R/W
R/W
6
D6_ILVL
R/W
5
D5_ILVL
R/W
4
D4_ILVL
R/W
3
D3_ILVL
R/W
2
D2_ILVL
R/W
1
D1_ILVL
R/W
0
D0_ILVL
R/W
Description
0 = interrupt generated when D7_IN is low.
1 = interrupt generated when D7_IN is high.
0 = interrupt generated when D6_IN is low.
1 = interrupt generated when D6_IN is high.
0 = interrupt generated when D5_IN is low.
1 = interrupt generated when D5_IN is high.
0 = interrupt generated when D4_IN is low.
1 = interrupt generated when D4_IN is high.
0 = interrupt generated when D3_IN is low.
1 = interrupt generated when D3_IN is high.
0 = interrupt generated when D2_IN is low.
1 = interrupt generated when D2_IN is high.
0 = interrupt generated when D1_IN is low.
1 = interrupt generated when D1_IN is high.
0 = interrupt generated when D0_IN is low.
1 = interrupt generated when D0_IN is high.
Rev. B | Page 30 of 38
Data Sheet
ADP5520
Table 38. Register 0x1E, GPIO Input Debounce Enable/Disable (GPIO_DEBOUNCE)
Bit
7
Mnemonic
D7_ IN_ DBNC
R/W
R/W
6
D6_ IN_ DBNC
R/W
5
D5_ IN_ DBNC
R/W
4
D4_ IN_ DBNC
R/W
3
D3_ IN_ DBNC
R/W
2
D2_ IN_ DBNC
R/W
1
D1_ IN_ DBNC
R/W
0
D0_ IN_ DBNC
R/W
Description
0 = D7_IN debounce enabled.
1 = D7_IN debounce disabled.
0 = D6_IN debounce enabled.
1 = D6_IN debounce disabled.
0 = D5_IN debounce enabled.
1 = D5_IN debounce disabled.
0 = D4_IN debounce enabled.
1 = D4_IN debounce disabled.
0 = D3_IN debounce enabled.
1 = D3_IN debounce disabled.
0 = D2_IN debounce enabled.
1 = D2_IN debounce disabled.
0 = D1_IN debounce enabled.
1 = D1_IN debounce disabled.
0 = D0_IN debounce enabled.
1 = D0_IN debounce disabled.
Table 39. Register 0x1F, GPIO Pull-Up Enable/Disable (GPIO_PULLUP)
Bit
7
Mnemonic
D7_PULL
R/W
R/W
6
D6_PULL
R/W
5
D5_PULL
R/W
4
D4_PULL
R/W
3
D3_PULL
R/W
2
D2_PULL
R/W
1
D1_PULL
R/W
0
D0_PULL
R/W
Description
0 = D7_IN pull-up disabled.
1 = D7_IN pull-up enabled.
0 = D6_IN pull-up disabled.
1 = D6_IN pull-up enabled.
0 = D5_IN pull-up disabled.
1 = D5_IN pull-up enabled.
0 = D4_IN pull-up disabled.
1 = D4_IN pull-up enabled.
0 = D3_IN pull-up disabled.
1 = D3_IN pull-up enabled.
0 = D2_IN pull-up disabled.
1 = D2_IN pull-up enabled.
0 = D1_IN pull-up disabled.
1 = D1_IN pull-up enabled.
0 = D0_IN pull-up disabled.
1 = D0_IN pull-up enabled.
Table 40. Register 0x20, Key Press Interrupt Status 1 (KP_INT_STAT_1)
Bit
7
Mnemonic
KP_A_ISTAT
R/W
R
6
KP_B_ISTAT
R
5
KP_C_ISTAT
R
4
KP_D_ISTAT
R
3
KP_E_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key A press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key B press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key C press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key D press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key E press. Bit cleared on read.
Rev. B | Page 31 of 38
ADP5520
Data Sheet
Bit
2
Mnemonic
KP_F_ISTAT
R/W
R
1
KP_G_ISTAT
R
0
KP_H_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key F press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key G press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key H press. Bit cleared on read.
Table 41. Register 0x21, Key Press Interrupt Status 2 (KP_INT_STAT_2)
Bit
7
Mnemonic
KP_I_ISTAT
R/W
R
6
KP_J_ISTAT
R
5
KP_K_ISTAT
R
4
KP_L_ISTAT
R
3
KP_M_ISTAT
R
2
KP_N_ISTAT
R
1
KP_O_ISTAT
R
0
KP_P_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key I press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key J press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key K press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key L press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key M press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key N press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key O press. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key P press. Bit cleared on read.
Table 42. Register 0x22, Key Release Interrupt Status 1 (KR_INT_STAT_1)
Bit
7
Mnemonic
KR_A_ISTAT
R/W
R
6
KR_B_ISTAT
R
5
KR_C_ISTAT
R
4
KR_D_ISTAT
R
3
KR_E_ISTAT
R
2
KR_F_ISTAT
R
1
KR_G_ISTAT
R
0
KR_H_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key A release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key B release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key C release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key D release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key E release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key F release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key G release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key H release. Bit cleared on read.
Table 43. Register 0x23, Key Release Interrupt Status 2 (KR_INT_STAT_2)
Bit
7
Mnemonic
KR_I_ISTAT
R/W
R
6
KR_J_ISTAT
R
5
KR_K_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key I release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key J release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key K release. Bit cleared on read.
Rev. B | Page 32 of 38
Data Sheet
ADP5520
Bit
4
Mnemonic
KR_L_ISTAT
R/W
R
3
KR_M_ISTAT
R
2
KR_N_ISTAT
R
1
KR_O_ISTAT
R
0
KR_P_ISTAT
R
Description
0 = no interrupt detected.
1 = interrupt due to Key L release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key M release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key N release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key O release. Bit cleared on read.
0 = no interrupt detected.
1 = interrupt due to Key P release. Bit cleared on read.
Table 44. Register 0x24, Key Status 1 (KEY_STAT_1)
Bit
7
Mnemonic
KEY_A_STAT
R/W
R
6
KEY_B_STAT
R
5
KEY_C_STAT
R
4
KEY_D_STAT
R
3
KEY_E_STAT
R
2
KEY_F_STAT
R
1
KEY_G_STAT
R
0
KEY_H_STAT
R
Description
0 = Key A is currently released.
1 = Key A is currently pressed.
0 = Key B is currently released.
1 = Key B is currently pressed.
0 = Key C is currently released.
1 = Key C is currently pressed.
0 = Key D is currently released.
1 = Key D is currently pressed.
0 = Key E is currently released.
1 = Key E is currently pressed.
0 = Key F is currently released.
1 = Key F is currently pressed.
0 = Key G is currently released.
1 = Key G is currently pressed.
0 = Key H is currently released.
1 = Key H is currently pressed.
Table 45. Register 0x25, Key Status 2 (KEY_STAT_2)
Bit
7
Mnemonic
KEY_I_STAT
R/W
R
6
KEY_J_STAT
R
5
KEY_K_STAT
R
4
KEY_L_STAT
R
3
KEY_M_STAT
R
2
KEY_N_STAT
R
1
KEY_O_STAT
R
0
KEY_P_STAT
R
Description
0 = Key I is currently released.
1 = Key I is currently pressed.
0 = Key J is currently released.
1 = Key J is currently pressed.
0 = Key K is currently released.
1 = Key K is currently pressed.
0 = Key L is currently released.
1 = Key L is currently pressed.
0 = Key M is currently released.
1 = Key M is currently pressed.
0 = Key N is currently released.
1 = Key N is currently pressed.
0 = Key O is currently released.
1 = Key O is currently pressed.
0 = Key P is currently released.
1 = Key P is currently pressed.
Rev. B | Page 33 of 38
ADP5520
Data Sheet
APPLICATIONS INFORMATION
CONVERTER TOPOLOGY
The ADP5520 backlight driver utilizes a dc-to-dc step-up
(boost) converter to achieve the high voltage levels required to
drive up to six white LEDs in series. Figure 50 shows the basic
asynchronous boost converter topology.
4.7µH
SW
1µF
BST
2
BL_SNK
22
27V
I-LIMIT
23
AUTO
LOAD
FB
0.65V
OVP
VOUT
PGND
07445-058
VBAT
BACKLIGHT
CURRENT
CONTROL
BOOST
CONTROL
1
THERMAL S/D
21
07445-059
VIN
1µF
VBAT
Figure 51. Boost Configuration
Figure 50. Basic Asynchronous Boost Converter Topology
Assuming an initial steady state condition where the switch has
been open for a long time, then the output voltage (VOUT) is
equal to the input voltage (VIN), minus a diode drop.
If the switch is closed, the output voltage maintains its value as
the diode blocks its path to ground. The inductor, however, has
a voltage differential across its terminals. Current in an inductor
cannot change instantaneously, so it increases linearly at a rate of
di/dt = VIN/L
where L is the inductance value in Henrys.
If the switch is kept closed, the current increases until the inductor
reaches its saturation limit, at which point the inductor becomes
a dc path to ground. Therefore, keep the switch closed only long
enough to build some transient energy in the inductor, but not so
long that the inductor becomes saturated.
When the switch is opened, the current that has built up in the
inductor continues to flow (as previously mentioned, the current
in an inductor cannot change instantaneously), so the voltage
at the top of the switch increases and forward biases the diode,
allowing the inductor current to charge the capacitor, and,
therefore, increase the overall output voltage level. If the switch
is continuously opened and closed, the output voltage continues
to increase.
Figure 51 shows the boost configuration as used in the ADP5520.
A Schottky diode is used due to its fast turn-on time and low
forward voltage drop. An input capacitor is added to reduce ripple
voltage that is generated on the input supply due to charging/
discharging of the inductor. An integrated power switch is used
to control current levels in the inductor. A control loop consisting
of a feedback signal, some safety limiting features, and a switch
drive signal complete the boost converter topology.
The ADP5520 uses a current-limiting PFM control scheme. For
medium to large output currents, the converter operates in
pseudo continuous conduction mode (CCM). It generates
bursts of peak current limited pulses (600 mA typical) in the
inductor, as shown in Figure 9.
For light output currents, the converter operates in pseudo
discontinuous conduction mode (DCM). It generates bursts of
small (200 mA typical) and medium (400 mA typical) current
pulses in the inductor, as shown in Figure 11.
To maintain reasonable burst frequencies during very light
load conditions, an automatic dummy load feature is available.
When enabled, the 1 mA dummy load is activated if the backlight sink current code drops below 8 while in linear law mode,
or if the backlight sink current code drops below 32 while in
square law mode.
Safety Features
The ADP5520 utilizes an overvoltage protection (OVP) circuit
that monitors the boosted voltage on the output capacitor. If the
LED string becomes open (due to a broken LED), the control
circuit continually commands the boost voltage to increase.
If the boost level exceeds the maximum process rating for the
ADP5520, damage to the device can occur. The ADP5520 boost
converter has an OVP limit of 27 V (typical).
The ADP5520 also has a feature that ramps down the backlight
code when an OVP condition is detected. This may be useful in
conditions where LEDs with marginally high forward voltages
are used in low ambient conditions. The feature can be enabled
by setting the OVP_EN bit in Register 0x02.
The ADP5520 also features a thermal shutdown circuit. When
the die junction temperature reaches 150°C (typical), the boost
converter shuts down. It remains shut down until the die
temperature falls by 10°C (typical).
Rev. B | Page 34 of 38
Data Sheet
ADP5520
Component Selection
input capacitor with sufficient ripple current rating to handle
the inductor ripple. A 1 μF X5R/X7R ceramic capacitor rated
for 16 V dc bias is recommended for the input capacitance.
The ADP5520 boost converter is designed for use with a 4.7 μH
inductor. Choose an inductor with a sufficient current rating to
prevent it from going into saturation. The peak current limit of
the ADP5520 is 750 mA (maximum), so choose an inductor
with a greater saturation rating. To maximize efficiency, choose
an inductor with a low series resistance (DCR).
The output capacitor maintains the output voltage when the
Schottky diode is not conducting. Due to the high levels of
boost voltage required, a 1 μF X5R/X7R ceramic capacitor rated
for 50 V dc bias is recommended for output capacitance.
The ADP5520 is an asynchronous boost and, as such, requires
an external Schottky diode to conduct the inductor current to
the output capacitor and LED string when the power switch is
off. Ensure that the Schottky diode peak current rating is greater
than the maximum inductor current. Choose a Schottky diode
with an average current rating that is significantly larger than
the maximum LED current. To prevent thermal runaway, derate
the Schottky diode to ensure reliable operation at high junction
temperatures. To maximize efficiency, select a Schottky diode
with a low forward voltage. When the power switch is on, the
Schottky diode blocks the dc path from the output capacitor to
ground. Therefore, choose a Schottky diode with a reverse
breakdown greater than the maximum boost voltage. A 40 V,
1 A Schottky diode is recommended.
Note that dc bias characterization data is available from
capacitor manufacturers and must be taken into account when
selecting input and output capacitors.
PCB LAYOUT
Good PCB layout is important to maximize efficiency and to
minimize noise and electromagnetic interference (EMI). To
minimize large current loops, place the input capacitor, inductor,
Schottky diode, and output capacitor as close as possible to each
other and to the ADP5520 using wide tracks (use shapes where
possible). For thermal relief, connect the exposed pad of the
LFCSP package to ground (GND).
Connect PGND and GND to each other at the bottom of the
output capacitor.
The input capacitor carries the input ripple current, allowing
the input power source to supply only the dc current. Use an
Figure 52 shows an example PCB layout with the main power
components required for backlight driving.
GND
VBAT
TOP OF LED STRING
VBAT
CAP_OUT
SW
BST
GND
PGND
BL_SNK
BOTTOM OF LED STRING
GND
GND
CMP_IN
VDDIO
INT
ADP5520
RST
SCL
ILED
R2
CONNECT EXPOSED
PAD TO GND
Figure 52. Example PCB Layout
Rev. B | Page 35 of 38
07445-061
C3
C2
C1
C0
R1
R3
R0
SOLUTION SIZE
APPROXIMATELY 47mm2
SDA
ADP5520
Data Sheet
EXAMPLE CIRCUITS
1µF
VBAT
4.7µH
SW
BST
BL_SNK
CAP_OUT 20
GND 18
ADP5520
5 SCL
11
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
R2 R1 R0 C0 C1 C2
14
12
6
VBAT
1µF
2
22
23
SW
BST
BL_SNK
GND 18
GND 24
4 SDA
100nF
CMP_IN 17
15 RST
R3
C3
ILED
13
12
14
6
7
8
9
10
11
A
B
C
E
F
G
I
J
K
VBAT
VBAT
21
VBAT
16
VDDIO
5
SCL
A
B
C
E
F
G
I
J
K
R3 C3
13
12
ILED
VBAT
14
VBAT
4
SDA
3
INT
15
RST
Figure 54. I/O Configuration Example 2
22
23
BST
BL_SNK
CAP_OUT 20
1µF
GND 19
GND 18
ADP5520
GND 24
100nF
CMP_IN 17
R3 R2 R1 R0 C0 C1 C2 C3
13
07445-040
R2 R1 R0 C0 C1 C2
PGND SW
I/O
ADP5520
1
2.2kΩ
10kΩ
GND 19
2.2kΩ
16 VDDIO
10kΩ
I/O RAIL
1µF
3 INT
11
4.7µH
2
CAP_OUT 20
5 SCL
10
1µF
VBAT
21 VBAT
9
Figure 55. I/O Configuration Example 3
4.7µH
1 PGND
8
7
07445-041
10
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
Figure 56. I/O Configuration Example 4
Rev. B | Page 36 of 38
ILED
VBAT
14
VBAT
07445-042
9
I/O
8
I/O
7
1µF
2.2kΩ
100nF
CMP_IN 17
I/O
6
VBAT
2.2kΩ
GND 24
INT
VBAT
Figure 53. I/O Configuration Example 1
10kΩ
GND 18
ADP5520
07445-039
13
10kΩ
1µF
GND 19
15 RST
ILED
R3 R2 R1 R0 C0 C1 C2 C3
I/O RAIL
CAP_OUT 20
16 VDDIO
3
CMP_IN 17
15 RST
1µF
23
BL_SNK
4 SDA
100nF
INT
22
BST
5 SCL
GND 24
4 SDA
3
2.2kΩ
GND 19
2
SW
21 VBAT
I/O RAIL
1µF
16 VDDIO
4.7µH
1 PGND
10kΩ
2.2kΩ
2.2kΩ
10kΩ
23
21 VBAT
I/O RAIL
10kΩ
22
2.2kΩ
1 PGND
1µF
2
10kΩ
1µF
1µF
VBAT
Data Sheet
ADP5520
1µF
VBAT
4.7µH
2
PGND SW
21
VBAT
4
SDA
3
INT
15
RST
CAP_OUT 20
GND 19
GND 18
2
22
23
SW
BST
BL_SNK
CAP_OUT 20
21 VBAT
I/O RAIL
1µF
ADP5520
4.7µH
1 PGND
2.2kΩ
SCL
BL_SNK
10kΩ
5
BST
2.2kΩ
VDDIO
23
10kΩ
16
1µF
16 VDDIO
GND 19
GND 18
ADP5520
5 SCL
GND 24
GND 24
4 SDA
100nF
100nF
3 INT
CMP_IN 17
CMP_IN 17
15 RST
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R2 R1 R0 C0 C1 C2
14
VBAT
6
7
8
9
10
11
R3
C3
ILED
13
12
14
VBAT
07445-045
11
VBAT
Figure 59. I/O Configuration Example 7
Figure 57. I/O Configuration Example 5
1µF
VBAT
4.7µH
1µF
22
23
BST
BL_SNK
2
PGND SW
21
VBAT
SDA
3
INT
15
RST
GND 19
GND 18
ADP5520
GND 24
100nF
CMP_IN 17
R3 R2 R1 R0 C0 C1
C2
C3
ILED
9
10
11
12
14
A
B
E
F
I
J
M
N
13
6
7
8
VBAT
1
PGND SW
21
VBAT
16
VDDIO
5
SCL
4
SDA
3
INT
15
RST
2.2kΩ
4
I/O RAIL
1µF
2.2kΩ
SCL
CAP_OUT 20
10kΩ
5
2
10kΩ
VDDIO
4.7µH
22
23
BST
BL_SNK
CAP_OUT 20
1µF
GND 19
GND 18
ADP5520
GND 24
100nF
CMP_IN 17
R3 R2 R1 R0 C0 C1 C2 C3
13
6
7
8
9
10
11
12
ILED
VBAT
Figure 58. I/O Configuration Example 6
Figure 60. I/O Configuration Example 8
Rev. B | Page 37 of 38
VBAT
14
I/O PORT UNUSED
07445-044
16
2.2kΩ
2.2kΩ
10kΩ
10kΩ
I/O RAIL
1
I/O
1µF
1µF
VBAT
07445-046
10
I/O
9
I/O
8
I/O
7
VBAT
I/O
6
ILED
I/O
13
I/O
R3 R2 R1 R0 C0 C1 C2 C3
I/O
2.2kΩ
10kΩ
2.2kΩ
10kΩ
I/O RAIL
1
1µF
22
07445-043
1µF
1µF
VBAT
ADP5520
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
1
0.50
BSC
2.44
2.30 SQ
2.16
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
PKG-003994/5111
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
03-09-2017-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 61. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADP5520ACPZ-RL
1
Temperature Range
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07445-0-10/17(B)
Rev. B | Page 38 of 38
Package Option
CP-24-14
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湘ICP备2023018690号
