SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
DEDICATED AUDIO COMPONENTS
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multiplier/divider ratios
Available in a 208-lead LQFP_EP package
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Ordering Guide on Page 56.
Internal Memory
SIMD Core
Instruction
Cache
Block 0
RAM/ROM
Block 2
RAM
Block 3
RAM
5 stage
Sequencer
DAG1/2
Timer
PEx
PEy
S
PMD 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DMD 64-BIT
DMD 64-BIT
FLAGx/IRQx/
TMREXP
Block 1
RAM/ROM
Core Bus
Cross Bar
Internal Memory I/F
PMD 64-BIT
IODO 32-BIT
EPD BUS 48-BIT
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM/
DTCP
PERIPHERAL BUS
CORE PCG
FLAGS C-D
TIMER
1-0
TWI
EP
SPI/B
UART
DPI Routing/Pins
PCG
A-D
S/PDIF IDP/ SPORT
Tx/Rx PDAP
7-0
7-0
DAI Routing/Pins
DPI Peripherals
DAI Peripherals
CORE PWM
FLAGS 3-0
AMI
SDRAM
External Port Pin MUX
Peripherals
External
Port
Figure 1. Functional Block Diagram
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Rev. D
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ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Package Information ............................................ 18
Dedicated Audio Components ................................. 1
Maximum Power Dissipation ................................. 18
General Description ................................................. 3
Absolute Maximum Ratings ................................... 18
SHARC Family Core Architecture ............................ 4
ESD Sensitivity ................................................... 18
Family Peripheral Architecture ................................ 6
Timing Specifications ........................................... 18
I/O Processor Features ......................................... 10
Output Drive Currents ......................................... 49
System Design .................................................... 10
Test Conditions .................................................. 49
Development Tools ............................................. 11
Capacitive Loading .............................................. 49
Additional Information ........................................ 12
Thermal Characteristics ........................................ 50
Related Signal Chains .......................................... 12
208-Lead LQFP_EP Pinout ....................................... 51
Pin Function Descriptions ....................................... 13
Package Dimensions ............................................... 55
ADSP-21371/ADSP-21375 Specifications .................... 16
Automotive Products .............................................. 56
Operating Conditions .......................................... 16
Ordering Guide ..................................................... 56
Electrical Characteristics ....................................... 17
REVISION HISTORY
4/13—Rev. C to Rev. D
Corrected Extended Precision Normal or Instruction Word
(48 bits) ADSP-21375 Internal Memory Space .................7
Added 1.0 V, 200 MHz specifications to the following timing
specifications.
Clock Input ............................................................21
Updated Development Tools ..................................... 11
Precision Clock Generator (Direct Pin Routing) .............26
Added section Related Signal Chains ...........................12
SDRAM Interface Timing ..........................................28
Revised MS1-0 pin description in
Pin Function Descriptions ........................................ 13
Memory Read—Bus Master .......................................29
Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in
Pin Function Descriptions ........................................ 13
Serial Ports ............................................................33
Corrected TJUNCTION specifications in
Operating Conditions .............................................. 16
S/PDIF Transmitter Input Data Timing ........................42
Added footnote 3 to Table 25 in
Memory Read—Bus Master ....................................... 29
Memory Write—Bus Master ......................................31
Input Data Port (IDP) ..............................................38
S/PDIF Receiver ......................................................43
SPI Interface—Slave .................................................45
Updated Serial Ports timing parameter data in Serial Ports—
External Clock ....................................................... 33
Updated Serial Ports timing parameter data in Serial Ports—
Internal Clock ........................................................ 34
Changed Max values in Table 33 in Pulse-Width Modulation
Generators (PWM) ................................................. 40
Updated timing parameters in Table 37 and in Figure 31 in
SPI Interface—Master .............................................. 44
Rev. D | Page 2 of 56 | April 2013
ADSP-21371/ADSP-21375
GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are members of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point processors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
As shown in the functional block diagram on Page 1, the processors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
Table 1. Processor Benchmarks (at 266 MHz)
Feature
ADSP-21371
Digital Peripheral Interface
(DPI)
S/PDIF Transceiver
ADSP-21375
Yes
Yes
No
SPI
2
TWI
Yes
Package
208-Lead LQFP_EP
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• One periodic interval timer with pinout
Speed
Benchmark Algorithm
(at 266 MHz)
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s
FIR Filter (per Tap)1
1.88 ns
IIR Filter (per Biquad)1
7.5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
16.91 ns
[4 × 4] × [4 × 1]
30.07 ns
Divide (y/x)
13.1 ns
Inverse Square Root
20.4 ns
1
Assumes two files in multichannel SIMD mode
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user breakpoints which allow flexible exception handling.
The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:
• Peripheral and external port bus for core connection
Feature
ADSP-21371
ADSP-21375
Frequency
266 MHz
(3.75 ns)
266 MHz
(3.75 ns)
RAM
1M bit
0.5M bit
ROM
4M bits
2M bits
Pulse-Width Modulation
Yes
No
Serial Ports
8
4
Digital Application
Interface (DAI)
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
Table 2. ADSP-21371/ADSP-21375 Features
UART
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)
1
Yes
• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
• External port with AMI and SDRAM controller
• Four units for PWM control
• One MTM for internal to internal memory transfers
Rev. D | Page 3 of 56 | April 2013
ADSP-21371/ADSP-21375
SHARC FAMILY CORE ARCHITECTURE
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
The ADSP-21371/ADSP-21375 processors are code compatible
at the assembly level with the ADSP-2136x, ADSP-2126x,
ADSP-21160x, and ADSP-21161N, and with the first generation
ADSP-2106x SHARC processors. The ADSP-21371/
ADSP-21375 processors share architectural features with the
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC
processors, as shown in Figure 2 and detailed in the following
sections.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
SIMD Computational Engine
The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
S
JTAG
FLAG
TIMER INTERRUPT CACHE
SIMD Core
PM ADDRESS 24
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
DAG1
16x32
DAG2
16x32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
USTAT
4x32-BIT
PM DATA 64
PX
64-BIT
DM DATA 64
MULTIPLIER
MRF
80-BIT
MRB
80-BIT
SHIFTER
ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ASTATx
ASTATy
STYKx
STYKy
Figure 2. SHARC Core Block Diagram
Rev. D | Page 4 of 56 | April 2013
ALU
SHIFTER
MULTIPLIER
MSB
80-BIT
MSF
80-BIT
ADSP-21371/ADSP-21375
Data Register File
Each processing element contains a general-purpose data register file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the SHARC’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
Universal registers can be used for general purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register PX permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These registers contain hardware to handle the data width difference.
Timer
The processors contain a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Single-Cycle Fetch of an Instruction and Four Operands
The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 2). With the processor’s separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch four operands (two over each data bus)
and one instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract
in both processing elements while branching and fetching up to
four 32-bit values from memory—all in a single instruction.
On-Chip Memory
The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM (see
Table 3 on Page 6) and the ADSP-21375 processor contains 0.5
megabits of internal RAM and two megabits of internal maskprogrammable ROM (see Table 4 on Page 7). Each block can be
configured for different combinations of code and data storage.
Each memory block supports single-cycle, independent accesses
by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.
The ADSP-21371 processor’s SRAM can be configured as a
maximum of 32k words of 32-bit data, 64k words of 16-bit data,
21.3k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 1 megabit. All of the memory
can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16bit floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows four accesses at the
same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses
(2 64-bits, core CLK) and the IOD0/1 buses (2 32-bit,
PCLK).
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
ROM-Based Security
The processors’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
The processors have a ROM security feature that provides hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
Rev. D | Page 5 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 3. ADSP-21371 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits)
Normal Word (32 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAA9
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 BFFF
Reserved
0x0008 AAAA–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 CFFF
BLOCK 0 RAM
0x0009 0000–0x0009 1554
BLOCK 0 RAM
0x0009 8000–0x0009 9FFF
BLOCK 0 RAM
0x0013 0000–0x0013 3FFF
Reserved
0x0004 D000–0x0004 FFFF
Reserved
0x0009 1555–0x0009 FFFF
Reserved
0x0009 A000–0x0009 FFFF
Reserved
0x0013 4000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
BLOCK 1 ROM
0x000A 0000–0x000A AAA9
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 BFFF
Reserved
0x000A AAAA–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 CFFF
BLOCK 1 RAM
0x000B 0000–0x000B 1554
BLOCK 1 RAM
0x000B 8000–0x000B 9FFF
BLOCK 1 RAM
0x0017 0000–0x0017 3FFF
Reserved
0x0005 D000–0x0005 FFFF
Reserved
0x000B 1555–0x000B FFFF
Reserved
0x000B A000–0x000B FFFF
Reserved
0x0017 4000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 0FFF
BLOCK 2 RAM
0x000C 0000–0x000C 1554
BLOCK 2 RAM
0x000C 0000–0x000C 1FFF
BLOCK 2 RAM
0x0018 0000–0x0018 3FFF
Reserved
0x0006 1000–0x0006 FFFF
Reserved
0x000C 1555–0x000D FFFF
Reserved
0x000C 2000–0x000D FFFF
Reserved
0x0018 4000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 0FFF
BLOCK 3 RAM
0x000E 0000–0x000E 1554
BLOCK 3 RAM
0x000E 0000–0x000E 1FFF
BLOCK 3 RAM
0x001C 0000–0x001C 3FFF
Reserved
0x0007 1000–0x0007 FFFF
Reserved
0x000E 1555–0x000F FFFF
Reserved
0x000E 2000–0x000F FFFF
Reserved
0x001C 4000–0x001F FFFF
external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21371/ADSP-21375 family contains a rich set of
peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications,
military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications.
External Port
The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchronous and/or asynchronous memory devices through the use of
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asynchronous device types.
Rev. D | Page 6 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 4. ADSP-21375 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits)
Normal Word (32 bits)
Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 3FFF
BLOCK 0 ROM
0x0008 0000–0x0008 5554
BLOCK 0 ROM
0x0008 0000–0x0008 7FFF
BLOCK 0 ROM
0x0010 0000–0x0010 FFFF
Reserved
0x0004 4000–0x0004 BFFF
Reserved
0x0008 5555–0x0008 FFFF
Reserved
0x0008 8000–0x0009 7FFF
Reserved
0x0011 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 C7FF
BLOCK 0 RAM
0x0009 0000–0x0009 0AA9
BLOCK 0 RAM
0x0009 8000–0x0009 8FFF
BLOCK 0 RAM
0x0013 0000–0x0013 1FFF
Reserved
0x0004 C800–0x0004 FFFF
Reserved
0x0009 0AAA–0x0009 FFFF
Reserved
0x0009 9000–0x0009 FFFF
Reserved
0x0013 2000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 3FFF
BLOCK 1 ROM
0x000A 0000–0x000A 5554
BLOCK 1 ROM
0x000A 0000–0x000A 7FFF
BLOCK 1 ROM
0x0014 0000–0x0014 FFFF
Reserved
0x0005 4000–0x0005 BFFF
Reserved
0x000A 5555–0x000A FFFF
Reserved
0x000A 8000–0x000B 7FFF
Reserved
0x0015 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 C7FF
BLOCK 1 RAM
0x000B 0000–0x000B 0AA9
BLOCK 1 RAM
0x000B 8000–0x000B 8FFF
BLOCK 1 RAM
0x0017 0000–0x0017 1FFF
Reserved
0x0005 C800–0x0005 FFFF
Reserved
0x000B 0AAA–0x000B FFFF
Reserved
0x000B 9000–0x000B FFFF
Reserved
0x0017 2000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 07FF
BLOCK 2 RAM
0x000C 0000–0x000C 0AA9
BLOCK 2 RAM
0x000C 0000–0x000C 0FFF
BLOCK 2 RAM
0x0018 0000–0x0018 1FFF
Reserved
0x0006 0800–0x0006 FFFF
Reserved
0x000C 0AAA–0x000D FFFF
Reserved
0x000C 1000–0x000D FFFF
Reserved
0x0018 2000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 07FF
BLOCK 3 RAM
0x000E 0000–0x000E 0AA9
BLOCK 3 RAM
0x000E 0000–0x000E 0FFF
BLOCK 3 RAM
0x001C 0000–0x001C 1FFF
Reserved
0x0007 0800–0x0007 FFFF
Reserved
0x000E 0AAA–0x000F FFFF
Reserved
0x000E 1000–0x000F FFFF
Reserved
0x001C 2000–0x001F FFFF
SDRAM Controller
Table 5. External Memory for SDRAM Addresses
The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs.
Fully compliant with the SDRAM standard, each bank has its
own memory select line (MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 5.
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the
different banks.
A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide or as
32 bits wide. The SDRAM controller address, data, clock, and
command pins can drive loads up to 30 pF. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in Words
62M
64M
64M
64M
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
Note that the external memory bank addresses shown in Table 5
are for normal word accesses. If 48-bit instructions are placed in
any such bank (with two instructions packed into three 32-bit
locations), then care must be taken to map data buffers in the
same bank. For example, if 2k instructions are placed starting at
the bank 0 base address (0x0020 0000), then the data buffers can
be placed starting at an address that is offset by 3k words
(0x0020 0C00).
External Memory Code Execution
The program sequencer can execute code directly from external
memory bank 0 (SRAM, SDRAM) over the 48-bit external port
data bus (EPD). This allows a reduction in internal memory
size, thereby reducing the die area. Because instructions on the
Rev. D | Page 7 of 56 | April 2013
ADSP-21371/ADSP-21375
SHARC processor are 48 bits wide, instruction throughput
when executing code from external SDRAM memory is 2
instructions every 3 SDCLK (peripheral) clock cycles over a 32bit wide external port, and 2 instructions every 6 SDCLK clock
cycles over a 16-bit external port. Non SDRAM external memory address space is shown in Table 6.
Table 6. External Memory for Non SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in Words
14M
16M
16M
16M
Address Range
0x0020 0000–0x00FF FFFF
0x0400 0000–0x04FF FFFF
0x0800 0000–0x08FF FFFF
0x0C00 0000–0x0CFF FFFF
External Port Throughput
The throughput for the external port, based on 133 MHz clock
and 32-bit data bus, is 177M bytes/s for the AMI and 532M
bytes/s for SDRAM.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfacing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the mid-
point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the processor’s DAI pins
(DAI_P1 to DAI_P20).
Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with nonconfigurable signal paths.
In the ADSP-21371, the DAI includes eight serial ports, four
precision clock generators (PCG), and an input data port (IDP).
For the ADSP-21375, the DAI includes four serial ports, four
precision clock generators (PCG) and an input data port (IDP).
The IDP provides an additional input path to the core of the
processor, configurable as either eight channels of I2S serial
data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.
Serial Ports
The processors feature eight synchronous serial ports on the
ADSP-21371 and four on the ADSP-21375. The SPORTs provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
For the ADSP-21371, serial ports are enabled via 16 programmable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.
For the ADSP-21375, serial ports are enabled via eight programmable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.
The serial ports operate at a maximum data rate of fPCLK/4.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Rev. D | Page 8 of 56 | April 2013
ADSP-21371/ADSP-21375
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode with support for packed I2S
mode
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I2S, 24and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats.
• I2S mode
Precision Clock Generator (PCG)
• Packed I2S mode
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
• Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I2S channels (using two stereo
devices) per serial port, with a maximum of up to 32 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/reception of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The ADSP-21371 S/PDIF receiver/transmitter has no separate
DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to
the receiver/transmitter can be formatted as left justified, I2S or
right justified with word widths of 16, 18, 20, or
24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.
Input Data Port (IDP)
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I2S, left-justified sample pair, or right-justified
mode. One frame sync cycle indicates one 64-bit left/right pair,
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral (Compatible) Interface
The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface ports (SPIs). The SPI is an industrystandard synchronous serial link, enabling the SPI-compatible
ports of the processors to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a master or slave device.
The SPI-compatible peripheral implementation also features
programmable baud rates and clock phases and polarities. The
SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1
or 2 stop bits, and none, even, or odd parity. The UART port
supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
Rev. D | Page 9 of 56 | April 2013
ADSP-21371/ADSP-21375
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable. The port:
• Supports bit rates ranging from (fPCLK/1,048,576) to
(fPCLK/16) bits per second.
• Supports data formats from 7 to 12 bits per frame.
• Can be configured to generate maskable interrupts for both
transmit and receive operations.
In conjunction with the general-purpose timer functions, autobaud detection is supported.
port (PDAP), or the UART (see Table 7).
Table 7. DMA Channels
Peripheral
SPORT
PDAP
SPI
UART
EP
MTM/DTCP
Total DMA Channels
ADSP-21371
16
8
2
2
2
2
32
ADSP-21375
8
8
2
2
2
2
24
Peripheral Timers
Delay Line DMA
Two general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
The processors provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and hence to external memory) with limited core interaction.
• Pulse waveform generation mode
• Pulse width count/capture mode
Scatter/Gather DMA
• External event watchdog mode
The ADSP-2137x processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks.
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables the general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
• Digital filtering and timed event processing
• 7-bit addressing
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues. For complete system design
information, see the ADSP-2137x SHARC Processor Hardware
Reference.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the external port, an SPI master, or an
SPI slave. Booting is determined by the boot configuration
(BOOT_CFG1–0) pins in Table 8. Selection of the boot source
is controlled via the SPI as either a master or slave device, or it
can immediately begin executing from ROM.
Table 8. Boot Mode Selection
• 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA and controls the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur
between the ADSP-2137x processor’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
BOOT_CFG1–0
00
01
10
11
Booting Mode
SPI Slave Boot
SPI Master Boot
EPROM/FLASH Boot
No boot (processor executes from
internal ROM after reset)
The “Running Reset” feature allows programs to perform a reset
of the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The RESETOUT pin acts as the input for initiating a running reset.
Rev. D | Page 10 of 56 | April 2013
ADSP-21371/ADSP-21375
Power Supplies
EZ-KIT Lite Evaluation Kits
The processors have separate power supply connections for the
internal (VDDINT), and external (VDDEXT) power supplies. The
internal supplies must meet the 1.2 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same power supply.
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor’s JTAG interface ensures that the emulator will not
affect target system loading
or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide”.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
EZ-KIT Lite Evaluation Board
Algorithmic Modules
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com
and search on “Blackfin software modules” or “SHARC software
modules”.
Rev. D | Page 11 of 56 | April 2013
ADSP-21371/ADSP-21375
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the processor’s
architecture and functionality. For detailed information on the
core architecture and instruction set, refer to the ADSP-2137x
SHARC Processor Hardware Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Circuits from the LabTM site (www.analog.com/signal
chains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. D | Page 12 of 56 | April 2013
ADSP-21371/ADSP-21375
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 9:
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 9. Pin Descriptions
State During
and After
Reset
Description
Name
Type
ADDR23–0
O/T (pu)
Pulled high/
driven low
External Address. The processor outputs addresses for external memory and peripherals on these pins.
DATA31–0
I/O (pu)
Pulled high/
pulled high
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port
data pins for parallel input data. PDAP over 16-bit external port DATA is not supported
on the ADSP-21375 processor.
DAI _P20–1
I/O with
programmable
(pu)1
Pulled high/
pulled high
Digital Applications Interface Pins. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module
(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.
DPI _P14–1
I/O with
programmable
(pu)1
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and generalpurpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP
register.
ACK
I (pu)
RD
O/T (pu)
Pulled high/
driven high
External Port Read Enable. RD is asserted whenever the processor reads a word from
external memory. RD has a 22.5 k internal pull-up resistor.
WR
O/T (pu)
Pulled high/
driven high
External Port Write Enable. WR is asserted when the processor writes a word to
external memory. WR has a 22.5 k internal pull-up resistor.
SDRAS
O/T (pu)
Pulled high/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (pu)
Pulled high/
driven high
SDRAM Column Address Select. Connect to SDRAM's CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (pu)
Pulled high/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.
Rev. D | Page 13 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 9. Pin Descriptions (Continued)
State During
and After
Reset
Description
Name
Type
SDCKE
O/T (pu)
Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (pu)
Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a nonSDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK
O/T
High-Z/driving
SDRAM Clock.
MS0–1
O/T (pu)
Pulled high/
driven high
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corresponding banks of external memory. The MS1-0 lines are decoded memory address lines
that change at the same time as the other address lines. The MS1 pin can be used in
EPORT/FLASH boot mode. For more information, see the ADSP-2137x SHARC Processor
Hardware Reference.
FLAG[0]/IRQ0
I/O
FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1
I/O
FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable pu
(for MS mode)
FLAG[2] INPUT
FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/
TMREXP/ MS3
I/O with
programmable pu
(for MS mode)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3.
TDI
I (pu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k internal pull-up resistor.
TDO
O/T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k
internal pull-up resistor.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
TRST
I (pu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST has a 22.5 k
internal pull-up resistor.
EMU
O (O/D) (pu)
Emulation Status. Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 k internal
pull-up resistor.
CLK_CFG1–0
I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. See the
ADSP-2137x SHARC Processor Hardware Reference for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG1–0
I
Boot Configuration Select. These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the ADSP-2137x SHARC
Processor Hardware Reference for information about boot modes.
Rev. D | Page 14 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 9. Pin Descriptions (Continued)
1
State During
and After
Reset
Name
Type
Description
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
XTAL
O
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
CLKIN
I
Local Clock In. Used in conjunction with XTAL. CLKIN is the processor clock input. It
configures the processor to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
RESETOUT/
RUNRSTIN
I/O (pu)
Reset Out/Running Reset In. The default setting is reset out. This pin also has a second
function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For
more information, see the ADSP-2137x SHARC Processor Hardware Reference.
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Rev. D | Page 15 of 56 | April 2013
ADSP-21371/ADSP-21375
ADSP-21371/ADSP-21375 SPECIFICATIONS
OPERATING CONDITIONS
1.0 V, 200 MHz
Parameter1 Description
VDDINT
VDDEXT
VIH2
VIL2
VIH_CLKIN3
VIL_CLKIN3
TJUNCTION
TJUNCTION
TJUNCTION
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
High Level Input Voltage @ VDDEXT = Max
Low Level Input Voltage @ VDDEXT = Min
High Level Input Voltage @ VDDEXT = Max
Low Level Input Voltage @ VDDEXT = Min
Junction Temperature 208-Lead LQFP_EP @ TAMBIENT
0°C to +70°C
Junction Temperature 208-Lead LQFP_EP @ TAMBIENT
–40°C to +85°C
Junction Temperature 208-Lead LQFP_EP @ TAMBIENT
–40°C to +105°C
1.2 V, 266 MHz
Min
Max
Min
Max
Unit
0.95
3.13
2.0
–0.5
1.74
–0.5
N/A
1.05
3.47
VDDEXT + 0.5
+0.8
VDDEXT + 0.5
+1.10
N/A
1.14
3.13
2.0
–0.5
1.74
–0.5
0
1.26
3.47
VDDEXT + 0.5
+0.8
VDDEXT + 0.5
+1.10
95
V
V
V
V
V
V
ºC
N/A
N/A
–40
+110
ºC
–40
+120
N/A
N/A
ºC
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLK_CFGx, RUNRSTIN,
RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
2
Rev. D | Page 16 of 56 | April 2013
ADSP-21371/ADSP-21375
ELECTRICAL CHARACTERISTICS
1.0 V, 200 MHz
Parameter1 Description
Test Conditions
Min
VOH2
VOL2
IIH4, 5
IIL4
IILPU5
@ VDDEXT = Min, IOH = –1.0 mA3
@ VDDEXT = Min, IOL = 1.0 mA3
@ VDDEXT = Max, VIN = VDDEXT max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
2.4
IOZH6, 7
IOZL6
IOZLPU7
IDD-INTYP8, 9
10, 11
CIN
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Pull-up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Pull-up
Supply Current (Internal)
Input Capacitance
Typ
1
Min
Typ
Max
Unit
0.4
10
10
200
0.4
10
10
200
V
V
μA
μA
μA
10
10
200
10
10
200
μA
μA
μA
2.4
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT= Max, VIN = 0 V
@ VDDEXT= Max, VIN = 0 V
1.0V, 200 MHz: tCCLK = 5.00 ns,
VDDINT = 1.0 V, 25ºC
1.2V, 266 MHz: tCCLK = 3.75 ns,
VDDINT = 1.2 V, 25ºC
fIN = 1 MHz, TCASE = 25°C, VIN= 1.2 V
Max
1.2 V, 266 MHz
400
mA
600
4.7
mA
4.7
pF
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,
SDCKE, SDA10, and SDCLK.
3
See Output Drive Currents on Page 49 for typical drive current capabilities.
4
Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 k internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 k pull-ups: DAI_Px, DPI_Px, EMU.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.
10
Applies to all signal pins.
11
Guaranteed, but not tested.
Rev. D | Page 17 of 56 | April 2013
ADSP-21371/ADSP-21375
PACKAGE INFORMATION
Table 11. Absolute Maximum Ratings (Continued)
The information presented in Figure 3 provides details about
the package branding for the ADSP-21371/ADSP-21375 processor. For a complete listing of product availability, see Ordering
Guide on Page 56.
Parameter
Load Capacitance
Storage Temperature Range
Junction Temperature under Bias
Rating
200 pF
–65C to +150C
125C
ESD SENSITIVITY
a
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
ADSP-2137x
tppZ-cc
vvvvvv.x n.n
yyww country_of_origin
S
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on Page 49 under Test Conditions for voltage reference levels.
Figure 3. Typical Package Brand
Table 10. Package Brand Information
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
yyww
Field Description
Temperature Range
Package Type
RoHS Compliant Part
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note “Estimating Power Dissipation
for ADSP-2137x SHARC Processors” (EE-318) for detailed thermal and power information regarding maximum power
dissipation. For information on package thermal specifications,
see Thermal Characteristics on Page 50.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 11 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 11. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage –0.5 V to VDDEXT
Output Voltage Swing –0.5 V to VDDEXT
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Rating
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+0.5 V
+0.5 V
Rev. D | Page 18 of 56 | April 2013
ADSP-21371/ADSP-21375
Voltage Controlled Oscillator
fINPUT = CLKIN when the input divider is disabled or
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
fVCO specified in Table 14.
fINPUT = CLKIN 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12. All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to tPCLK. See the peripheral specific section
for each peripheral’s timing information.
• The product of CLKIN and PLLM must never exceed 1/2
fVCO (max) in Table 14 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed fVCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
Table 12. Clock Periods
Timing
Requirements
tCK
tCCLK
tPCLK
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) (2 × PLLD)
where:
fVCO = VCO output
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × tCCLK
Figure 4 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hardware Reference.
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
fINPUT = Input frequency to the PLL.
PMCTL
(SDCKR)
PMCTL
(PLLBP)
CLKIN
DIVIDER
fINPUT
LOOP
FILTER
fVCO
VCO
PLL
DIVIDER
fCCLK
XTAL
CCLK
SDRAM
DIVIDER
BYPASS
MUX
CLKIN
BYPASS
MUX
PLL
PMCTL
(2xPLLD)
BUF
PMCTL
(INDIV)
PLL
MULTIPLIER
DIVIDE
BY 2
PMCTL
(PLLBP)
SDCLK
PCLK
PCLK
CLK_CFGx/PMCTL (2xPLLM)
CCLK
RESET
DELAY OF
4096 CLKIN
CYCLES
PIN MUX
CLKOUT (TEST ONLY)
RESETOUT
BUF
RESETOUT
CORERST
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. D | Page 19 of 56 | April 2013
ADSP-21371/ADSP-21375
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 13.
Note that during power-up, a leakage current of approximately
200 μA may be observed on the RESET pin. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT On
tIVDDEVDD
VDDINT on Before VDDEXT
1
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid
tCLKRST
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
tPLLRST
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
Min
Max
0
–50
0
102
203
+200
200
Unit
ns
ms
ms
μs
μs
4096 × tCK + 2 × tCCLK 4, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on tSRST specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
VDDINT
VDDEXT
tRSTVDD
tIVDDEVDD
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1–0
tPLLRST
RESETOUT
Figure 5. Power-Up Sequencing
Rev. D | Page 20 of 56 | April 2013
tCORERST
ADSP-21371/ADSP-21375
Clock Input
Table 14. Clock Input
Min
Parameter
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
tCCLK2
CCLK Period
VCO Frequency
fVCO
1
2
200 MHz
Max
301
151
151
5
200
266 MHz
Max
Min
22.51
11.251
11.251
100
45
45
6
10
800
100
45
45
6
10
800
3.75
200
Unit
ns
ns
ns
ns
ns
MHz
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
tCK
CLKIN
tCKH
tCKL
Figure 6. Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in fundamental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multiplier bits in the PMCTL register.
ADSP-2137x
R1
1M⍀*
CLKIN
XTAL
R2
47⍀*
C1
22pF
Y1
C2
22pF
16.67 MHz
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
Rev. D | Page 21 of 56 | April 2013
ADSP-21371/ADSP-21375
Reset
Table 15. Reset
Parameter
Timing Requirements
tWRST1
RESET Pulse Width Low
tSRST
RESET Setup Before CLKIN Low
1
Min
Max
4 × tCK
8
Unit
ns
ns
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
tWRST
tSRST
RESET
Figure 8. Reset
Running Reset
The following timing specification applies to the RESETOUT/
RUNRSTIN pin when it is configured as RUNRSTIN.
Table 16. Running Reset
Parameter
Timing Requirements
tWRUNRST
Running RESET Pulse Width Low
tSRUNRST
Running RESET Setup Before CLKIN High
Min
4 × tCK
8
CLKIN
tWRUNRST
tSRUNRST
RUNRSTIN
Figure 9. Running Reset
Rev. D | Page 22 of 56 | April 2013
Max
Unit
ns
ns
ADSP-21371/ADSP-21375
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP pin).
Table 17. Core Timer
Parameter
Switching Characteristic
tWCTIM
TMREXP Pulse Width
Min
Max
4 × tPCLK – 1
Unit
ns
tWCTIM
FLAG3
(TMREXP)
Figure 10. Core Timer
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and
DPI_P14–1 pins when they are configured as interrupts.
Table 18. Interrupts
Parameter
Timing Requirement
tIPW
IRQx Pulse Width
Min
2 × tPCLK +2
INTERRUPT
INPUTS
tIPW
Figure 11. Interrupts
Rev. D | Page 23 of 56 | April 2013
Max
Unit
ns
ADSP-21371/ADSP-21375
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the specifications provided below are valid at the
DPI_P14–1 pins.
Table 19. Timer PWM_OUT Timing
Parameter
Switching Characteristic
tPWMO
Timer Pulse Width Output
Min
Max
Unit
2 × tPCLK – 2
2 × (231 – 1) × tPCLK
ns
tPWMO
PWM
OUTPUTS
Figure 12. Timer PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the specifications provided below are valid at
the DPI_P14–1 pins.
Table 20. Timer Width Capture Timing
Parameter
Timing Requirement
tPWI
Timer Pulse Width
Min
Max
Unit
2 × tPCLK
2 × (231– 1) × tPCLK
ns
tPWI
TIMER
CAPTURE
INPUTS
Figure 13. Timer Width Capture Timing
Rev. D | Page 24 of 56 | April 2013
ADSP-21371/ADSP-21375
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 21. DAI/DPI Pin to Pin Routing
Parameter
Timing Requirement
tDPIO
Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid
Min
Max
Unit
1.5
10
ns
DAI_Pn
DPI_Pn
tDPIO
DAI_Pm
DPI_Pm
Figure 14. DAI/DPI Pin to Pin Direct Routing
Rev. D | Page 25 of 56 | April 2013
ADSP-21371/ADSP-21375
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Table 22. Precision Clock Generator (Direct Pin Routing)
1.0 V, 200 MHz
1.2 V, 266 MHz
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
tPCLK × 4
tPCLK × 4
ns
PCG Trigger Setup Before
4.5
4.5
ns
tSTRIG
Falling Edge of PCG Input Clock
tHTRIG
PCG Trigger Hold After Falling 3
3
ns
Edge of PCG Input Clock
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame
Sync Active Edge Delay After 2.5
12.8
2.5
10
ns
PCG Input Clock
tDTRIGCLK
PCG Output Clock Delay After 2.5 + ((2.5) × tPCGIW)
12.8 + ((2.5) × tPCGIW)
2.5 + ((2.5) × tPCGIW)
10 + ((2.5) × tPCGIW)
ns
PCG Trigger
tDTRIGFS
ns
PCG Frame Sync Delay After
2.5 + ((2.5 + D – PH) 12.8 + ((2.5 + D – PH) 2.5 + ((2.5 + D – PH) 10 + ((2.5 + D – PH)
× tPCGIW)
× tPCGIW)
× tPCGIW)
PCG Trigger
× tPCGIW)
tPCGOW1
Output Clock Period
2 × tPCGIW – 1
2 × tPCGIW – 1
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.
1
Normal mode of operation.
tSTRIG
tHTRIG
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
tPCGIP
tDPCGIO
DAI_Py
DPI_Py
PCG_CLKx_O
tDTRIGCLK
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
Figure 15. Precision Clock Generator (Direct Pin Routing)
Rev. D | Page 26 of 56 | April 2013
tPCGOW
ADSP-21371/ADSP-21375
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on
Page 13 for more information on flag use.
Table 23. Flags
Parameter
Timing Requirement
DPI_P14–1, DATA31–0, FLAG3–0 IN Pulse Width
tFIPW
Switching Characteristic
tFOPW
DPI_P14–1, DATA31–0, FLAG3–0 OUT Pulse Width
Min
FLAG
INPUTS
tFIPW
FLAG
OUTPUTS
tFOPW
Figure 16. Flags
Rev. D | Page 27 of 56 | April 2013
Max
Unit
2 × tPCLK + 3
ns
2 × tPCLK – 2
ns
ADSP-21371/ADSP-21375
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 24. SDRAM Interface Timing1
Parameter
Timing Requirements
tSSDAT
DATA Setup Before SDCLK
DATA Hold After SDCLK
tHSDAT
Switching Characteristics
tSDCLK
SDCLK Period
tSDCLKH
SDCLK Width High
tSDCLKL
SDCLK Width Low
tDCAD
Command, ADDR, Data Delay After SDCLK2
Command, ADDR, Data Hold After SDCLK2
tHCAD
tDSDAT
Data Disable After SDCLK
tENSDAT
Data Enable After SDCLK
1
2
Min
1.0 V, 200 MHz
Max
1.2 V, 266 MHz
Max
Min
0.58
2.2
0.58
2.2
ns
ns
10
4
4
7.5
3
3
ns
ns
ns
ns
ns
ns
ns
6.4
5.3
1.3
1.3
5.3
5.3
1.6
1.6
For FCCLK = 133 MHz (SDCLK ratio = 1:2).
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
tSDCLKH
tSDCLK
SDCLK
tSSDAT
Unit
tHSDAT
tSDCLKL
DATA (IN)
tDCAD
tENSDAT
tHCAD
DATA (OUT)
tDCAD
tHCAD
COMMAND/ADDR
(OUT)
Figure 17. SDRAM Interface Timing for 133 MHz SDCLK
Rev. D | Page 28 of 56 | April 2013
tDSDAT
ADSP-21371/ADSP-21375
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read—Bus Master
1.0 V, 200 MHz
Max
Parameter
Min
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2, 3
W + tSDCLK – 5.12
1, 3
tDRLD
RD Low to Data Valid
W–3
tSDS
Data Setup to RD High
2.2
tHDRH
Data Hold from RD High4, 5
0
2, 6
tDAAK
ACK Delay from Address, Selects
tSCDCLK – 11.4 + W
tDSAK
ACK Delay from RD Low5
W – 7.25
Switching Characteristics
tDRHA
Address Selects Hold After RD High
RHC + 0.38
tDARL
Address Selects to RD Low2
tSDCLK – 3.8
tRW
RD Pulse Width
W – 1.4
tRWR
RD High to WR, RD, Low
HI + tSDCLK – 0.8
W = (number of wait states specified in AMICTLx register) × tSDCLK
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × tSDCLK
IC = (number of idle cycles specified in AMICTLx register) × tSDCLK)
H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
Min
1.2 V, 266 MHz
Max
W + tSDCLK – 5.12
W–3
2.2
0
tSCDCLK – 10.1 + W
W – 7.0
RHC + 0.38
tSDCLK – 3.3
W – 1.4
HI + tSDCLK – 0.8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, is referenced.
3
The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
5
Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 49 for the calculation of hold times given capacitive and dc loads.
6
ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
2
Rev. D | Page 29 of 56 | April 2013
ADSP-21371/ADSP-21375
ADDR
MSx
tDARL
tRW
tDRHA
RD
tDRLD
tSDS
tDAD
tHDRH
DATA
tDSAK
tDAAK
ACK
WR
Figure 18. Memory Read—Bus Master
Rev. D | Page 30 of 56 | April 2013
tRWR
ADSP-21371/ADSP-21375
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memories. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write—Bus Master
1.0 V, 200 MHz
1.2 V, 266 MHz
Parameter
Min
Max
Min
Max
Timing Requirements
tDAAK
ACK Delay from Address, Selects1, 2
tSDCLK – 11 + W
tSDCLK – 10.1 + W
tDSAK
ACK Delay from WR Low 1, 3
W – 7.35
W – 7.1
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tSDCLK – 4.3 + W
tSDCLK – 3.6 + W
tDAWL
Address, Selects to WR Low2
tSDCLK – 2.7
tSDCLK – 2.7
WR Pulse Width
W – 1.3
W – 1.3
tWW
tDDWH
Data Setup Before WR High
tSDCLK – 3.0 + W
tSDCLK – 3.0 + W
tDWHA
Address Hold After WR Deasserted
H + 0.15
H + 0.15
tDWHD
Data Hold After WR Deasserted
H + 0.02
H + 0.02
tDATRWH
Data Disable After WR Deasserted4
tSDCLK – 1.37 + H
tSDCLK + 10.7+ H
tSDCLK – 1.37 + H
tSDCLK + 4.9+ H
tWWR
WR High to WR, RD Low
tSDCLK – 1.5+ H
tSDCLK – 1.5+ H
Data Disable Before RD Low
2tSDCLK – 12
2tSDCLK – 5.1
tDDWR
tWDE
WR Low to Data Enabled
tSDCLK – 4.1
tSDCLK – 4.1
W = (number of wait states specified in AMICTLx register) × tSDCLK, H = (number of hold cycles specified in AMICTLx register) × tSDCLK
1
ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet tDAAK or tDSAK.
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 49 for calculation of hold times given capacitive and dc loads.
2
Rev. D | Page 31 of 56 | April 2013
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21371/ADSP-21375
ADDR
MSx
tDWHA
tDAWH
tDAWL
tWW
WR
tWWR
tWDE
tDDWH
tDATRWH
DATA
tDSAK
tDWHD
tDAAK
ACK
RD
Figure 19. Memory Write—Bus Master
Rev. D | Page 32 of 56 | April 2013
tDDWR
ADSP-21371/ADSP-21375
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
tHFSE1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
tSDRE1
Receive Data Setup Before Receive SCLK
tHDRE1
Receive Data Hold After SCLK
tSCLKW
SCLK Width
SCLK Period
tSCLK
Switching Characteristics
tDFSE2
Frame Sync Delay After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode)
2
tHOFSE
Frame Sync Hold After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode)
tDDTE2
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
tHDTE2
1
2
Min
1.0 V, 200 MHz
Max
Min
1.2 V, 266 MHz
Max
Unit
2.8
2.5
ns
2.5
2.5
ns
3.1
2.5
(tPCLK × 4) ÷ 2 – 1.5
tPCLK × 4
2.5
2.5
(tPCLK × 4) ÷ 2 – 1.5
tPCLK × 4
ns
ns
ns
ns
13.5
2
10.5
ns
11
ns
ns
ns
2
13.9
2
Referenced to sample edge.
Referenced to drive edge.
Rev. D | Page 33 of 56 | April 2013
2
ADSP-21371/ADSP-21375
Table 28. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI1
Frame Sync Setup Before SCLK (Externally Generated Frame
Sync in either Transmit or Receive Mode)
tHFSI1
Frame Sync Hold After SCLK (Externally Generated Frame Sync
in either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
1
tHDRI
Receive Data Hold After SCLK
Switching Characteristics
Frame Sync Delay After SCLK (Internally Generated Frame Sync
tDFSI2
in Transmit Mode)
tHOFSI2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Transmit Mode)
tDFSIR2
Frame Sync Delay After SCLK (Internally Generated Frame Sync
in Receive Mode)
tHOFSIR2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Receive Mode)
tDDTI2
Transmit Data Delay After SCLK
2
tHDTI
Transmit Data Hold After SCLK
tSCKLIW3
Transmit or Receive SCLK Width
Min
1.0 V, 200 MHz
Max
Min
1.2 V, 266 MHz
Max
Unit
7
7
ns
2.5
7
2.5
2.5
7
2.5
ns
ns
ns
4
–1.0
4
–1.0
13.5
–1.0
–1.0
2 × tPCLK – 1.5
1
Referenced to the sample edge.
Referenced to drive edge.
3
Minimum SPORT divisor register value.
2
Rev. D | Page 34 of 56 | April 2013
ns
10.7
–1.0
4.6
–1.0
2 × tPCLK + 1.5 2 × tPCLK – 1.5
ns
ns
ns
3.6
ns
ns
2 × tPCLK + 1.5 ns
ADSP-21371/ADSP-21375
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA RECEIVE—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tSFSI
tHOFSI
tHFSI
DAI_P20–1
(FS)
tSFSE
tHFSE
tSDRE
tHDRE
tHOFSE
DAI_P20–1
(FS)
tSDRI
tHDRI
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(DATA
CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK)
tSCLKW
SAMPLE EDGE
DAI_P20–1
(SCLK)
tDFSI
tDFSE
tHOFSI
tSFSI
DAI_P20–1
(FS)
tHFSI
tSFSE
tHOFSE
DAI_P20–1
(FS)
tHDTI
DAI_P20–1
(DATA
CHANNEL A/B)
SAMPLE EDGE
tSCLKW
tDDTI
tHDTE
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 20. Serial Ports
Rev. D | Page 35 of 56 | April 2013
tDDTE
tHFSE
ADSP-21371/ADSP-21375
Table 29. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN1
Data Enable from External Transmit SCLK
tDDTTE1
Data Disable from External Transmit SCLK
1
tDDTIN
Data Enable from Internal Transmit SCLK
1
Min
1.0 V, 200 MHz
Max
2
Min
1.2 V, 266 MHz
Max
2
11.3
–1
10
–1
Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
DAI_P20–1
(SCLK, EXT)
tDDTEN
tDDTTE
DAI_P20–1
(DATA
CHANNEL A/B)
DRIVE EDGE
DAI_P20–1
(SCLK, INT)
tDDTIN
DAI_P20–1
(DATA
CHANNEL A/B)
Figure 21. Enable and Three-State
Rev. D | Page 36 of 56 | April 2013
Unit
ns
ns
ns
ADSP-21371/ADSP-21375
Table 30. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE1
Data Delay from Late External Transmit Frame Sync
or External Receive Frame Sync with
MCE = 1, MFD = 0
tDDTENFS1
Data Enable for MCE = 1, MFD = 0
0.5
1
1.0 V, 200 MHz
Max
Min
1.2 V, 266 MHz
Max
12.7
10
0.5
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tSFSE/I
tHFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
2ND BIT
1ST BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
tSFSE/I
tHFSE/I
DAI_P20–1
(FS)
tDDTE/I
tDDTENFS
tHDTE/I
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
tDDTLFSE
Figure 22. External Late Frame Sync1
1
This figure reflects changes made to support left-justified sample pair mode.
Rev. D | Page 37 of 56 | April 2013
ns
ns
The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
DRIVE
Unit
2ND BIT
ADSP-21371/ADSP-21375
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
Parameter
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
Frame Sync Hold After Serial Clock Rising Edge
tSIHFS1
tSISD1
Data Setup Before Serial Clock Rising Edge
1
tSIHD
Data Hold After Serial Clock Rising Edge
tIDPCLKW
Clock Width
tIDPCLK
Clock Period
1
Min
1.0 V, 200 MHz
Max
4.95
2.5
3.35
2.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Min
1.2 V, 266 MHz
Max
3.8
2.5
2.5
2.5
(tPCLK × 4) ÷ 2 – 1
tPCLK × 4
Unit
ns
ns
ns
ns
ns
ns
The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either
CLKIN or any of the DAI pins.
tIDPCLK
SAMPLE EDGE
DAI_P20–1
(SCLK)
tIDPCLKW
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 23. IDP Master Timing
Rev. D | Page 38 of 56 | April 2013
ADSP-21371/ADSP-21375
Note that the 20-bits of external PDAP data can be provided
through the external port DATA31–12 pins. On the
ADSP-21375 processors, PDAP can not be multiplexed on the
external port (since only DATA15–0). Use the SRU DAI
instead.
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2137x SHARC Processor Hardware
Reference.
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
tSPCLKEN1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
tHPCLKEN1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
tPDSD1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge
tPDHD1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge
Clock Width
tPDCLKW
tPDCLK
Clock Period
Switching Characteristics
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
tPDSTRIB
PDAP Strobe Pulse Width
1
Min
ns
ns
ns
ns
ns
ns
2 × tPCLK + 3
2 × tPCLK – 1
ns
ns
tPDCLK
tPDCLKW
DAI_P20–1
(PDAP_CLK)
tSPHOLD
tHPHOLD
DAI_P20–1
(PDAP_HOLD)
tPDSD
tPDHD
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
tPDHLDD
DAI_P20–1
(PDAP_STROBE)
Figure 24. PDAP Timing
Rev. D | Page 39 of 56 | April 2013
Unit
2.5
2.5
3.85
2.5
(tPCLK × 4) ÷ 2 – 3
tPCLK × 4
Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins.
SAMPLE EDGE
Max
tPDSTRB
ADSP-21371/ADSP-21375
Pulse-width modulation generator information does not apply
to the ADSP-21375.
Pulse-Width Modulation Generators (PWM)
For the ADSP-21371, the following timing specifications apply
when the DATA31–16 pins are configured as PWM.
Table 33. Pulse-Width Modulation (PWM) Timing
Parameter
Switching Characteristics
tPWMW
PWM Output Pulse Width
tPWMP
PWM Output Period
Min
Max
Unit
tPCLK – 2.5
2 × tPCLK – 2.5
(216 – 2) × tPCLK
(216 – 1) × tPCLK
ns
ns
tPWMW
PWM
OUTPUTS
tPWMP
Figure 25. PWM Timing
Rev. D | Page 40 of 56 | April 2013
ADSP-21371/ADSP-21375
output mode) from an LRCLK transition, so that when there are
64 serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
S/PDIF Transmitter
For the ADSP-21371, serial data input to the S/PDIF transmitter
can be formatted as left-justified, I2S, or right-justified with
word widths of 16-, 18-, 20-, or 24-bits. The following sections
provide timing for the transmitter.
S/PDIF transmitter information does not apply to the
ADSP-21375.
Figure 27 shows the default I2S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a single serial clock period delay.
S/PDIF Transmitter-Serial Input Waveforms
Figure 26 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
Figure 28 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
tRJD
DAI_P20–1
SDATA
LSB
MSB
MSB–1
MSB–2
LSB+2
Figure 26. Right-Justified Mode
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tI2SD
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 27. I2S-Justified Mode
DAI_P20–1
FS
LEFT/RIGHT CHANNEL
DAI_P20–1
SCLK
tLJD
DAI_P20–1
SDATA
MSB
MSB–1
MSB–2
LSB+2
LSB+1
Figure 28. Left-Justified Mode
Rev. D | Page 41 of 56 | April 2013
LSB
LSB+1
LSB
ADSP-21371/ADSP-21375
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 34. S/PDIF Transmitter Input Data Timing
Parameter
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
tSIHRS1
Frame Sync Hold After Serial Clock Rising Edge
tSISD1
Data Setup Before Serial Clock Rising Edge
Data Hold After Serial Clock Rising Edge
tSIHD1
tSITXCLKW
Transmit Clock Width
tSITXCLK
Transmit Clock Period
tSISCLKW
Clock Width
tSISCLK
Clock Period
1
Min
1.0 V, 200 MHz
Max
3
3
3.2
3
9
20
36
80
Min
1.2 V, 266 MHz
Max
Unit
3
3
3
3
9
20
36
80
ns
ns
ns
ns
ns
ns
ns
ns
The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN
or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAI_P20–1
(TxCLK)
tSISCLK
tSISCLKW
DAI_P20–1
(SCLK)
tSISFS
tSIHFS
DAI_P20–1
(FS)
tSISD
tSIHD
DAI_P20–1
(SDATA)
Figure 29. S/PDIF Transmitter Input Timing
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 35. Oversampling Clock HFxCLK) Switching Characteristics
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (FS)
Max
Oversampling Ratio × Frame Sync
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