SHARC+ Dual-Core
DSP with Arm Cortex-A5
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SYSTEM FEATURES
19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant
Low system power across automotive temperature range
Dual enhanced SHARC+ high performance floating-point
cores
Up to 500 MHz per SHARC+ core
Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core
with parity (optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short-word, word, long-word addressed
Arm Cortex-A5 core
500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
32 kB L1 instruction cache/32 kB L1 data cache
256 kB Level 2 (L2) cache with parity
Powerful DMA system
On-chip memory protection
Integrated safety features
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 256 kB
On-chip L2 ROM (512 kB)
Two Level 3 (L3) interfaces optimized for low system power,
providing a 16-bit interface to DDR3 (supporting 1.5 V
capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection
Cryptographic hardware accelerators
Fast secure boot with IP protection
Support for Arm TrustZone
Accelerators
High performance pipelined FFT/IFFT engine
FIR, IIR, HAE, SINC offload engines
AEC-Q100 qualified for automotive applications
PERIPHERALS
SYSTEM CONTROL
SIGNAL ROUTING UNIT (SRU)
SECURITY AND PROTECTION
CORE 0
SYSTEM PROTECTION (SPU)
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
FAULT MANAGEMENT
CORE 1
CORE 2
Arm®
®
Cortex-A5
S
S
L1 CACHE
32 kB L1 I-CACHE
32 kB L1 D-CACHE
L1 SRAM (PARITY)
L1 SRAM (PARITY)
2×2 PRECISION CLOCK
GENERATORS
ASRC
2×4 PAIRS
2x DAI
FULL SPORT 2x PIN
2×4
BUFFER
40–28
2×1 S/PDIF Rx/Tx
Arm® TrustZone® SECURITY
2
DUAL CRC
WATCHDOGS
OTP MEMORY
THERMAL MONITOR UNIT (TMU)
3× I C
6
5 Mb (640 kB)
SRAM/CACHE
L2 CACHE
256 kB (PARITY)
5 Mb (640 kB)
SRAM/CACHE
2× LINK PORTS
2× SPI + 1× QUAD SPI
3× UARTs
1× EPPI
PROGRAM FLOW
3× ePWM
SYS EVENT CORE 0 (GIC)
8× TIMERS + 1× COUNTER
SYS EVENT CORES 1-2 (SEC)
ADC CONTROL MODULE
(ACM)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
TRIGGER ROUTING (TRU)
ASYNC MEMORY (16-BIT)
G
P
I
O
102–80
CLOCK, RESET, AND POWER
2× CAN2.0
CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION
UNIT (CDU)
REAL TIME CLOCK (RTC)
RESET CONTROL (RCU)
L3 MEMORY
INTERFACES
DDR3
DDR2
LPDDR1
DDR3
DDR2
LPDDR1
16
16
POWER MANAGEMENT (DPM)
DEBUG UNIT
Arm® CoreSightTM
DATA
SYSTEM
L2 MEMORY
SRAM
(ECC)
2 Mb
(256 kB)
ROM
2 Mb
(256 kB)
ROM
2 Mb
(256 kB)
SYSTEM
ACCELERATION
DSP FUNCTIONS
(FFT/IFFT, FIR, IIR, HAE/SINC)
ENCRYPTION/DECRYPTION
SD/SDIO/eMMC
MLB 3-PIN
2× EMAC
SINC FILTER
8x SHARC FLAGS
2× USB 2.0 HS
10
6
MLB 6-PIN
DATA
7
PCIe2.0 (1 lane)
WATCHPOINTS (SWU)
HADC (8 CHAN, 12-BIT)
8
Figure 1. Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. B
Document Feedback
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
TABLE OF CONTENTS
System Features ....................................................... 1
GPIO Multiplexing for the 529-Ball CSP_BGA Package ... 55
Memory ................................................................ 1
ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58
Additional Features .................................................. 1
Specifications ........................................................ 79
Table of Contents ..................................................... 2
Operating Conditions ........................................... 79
Revision History ...................................................... 2
Electrical Characteristics ....................................... 83
General Description ................................................. 3
HADC .............................................................. 87
ARM Cortex-A5 Processor ...................................... 5
TMU ................................................................ 87
SHARC Processor ................................................. 6
Absolute Maximum Ratings ................................... 88
SHARC+ Core Architecture .................................... 8
ESD Caution ...................................................... 88
System Infrastructure ........................................... 10
Timing Specifications ........................................... 89
System Memory Map ........................................... 11
Output Drive Currents ....................................... 153
Security Features ................................................ 14
Test Conditions ................................................ 155
Security Features Disclaimer .................................. 15
Environmental Conditions .................................. 157
Safety Features ................................................... 15
Processor Peripherals ........................................... 15
ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball
Assignments .................................................... 158
System Acceleration ............................................ 20
Numerical by Ball Number .................................. 158
System Design .................................................... 21
Alphabetical by Pin Name ................................... 160
System Debug .................................................... 23
Configuration of the 349-Ball CSP_BGA ................. 162
Development Tools ............................................. 24
ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball
Assignments .................................................... 163
Additional Information ........................................ 25
Related Signal Chains .......................................... 25
ADSP-SC58x/ADSP-2158x Detailed Signal
Descriptions ...................................................... 26
349-Ball CSP_BGA Signal Descriptions ....................... 31
Numerical by Ball Number .................................. 163
Alphabetical by Pin Name ................................... 166
Configuration of the 529-Ball CSP_BGA ................. 169
Outline Dimensions .............................................. 170
GPIO Multiplexing for the 349-Ball CSP_BGA Package .. 40
Surface-Mount Design ........................................ 171
529-Ball CSP_BGA Signal Descriptions ....................... 43
Automotive Products ............................................ 172
Ordering Guide ................................................... 173
REVISION HISTORY
Changes to Additional Features ................................... 1
Changes to ADSP-SC58x/ADSP-2158x Designer Quick Reference .................................................................... 58
Changes to Table 3, General Description ....................... 3
Deleted Package Information from Specifications ........... 79
Changes to One Time Programmable Memory (OTP) .... 10
Changes to Operating Conditions .............................. 79
Changes to Table 7 and Table 8, System Memory Map .... 11
Changes to Table 28, Operating Conditions .................. 79
Changes to Housekeeping Analog-to-Digital Converter
(HADC) .............................................................. 19
Changes to Table 29, Clock Related Operating Conditions 81
Changes to Media Local Bus (Media LB) ...................... 19
Changes Universal Serial Bus (USB) .......................... 138
Changes to ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions ................................................................... 26
Changes 10/100 EMAC Timing (ETH0 and ETH1) ...... 139
Changes to ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions .................................................... 31
Changes to Test Conditions .................................... 155
12/2018—Rev. A to Rev. B
Changes to ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions .................................................... 43
Rev. B |
Page 2 of 173 |
Changes to Total Internal Power Dissipation ................ 85
Changes to Program Trace Macrocell (PTM) Timing .... 151
Changes to Automotive Products ............................. 172
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
GENERAL DESCRIPTION
The ADSP-SC58x/ADSP-2158x processors are members of the
SHARC® family of products. The ADSP-SC58x processor is
based on the SHARC+ dual core and the Arm® Cortex®-A5
core. The ADSP-SC58x/ADSP-2158x SHARC processors are
members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard
Architecture®. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point
applications with large, on-chip, static random-access memory
(SRAM), multiple internal buses that eliminate input/output
(I/O) bottlenecks, and innovative digital audio interfaces (DAI).
New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set
compatibility to previous SHARC products.
Table 1. Common Product Features
Product Features
DAI (includes SRU)
Full SPORTs
S/PDIF receive/transmit
ASRCs
PCGs
I2C (TWI)
Quad-data bit SPI
Dual-data bit SPI
CAN2.0
UARTs
Link ports
Enhanced PPI
GP timer1
GP counter
Enhanced PWMs2
Watchdog timers
ADC control module
Static memory controller
Hardware accelerators
High performance FFT/IFFT
FIR/IIR
Harmonic analysis engine
SINC filter
Security cryptographic engine
Multichannel 12-bit ADC
By integrating a set of industry leading system peripherals and
memory (see Table 1, Table 2, and Table 3), the Arm Cortex-A5
and SHARC processor is the platform of choice for applications
that require programmability similar to reduced instruction set
computing (RISC), multimedia support, and leading edge signal
processing in one integrated package. These applications span a
wide array of markets, including automotive, professional
audio, and industrial-based applications that require high floating-point performance.
Table 2 provides comparison information for features that vary
across the standard processors. (N/A in the table means not
applicable.)
Table 3 provides comparison information for features that vary
across the automotive processors. (N/A in the table means not
applicable.)
1
2
Rev. B |
Page 3 of 173 |
ADSP-SC58x/ADSP-2158x
2
4 per DAI
1per DAI
4 pair per DAI
2 per DAI
3
1
2
2
3
2
1
8
1
3
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8-channel
Eight timers are available in the 529-BGA package only. The 349-BGA package
does not include Timer 6 and Timer 7.
On the 349-BGA package, the PWM2_AH/AL and PWM2_BH/BL signals are
not available. The PWM2_CH/CL and PWM2_DH/DL signals, however, are
available and can be used in conjunction with PWM2_TRIP0 and PWM2_SYNC
signals.
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 2. Comparison of ADSP-SC58x/ADSP-2158x Processor Features
System
Memory
ADSPADSPADSPADSPADSPADSPADSPADSPProcessor Feature
SC582
SC583
SC584
SC587
SC589
21583
21584
21587
Arm Cortex-A5 (MHz, Max)
500
500
500
500
500
N/A
N/A
N/A
Arm Core L1 Cache (I, D kB)
32, 32
32, 32
32, 32
32, 32
32, 32
N/A
N/A
N/A
Arm Core L2 Cache (kB)
256
256
256
256
256
N/A
N/A
N/A
SHARC+ Core1 (MHz, Max)
500
500
500
500
500
500
500
500
SHARC+ Core2 (MHz, Max)
N/A
500
500
500
500
500
500
500
SHARC L1 SRAM (kB)
640
384
640
640
640
384
640
640
L2 SRAM (Shared) (kB)
256
256
256
256
256
256
256
256
L2 ROM (Shared) (kB)
512
512
512
512
512
512
512
512
DDR3/DDR2/LPDDR1
1
1
1
2
2
1
1
2
Controller (16-bit)
USB 2.0 HS + PHY (Host/Device/OTG)
1
1
1
1
1
N/A
N/A
N/A
USB 2.0 HS + PHY (Host/Device)
N/A
N/A
N/A
1
1
N/A
N/A
N/A
10/100 Std EMAC
N/A
N/A
N/A
1
1
N/A
N/A
N/A
10/100/1000 /AVB EMAC + Timer
1
1
1
1
1
N/A
N/A
N/A
IEEE 1588
SDIO/eMMC
N/A
N/A
N/A
1
1
N/A
N/A
N/A
PCIe 2.0 (1 Lane)
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
RTC
N/A
N/A
N/A
1
1
N/A
N/A
1
GPIO Ports
Port A to E Port A to E Port A to E Port A to G Port A to G Port A to E Port A to E Port A to G
GPIO + DAI Pins
80 + 28
80 + 28
80 + 28
102 + 40
102 + 40
80 + 28
80 + 28
102 + 40
19 mm × 19 mm Package Options
349-BGA
349-BGA
349-BGA
529-BGA
529-BGA
349-BGA
349-BGA
529-BGA
Table 3. Comparison of ADSP-SC58x/ADSP-2158x Processor Features for Automotive
System
Memory
Processor Feature
ADSP-SC582W ADSP-SC583W ADSP-SC584W ADSP-SC587W ADSP-21583W ADSP-21584W
Arm Cortex-A5 (MHz, Max)
450
450
500
500
N/A
N/A
Arm Core L1 Cache (I, D kB)
32, 32
32, 32
32, 32
32, 32
N/A
N/A
Arm Core L2 Cache (kB)
256
256
256
256
N/A
N/A
SHARC+ Core1 (MHz, Max)
450
450
500
500
450
500
SHARC+ Core2 (MHz, Max)
N/A
450
500
500
450
500
SHARC L1 SRAM (kB)
640
384
640
640
384
640
L2 SRAM (Shared) (kB)
256
256
256
256
256
256
L2 ROM (Shared) (kB)
512
512
512
512
512
512
DDR3/DDR2/LPDDR1
1
1
1
2
1
1
Controller (16-bit)
USB 2.0 HS + PHY (Host/Device/OTG)
1
1
1
1
N/A
N/A
USB 2.0 HS + PHY (Host/Device)
N/A
N/A
N/A
1
N/A
N/A
10/100 Std EMAC
N/A
N/A
N/A
1
N/A
N/A
10/100/1000/AVB EMAC + Timer
1
1
1
1
N/A
N/A
IEEE 1588
SDIO/eMMC
N/A
N/A
N/A
1
N/A
N/A
PCIe 2.0 (1 Lane)
N/A
N/A
N/A
N/A
N/A
N/A
MLB 3-Pin/6-Pin
1
1
1
1
1
1
RTC
N/A
N/A
N/A
1
N/A
N/A
GPIO Ports
Port A to E
Port A to E
Port A to E
Port A to G
Port A to E
Port A to E
GPIO + DAI Pins
80 + 28
80 + 28
80 + 28
102 + 40
80 + 28
80 + 28
19 mm × 19 mm Package Options
349-BGA
349-BGA
349-BGA
529-BGA
349-BGA
349-BGA
Rev. B |
Page 4 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ARM CORTEX-A5 PROCESSOR
• Harvard L1 memory system with a memory management
unit (MMU)
The Arm Cortex-A5 processor (see Figure 2) is a high performance processor with the following features:
• Arm7TM debug architecture
• Instruction cache unit (32 kB) and data L1 cache unit
(32 Kb)
• Trace support through an embedded trace macrocell
(ETM) interface
• In order pipeline with dynamic branch prediction
• Extension—vector floating-point unit (IEEE 754) with
trapless execution
®
• Arm, Thumb , and ThumbEE instruction set support
• Extension—media processing engine (MPE) with NEONTM
technology
• Arm TrustZone® security extensions
• Extension—Jazelle® hardware acceleration
EMBEDDED TRACE MACROCELL
(ETM) INTERFACE
TM
CoreSight INTERFACE
TM
DEBUG
CP15
DATA PROCESSING UNIT (DPU)
Arm® Cortex®-A5
PROCESSOR
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
DATA MICRO-TLB
INSTRUCTION MICRO-TLB
DATA CACHE
UNIT (DCU)
DATA STORE
BUFFER (STB)
NEON MEDIA
PROCESSING
ENGINE
INSTRUCTION CACHE
UNIT (ICU)
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
32 kB
32 kB
BUS INTERFACE UNIT (BIU)
Arm® Cortex®-A5 BUS MASTER PORT
GENERIC INTERRUPT
CONTROLLER
(PrimeCell® PL-390)
L2 CACHE
CONTROLLER
(CoreLinkTM PL-310)
DATA MASTER PORTS
SHARC PROCESSORS
256 kB
SYSTEM FABRIC
TO OTHER CORES
Figure 2. Arm Cortex-A5 Processor Block Diagram
Rev. B |
Page 5 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Generic Interrupt Controller (GIC), PL390
(ADSP-SC58x Only)
L2 Cache Controller, PL310 (ADSP-SC58x Only)
The L2 cache controller, PL310 (see Figure 2), works efficiently
with the Arm Cortex-A5 processors that implement system fabric. The cache controller directly interfaces on the data and
instruction interface. The internal pipelining of the cache controller is optimized to enable the processors to operate at the
same clock frequency. The cache controller supports the
following:
The generic interrupt controller (GIC) is a centralized resource
for supporting and managing interrupts. The GIC splits into the
distributor block (GICPORT0) and the CPU interface block
(GICPORT1).
Generic Interrupt Controller Port0 (GICPORT0)
The GICPORT0 distributor block performs interrupt prioritization and distribution to the GICPORT1 blocks that connect to
the processors in the system. It centralizes all interrupt sources,
determines the priority of each interrupt, and forwards the
interrupt with the highest priority to the interface, for priority
masking and preemption handling.
• Two read/write 64-bit slave ports, one connected to the
Arm Cortex-A5 instruction and data interfaces, and one
connecting the Arm Cortex-A5 and SHARC+ cores for
data coherency.
• Two read/write 64-bit master ports for interfacing with the
system fabric.
Generic Interrupt Controller Port1 (GICPORT1)
SHARC PROCESSOR
The GICPORT1 CPU interface block performs priority masking
and preemption handling for a connected processor in the system. GICPORT1 supports 8 software generated interrupts
(SGIs) and 254 shared peripheral interrupts (SPIs).
Figure 3 shows the SHARC processor integrates a SHARC+
SIMD core, L1 memory crossbar, I/D cache controller, L1 memory blocks, and the master/slave ports. Figure 4 shows the
SHARC+ SIMD core block diagram.
The SHARC processor supports a modified Harvard architecture in combination with a hierarchical memory structure. L1
memories typically operate at the full processor speed with little
or no latency.
B2
RAM
B2
B1
RAM
S
P-CACHE
B0
RAM
B2
RAM
SIMD Processor
CCLK DOMAIN
B0 (64)
B3
RAM
B1 (64)
D-CACHE
P-CACHE
B2 (64)
P-CACHE
D-CACHE
B3 (64)
I-CACHE
IO (32)
IO (32)
SLAVE
PORT 1
IO (32)
PM (64)
DM (64)
INTERNAL MEMORY INTERFACE (IMIF)
I/D CACHE CONTROL
SLAVE
PORT 2
IO (32)
SYSTEM FABRIC
SYSCLK
DOMAIN
CORE
MMR
(32)
DM (64)
CMD (64)
PM (64)
SHARC+®
SIMD CORE
MASTER
PORT DATA
CMI (64)
PS (64/48)
MASTER
PORT INSTRUCTION
INTERRUPT
SEC
Figure 3. SHARC Processor Block Diagram
Rev. B |
Page 6 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
S+
DEBUG
TRACE
SIMD Core
BTB
BP
CEC
FLAGS
CONFLICT
CACHE
PM DATA 48
DMD/PMD 64
11-STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
DAG1
16 × 32
DAG2
16 × 32
PM ADDRESS 32
SYSTEM
I/F
DM ADDRESS 32
PM DATA 64
TO
IMIF
USTAT
PX
DM DATA 64
MULTIPLIER
MRF
80-BIT
MRB
80-BIT
SHIFTER
ALU
PEx
DATA
REGISTER
Rx
16 × 40-BIT
DATA
SWAP
PEy
DATA
REGISTER
Sx
16 × 40-BIT
ASTATx
ASTATy
STYKx
STYKy
ALU
SHIFTER
MULTIPLIER
MSB
80-BIT
MSF
80-BIT
Figure 4. SHARC+ SIMD Core Block Diagram
L1 Memory
Figure 5 shows the ADSP-SC58x/ADSP-2158x memory map.
Each SHARC+ core has a tightly coupled L1 SRAM of up to
5 Mb. Each SHARC+ core can access code and data in a single
cycle from this memory space. The Arm Cortex-A5 core can
also access this memory space with multicycle accesses.
In the SHARC+ core private address space, both cores have L1
memory.
SHARC+ core memory-mapped register (CMMR) address
space is 0x 0000 0000 through 0x 0003 FFFF in normal word
(32-bit). Each block can be configured for different combinations of code and data storage. Of the 5 Mb SRAM, up to
1024 Kb can be configured for data memory (DM), program
memory (PM), and instruction cache. Each memory block supports single-cycle, independent accesses by the core processor
and I/O processor. The memory architecture, in combination
with its separate on-chip buses, allows two data transfers from
the core and one from the DMA engine in a single cycle. The
SRAM of the processor can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data,
Rev. B |
Page 7 of 173 |
106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 Mb. All of the memory
can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words.
Support of a 16-bit floating-point storage format doubles the
amount of data that can be stored on chip.
Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While
each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers.
Using the DM and PM buses, with each bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. The system configuration is flexible, but a typical configuration is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction
cache, with the remaining L1 memory configured as SRAM.
Each addressable memory space outside the L1 memory can be
accessed either directly or via cache.
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
The memory map in Table 4 gives the L1 memory address space
and shows multiple L1 memory blocks offering a configurable
mix of SRAM and cache.
0x FFFF FFFF
DMC1 (1GB)
0x C000 0000
DMC0 (1GB)
0x 8000 0000
L1 Master and Slave Ports
SPI2 FLASH (512MB)
0x 6000 0000
Each SHARC+ core has two master and two slave ports to and
from the system fabric. One master port fetches instructions.
The second master port drives data to the system world. Both
slave ports allow conflict free core/direct memory access (DMA)
streams to the individual memory blocks. For slave port
addresses, refer to the L1 memory address map in Table 4.
PCIe (256MB)
0x 5000 0000
SMC BANK 3 (64MB)
0x 4C00 0000
SMC BANK 2 (64MB)
0x 4800 0000
SMC BANK 1 (64MB)
0x 4400 0000
SMC BANK 0 (64MB)
0x 4000 0000
SYSTEM MMR
L1 On-Chip Memory Bandwidth
0x 3000 0000
RESERVED
0x 28F9 FFFF
The internal memory architecture allows programs to have four
accesses at the same time to any of the four blocks, assuming no
block conflicts. The total bandwidth is realized using both the
DMD and PMD buses.
SHARC2 L1 MULTI-MEMORY SPACE
0x 28A4 0000
RESERVED
0x 2879 FFFF
SHARC1 L1 MULTI-MEMORY SPACE
0x 2824 0000
UNIFIED
BYTE ADDRESS
SPACE
RESERVED
Instruction and Data Cache
0x 202B FFFF
L2 ROM 2 (2Mb)
0x 2028 0000
The ADSP-SC58x/ADSP-2158x processors also include a
traditional instruction cache (I-cache) and two data caches
(D-cache) (PM and DM caches). These caches support one
instruction access and two data accesses over the DM and PM
buses, per CCLK cycle. The cache controllers automatically
manage the configured L1 memory. The system can configure
part of the L1 memory for automatic management by the cache
controllers. The sizes of these caches are independently configurable from 0 kB to a maximum of 128 kB each. The memory not
managed by the cache controllers is directly addressable by the
processors. The controllers ensure the data coherence between
the two data caches. The caches provide user-controllable features such as full and partial locking, range-bound invalidation,
and flushing.
RESERVED
0x 2020 7FFF
0x 2020 0000
L2 BOOT ROM 2 (0.25Mb)
(SHARC Cores)
RESERVED
0x 201B FFFF
L2 ROM 1 (2Mb)
0x 2018 0000
RESERVED
0x 2010 7FFF
L2 BOOT ROM 1 (0.25Mb)
(SHARC Cores)
0x 2010 0000
RESERVED
0x 200B FFFF
L2 SRAM (2Mb)
0x 2008 0000
RESERVED
0x 2000 7FFF
0x 2000 0000
L2 BOOT ROM 0 (0.25Mb)
(ARM CORE 0)
0x 2000 0000
RESERVED
0x 0039 FFFF
L1 BLOCK 3 SRAM (1Mb)
System Event Controller (SEC) Input
0x 0038 0000
RESERVED
Core Memory-Mapped Registers (CMMR)
ARM
ADDRESS SPACE
0x 0031 FFFF
L1 BLOCK 2 SRAM (1Mb)
0x 0030 0000
RESERVED
0x 002E FFFF
L1 BLOCK 1 SRAM (1.5Mb)
SHARC PRIVATE
ADDRESS SPACE
The output of the system event controller (SEC) controller is
forwarded to the core event controller (CEC) to respond
directly to all unmasked system-based interrupts. The SEC also
supports nesting including various SEC interrupt channel arbitration options. For all SEC channels, the processor
automatically stacks the arithmetic status (ASTATx and
ASTATy) registers and mode (MODE1) register in parallel with
the interrupt servicing.
RESERVED
0x 002C 0000
0x 1000 1000
ARM L2 CONFIG REGS (4KB)
RESERVED
0x 1000 0000
0x 0026 FFFF
RESERVED
L1 BLOCK 0 SRAM (1.5Mb)
0x 0000 7FFF
0x 0024 0000
ARM BOOT (32KB)
0x 0000 0000
RESERVED/CORE MMRs/
OTHER MEMORY ALIASES
0x 0000 0000
Figure 5. ADSP-SC58x/ADSP-2158x Memory Map
The core memory-mapped registers control the L1 instruction
and data cache, BTB, L2 cache, parity error, system control,
debug, and monitor functions.
SHARC+ CORE ARCHITECTURE
The ADSP-SC58x/ADSP-2158x processors are code compatible
at the assembly level with the ADSP-2148x, ADSP-2147x,
ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x,
ADSP-2116x, and with the first-generation ADSP-2106x
SHARC processors.
Rev. B |
Page 8 of 173 |
The ADSP-SC58x/ADSP-2158x processors share architectural
features with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-214xx, and ADSP-2116x SIMD SHARC processors,
shown in Figure 4 and detailed in the following sections.
SIMD Computational Engine
The SHARC+ core contains two computational processing elements that operate as a single-instruction, multiple data (SIMD)
engine.
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The processing elements are referred to as PEx and PEy data
registers and each contain an arithmetic logic unit (ALU), multiplier, shifter, and register file. PEx is always active and PEy is
enabled by setting the PEYEN mode bit in the mode control
register (MODE1).
Single instruction multiple data (SIMD) mode allows the processors to execute the same instruction in both processing
elements, but each processing element operates on different
data. This architecture efficiently executes math intensive DSP
algorithms. In addition to all the features of previous generation
SHARC cores, the SHARC+ core also provides a new and simpler way to execute an instruction only on the PEy data register.
SIMD mode also affects the way data transfers between memory
and processing elements because to sustain computational
operation in the processing elements requires twice the data
bandwidth. Therefore, entering SIMD mode doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
transfer with each memory or register file access.
Independent, Parallel Computation Units
Within each processing element is a set of pipelined computational units. The computational units consist of a multiplier,
arithmetic/logic unit (ALU), and shifter. These units are
arranged in parallel, maximizing computational throughput.
These computational units support IEEE 32-bit single-precision
floating-point, 40-bit extended-precision floating-point, IEEE
64-bit double-precision floating-point, and 32-bit fixed-point
data formats.
A multifunction instruction set supports parallel execution of
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements per core.
All processing operations take one cycle to complete. For all
floating-point operations, the processor takes two cycles to
complete in case of data dependency. Double-precision floating-point data take two to six cycles to complete. The processor
stalls for the appropriate number of cycles for an interlocked
pipeline plus data dependency check.
Core Timer
Each SHARC+ processor core also has a timer. This extra timer
is clocked by the internal processor clock and is typically used as
a system tick clock for generating periodic operating system
interrupts.
Data Register File
Each processing element contains a general-purpose data register file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register register files (16 primary, 16 secondary),
combined with the enhanced Harvard architecture of the processor, allow unconstrained data flow between computation
units and internal memory. The registers in the PEx data register file are referred to as R0–R15 and in the PEy data register file
as S0–S15.
Rev. B |
Page 9 of 173 |
Context Switch
Many of the registers of the processor have secondary registers
that can activate during interrupt servicing for a fast context
switch. The data, DAG, and multiplier result registers have secondary registers. The primary registers are active at reset, while
control bits in MODE1 activate the secondary registers.
Universal Registers (USTAT)
General-purpose tasks use the universal registers. The four
USTAT registers allow easy bit manipulations (set, clear, toggle,
test, XOR) for all control and status peripheral registers.
The data bus exchange register (PX) permits data to pass
between the 64-bit PM data bus and the 64-bit DM data bus or
between the 40-bit register file and the PM or DM data bus.
These registers contain hardware to handle the data width
difference.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
For indirect addressing and implementing circular data buffers
in hardware, the ADSP-SC58x/ADSP-2158x processor uses the
two data address generators (DAGs). Circular buffers allow efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to
32 circular buffers (16 primary register sets and 16 secondary
sets). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify
implementation. Circular buffers can start and end at any memory location.
Flexible Instruction Set Architecture (ISA)
The ISA, a 48-bit instruction word, accommodates various parallel operations for concise programming. For example, the
processors can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single
instruction. Additionally, the double-precision floating-point
instruction set is an addition to the SHARC+ core.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the SHARC+ core processors support 16-bit and 32-bit opcodes for many instructions, formerly
48-bit in the ISA. This feature, called variable instruction set
architecture (VISA), drops redundant or unused bits within the
48-bit instruction to create more efficient and compact code.
The program sequencer supports fetching these 16-bit and 32bit instructions from both internal and external memories.
VISA is not an operating mode; it is only address dependent
(refer to memory map ISA/VISA address spaces in Table 7).
Furthermore, it allows jumps between ISA and VISA instruction fetches.
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Single-Cycle Fetch of Instructional Four Operands
SYSTEM INFRASTRUCTURE
The ADSP-SC58x/ADSP-2158x processors feature an enhanced
Harvard architecture in which the DM bus transfers data and
PM bus transfers both instructions and data.
The following sections describe the system infrastructure of the
ADSP-SC58x/ADSP-2158x processors.
With the separate program memory bus, data memory buses,
and on-chip instruction conflict-cache, the processor can simultaneously fetch four operands (two over each data bus) and one
instruction from the conflict cache, in a single cycle.
Core Event Controller (CEC)
The SHARC+ core generates various core interrupts (including
arithmetic and circular buffer instruction flow exceptions) and
SEC events (debug/monitor and software). The core only
responds to unmasked interrupts (enabled in the IMASK
register).
Instruction Conflict-Cache
The processors include a 32-entry instruction cache that enables
three-bus operation for fetching an instruction and four data
values. The cache is selective—only the instructions that require
fetches conflict with the PM bus data accesses cache. This cache
allows full speed execution of core, looped operations, such as
digital filter multiply accumulates, and fast Fourier transforms
(FFT) butterfly processing. The conflict cache serves for on-chip
bus conflicts only.
System L2 Memory
A system L2 SRAM memory of 2 Mb (256 kB) and two ROM
memories, each 2 Mb (256 kB), are available to both SHARC+
cores, the Arm Cortex-A5 core, and the system DMA channels
(see Table 5). All L2 SRAM/ROM blocks are subdivided into
eight banks to support concurrent access to the L2 memory
ports. Memory accesses to the L2 memory space are multicycle
accesses by both the Arm Cortex-A5 and SHARC+ cores.
The memory space is used for various cases including
• Arm Cortex-A5 to SHARC+ core data sharing and intercore communications
• Accelerator and peripheral sources and destination memory to avoid accessing data in the external memory
• A location for DMA descriptors
• Storage for additional data for either the Arm Cortex-A5 or
SHARC+ cores to avoid external memory latencies and
reduce external memory bandwidth
• Storage for incoming Ethernet traffic to improve
performance
• Storage for data coefficient tables cached by the
SHARC+ core
Branch Target Buffer/Branch Predictor
Implementation of a hardware-based branch predictor (BP) and
branch target buffer (BTB) reduce branch delay. The program
sequencer supports efficient branching using the BTB for conditional and unconditional instructions.
Addressing Spaces
In addition to traditionally supported long word, normal word,
extended precision word and short word addressing aliases, the
processors support byte addressing for the data and instruction
accesses. The enhanced ISA/VISA provides new instructions for
accessing all sizes of data from byte space as well as converting
word addresses to byte and byte to word addresses.
Additional Features
The enhanced ISA/VISA of the ADSP-SC58x/ADSP-2158x processors also provides a memory barrier instruction for data
synchronization, exclusive data access support for multicore
data sharing, and exclusive data access to enable multiprocessor
programming. To enhance the reliability of the application, L1
data RAMs support parity error detection logic for every byte.
Additionally, the processors detect illegal opcodes. Core interrupts flag both errors. Master ports of the core also detect for
failed external accesses.
Rev. B |
Page 10 of 173 |
See the System Memory Protection Unit (SMPU) section for
options in limiting access by specific cores and DMA masters.
The Arm Cortex-A5 core has an L1 instruction and data cache,
each of which is 32 kB in size. The core also has an L2 cache
controller of 256 kB. When enabling the caches, accesses to all
other memory spaces (internal and external) go through the
cache.
SHARC+ Core L1 Memory in Multiprocessor Space
The Arm Cortex-A5 core can access the L1 memory of the
SHARC+ core. See Table 6 for the L1 memory address in multiprocessor space. The SHARC+ core can access the L1 memory
of the other SHARC+ core in the multiprocessor space.
One Time Programmable Memory (OTP)
The processors feature 7 kB of one time programmable (OTP)
memory which is memory-map accessible. This memory contains space for programmable unique keys and supports secure
boot and secure operation.
I/O Memory Space
The static memory controller (SMC) is programmed to control
up to two blocks of external memories or memory-mapped
devices, with flexible timing parameters. Each block occupies an
8 Kb segment regardless of the size of the device used. Mapped
I/Os also include PCIe data and SPI2 memory address space
(see Table 7).
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SYSTEM MEMORY MAP
Table 4. L1 Block 0, Block 1, Block 2, and Block 3 SHARC+ Addressing Memory Map (Private Address Space)
Memory
L1 Block 0 SRAM
(1.5 Mb)
L1 Block 1 SRAM
(1.5 Mb)
L1 Block 2 SRAM
(1 Mb)
L1 Block 3 SRAM
(1 Mb)
Long Word (64 Bits)
0x00048000–
0x0004DFFF
0x00058000–
0x0005DFFF
0x00060000–
0x00063FFF
0x00070000–
0x00073FFF
Extended Precision/
ISA Code (48 Bits)
0x00090000–
0x00097FFF
0x000B0000–
0x000B7FFF
0x000C0000–
0x000C5554
0x000E0000–
0x000E5554
Normal Word (32 Bits)
0x00090000–
0x0009BFFF
0x000B0000–
0x000BBFFF
0x000C0000–
0x000C7FFF
0x000E0000–
0x000E7FFF
Short Word/
VISA Code (16 Bits)
0x00120000–
0x00137FFF
0x00160000–
0x00177FFF
0x00180000–
0x0018FFFF
0x001C0000–
0x001CFFFF
Byte Access (8 Bits)
0x00240000–
0x0026FFFF
0x002C0000–
0x002EFFFF
0x00300000–
0x0031FFFF
0x00380000–
0x0039FFFF
Table 5. L2 Memory Addressing Map
Memory1
L2 Boot ROM02
L2 RAM (2 Mb)
L2 Boot ROM1
L2 ROM1
L2 Boot ROM23
L2 ROM2
Byte Address Space
Arm Cortex-A5: Data Access
and Instruction Fetch;
SHARC+: Data Access
Arm: 0x00000000–0x00007FFF
SHARC+/DMA: 0x20000000–0x20007FFF
0x20080000–0x200BFFFF
0x20100000–0x20107FFF
0x20180000–0x201BFFFF
0x20200000–0x20207FFF
0x20280000–0x202BFFFF
Normal Word Address
Space for Data Access
SHARC+
Instruction Fetch VISA
Address Space SHARC+
Instruction Fetch ISA
Address Space SHARC+
0x08000000–0x08001FFF
0x08020000–0x0802FFFF
0x08040000–0x08041FFF
0x08060000–0x0806FFFF
0x08080000–0x08081FFF
0x080A0000–0x080AFFFF
0x00B80000–0x00B83FFF
0x00BA0000–0x00BBFFFF
0x00B00000–0x00B03FFF
0x00B20000–0x00B3FFFF
0x00B40000–0x00B43FFF
0x00B60000–0x00B7FFFF
0x00580000–0x00581555
0x005A0000–0x005AAAAF
0x00500000–0x00501555
0x00520000–0x0052AAAF
0x00540000–0x00541555
0x00560000–0x0056AAAF
1
All L2 RAM/ROM blocks are subdivided into eight banks.
For ADSP-SC58x products, the L2 Boot ROM0 byte address space is 0x 0000 0000–0x 0000 7FFF.
3
L2 Boot ROM address for ADSP-2158x products.
2
Table 6. SHARC+ L1 Memory in Multiprocessor Space
L1 memory of SHARC1 in
multiprocessor space
Address via Slave1 Port
Address via Slave2 Port
L1 memory of SHARC2 in
multiprocessor space
Address via Slave1 Port
Address via Slave2 Port
Memory
Block
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
Block 0
Block 1
Block 2
Block 3
Rev. B |
Byte Address Space
for Arm Cortex-A5 and SHARC+
0x28240000–0x2826FFFF
0x282C0000–0x282EFFFF
0x28300000–0x2831FFFF
0x28380000–0x2839FFFF
0x28640000–0x2866FFFF
0x286C0000–0x286EFFFF
0x28700000–0x2871FFFF
0x28780000–0x2879FFFF
0x28A40000–0x28A6FFFF
0x28AC0000–0x28AEFFFF
0x28B00000–0x28B1FFFF
0x28B80000–0x28B9FFFF
0x28E40000–0x28E6FFFF
0x28EC0000–0x28EEFFFF
0x28F00000–0x28F1FFFF
0x28F80000–0x28F9FFFF
Page 11 of 173 |
December 2018
Normal Word Address Space
for SHARC+
0x0A090000–0xA09BFFF
0x0A0B0000–0xA0BBFFF
0x0A0C0000–0x0A0C7FFF
0x0A0E0000–0x0A0E7FFF
0x0A190000–0x0A19BFFF
0x0A1B0000–0x0A1BBFFF
0x0A1C0000–0x0A1C7FFF
0x0A1E0000–0x0A1E7FFF
0x0A290000–0x0A29BFFF
0x0A2B0000–0x0A2BBFFF
0x0A2C0000–0x0A2C7FFF
0x0A2E0000–0x0A2E7FFF
0x0A390000–0x0A39BFFF
0x0A3B0000–0x0A3BBFFF
0x0A3C0000–0x0A3C7FFF
0x0A3E0000–0x0A3E7FFF
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 7. Memory Map of Mapped I/Os1
SMC Bank 0 (64 MB)
SMC Bank 1 (64 MB)
SMC Bank 2 (64 MB)
SMC Bank 3 (64 MB)
PCIe Data (256 MB)
SPI2 Memory
(512 MB)
1
Byte Address Space
Arm Cortex-A5: Data Access
and Instruction Fetch;
Normal Word Address Space
SHARC+: Data Access
SHARC+ Data Access
0x40000000–0x43FFFFFF
0x01000000–0x01FFFFFF
0x44000000–0x47FFFFFF
Not applicable
0x48000000–0x4BFFFFFF
Not applicable
0x4C000000–0x4FFFFFFF
Not applicable
0x50000000–0x5007FFFF
0x50080000–0x5017FFFF
0x02000000–0x03FFFFFF
0x50180000–0x57FFFFFF
0x58000000–0x5FFFFFFF
Not applicable
0x60000000–0x600FFFFF
0x60100000–0x602FFFFF
0x04000000–0x07FFFFFF
0x60300000–0x6FFFFFFF
0x70000000–0x7FFFFFFF
Not applicable
VISA Address Space
SHARC+ Instruction Fetch
0x00F00000–0x00F3FFFF
Not applicable
Not applicable
Not applicable
0x00F40000–0x00F7FFFF
Not applicable
Not applicable
Not applicable
0x00F80000–0x00FFFFFF
Not applicable
Not applicable
Not applicable
ISA Address Space
SHARC+ Instruction Fetch
0x00700000–0x0073FFFF
Not applicable
Not applicable
Not applicable
0x00740000–0x0077FFFF
Not applicable
Not applicable
0x00780000–0x007FFFFF
Not applicable
Not applicable
The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access do
not cover the entire byte address space.
Table 8. DMC Memory Map1
DMC0 (1 GB)
DMC1 (1 GB)
Byte Address Space
Arm Cortex-A5: Data Access
and Instruction Fetch;
SHARC+: Data Access
0x80000000–0x805FFFFF
0x80600000–0x809FFFFF
0x80A00000–0x80FFFFFF
0x81000000–0x9FFFFFFF
0xA0000000–0xBFFFFFFF
0x10000000–0x17FFFFFF
Not applicable
0xC0000000–0xC05FFFFF
0xC0600000–0xC09FFFFF
0xC0A00000–0xC0FFFFFF
0xC1000000–0xDFFFFFFF
0xE0000000–0xFFFFFFFF
1
Normal Word Address Space
SHARC+ Data Access
0x18000000–0x1FFFFFFF
Not applicable
VISA Address Space
SHARC+ Instruction Fetch
Not applicable
Not applicable
0x00800000–0x00AFFFFF
Not applicable
Not applicable
Not applicable
ISA Address Space
SHARC+ Instruction Fetch
0x00400000–0x004FFFFF
Not applicable
Not applicable
Not applicable
Not applicable
0x00600000–0x006FFFFF
Not applicable
0x00C00000–0x00EFFFFF
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
The Arm Cortex-A5 can access the entire byte address space. The SHARC+ VISA/ISA address space for instruction fetch and the normal word address space for data access
do not cover the entire byte address space.
System Crossbars (SCBs)
The SCBs provide the following features:
The system crossbars (SCBs) are the fundamental building
blocks of a switch-fabric style for on-chip system bus interconnection. The SCBs connect system bus masters to system bus
slaves, providing concurrent data transfer between multiple bus
masters and multiple bus slaves. A hierarchical model—built
from multiple SCBs—provides a power and area efficient system interconnection.
• Highly efficient, pipelined bus transfer protocol for sustained throughput
• Full-duplex bus operation for flexibility and reduced
latency
• Concurrent bus transfer support to allow multiple bus
masters to access bus slaves simultaneously
• Protection model (privileged/secure) support for selective
bus interconnect protection
Rev. B |
Page 12 of 173 |
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Direct Memory Access (DMA)
Extended Memory DMA
The processors use direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processors can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of processor activity.
Extended memory DMA supports various operating modes
such as delay line (which allows processor reads and writes to
external delay line buffers and to the external memory) with
limited core interaction and scatter/gather DMA (writes to and
from noncontiguous memory blocks).
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory to
memory DMA stream uses two channels: one channel is the
source channel and the second is the destination channel.
All DMA channels can transport data to and from all on-chip
and off-chip memories. Programs can use two types of DMA
transfers: descriptor-based or register-based.
Register-based DMA allows the processors to program DMA
control registers directly to initiate a DMA transfer. On completion, the DMA control registers automatically update with
original setup values for continuous transfer. Descriptor-based
DMA transfers require a set of parameters stored within memory to initiate a DMA sequence. Descriptor-based DMA
transfers allow multiple DMA sequences to be chained together.
Program a DMA channel to set up and start another DMA
transfer automatically after the current sequence completes.
The DMA engine supports the following DMA operations:
Cyclic Redundant C ode (CRC) Protection
The cyclic redundant codes (CRC) protection modules allow
system software to calculate the signature of code, data, or both
in memory, the content of memory-mapped registers, or periodic communication message objects. Dedicated hardware
circuitry compares the signature with precalculated values and
triggers appropriate fault events.
For example, every 100 ms the system software initiates the signature calculation of the entire memory contents and compares
these contents with expected, precalculated values. If a mismatch occurs, a fault condition is generated through the
processor core or the trigger routing unit.
The CRC is a hardware module based on a CRC32 engine that
computes the CRC value of the 32-bit data-words presented to
it. The source channel of the memory to memory DMA (in
memory scan mode) provides data. The data can be optionally
forwarded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are as follows:
• A single linear buffer that stops on completion
• Memory scan mode
• A linear buffer with negative, positive, or zero stride length
• Memory transfer mode
• A circular autorefreshing buffer that interrupts when each
buffer becomes full
• Data verify mode
• A similar circular buffer that interrupts on fractional buffers, such as at the halfway point
• User-programmable CRC32 polynomial
• Data fill mode
• The 1D DMA uses a set of identical ping pong buffers
defined by a linked ring of two-word descriptor sets, each
containing a link pointer and an address
• Bit/byte mirroring option (endianness)
• The 1D DMA uses a linked list of four-word descriptor sets
containing a link pointer, an address, a length, and a
configuration
• 32-bit CRC signature of a block of a memory or an MMR
block
• The 2D DMA uses an array of one-word descriptor sets,
specifying only the base DMA address
• The 2D DMA uses a linked list of multiword descriptor
sets, specifying all configurable parameters
Memory Direct Memory Access (MDMA)
The processor supports various MDMA operations, including,
• Standard bandwidth MDMA channels with CRC protection (32-bit bus width, run on SCLK0)
• Enhanced bandwidth MDMA channel (32-bit bus width,
runs on SYSCLK)
• Maximum bandwidth MDMA channels (64-bit bus width,
run on SYCLK, one channel can be assigned to the FFT
accelerator)
Rev. B |
Page 13 of 173 |
• Fault/error interrupt mechanisms
• 1D and 2D fill block to initialize an array with constants
Event Handling
The processors provide event handling that supports both nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing a higher priority event takes precedence over servicing
a lower priority event.
The processors provide support for five different types of
events:
• An emulation event causes the processors to enter emulation mode, allowing command and control of the
processors through the JTAG interface.
• A reset event resets the processors.
• An exceptions event occur synchronously to program flow
(in other words, the exception is taken before the instruction is allowed to complete). Conditions triggered on the
one side by the SHARC+ core, such as data alignment
(SIMD/long word) or compute violations (fixed or floating
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point), and illegal instructions cause core exceptions. Conditions triggered on the other side by the SEC, such as error
correcting codes (ECC)/parity/watchdog/system clock,
cause system exceptions.
• An interrupts event occurs asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Support for the hardware-accelerated cryptographic ciphers
includes the following:
• AES in ECB, CBC, ICM, and CTR modes with 128-bit,
192-bit, and 256-bit keys
• DES in ECB and CBC mode with 56-bit key
• 3DES in ECB and CBC mode with 3x 56-bit key
• ARC4 in stateful, stateless mode, up to 128-bit key
System Event Controller (SEC)
Both SHARC+ cores feature a system event controller. The SEC
features include the following:
• Comprehensive system event source management including interrupt enable, fault enable, priority, core mapping,
and source grouping
• A distributed programming model where each system
event source control and all status fields are independent of
each other
• Determinism where all system events have the same propagation delay and provide unique identification of a specific
system event source
• A slave control port that provides access to all SEC registers
for configuration, status, and interrupt/fault services
• Global locking that supports a register level protection
model to prevent writes to locked registers
• Fault management including fault action configuration,
time out, external indication, and system reset
Support for the hardware accelerated hash functions includes
the following:
• SHA-1
• SHA-2 with 224-bit and 256-bit digests
• HMAC transforms for SHA-1 and SHA-2
• MD5
Public key accelerator (PKA) is available to offload computation
intensive public key cryptography operations.
Both a hardware-based nondeterministic random number generator and pseudorandom number generator are available.
Secure boot is also available with 224-bit elliptic curve digital
signatures ensuring integrity and authenticity of the boot
stream. Optionally, ensuring confidentiality through AES-128
encryption is available.
Employ secure debug to allow only trusted users to access the
system with debug tools.
Trigger Routing Unit (TRU)
CAUTION
This product includes security features that can be
used to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device
(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices is
limited. Contact Analog Devices for details on the
failure analysis limitations for this device.
The trigger routing unit (TRU) provides system-level sequence
control without core intervention. The TRU maps trigger
masters (generators of triggers) to trigger slaves (receivers of
triggers). Slave endpoints can be configured to respond to triggers in various ways. Common applications enabled by the TRU
include,
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
System Protection Unit (SPU)
• Synchronization of concurrent activities
The system protection unit (SPU) guards against accidental or
unwanted access to an MMR space of the peripheral by providing a write protection mechanism. The user can choose and
configure the protected peripherals as well as configure which of
the four system MMR masters (two SHARC+ cores, memory
DMA, and CoreSight debug) the peripherals are guarded
against.
SECURITY FEATURES
The following sections describe the security features of the
ADSP-SC58x/ADSP-2158x processors.
Arm TrustZone
The ADSP-SC58x processors provide TrustZone technology
that is integrated into the Arm Cortex-A5 processors. The
TrustZone technology enables a secure state that is extended
throughout the system fabric.
The SPU is also part of the security infrastructure. Along with
providing write protection functionality, the SPU is employed
to define which resources in the system are secure or nonsecure
and to block access to secure resources from nonsecure masters.
Cryptographic Hardware Accelerators
The ADSP-SC58x/ADSP-2158x processors support standardsbased hardware accelerated encryption, decryption, authentication, and true random number generation.
Rev. B |
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System Memory Protection Unit (SMPU)
Synonymously, the system memory protection unit (SMPU)
provides memory protection against read and/or write transactions to defined regions of memory. There are SMPU units in
the ADSP-SC58x/ADSP-2158x processors for each memory
space, except for SHARC L1 and SPI direct memory slave.
The SMPU is also part of the security infrastructure. It allows
the user to protect against arbitrary read and/or write transactions and allows regions of memory to be defined as secure and
prevent nonsecure masters from accessing those memory
regions.
SECURITY FEATURES DISCLAIMER
To our knowledge, the Security Features, when used in accordance with the data sheet and hardware reference manual
specifications, provide a secure method of implementing code
and data safeguards. However, Analog Devices does not guarantee that this technology provides absolute security.
ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS
ANY AND ALL EXPRESS AND IMPLIED WARRANTIES
THAT THE SECURITY FEATURES CANNOT BE
BREACHED, COMPROMISED, OR OTHERWISE CIRCUMVENTED AND IN NO EVENT SHALL ANALOG DEVICES
BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR
RELEASE OF DATA, INFORMATION, PHYSICAL PROPERTY, OR INTELLECTUAL PROPERTY.
SAFETY FEATURES
The ADSP-SC58x/ADSP-2158x processors are designed to support functional safety applications. While the level of safety is
mainly dominated by the system concept, the following primitives are provided by the processors to build a robust safety
concept.
Multiparity Bit Protected SHARC+ Core L1 Memories
In the SHARC+ core L1 memory space, whether SRAM or
cache, multiple parity bits protect each word to detect the single
event upsets that occur in all RAMs. Parity does not protect the
cache tags.
Error Correcting Codes (ECC) Protected L2 Memories
Error correcting codes (ECC) correct single event upsets. A single error correct-double error detect (SEC-DED) code protects
the L2 memory. By default, ECC is enabled, but it can be disabled on a per bank basis. Single-bit errors correct
transparently. If enabled, dual-bit errors can issue a system
event or fault. ECC protection is fully transparent to the user,
even if L2 memory is read or written by 8-bit or 16-bit entities.
Cyclic Redundant Code (CRC) Protected Memories
While parity bit and ECC protection mainly protect against random soft errors in L1 and L2 memory cells, the cyclic redundant
code (CRC) engines can protect against systematic errors
(pointer errors) and static content (instruction code) of L1, L2,
and even L3 memories (DDR2, LPDDR). The processors feature
two CRC engines that are embedded in the memory to memory
DMA controllers.
Rev. B |
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CRC checksums can be calculated or compared automatically
during memory transfers, or one or multiple memory regions
can be continuously scrubbed by a single DMA work unit as per
DMA descriptor chain instructions. The CRC engine also protects data loaded during the boot process.
Signal Watchdogs
The eight general-purpose timers feature modes to monitor offchip signals. The watchdog period mode monitors whether
external signals toggle with a period within an expected range.
The watchdog width mode monitors whether the pulse widths
of external signals are within an expected range. Both modes
help to detect undesired toggling or lack of toggling of system
level signals.
System Event Controller (SEC)
Besides system events, the system event controller (SEC) further
supports fault management including fault action configuration
as timeout, internal indication by system interrupt, or external
indication through the SYS_FAULT pin and system reset.
PROCESSOR PERIPHERALS
The following sections describe the peripherals of the ADSPSC58x/ADSP-2158x processors.
Dynamic Memory Controller (DMC)
The 16-bit dynamic memory controller (DMC) interfaces to:
• LPDDR1 (JESD209A) maximum frequency 200 MHz,
DDRCLK (64 Mb to 2 Gb)
• DDR2 (JESD79-2E) maximum frequency 400 MHz,
DDRCLK (256 Mb to 4 Gb)
• DDR3 (JESD79-3E) maximum frequency 450 MHz,
DDRCLK (512 Mb to 8 Gb)
• DDR3L (1.5 V compatible only) maximum frequency
450 MHz, DDRCLK (512 Mb to 8 Gb)
See Table 8 for the DMC memory map.
Digital Audio Interface (DAI)
The processors support two mirrored digital audio interface
(DAI) units. Each DAI can connect various peripherals to any of
the DAI pins (DAI_PIN20–DAI_PIN01).
The application code makes these connections using the signal
routing unit (SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to interconnect
under software control. This functionality allows easy use of the
DAI associated peripherals for a wider variety of applications by
using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI includes the peripherals described in the following sections (SPORTs, ASRC, S/PDIF, and PCG). DAI Pin Buffers 20
and 19 can change the polarity of the input signals. Most signals
of the peripherals belonging to different DAIs cannot be interconnected, with few exceptions.
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The DAI_PINx pin buffers may also be used as GPIO pins. DAI
input signals allow the triggering of interrupts on the rising
edge, the falling edge, or both edges.
blocks on the processor. The digital audio interface carries three
types of information: audio data, nonaudio data (compressed
data), and timing information.
See the “Digital Audio Interface (DAI)” chapter of the ADSPSC58x/ADSP-2158x SHARC+ Processor Hardware Reference
for complete information on the use of the DAIs and SRUs.
The S/PDIF interface supports one stereo channel or compressed audio streams. The S/PDIF transmitter and receiver are
AES3 compliant and support the sample rate from 24 KHz to
192 KHz. The S/PDIF receiver supports professional jitter
standards.
Serial Ports (SPORTs)
The processors feature eight synchronous full serial ports. These
ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. These devices include
Analog Devices AD19xx and ADAU19xx family of audio
codecs, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Two data lines, a clock, and frame sync
make up the serial ports. The data lines can be programmed to
either transmit or receive data and each data line has a dedicated
DMA channel.
An individual full SPORT module consists of two independently configurable SPORT halves with identical
functionality. Two bidirectional data lines—primary (0) and
secondary (1)—are available per SPORT half and are configurable as either transmitters or receivers. Therefore, each SPORT
half permits two unidirectional streams into or out of the same
SPORT. This bidirectional functionality provides greater
flexibility for serial communications. For full-duplex configuration, one half SPORT provides two transmit signals, while the
other half SPORT provides the two receive signals. The frame
sync and clock are shared.
Serial ports operate in the following six modes:
The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the
receiver/transmitter can be formatted as left justified, I2S, or
right justified with word widths of 16, 18, 20, or 24 bits. The
serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from various sources, such as the
SPORTs, external pins, and the precision clock generators
(PCGs), and are controlled by the SRU control registers.
Precision Clock Generators (PCG)
The precision clock generators (PCG) consist of four units:
units A/B located in the DAI0 block, and units C/D located in
the DAI1 block. The PCG can generate a pair of signals (clock
and frame sync) derived from a clock input signal (CLKIN1-0,
SCLK0, or DAI pin buffer). Each unit can also access the opposite DAI unit. All units are identical in functionality and operate
independently of each other. The two signals generated by each
unit are normally used as a serial bit clock/frame sync pair.
Enhanced Parallel Peripheral Interface (EPPI)
• Standard DSP serial mode
• Multichannel time division multiplexing (TDM) mode
• I2S mode
• Packed I2S mode
• Left justified mode
The processors provide an enhanced parallel peripheral interface (EPPI) that supports data widths up to 24 bits. The EPPI
supports direct connection to TFT LCD panels, parallel ADCs
and DACs, video encoders and decoders, image sensor modules, and other general-purpose peripherals.
The features supported in the EPPI module include the
following:
• Right justified mode
Asynchronous Sample Rate Converter (ASRC)
The asynchronous sample rate converter (ASRC) contains eight
ASRC blocks. It is the same core in the AD1896 192 kHz stereo
asynchronous sample rate converter. The ASRC provides up to
140 dB signal-to-noise ratio (SNR). The ASRC block performs
synchronous or asynchronous sample rate conversion across
independent stereo channels, without using internal processor
resources. The ASRC blocks can also be configured to operate
together to convert multichannel audio data without phase mismatches. Finally, the ASRC can clean up audio data from jittery
clock sources such as the S/PDIF receiver.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The Sony/Philips Digital Interface Format (S/PDIF) is a standard audio data transfer format that allows the transfer of digital
audio signals from one device to another without converting
them to an analog signal. There are two S/PDIF transmit/receive
• Programmable data length of 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, 18 bits, and 24 bits per clock.
• Various framed, nonframed, and general-purpose operating modes. Frame syncs can be generated internally or can
be supplied by an external device.
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decoding.
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits, and 24 bits. If packing/unpacking is
enabled, configure endianness to change the order of packing/unpacking of the bytes/words.
• RGB888 can be converted to RGB666 or RGB565 for transmit modes.
• Various deinterleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable output available on Frame
Sync 3.
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Universal Asynchronous Receiver/Transmitter
(UART) Ports
ADC Control Module (ACM) Interface
The processors provide three full-duplex universal asynchronous receiver/transmitter (UART) ports, fully compatible with
PC standard UARTs. Each UART port provides a simplified
UART interface to other peripherals or hosts, supporting fullduplex, DMA supported, asynchronous transfers of serial data.
A UART port includes support for five to eight data bits as well
as no parity, even parity, or odd parity.
Optionally, an additional address bit can be transferred to interrupt only addressed nodes in multidrop bus (MDB) systems. A
frame is terminated by a configurable number of stop bits.
The UART ports support automatic hardware flow control
through the clear to send (CTS) input and request to send (RTS)
output with programmable assertion first in, first out (FIFO)
levels.
To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a programmable interframe space.
Serial Peripheral Interface (SPI) Ports
The processors have three industry-standard SPI-compatible
ports that allow the processors to communicate with multiple
SPI-compatible devices.
The baseline SPI peripheral is a synchronous, four-wire interface consisting of two data pins, one device select pin, and a
gated clock pin. The two data pins allow full-duplex operation
to other SPI-compatible devices. An extra two (optional) data
pins are provided to support quad SPI operation. Enhanced
modes of operation, such as flow control, fast mode, and dual
I/O mode (DIOM), are also supported. A direct memory access
(DMA) mode allows for transferring several words with minimal central processing unit (CPU) interaction.
With a range of configurable options, the SPI ports provide a
glueless hardware interface with other SPI-compatible devices
in master mode, slave mode, and multimaster environments.
The SPI peripheral includes programmable baud rates, clock
phase, and clock polarity. The peripheral can operate in a multimaster environment by interfacing with several other devices,
acting as either a master device or a slave device. In a multimaster environment, the SPI peripheral uses open-drain outputs to
avoid data bus contention. The flow control features enable slow
slave devices to interface with fast master devices by providing
an SPI ready pin (SPI_RDY) which flexibly controls the
transfers.
The baud rate and clock phase/polarities of the SPI port are programmable. The port has integrated DMA channels for both
transmit and receive data streams.
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processors and an ADC.
The analog-to-digital conversions are initiated by the processors, based on external or internal events.
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
The ACM synchronizes the ADC conversion process, generating the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by an internal DAI routing of the ACM with the SPORT0 block.
The processors interface directly to many ADCs without any
glue logic required.
3-Phase Pulse Width Modulator (PWM) Units
The pulse width modulator (PWM) module is a flexible and
programmable waveform generator. With minimal CPU intervention, the PWM generates complex waveforms for motor
control, pulse coded modulation (PCM), DAC conversions,
power switching, and power conversion. The PWM module has
four PWM pairs capable of 3-phase PWM generation for source
inverters for ac induction and dc brushless motors.
Each of the three 3-phase PWM generation units features the
following:
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single update mode with an option for asymmetric duty
• Programmable dead time and switching frequency
• Programmable dead time per channel
• Twos complement implementation which permits smooth
transition to full on and full off states
• Dedicated asynchronous PWM shutdown signal
Ethernet Media Access Controller (EMAC)
The processor features two ethernet media access controllers
(EMACs): 10/100 Ethernet and 10/100/1000/AVB Ethernet
with precision time protocol IEEE 1588.
The processors can directly connect to a network through
embedded fast EMAC that supports 10-BaseT (10 Mb/sec),
100-BaseT (100 Mb/sec) and 1000-BaseT (1 Gb/sec) operations.
The 10/100 EMAC peripheral on the processors is fully compliant to the IEEE 802.3-2002 standard. The peripheral provides
programmable features designed to minimize supervision, bus
use, or message processing by the rest of the processor system.
Some standard features of the EMAC are as follows:
• Support and RMII/RGMII protocols for external PHYs
• Full-duplex and half-duplex modes
Link Ports (LP)
• Media access management (in half-duplex operation)
Two 8-bit wide link ports (LP) can connect to the link ports of
other DSPs or peripherals. LP are bidirectional ports that have
eight data lines, an acknowledge line, and a clock line.
• Flow control
Rev. B |
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• Station management, including the generation of
MDC/MDIO frames for read/write access to PHY registers
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Some advanced features of the EMAC are as follows:
• Automatic checksum computation of IP header and IP
payload fields of receive frames
• Independent 32-bit descriptor driven receive and transmit
DMA channels
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• Automatic detection of IPv4 and IPv6 packets, as well as
PTP messages
• Multiple input clock sources (SCLK0, RGMII, RMII, RMII
clock, and external clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
Controller Area Network (CAN)
• 47 MAC management statistics counters with selectable
clear on read behavior and programmable interrupts on
half maximum value
There are two controller area network (CAN) modules. A CAN
controller implements the CAN 2.0B (active) protocol. This
protocol is an asynchronous communications protocol used in
both industrial and automotive control systems. The CAN protocol is well suited for control applications due to the capability
to communicate reliably over a network. This is because the
protocol incorporates CRC checking, message error tracking,
and fault node confinement.
• Advanced power management
The CAN controller offers the following features:
• Transmit DMA support for separate descriptors for MAC
header and payload fields to eliminate buffer copy
operations
• Convenient frame alignment modes
• Support for 802.3Q tagged VLAN frames
• 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit)
• Programmable MDC clock rate and preamble suppression
• Dedicated acceptance masks for each mailbox
• Magic packet detection and wakeup frame filtering
• Additional data filtering on the first two bytes
Audio Video Bridging (AVB) Support
(10/100/1000 EMAC Only)
The 10/100/1000 EMAC supports the following audio video
(AVB) features:
• Support for remote frames
• Active or passive network support
• Separate channels or queues for AV data transfer in
100 Mbps and 1000 Mbps modes
• IEEE 802.1-Qav specified credit-based shaper (CBS) algorithm for the additional transmit channels
• Configuring up to two additional channels (Channel 1 and
Channel 2) on the transmit and receive paths for AV traffic.
Channel 0 is available by default and carries the legacy best
effort Ethernet traffic on the transmit side.
• Separate DMA, transmit and receive FIFO for AVB latency
class
• Programmable control to route received VLAN tagged
non AV packets to channels or queues
Precision Time Protocol (PTP) IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processors include hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
(PTP_TSYNC).
This engine provides hardware assisted time stamping to
improve the accuracy of clock synchronization between PTP
nodes. The main features of the engine are as follows:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
• Lock adjustment
Rev. B |
• Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats
Page 18 of 173 |
• Interrupts, including transmit and receive complete, error,
and global
An additional crystal is not required to supply the CAN clock
because it is derived from a system clock through a programmable divider.
Timers
The processors include several timers that are described in the
following sections.
General-Purpose (GP) Timers (TIMER)
There is one general-purpose (GP) timer unit, providing eight
general-purpose programmable timers. Each timer has an external pin that can be configured either as PWM or timer output,
as an input to clock the timer, or as a mechanism for measuring
pulse widths and periods of external events. These timers can be
synchronized to an external clock input on the TM_TMR[n]
pins, an external TM_CLK input pin, or to the internal SCLK0.
These timer units can be used in conjunction with the UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software autobaud detect function
for the respective serial channels.
The GP timers can generate interrupts to the processor core,
providing periodic events for synchronization to either the system clock or to external signals. Timer events can also trigger
other peripherals via the TRU (for instance, to signal a fault).
Each timer can also be started and/or stopped by any TRU master without core intervention.
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Watchdog Timer (WDT)
Two on-chip software watchdog timers (WDT) can be used by
the Arm Cortex-A5 and/or SHARC+ cores. A software watchdog can improve system availability by forcing the processors to
a known state, via a general-purpose interrupt, or a fault, if the
timer expires before being reset by software.
The programmer initializes the count value of the timer, enables
the appropriate interrupt, then enables the timer. Thereafter,
the software must reload the counter before it counts down to
zero from the programmed value, protecting the system from
remaining in an unknown state where software that normally
resets the timer stops running due to an external noise condition or software error.
General-Purpose Counters (CNT)
A 32-bit counter (CNT) is provided that can operate in generalpurpose up/down count modes and can sense 2-bit quadrature
or binary codes as typically emitted by industrial drives or manual thumbwheels. Count direction is either controlled by a levelsensitive input pin or by two edge detectors.
A third counter input can provide flexible zero marker support
and can input the push button signal of thumbwheel devices. All
three CNT0 pins have a programmable debouncing circuit.
Internal signals forwarded to a GP timer enable this timer to
measure the intervals between count events. Boundary registers
enable auto-zero operation or simple system warning by interrupts when programmed count values are exceeded.
PCI Express (PCIe)
A PCI express interface (PCIe) is available on some product
variants (see Table 2 and Table 3). This single, bidirectional lane
can be configured to be either a root complex (RC) or end point
(EP) system. The PCIe interface has the following features:
• Designed to be compliant with the PCI Express Base
Specification 3.0
• Support for transfers at either 2.5 Gbps (Gen 1) or 5.0 Gbps
(Gen 2) in each direction
• Support for 8b/10b encode and decode
• Selectable ADC clock frequency including the ability to
program a prescaler.
• Adaptable conversion type; allows single or continuous
conversion with option of autoscan.
• Autosequencing capability with up to 15 autoconversions
in a single session. Each conversion can be programmed to
select 1 to 15 input channels.
• 16 data registers (individually addressable) to store conversion values.
USB 2.0 On the Go (OTG) Dual-Role Device Controller
There are two USB modules + PHY. USB0 supports HS/FS/LS
USB 2.0 on the go (OTG) and USB1 supports HS/FS USB 2.0
only and can be programmed to be a host or device.
The USB 2.0 OTG dual-role device controller provides a low
cost connectivity solution in industrial applications, as well as
consumer mobile devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller allows these
devices to transfer data using a point to point USB connection
without the need for a PC host. The module can operate in a traditional USB peripheral only mode as well as the host mode
presented in the OTG supplement to the USB 2.0 specification.
The USB clock is provided through a dedicated external crystal
or crystal oscillator.
The USB OTG dual-role device controller includes a PLL with
programmable multipliers to generate the necessary internal
clocking frequency for the USB.
Media Local Bus (Media LB)
The automotive model has a Media LB (MLB) slave interface
that allows the processors to function as a media local bus
device. It includes support for both 3-pin and 6-pin media local
bus protocols. The MLB 3-pin configuration supports speeds up
to 1024 × FS. The MLB 6-pin configuration supports a speed of
2048 × FS. The MLB also supports up to 64 logical channels
with up to 468 bytes of data per MLB frame.
The MLB interface supports MOST25, MOST50, and MOST150
data rates and operates in slave mode only.
• Lane reversal and lane polarity inversion
• Flow control of data in both the transmit and receive
directions
2-Wire Controller Interface (TWI)
• Support for removal of corrupted packets for error detection and recovery
• Maximum transaction payload of 256 bytes
Housekeeping Analog-to-Digital Converter (HADC)
The housekeeping analog-to-digital converter (HADC) provides a general-purpose, multichannel successive
approximation ADC. It supports the following set of features:
• 12-bit ADC core with built in sample-and-hold.
• 8 single-ended input channels that can be extended to 15
channels by adding an external channel multiplexer.
• Throughput rates up to 1 MSPS.
Rev. B |
• Single external reference with analog inputs between
0 V and 3.3 V.
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The processors include three 2-wire interface (TWI) modules
that provide a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I2C bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400 kb/sec. The TWI interface pins are compatible
with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
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General-Purpose I/O (GPIO)
SYSTEM ACCELERATION
Each general-purpose port pin can be individually controlled by
manipulating the port control, status, and interrupt registers:
The following sections describe the system acceleration blocks
of the ADSP-SC58x/ADSP-2158x processors.
• GPIO direction control register specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers have a write one to modify mechanism that allows any combination of individual
GPIO pins to be modified in a single instruction, without
affecting the level of any other GPIO pins.
• GPIO interrupt mask registers allow each individual GPIO
pin to function as an interrupt to the processors. GPIO pins
defined as inputs can be configured to generate hardware
interrupts, while output pins can be triggered by software
interrupts.
• GPIO interrupt sensitivity registers specify whether individual pins are level or edge sensitive and specify, if edge
sensitive, whether the rising edge or both the rising and
falling edges of the signal are significant.
Pin Interrupts
Every port pin on the processors can request interrupts in either
an edge sensitive or a level sensitive manner with programmable
polarity. Interrupt functionality is decoupled from GPIO operation. Six system-level interrupt channels (PINT0–PINT5) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin by pin basis. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and
interrupt management. This includes masking, identification,
and clearing of requests. These registers also enable access to the
respective pin states and use of the interrupt latches, regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
FFT/IFFT Accelerator
A high performance FFT/IFFT accelerator is available to
improve the overall floating-point computation power of the
ADSP-SC58x/ADSP-2158x processors.
The following features are available to improve the overall performance of the FFT/IFFT accelerator:
• Support for the IEEE-754/854 single-precision floatingpoint data format.
• Automatic twiddle factor generation to reduce system
bandwidth.
• Support for a vector complex multiply for windowing and
frequency domain filtering.
• Ability to pipeline the data flow. This allows the accelerator
to bring in a new data set while the current data set is processed and the previous data set is sent out to memory. This
can provide a significant system level performance
improvement.
• Ability to output the result as the magnitude squared of the
complex samples.
• Dedicated, high speed DMA controller with 64-bit buses
that can read and write data from any memory space.
The FFT/IFFT accelerator can run concurrently with the other
accelerators on the processor.
Finite Impulse Response (FIR) Accelerator
The finite impulse response (FIR) accelerator consists of a
1024 word coefficient memory, a 1024 word deep delay line for
the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency.
The FIR accelerator can access all memory spaces and can run
concurrently with the other accelerators on the processor.
Infinite Impulse Response (IIR) Accelerator
Mobile Storage Interface (MSI)
The mobile storage interface (MSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), and secure digital input/output cards (SDIO). The
MSI controller has the following features:
• Support for a single MMC, SD memory, and SDIO card
• Support for 1-bit and 4-bit SD modes
The infinite impulse response (IIR) accelerator consists of a
1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one
MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency. The IIR
accelerator can access all memory spaces and run concurrently
with the other accelerators on the processor.
• Support for 1-bit, 4-bit, and 8-bit MMC modes
Harmonic Analysis Engine (HAE)
• Support for eMMC 4.3 embedded NAND flash devices
The harmonic analysis engine (HAE) block receives 8 kHz input
samples from two source signals whose frequencies are between
45 Hz and 65 Hz. The HAE processes the input samples and
produces output results. The output results consist of power
quality measurements of the fundamental and up to 12 additional harmonics.
• An eleven-signal external interface with clock, command,
optional interrupt, and up to eight data lines
• Integrated DMA controller
• Card interface clock generation in the clock distribution
unit (CDU)
• SDIO interrupt and read wait features
Rev. B |
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The reset target is defined as the following:
Sinus Cardinalis (SINC) Filter
The sinus cardinalis (SINC) filter module processes four bit
streams using a pair of configurable SINC filters for each bit
stream. The purpose of the primary SINC filter of each pair is to
produce the filtered and decimated output for the pair. The output can decimate any integer rate between 8 and 256 times
lower than the input rate. Greater decimation allows greater
removal of noise, and, therefore, greater effective number of bits
(ENOB).
• System reset—all functional units except the RCU are set to
default states.
• Hardware reset—all functional units are set to default states
without exception. History is lost.
• Core only reset— affects the core only. When in reset state,
the core is not accessed by any bus master.
The reset source is defined as the following:
Optional additional filtering outside the SINC module can further increase ENOB. The primary SINC filter output is
accessible through transfer to processor memory, or to another
peripheral, via DMA.
• System reset—can be triggered by software (writing to the
RCU_CTL register) or by another functional unit such as
the dynamic power management (DPM) unit or any of the
SEC, TRU, or emulator inputs.
Each of the four channels is also provided with a low latency
secondary filter with programmable positive and negative overrange detection comparators. These limit detection events can
interrupt the core, generate a trigger, or signal a system fault.
• Hardware reset—the SYS_HWRST input signal asserts
active (pulled down).
• Core only reset—affects only the core. The core is not
accessed by any bus master when in reset state.
Digital Transmission Content Protection (DTCP)
• Trigger request (peripheral).
Contact Analog Devices for more information on DTCP.
Real-Time Clock (RTC)
SYSTEM DESIGN
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the processor.
Connect the RTC0_CLKIN and RTC0_XTAL pins with external
components as shown in Figure 6.
The following sections provide an introduction to system design
features and power supply issues.
Clock Management
The processors provide three operating modes, each with a different performance and power profile. Control of clocking to
each of the processor peripherals reduces power consumption.
The processors do not support any low power operation modes.
Control of clocking to each of the processor peripherals can
reduce the power consumption.
Reset Control Unit (RCU)
Reset is the initial state of the whole processor, or the core, and
is the result of a hardware or software triggered event. In this
state, all control registers are set to default values and functional
units are idle. Exiting a full system reset starts with the core
ready to boot.
The reset control unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions put the system into an undefined state or causes
resources to stall. This is particularly important when the core
resets (programs must ensure that there is no pending system
activity involving the core when it is reset).
From a system perspective, reset is defined by both the reset target and the reset source.
Rev. B |
Page 21 of 173 |
The RTC peripheral has dedicated power supply pins so it can
remain powered up and clocked even when the remainder of the
processor is in a low power state. The RTC provides several
programmable interrupt options, including interrupt per
second, minute, hour, or day clock ticks; interrupt on programmable stopwatch countdown; or interrupt at a programmed
alarm time.
RTC0_CLKIN
RTC0_XTAL
R1
X1
C1
C2
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.
Figure 6. External Components for RTC
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a
24 hour counter, and a 32,768 day counter. When the alarm
interrupt is enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value in
the alarm control register (RTC_ALARM). There are two
alarms: a time of day and a day and time of that day.
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The stopwatch function counts down from a programmed
value, with 1 sec resolution. When the stopwatch interrupt is
enabled and the counter underflows, an interrupt is generated.
SHARC PROCESSOR
TO PLL
CIRCUITRY
Clock Generation Unit (CGU)
The ADSP-SC58x/ADSP-2158x processors support two independent PLLs. Each PLL is part of a clock generation unit
(CGU); see Figure 8. Each CGU can be either driven externally
by the same clock source or each can be driven by separate
sources. This provides flexibility in determining the internal
clocking frequencies for each clock domain.
ȍ
SYS_CLKINx
FOR OVERTONE
OPERATION ONLY:
Frequencies generated by each CGU are derived from a common multiplier with different divider values available for each
output.
The CGU generates all on-chip clocks and synchronization signals. Multiplication factors are programmed to define the
PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks, the DDR1/DDR2/
DDR3 clock (DCLK), and the output clock (OCLK). For more
information on clocking, see the ADSP-SC58x/ADSP-2158x
SHARC+ Processor Hardware Reference.
SYS_XTALx
Nȍ *
18 pF*
18 pF*
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18 pF MUST BE TREATED AS A MAXIMUM.
Figure 7. External Crystal Connection
Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with
a new value and the PLL logic executes the changes so it transitions smoothly from the current conditions to the new
conditions.
A third overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit,
shown in Figure 7. A design procedure for the third overtone
operation is discussed in detail in Using Third Overtone Crystals with the ADSP-218x DSP (EE-168). The same
recommendations can be used for the USB crystal oscillator.
System Crystal Oscillator and USB Crystal Oscillator
Clock Distribution Unit (CDU)
The processor can be clocked by an external crystal (see
Figure 7), a sine wave input, or a buffered, shaped clock derived
from an external clock oscillator. If using an external clock, it
should be a TTL-compatible signal and must not be halted,
changed, or operated below the specified frequency during normal operation. This signal is connected to the SYS_CLKINx pin
and the USB_CLKIN pin of the processor. When using an
external clock, the SYS_XTALx pin and the USB_XTAL pin
must be left unconnected. Alternatively, because the processor
includes an on-chip oscillator circuit, an external crystal can be
used.
The two CGUs each provide outputs which feed a clock distribution unit (CDU). The clock outputs CLKO0–CLKO9 are
connected to various targets. For more information, refer to the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware
Reference.
For fundamental frequency operation, use the circuit shown in
Figure 7. A parallel resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKINx
pin and the SYS_XTALx pin. The on-chip resistance between
the SYS_CLKINx pin and the SYS_XTALx pin is in the 500 kΩ
range. Further parallel resistors are typically not recommended.
The two capacitors and the series resistor, shown in Figure 7,
fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 7 are typical values
only. The capacitor values are dependent upon the load capacitance recommendations of the crystal manufacturer and the
physical layout of the printed circuit board (PCB). The resistor
value depends on the drive level specified by the crystal manufacturer. The user must verify the customized values based on
careful investigations on multiple devices over the required
temperature range.
Rev. B |
Page 22 of 173 |
Power-Up
SYS_XTALx oscillations (SYS_CLKINx) start when power is
applied to the VDD_EXT pins. The rising edge of SYS_HWRST
starts on-chip PLL locking (PLL lock counter). The deassertion
must apply only if all voltage supplies and SYS_CLKINx oscillations are valid (refer to the Power-Up Reset Timing section).
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the
SYS_ CLKIN0 input. Refer to the ADSP-SC58x/ADSP-2158x
SHARC+ Processor Hardware Reference to change the default
mapping of clocks.
Booting
The processors have several mechanisms for automatically loading internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE[n] input pins. There are two
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categories of boot modes. In master boot mode, the processors
actively load data from serial memories. In slave boot modes,
the processors receive data from external host devices.
The boot modes are shown in Table 9. These modes are implemented by the SYS_BMODE[n] bits of the reset configuration
register and are sampled during power-on resets and software
initiated resets.
In the ADSP-SC58x processors, the Arm Cortex-A5 (Core 0)
controls the boot process, including loading all internal and
external memory. Likewise, in the ADSP-2158x processors, the
SHARC+ (Core 1) controls the boot function. The option for
secure boot is available on all models.
Table 9. Boot Modes
SYS_BMODE[n] Setting
000
001
010
011
100
101
110
111
Boot Mode
No boot
SPI2 master
SPI2 slave
Reserved
Reserved
Reserved
Link0 slave
UART0 slave
Thermal Monitoring Unit (TMU)
The thermal monitoring unit (TMU) provides on-chip temperature measurement which is important in applications that
require substantial power consumption. The TMU is integrated
into the processor die and digital infrastructure using an MMRbased system access to measure the die temperature variations
in real-time.
TMU features include the following:
• On-chip temperature sensing
• Programmable over temperature and under temperature
limits
• Programmable conversion rate
Power Management
As shown in Table 10, the processors support four different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. There are
no sequencing requirements for the various power domains, but
all domains must be powered according to the appropriate specifications (see the Specifications section for processor operating
conditions). If the feature or the peripheral is not used, refer to
Table 27.)
Table 10. Power Domains
Power Domain
All internal logic
DDR3/DDR2/LPDDR
USB
HADC/TMU
RTC
PCIe_TX
PCIe_RX
PCIe
All other I/O (includes SYS, JTAG, and
port pins)
VDD Range
VDD_INT
VDD_DMC
VDD_USB
VDD_HADC
VDD_RTC
VDD_PCIE_TX
VDD_PCIE_RX
VDD_PCIE
VDD_EXT
The power dissipated by the processors is largely a function of
the clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Target Board JTAG Emulator Connector
The Analog Devices DSP tools product line of JTAG emulators
uses the IEEE 1149.1 JTAG test access port of the processors to
monitor and control the target board processor during emulation. The Analog Devices DSP tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and processor stacks. The processor JTAG interface ensures the emulator
does not affect target system loading or timing.
For information on JTAG emulator operation, see the appropriate emulator hardware user’s guide at SHARC Processors
Software and Tools.
• Averaging feature available
Power Supplies
The processors have separate power supply connections for:
SYSTEM DEBUG
The processors include various features that allow easy system
debug. These are described in the following sections.
• Internal (VDD_INT)
• External (VDD_EXT)
• USB (VDD_USB)
System Watchpoint Unit (SWU)
• HADC/TMU (VDD_HADC)
The system watchpoint unit (SWU) is a single module that connects to a single system bus and provides transaction
monitoring. One SWU is attached to the bus going to each
system slave. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of
registers with associated hardware. These four SWU match
groups operate independently but share common event (for
example, interrupt and trigger) outputs.
• RTC (VDD_RTC)
• DMC (VDD_DMC)
• PCIe (VDD_PCIE, VDD_PCIE_TX and VDD_PCIE_RX)
All power supplies must meet the specifications provided in the
Operating Conditions section. All external supply pins must be
connected to the same power supply.
Rev. B |
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Debug Access Port (DAP)
Software Add-Ins for CrossCore Embedded Studio
Debug access port (DAP) provides IEEE 1149.1 JTAG interface
support through the JTAG debug. The DAP provides an
optional instrumentation trace for both the core and system. It
provides a trace stream that conforms to MIPI System Trace
Protocol version 2 (STPv2).
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend the
capabilities and reduce development time. Add-ins include
board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation,
help, configuration dialogs, and coding examples present in
these add-ins are viewable through the CrossCore Embedded
Studio IDE once the add-in is installed.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including an integrated development environment (CrossCore® Embedded
Studio), evaluation products, emulators, and a variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers the CrossCore Embedded
Studio integrated development environment (IDE).
CrossCore Embedded Studio is based on the Eclipse framework.
Supporting most Analog Devices processor families, it is the
IDE of choice for processors, including multicore devices.
CrossCore Embedded Studio seamlessly integrates available
software add-ins to support real-time operating systems, file
systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For
more information, visit www.analog.com/cces.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
board support packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product.
Middleware Packages
Analog Devices offers middleware add-ins such as real-time
operating systems, file systems, USB stacks, and TCP/IP stacks.
For more information, see the following web pages:
• www.analog.com/ucos2
• www.analog.com/ucos3
• www.analog.com/ucfs
EZ-KIT Lite Evaluation Board
• www.analog.com/ucusbd
For processor evaluation, Analog Devices provides a wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Various EZ-Extenders® are also available, which are
daughter cards that deliver additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com.
• www.analog.com/ucusbh
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit.
This permits users to download, execute, and debug programs
for the EZ-KIT Lite system. It also supports in circuit programming of the on-board Flash device to store user specific boot
code, enabling standalone operation. With the full version of
CrossCore Embedded Studio installed (sold separately), engineers can develop software for supported EZ-KITs or any
custom system utilizing supported Analog Devices processors.
Rev. B |
Page 24 of 173 |
• www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with CrossCore Embedded Studio. For more
information visit www.analog.com.
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG test access port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The
emulator accesses the internal features of the processor via the
TAP, allowing the developer to load code, set breakpoints, and
view variables, memory, and registers.
The processor must be halted to send data and commands, but
once an operation is completed by the emulator, the DSP system
is set to run at full speed with no impact on system timing. The
emulators require the target board to include a header that supports connection of the JTAG port of the DSP to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see Analog Devices JTAG
Emulation Technical Reference (EE-68).
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ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSPSC58x/ADSP-2158x architecture and functionality. For detailed
information on the core architecture and instruction set, refer to
the SHARC+ Core Programming Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The application signal chains page in the Circuits from the Lab®
site (www.analog.com\circuits) provides the following:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Rev. B |
Page 25 of 173 |
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ADSP-SC58x/ADSP-2158x DETAILED SIGNAL DESCRIPTIONS
Table 11 provides a detailed description of each pin.
Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions
Signal Name
ACM_A[n]
ACM_T[n]
C1_FLG[n]
C2_FLG[n]
CAN_RX
CAN_TX
CNT_DG
Direction
Output
Input
InOut
InOut
Input
Output
Input
CNT_UD
Input
CNT_ZM
Input
DAI_PIN[nn]
InOut
DMC_A[nn]
DMC_BA[n]
Output
Output
DMC_CAS
Output
DMC_CK
DMC_CKE
DMC_CK
DMC_CS[n]
DMC_DQ[nn]
DMC_LDM
Output
Output
Output
Output
InOut
Output
DMC_LDQS
InOut
DMC_LDQS
DMC_ODT
InOut
Output
DMC_RAS
Output
DMC_RESET
DMC_RZQ
DMC_UDM
Output
InOut
Output
DMC_UDQS
InOut
Description
ADC Control Signals. Function varies by mode.
External Trigger n. Input for external trigger events.
SHARC+ Core 1 Flag Pin.
SHARC+ Core 2 Flag Pin.
Receive. Typically an external CAN transceiver RX output.
Transmit. Typically an external CAN transceiver TX input.
Count Down and Gate. Depending on the mode of operation, this input acts either as a count down
signal or a gate signal.
Count down—this input causes the GP counter to decrement.
Gate—stops the GP counter from incrementing or decrementing.
Count Up and Direction. Depending on the mode of operation, this input acts either as a count up
signal or a direction signal.
Count up—this input causes the GP counter to increment.
Direction—selects whether the GP counter is incrementing or decrementing.
Count Zero Marker. Input that connects to the zero marker output of a rotary device or detects the
pressing of a pushbutton.
Pin n. The digital applications interfaces (DAI0 and DAI1) connect various peripherals to any of the
DAI0_PINnn and DAI1_PINnn pins. Programs make these connections using the signal routing unit
(SRU). Both DAI units are symmetric. The shared DAIx__PIN03 and DAIx_PIN04 pins allow routing
between both DAI units.
Address n. Address bus.
Bank Address n. Defines which internal bank an activate, read, write, or precharge command is
applied to on the dynamic memory. Bank Address n also defines which mode registers (MR, EMR,
EMR2, and/or EMR3) load during the load mode register command.
Column Address Strobe. Defines the operation for external dynamic memory to perform in
conjunction with other DMC command signals. Connect to the CAS input of dynamic memory.
Clock. Outputs DCLK to external dynamic memory.
Clock Enable. Active high clock enables. Connects to the dynamic memory’s CKE input.
Clock (Complement). Complement of DMC_CK.
Chip Select n. Commands are recognized by the memory only when this signal is asserted.
Data n. Bidirectional data bus.
Data Mask for Lower Byte. Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
Data Strobe for Lower Byte. DMC_DQ07:DMC_DQ00 data strobe. Output with write data. Input with
read data. Can be single-ended or differential depending on register settings.
Data Strobe for Lower Byte (Complement). Complement of LDQS. Not used in single-ended mode.
On-Die Termination. Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured).
Row Address Strobe. Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
Reset (DDR3 Only).
External Calibration Resistor Connection.
Data Mask for Upper Byte. Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled
on both edges of the data strobe by the dynamic memory.
Data Strobe for Upper Byte. DMC_DQ15:DMC_DQ08 data strobe. Output with write data. Input with
read data. Not used in single-ended mode.
Rev. B |
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Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)
Signal Name
DMC_UDQS
DMC_VREF
DMC_WE
Direction
InOut
Input
Output
ETH_CRS
Input
ETH_MDC
ETH_MDIO
ETH_PTPAUXIN[n]
Output
InOut
Input
ETH_PTPCLKIN[n]
ETH_PTPPPS[n]
Input
Output
ETH_REFCLK
ETH_RXCLK_REFCLK
ETH_RXCTL_CRS
ETH_RXD[n]
ETH_TXCLK
ETH_TXCTL_TXEN
ETH_TXD[n]
ETH_TXEN
HADC_EOC_DOUT
Input
Input
Input
Input
Output
Output
Output
Output
Output
HADC_MUX[n]
Input
HADC_VIN[n]
HADC_VREFN
Input
Input
HADC_VREFP
Input
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK
Input
Input
Output
Input
Input
InOut
LP_CLK
InOut
LP_D[n]
MLB_CLKN
MLB_CLKP
MLB_DATN
MLB_DATP
MLB_SIGN
InOut
Input
Input
InOut
InOut
InOut
Description
Data Strobe for Upper Byte (Complement). Complement of UDQS. Not used in single-ended mode.
Voltage Reference. Externally driven to VDD_DMC/2. Applies to DMC0_VREF and DMC1_VREF pins.
Write Enable. Defines the operation for external dynamic memory to perform in conjunction with
other DMC command signals. Connect to the WE input of dynamic memory.
Carrier Sense/RMII Receive Data Valid. Multiplexed on alternate clock cycles.
CRS— asserted by the PHY when either the transmit or receive medium is not idle. Deasserted when
both are idle.
RXDV—asserted by the PHY when the data on RXDn is valid.
Management Channel Clock. Clocks the MDC input of the PHY for RMII/RGMII.
Management Channel Serial Data. Bidirectional data bus for PHY control for RMII/RGMII.
PTP Auxiliary Trigger Input. Assert this signal to take an auxiliary snapshot of the time and store it
in the auxiliary time stamp FIFO.
PTP Clock Input. Optional external PTP clock input.
PTP Pulse Per Second Output. When the advanced time stamp feature enables, this signal is asserted
based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter is
incremented.
Reference Clock. Externally supplied Ethernet clock.
RXCLK (10/100/1000) or REFCLK (10/100).
RXCTL (10/100/1000) or CRS (10/100).
Receive Data n. Receive data bus.
Transmit Clock.
TXCTL (10/100/1000) or TXEN (10/100).
Transmit Data n. Transmits data bus.
Transmit Enable. When asserted, signal indicates the data on TXDn is valid.
End of Conversion/Serial Data Out. Transitions high for one cycle of the HADC internal clock at the
end of every conversion. Alternatively, HADC serial data out can be seen by setting the appropriate
bit in HADC_CTL.
Controls to External Multiplexer. Allows additional input channels when connected to an external
multiplexer.
Analog Input at Channel n. Analog voltage inputs for digital conversion.
Ground Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
External Reference for ADC. Connect to an external voltage reference that meets data sheet
specifications.
JTAG Clock. JTAG test access port clock.
JTAG Serial Data In. JTAG test access port data input.
JTAG Serial Data Out. JTAG test access port data output.
JTAG Mode Select. JTAG test access port mode select.
JTAG Reset. JTAG test access port reset.
Acknowledge. Provides handshaking. When the link port is configured as a receiver, ACK is an output.
When the link port is configured as a transmitter, ACK is an input.
Clock. When the link port is configured as a receiver, CLK is an input. When the link port is configured
as a transmitter, CLK is an output.
Data n. Data bus. Input when receiving, output when transmitting.
Differential Clock (–).
Differential Clock (+).
Differential Data (–).
Differential Data (+).
Differential Signal (–).
Rev. B |
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Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)
Signal Name
MLB_SIGP
MLB_CLK
MLB_DAT
MLB_SIG
MLB_CLKOUT
MSI_CD
MSI_CLK
MSI_CMD
MSI_D[n]
MSI_INT
Direction
InOut
Input
InOut
InOut
Output
Input
Output
InOut
InOut
Input
PCIE_CLKM
PCIE_CLKP
PCIE_REF
PCIE_RXM
PCIE_RXP
PCIE_TXM
PCIE_TXP
PPI_CLK
PPI_D[nn]
PPI_FS1
Input
Input
InOut
Input
Input
Output
Output
InOut
InOut
InOut
PPI_FS2
InOut
PPI_FS3
InOut
PWM_AH
PWM_AL
PWM_BH
PWM_BL
PWM_CH
PWM_CL
PWM_DH
PWM_DL
PWM_SYNC
Output
Output
Output
Output
Output
Output
Output
Output
Input
PWM_TRIP[n]
P_[nn]
Input
InOut
RTC_CLKIN
RTC_XTAL
Input
Output
SINC_CLK0
SINC_D0
SINC_D1
SINC_D2
SINC_D3
Output
Input
Input
Input
Input
Description
Differential Signal (+).
Single-Ended Clock.
Single-Ended Data.
Single-Ended Signal.
Single-Ended Clock Out.
Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket.
Clock. The clock signal applied to the connected device from the MSI.
Command. Sends commands to and receives responses from the connected device.
Data n. Bidirectional data bus.
eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card interrupt output. An interrupt
may be sampled even when the MSI clock to the card is switched off.
CLK –.
CLK +.
Reference Resistor. Attach a 200 Ω, 1%, 100 ppm/C precision resistor to ground on the board.
RX –.
RX +.
TX –.
TX +.
Clock. Input in external clock mode, output in internal clock mode.
Data n. Bidirectional data bus.
Frame Sync 1 (HSYNC). Behavior depends on EPPI mode. See the “EPPI” chapter of the ADSPSC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.
Frame Sync 2 (VSYNC). Behavior depends on EPPI mode. See the “EPPI” chapter of the ADSPSC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.
Frame Sync 3 (FIELD). Behavior depends on EPPI mode. See the “EPPI” chapter of the ADSPSC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.
Channel A High Side. High-side drive signal.
Channel A Low Side. Low-side drive signal.
Channel B High Side. High-side drive signal.
Channel B Low Side. Low-side drive signal.
Channel C High Side. High-side drive signal.
Channel C Low Side. Low-side drive signal.
Channel D High Side. High-side drive signal.
Channel D Low Side. Low-side drive signal.
PWMTMR Grouped. This input is for an externally generated sync signal. If the sync signal is internally
generated, no connection is necessary.
Shutdown Input n. When asserted, the selected PWM channel outputs are shut down immediately.
Position n. General-purpose input/output. See the “GP Ports” chapter of the ADSP-SC58x/ADSP2158x SHARC+ Processor Hardware Reference for more details.
Crystal Input/External Oscillator Connection. Connect to an external clock source or crystal.
Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving
RTC_CLKIN.
Clock 0.
Data 0.
Data 1.
Data 2.
Data 3.
Rev. B |
Page 28 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)
Signal Name
SMC_ABE[n]
Direction
Output
SMC_AMS[n]
SMC_AOE
SMC_ARDY
Output
Output
Input
SMC_ARE
SMC_AWE
SMC_A[nn]
SMC_D[nn]
SPI_CLK
SPI_D2
SPI_D3
SPI_MISO
Output
Output
Output
InOut
InOut
InOut
InOut
InOut
SPI_MOSI
InOut
SPI_RDY
SPI_SEL[n]
SPI_SS
InOut
Output
Input
SPT_ACLK
InOut
SPT_AD0
InOut
SPT_AD1
InOut
SPT_AFS
InOut
SPT_ATDV
Output
SPT_BCLK
InOut
SPT_BD0
InOut
SPT_BD1
InOut
SPT_BFS
InOut
SPT_BTDV
Output
SYS_BMODE[n]
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
Input
Input
Input
Output
Description
Byte Enable n. Indicates whether the lower or upper byte of a memory is being accessed. When an
asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 = 0 and
SMC_ABE0 = 1. When an asynchronous write is made to the lower byte of a 16-bit memory,
SMC_ABE1 = 1 and SMC_ABE0 = 0.
Memory Select n. Typically connects to the chip select of a memory device.
Output Enable. Asserts at the beginning of the setup period of a read access.
Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when
further transactions may proceed.
Read Enable. Asserts at the beginning of a read access.
Write Enable. Asserts for the duration of a write access period.
Address n. Address bus.
Data n. Bidirectional data bus.
Clock. Input in slave mode, output in master mode.
Data 2. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.
Data 3. Transfers serial data in quad mode. Open-drain when ODM mode is enabled.
Master In, Slave Out. Transfers serial data. Operates in the same direction as SPI_MOSI in dual and
quad modes. Open-drain when ODM mode is enabled.
Master Out, Slave In. Transfers serial data. Operates in the same direction as SPI_MISO in dual and
quad modes. Open-drain when ODM mode is enabled.
Ready. Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n. Used in master mode to enable the desired slave.
Slave Select Input.
Slave mode—acts as the slave select input.
Master mode—optionally serves as an error detection input for the SPI when there are multiple
masters.
Channel A Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel A Frame Sync. The frame sync pulse initiates shifting of the serial data. This signal is either
generated internally or externally.
Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Channel B Clock. Data and frame sync are driven/sampled with respect to this clock. This signal can
be either internally or externally generated.
Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data or as an input to receive serial data.
Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in
multichannel transmit mode. It is asserted during enabled slots.
Boot Mode Control n. Selects the boot mode of the processor.
Clock/Crystal Input.
Clock/Crystal Input.
Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the “CGU” chapter
of the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference for more details.
Rev. B |
Page 29 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 11. ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions (Continued)
Signal Name
SYS_FAULT
Direction
InOut
SYS_FAULT
InOut
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TM_ACI[n]
TM_ACLK[n]
TM_CLK
TM_TMR[n]
TRACE_CLK
TRACE_D[nn]
TWI_SCL
TWI_SDA
UART_CTS
UART_RTS
UART_RX
Input
Output
Output
Output
Input
Input
Input
InOut
Output
Output
InOut
InOut
Input
Output
Input
UART_TX
Output
USB_CLKIN
Input
USB_DM
USB_DP
USB_ID
InOut
InOut
Input
USB_VBC
Output
USB_VBUS
USB_XTAL
InOut
Output
Description
Active High Fault Output. Indicates internal faults or senses external faults, depending on the
operating mode.
Active Low Fault Output. Indicates internal faults or senses external faults, depending on the
operating mode.
Processor Hardware Reset Control. Resets the device when asserted.
Reset Output. Indicates the device is in the reset state.
Crystal Output.
Crystal Output.
Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n. Provides an additional time base for an individual timer.
Clock. Provides an additional global time base for all GP timers.
Timer n. The main input/output signal for each timer.
Trace Clock. Clock output.
Trace Data n. Unidirectional data bus.
Serial Clock. Clock output when master, clock input when slave.
Serial Data. Receives or transmits data.
Clear to Send. Flow control signal.
Request to Send. Flow control signal.
Receive. Receives input. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
Transmit. Transmits output. Typically connects to a transceiver that meets the electrical requirements
of the device being communicated with.
Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet
specifications for frequency/tolerance information.
Data –. Bidirectional differential data line.
Data +. Bidirectional differential data line.
OTG ID. Senses whether the controller is a host or device. This signal is pulled low when an A-type
plug is sensed (signifying that the USB controller is the A device).The input is high when a B-type plug
is sensed (signifying that the USB controller is the B device).
VBUS Control. Controls an external voltage source to supply VBUS when in host mode. Can be
configured as open drain. Polarity is configurable as well.
Bus Voltage. Connects to bus voltage in host and device modes.
Crystal. Drives an external crystal. Must be left unconnected if an external clock is driving USB_CLKIN.
Rev. B |
Page 30 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
349-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown in Table 12 for the
349-ball CSP_BGA package. The columns in this table provide
the following information:
• The Signal Name column includes the signal name for
every pin and the GPIO multiplexed pin function, where
applicable.
• The Description column provides a descriptive name for
each signal.
• The Port column shows whether or not a signal is multiplexed with other signals on a general-purpose I/O port
pin.
• The Pin Name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a general-purpose
I/O pin).
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the “Digital Audio
Interface (DAI)” chapter of the ADSP-SC58x/ADSP-2158x
SHARC+ Processor Hardware Reference for complete
information on the use of the DAI and SRUs.
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions
Signal Name
ACM0_A0
ACM0_A1
ACM0_A2
ACM0_A3
ACM0_A4
ACM0_T0
C1_FLG0
C1_FLG1
C1_FLG2
C1_FLG3
C2_FLG0
C2_FLG1
C2_FLG2
C2_FLG3
CAN0_RX
CAN0_TX
CAN1_RX
CAN1_TX
CNT0_DG
CNT0_UD
CNT0_ZM
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
Description
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 External Trigger n
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
CAN0 Receive
CAN0 Transmit
CAN1 Receive
CAN1 Transmit
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 19
DAI0 Pin 20
Rev. B |
Page 31 of 173 |
Port
C
C
C
D
D
C
E
E
E
E
E
E
E
E
C
C
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
December 2018
Pin Name
PC_13
PC_14
PC_15
PD_00
PD_01
PC_12
PE_01
PE_03
PE_05
PE_07
PE_02
PE_04
PE_06
PE_08
PC_07
PC_08
PB_10
PB_09
PB_14
PB_12
PB_11
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
Description
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 19
DAI1 Pin 20
DMC0 Address 0
DMC0 Address 1
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
DMC0 Address 5
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address 0
DMC0 Bank Address 1
DMC0 Bank Address 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0 Clock Enable
DMC0 Clock (Complement)
DMC0 Chip Select 0
DMC0 Data 0
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
Rev. B |
Page 32 of 173 |
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
December 2018
Pin Name
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
ETH0_CRS
ETH0_MDC
ETH0_MDIO
ETH0_PTPAUXIN0
ETH0_PTPAUXIN1
ETH0_PTPAUXIN2
ETH0_PTPAUXIN3
ETH0_PTPCLKIN0
ETH0_PTPPPS0
ETH0_PTPPPS1
ETH0_PTPPPS2
ETH0_PTPPPS3
ETH0_RXCLK_REFCLK
ETH0_RXCTL_CRS
ETH0_RXD0
ETH0_RXD1
ETH0_RXD2
ETH0_RXD3
ETH0_TXCLK
ETH0_TXCTL_TXEN
ETH0_TXD0
ETH0_TXD1
ETH0_TXD2
ETH0_TXD3
ETH0_TXEN
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
Description
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-Die Termination
DMC0 Row Address Strobe
DMC0 Reset (DDR3 Only)
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Write Enable
ETH0 Carrier Sense/RMII Receive Data Valid
ETH0 Management Channel Clock
ETH0 Management Channel Serial Data
ETH0 PTP Auxiliary Trigger Input 0
ETH0 PTP Auxiliary Trigger Input 1
ETH0 PTP Auxiliary Trigger Input 2
ETH0 PTP Auxiliary Trigger Input 3
ETH0 PTP Clock Input 0
ETH0 PTP Pulse Per Second Output 0
ETH0 PTP Pulse Per Second Output 1
ETH0 PTP Pulse Per Second Output 2
ETH0 PTP Pulse Per Second Output 3
ETH0 RXCLK (10/100/1000) or REFCLK (10/100)
ETH0 RXCTL (10/100/1000) or CRS (10/100)
ETH0 Receive Data 0
ETH0 Receive Data 1
ETH0 Receive Data 2
ETH0 Receive Data 3
ETH0 Transmit Clock
ETH0 TXCTL (10/100/1000) or TXEN (10/100)
ETH0 Transmit Data 0
ETH0 Transmit Data 1
ETH0 Transmit Data 2
ETH0 Transmit Data 3
ETH0 Transmit Enable
HADC0 Analog Input at Channel 0
HADC0 Analog Input at Channel 1
HADC0 Analog Input at Channel 2
HADC0 Analog Input at Channel 3
HADC0 Analog Input at Channel 4
Rev. B |
Page 33 of 173 |
December 2018
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
A
A
A
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Pin Name
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
PA_07
PA_02
PA_03
PB_03
PB_04
PB_05
PB_06
PB_02
PB_01
PB_00
PA_15
PA_14
PA_06
PA_07
PA_04
PA_05
PA_08
PA_09
PA_11
PA_10
PA_00
PA_01
PA_12
PA_13
PA_10
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_ACK
LP1_CLK
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
MLB0_CLK
MLB0_DAT
MLB0_SIG
MLB0_CLKOUT
PA_00-15
PB_00-15
PC_00-15
PD_00-15
PE_00-15
PPI0_CLK
PPI0_D00
PPI0_D01
Description
HADC0 Analog Input at Channel 5
HADC0 Analog Input at Channel 6
HADC0 Analog Input at Channel 7
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
TAPC JTAG Clock
TAPC JTAG Serial Data In
TAPC JTAG Serial Data Out
TAPC JTAG Mode Select
TAPC JTAG Reset
LP0 Acknowledge
LP0 Clock
LP0 Data 0
LP0 Data 1
LP0 Data 2
LP0 Data 3
LP0 Data 4
LP0 Data 5
LP0 Data 6
LP0 Data 7
LP1 Acknowledge
LP1 Clock
LP1 Data 0
LP1 Data 1
LP1 Data 2
LP1 Data 3
LP1 Data 4
LP1 Data 5
LP1 Data 6
LP1 Data 7
MLB0 Negative Differential Clock (–)
MLB0 Positive Differential Clock (+)
MLB0 Negative Differential Data (–)
MLB0 Positive Differential Data (+)
MLB0 Negative Differential Signal (–)
MLB0 Positive Differential Signal (+)
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
MLB0 Single-Ended Clock Out
PORTA Position 00 Through Position 15
PORTB Position 00 Through Position 15
PORTC Position 00 Through Position 15
PORTD Position 00 Through Position 15
PORTE Position 00 Through Position 15
EPPI0 Clock
EPPI0 Data 0
EPPI0 Data 1
Rev. B |
Page 34 of 173 |
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
D
D
D
D
D
D
D
D
D
B
C
B
B
B
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
B
D
A
B
C
D
E
E
E
E
December 2018
Pin Name
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PD_11
PD_10
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PB_15
PC_00
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PB_04
PB_06
PB_05
PD_14
PA_00-15
PB_00-15
PC_00-15
PD_00-15
PE_00-15
PE_03
PE_12
PE_11
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
PPI0_FS1
PPI0_FS2
PPI0_FS3
PWM0_AH
PWM0_AL
PWM0_BH
PWM0_BL
PWM0_CH
PWM0_CL
PWM0_DH
PWM0_DL
PWM0_SYNC
PWM0_TRIP0
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM1_TRIP0
PWM2_CH
PWM2_CL
PWM2_DH
Description
EPPI0 Data 2
EPPI0 Data 3
EPPI0 Data 4
EPPI0 Data 5
EPPI0 Data 6
EPPI0 Data 7
EPPI0 Data 8
EPPI0 Data 9
EPPI0 Data 10
EPPI0 Data 11
EPPI0 Data 12
EPPI0 Data 13
EPPI0 Data 14
EPPI0 Data 15
EPPI0 Data 16
EPPI0 Data 17
EPPI0 Data 18
EPPI0 Data 19
EPPI0 Data 20
EPPI0 Data 21
EPPI0 Data 22
EPPI0 Data 23
EPPI0 Frame Sync 1 (HSYNC)
EPPI0 Frame Sync 2 (VSYNC)
EPPI0 Frame Sync 3 (FIELD)
PWM0 Channel A High Side
PWM0 Channel A Low Side
PWM0 Channel B High Side
PWM0 Channel B Low Side
PWM0 Channel C High Side
PWM0 Channel C Low Side
PWM0 Channel D High Side
PWM0 Channel D Low Side
PWM0 PWMTMR Grouped
PWM0 Shutdown Input 0
PWM1 Channel A High Side
PWM1 Channel A Low Side
PWM1 Channel B High Side
PWM1 Channel B Low Side
PWM1 Channel C High Side
PWM1 Channel C Low Side
PWM1 Channel D High Side
PWM1 Channel D Low Side
PWM1 PWMTMR Grouped
PWM1 Shutdown Input 0
PWM2 Channel C High Side
PWM2 Channel C Low Side
PWM2 Channel D High Side
Rev. B |
Page 35 of 173 |
Port
E
E
E
E
E
E
E
E
D
D
B
B
B
B
B
B
D
D
E
E
E
D
E
E
C
B
B
B
C
B
B
B
B
E
B
D
D
D
D
D
D
D
D
D
D
D
E
E
December 2018
Pin Name
PE_10
PE_09
PE_08
PE_07
PE_06
PE_05
PE_04
PE_00
PD_15
PD_14
PB_04
PB_05
PB_00
PB_01
PB_02
PB_03
PD_13
PD_12
PE_13
PE_14
PE_15
PD_00
PE_02
PE_01
PC_15
PB_07
PB_08
PB_06
PC_00
PB_13
PB_14
PB_11
PB_12
PE_09
PB_15
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_02
PD_15
PE_00
PE_04
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PWM2_DL
PWM2_SYNC
PWM2_TRIP0
GND
VDD_EXT
VDD_INT
SINC0_CLK0
SINC0_D0
SINC0_D1
SINC0_D2
SINC0_D3
SMC0_A01
SMC0_A02
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A13
SMC0_A14
SMC0_A15
SMC0_A16
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_A24
SMC0_A25
SMC0_ABE0
SMC0_ABE1
SMC0_AMS0
SMC0_AMS1
SMC0_AMS2
SMC0_AMS3
SMC0_AOE
SMC0_ARDY
SMC0_ARE
SMC0_AWE
SMC0_D00
SMC0_D01
Description
PWM2 Channel D Low Side
PWM2 PWMTMR Grouped
PWM2 Shutdown Input 0
Ground
External Voltage Domain
Internal Voltage Domain
SINC0 Clock 0
SINC0 Data 0
SINC0 Data 1
SINC0 Data 2
SINC0 Data 3
SMC0 Address 1
SMC0 Address 2
SMC0 Address 3
SMC0 Address 4
SMC0 Address 5
SMC0 Address 6
SMC0 Address 7
SMC0 Address 8
SMC0 Address 9
SMC0 Address 10
SMC0 Address 11
SMC0 Address 12
SMC0 Address 13
SMC0 Address 14
SMC0 Address 15
SMC0 Address 16
SMC0 Address 17
SMC0 Address 18
SMC0 Address 19
SMC0 Address 20
SMC0 Address 21
SMC0 Address 22
SMC0 Address 23
SMC0 Address 24
SMC0 Address 25
SMC0 Byte Enable 0
SMC0 Byte Enable 1
SMC0 Memory Select 0
SMC0 Memory Select 1
SMC0 Memory Select 2
SMC0 Memory Select 3
SMC0 Output Enable
SMC0 Asynchronous Ready
SMC0 Read Enable
SMC0 Write Enable
SMC0 Data 0
SMC0 Data 1
Rev. B |
Port
E
E
D
Not Muxed
Not Muxed
Not Muxed
B
A
A
B
B
B
B
B
B
D
D
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
E
E
C
E
C
C
D
B
C
B
E
E
Page 36 of 173 |
December 2018
Pin Name
PE_10
PE_05
PD_14
GND
VDD_EXT
VDD_INT
PB_01
PA_14
PA_15
PB_00
PB_04
PB_05
PB_06
PB_03
PB_02
PD_13
PD_12
PB_01
PB_00
PA_15
PA_14
PA_09
PA_08
PA_13
PA_12
PA_11
PA_07
PA_06
PA_05
PA_04
PA_01
PA_00
PA_10
PA_03
PA_02
PC_12
PE_14
PE_15
PC_15
PE_13
PC_07
PC_08
PD_01
PB_04
PC_00
PB_15
PE_12
PE_11
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
SPI0_SS
SPI1_CLK
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SS
SPI2_CLK
SPI2_D2
SPI2_D3
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SS
Description
SMC0 Data 2
SMC0 Data 3
SMC0 Data 4
SMC0 Data 5
SMC0 Data 6
SMC0 Data 7
SMC0 Data 8
SMC0 Data 9
SMC0 Data 10
SMC0 Data 11
SMC0 Data 12
SMC0 Data 13
SMC0 Data 14
SMC0 Data 15
SPI0 Clock
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Output 5
SPI0 Slave Select Output 6
SPI0 Slave Select Output 7
SPI0 Slave Select Input
SPI1 Clock
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Input
SPI2 Clock
SPI2 Data 2
SPI2 Data 3
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Input
Rev. B |
Port
E
E
E
D
D
D
B
B
B
B
B
B
B
B
C
C
C
C
C
D
C
C
E
E
E
D
E
E
E
E
C
E
E
E
E
E
C
C
C
C
C
E
C
E
E
E
E
C
Page 37 of 173 |
December 2018
Pin Name
PE_10
PE_09
PE_00
PD_15
PD_14
PD_00
PB_14
PB_13
PB_12
PB_11
PB_10
PB_09
PB_08
PB_07
PC_09
PC_10
PC_11
PC_12
PC_07
PD_01
PC_12
PC_00
PE_01
PE_02
PE_03
PD_01
PE_13
PE_14
PE_15
PE_08
PC_13
PE_07
PE_11
PE_12
PE_08
PE_11
PC_01
PC_04
PC_05
PC_02
PC_03
PE_12
PC_06
PE_03
PE_04
PE_05
PE_06
PC_06
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TM0_ACI0
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TRACE0_CLK
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
UART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
Description
Boot Mode Control n
Boot Mode Control n
Boot Mode Control n
Clock/Crystal Input
Clock/Crystal Input
Processor Clock Output
Active High Fault Output
Active Low Fault Output
Processor Hardware Reset Control
Reset Output
Crystal Output
Crystal Output
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TRACE0 Trace Clock
TRACE0 Trace Data 0
TRACE0 Trace Data 1
TRACE0 Trace Data 2
TRACE0 Trace Data 3
TRACE0 Trace Data 4
TRACE0 Trace Data 5
TRACE0 Trace Data 6
TRACE0 Trace Data 7
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send
Rev. B |
Page 38 of 173 |
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
C
B
D
C
B
D
D
B
B
C
E
B
B
B
B
B
D
D
D
D
D
D
D
D
D
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
C
C
C
E
December 2018
Pin Name
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
PC_14
PB_03
PD_13
PC_07
PB_10
PD_08
PD_09
PB_00
PB_01
PC_11
PE_09
PB_15
PB_10
PB_07
PB_08
PB_14
PD_10
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
PD_00
PC_15
PC_14
PC_13
PE_01
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 12. ADSP-SC58x/ADSP-2158x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
UART1_RTS
UART1_RX
UART1_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB0_XTAL
VDD_DMC
VDD_HADC
VDD_USB
Description
UART1 Request to Send
UART1 Receive
UART1 Transmit
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
UART2 Transmit
USB0 Clock/Crystal Input
USB0 Negative Data (–)
USB0 Positive Data (+)
USB0 OTG ID
USB0 VBUS Control
USB0 Bus Voltage
USB0 Crystal
DMC VDD
HADC/TMU VDD
USB VDD
Rev. B |
Port
E
B
B
E
E
D
D
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Page 39 of 173 |
December 2018
Pin Name
PE_02
PB_03
PB_02
PE_11
PE_10
PD_13
PD_12
USB_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB_XTAL
VDD_DMC
VDD_HADC
VDD_USB
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
GPIO MULTIPLEXING FOR THE 349-BALL CSP_BGA PACKAGE
Table 13 through Table 17 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the 349-ball
CSP_BGA package.
Table 13. Signal Multiplexing for Port A
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
Multiplexed
Function 0
ETH0_TXD0
ETH0_TXD1
ETH0_MDC
ETH0_MDIO
ETH0_RXD0
ETH0_RXD1
ETH0_RXCLK_REFCLK
ETH0_CRS
ETH0_RXD2
ETH0_RXD3
ETH0_TXEN
ETH0_TXCLK
ETH0_TXD2
ETH0_TXD3
ETH0_PTPPPS3
ETH0_PTPPPS2
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
SMC0_A21
SMC0_A20
SMC0_A24
SMC0_A23
SMC0_A19
SMC0_A18
SMC0_A17
SMC0_A16
SMC0_A12
SMC0_A11
SMC0_A22
SMC0_A15
SMC0_A14
SMC0_A13
SMC0_A10
SMC0_A09
Multiplexed
Function Input Tap
Multiplexed
Function 2
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D12
PPI0_D13
PWM0_BH
TM0_TMR3
TM0_TMR4
CAN1_TX
CAN1_RX
PWM0_DH
PWM0_DL
PWM0_CH
PWM0_CL
TM0_TMR1
Multiplexed
Function 3
SMC0_A08
SMC0_A07
SMC0_A04
SMC0_A03
SMC0_ARDY
SMC0_A01
SMC0_A02
SMC0_D15
SMC0_D14
SMC0_D13
SMC0_D12
SMC0_D11
SMC0_D10
SMC0_D09
SMC0_D08
SMC0_AWE
Multiplexed
Function Input Tap
TM0_ACLK3
TM0_ACLK4
SINC0_D0
SINC0_D1
Table 14. Signal Multiplexing for Port B
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
Multiplexed
Function 0
ETH0_PTPPPS1
ETH0_PTPPPS0
ETH0_PTPCLKIN0
ETH0_PTPAUXIN0
MLB0_CLK
MLB0_SIG
MLB0_DAT
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP1_ACK
Multiplexed
Function 1
SINC0_D2
SINC0_CLK0
UART1_TX
UART1_RX
SINC0_D3
PWM0_AH
PWM0_AL
TM0_TMR2
TM0_TMR5
PWM0_TRIP0
Rev. B |
Page 40 of 173 |
December 2018
TM0_ACI1
ETH0_PTPAUXIN1
ETH0_PTPAUXIN2
ETH0_PTPAUXIN3
TM0_ACI4
CNT0_ZM
CNT0_UD
CNT0_DG
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 15. Signal Multiplexing for Port C
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
Multiplexed
Function 0
LP1_CLK
SPI2_CLK
SPI2_MISO
SPI2_MOSI
SPI2_D2
SPI2_D3
SPI2_SEL1
CAN0_RX
CAN0_TX
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL3
UART0_TX
UART0_RX
UART0_RTS
Multiplexed
Function 1
PWM0_BL
Multiplexed
Function 2
SPI0_SEL4
SPI0_SEL1
Multiplexed
Function 3
SMC0_ARE
SMC0_AMS2
SMC0_AMS3
Multiplexed
Function Input Tap
SPI2_SS
TM0_ACI3
TM0_CLK
SPI0_RDY
SPI1_SEL1
PPI0_FS3
ACM0_T0
ACM0_A0
ACM0_A1
ACM0_A2
SMC0_A25
Multiplexed
Function 2
ACM0_A3
ACM0_A4
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TRACE0_CLK
Multiplexed
Function 3
SMC0_D07
SMC0_AOE
PPI0_D19
PPI0_D18
MLB0_CLKOUT
SMC0_A06
SMC0_A05
SMC0_D06
SMC0_D05
TM0_ACI0
SMC0_AMS0
Table 16. Signal Multiplexing for Port D
Signal Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
Multiplexed
Function 0
UART0_CTS
SPI0_SEL2
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP0_CLK
LP0_ACK
UART2_TX
UART2_RX
PPI0_D11
PPI0_D10
Multiplexed
Function 1
PPI0_D23
PWM1_TRIP0
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM2_TRIP0
PWM2_CH
Rev. B |
Page 41 of 173 |
December 2018
Multiplexed
Function Input Tap
SPI0_SS
TM0_ACLK1
TM0_ACLK2
TM0_ACI2
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 17. Signal Multiplexing for Port E
Signal Name
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
Multiplexed
Function 0
PPI0_D09
PPI0_FS2
PPI0_FS1
PPI0_CLK
PPI0_D08
PPI0_D07
PPI0_D06
PPI0_D05
PPI0_D04
PPI0_D03
PPI0_D02
PPI0_D01
PPI0_D00
SPI1_CLK
SPI1_MISO
SPI1_MOSI
Multiplexed
Function 1
PWM2_CL
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
PWM2_DH
PWM2_SYNC
SPI1_SEL5
PWM0_SYNC
PWM2_DL
SPI1_SEL3
SPI1_SEL4
Multiplexed
Function 2
UART1_CTS
UART1_RTS
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI1_SEL2
SPI1_RDY
TM0_TMR0
UART2_RTS
UART2_CTS
SPI2_RDY
PPI0_D20
PPI0_D21
PPI0_D22
Table 18 shows the internal timer signal routing. This table
applies to both the 349-ball and 529-ball CSP_BGA packages.
Table 18. Internal Timer Signal Routing
Timer Input Signal
TM0_ACLK0
TM0_ACI5
TM0_ACLK5
TM0_ACI6
TM0_ACLK6
TM0_ACI7
TM0_ACLK7
Internal Source
SYS_CLKIN1
DAI0_CRS_PB04_O
DAI0_CRS_PB03_O
DAI1_CRS_PB04_O
DAI1_CRS_PB03_O
CNT0_TO
SYS_CLKIN0
Rev. B |
Page 42 of 173 |
December 2018
Multiplexed
Function 3
SMC0_D04
C1_FLG0
C2_FLG0
C1_FLG1
C2_FLG1
C1_FLG2
C2_FLG2
C1_FLG3
C2_FLG3
SMC0_D03
SMC0_D02
SMC0_D01
SMC0_D00
SMC0_AMS1
SMC0_ABE0
SMC0_ABE1
Multiplexed
Function Input Tap
SPI1_SS
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
529-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processor pin definitions are shown Table 19 for the
529-ball CSP_BGA package. The columns in this table provide
the following information:
• The Signal Name column includes the signal name for
every pin and the GPIO multiplexed pin function, where
applicable.
• The Description column provides a descriptive name for
each signal.
• The Port column shows whether or not a signal is multiplexed with other signals on a general-purpose I/O port
pin.
• The Pin Name column identifies the name of the package
pin (at power on reset) on which the signal is located (if a
single function pin) or is multiplexed (if a general-purpose
I/O pin).
• The DAI pins and their associated signal routing units
(SRUs) connect inputs and outputs of the DAI peripherals
(SPORT, ASRC, S/PDIF, and PCG). See the “Digital Audio
Interface (DAI)” chapter of the ADSP-SC58x/ADSP-2158x
SHARC+ Processor Hardware Reference for complete
information on the use of the DAIs and SRUs.
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions
Signal Name
ACM0_A0
ACM0_A1
ACM0_A2
ACM0_A3
ACM0_A4
ACM0_T0
C1_FLG0
C1_FLG1
C1_FLG2
C1_FLG3
C2_FLG0
C2_FLG1
C2_FLG2
C2_FLG3
CAN0_RX
CAN0_TX
CAN1_RX
CAN1_TX
CNT0_DG
CNT0_UD
CNT0_ZM
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
Description
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 ADC Control Signals
ACM0 External Trigger n
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 1 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
SHARC Core 2 Flag Pin
CAN0 Receive
CAN0 Transmit
CAN1 Receive
CAN1 Transmit
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DAI0 Pin 1
DAI0 Pin 2
DAI0 Pin 3
DAI0 Pin 4
DAI0 Pin 5
DAI0 Pin 6
DAI0 Pin 7
DAI0 Pin 8
DAI0 Pin 9
DAI0 Pin 10
DAI0 Pin 11
DAI0 Pin 12
DAI0 Pin 13
DAI0 Pin 14
Rev. B |
Page 43 of 173 |
Port
C
C
C
D
D
C
E
E
E
E
E
E
E
E
C
C
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
December 2018
Pin Name
PC_13
PC_14
PC_15
PD_00
PD_01
PC_12
PE_01
PE_03
PE_05
PE_07
PE_02
PE_04
PE_06
PE_08
PC_07
PC_08
PB_10
PB_09
PB_14
PB_12
PB_11
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
Description
DAI0 Pin 15
DAI0 Pin 16
DAI0 Pin 17
DAI0 Pin 18
DAI0 Pin 19
DAI0 Pin 20
DAI1 Pin 1
DAI1 Pin 2
DAI1 Pin 3
DAI1 Pin 4
DAI1 Pin 5
DAI1 Pin 6
DAI1 Pin 7
DAI1 Pin 8
DAI1 Pin 9
DAI1 Pin 10
DAI1 Pin 11
DAI1 Pin 12
DAI1 Pin 13
DAI1 Pin 14
DAI1 Pin 15
DAI1 Pin 16
DAI1 Pin 17
DAI1 Pin 18
DAI1 Pin 19
DAI1 Pin 20
DMC0 Address 0
DMC0 Address 1
DMC0 Address 2
DMC0 Address 3
DMC0 Address 4
DMC0 Address 5
DMC0 Address 6
DMC0 Address 7
DMC0 Address 8
DMC0 Address 9
DMC0 Address 10
DMC0 Address 11
DMC0 Address 12
DMC0 Address 13
DMC0 Address 14
DMC0 Address 15
DMC0 Bank Address 0
DMC0 Bank Address 1
DMC0 Bank Address 2
DMC0 Column Address Strobe
DMC0 Clock
DMC0 Clock Enable
Rev. B |
Page 44 of 173 |
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
December 2018
Pin Name
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
DMC1_A00
DMC1_A01
DMC1_A02
DMC1_A03
DMC1_A04
DMC1_A05
DMC1_A06
DMC1_A07
DMC1_A08
DMC1_A09
DMC1_A10
DMC1_A11
DMC1_A12
DMC1_A13
DMC1_A14
DMC1_A15
DMC1_BA0
DMC1_BA1
Description
DMC0 Clock (Complement)
DMC0 Chip Select 0
DMC0 Data 0
DMC0 Data 1
DMC0 Data 2
DMC0 Data 3
DMC0 Data 4
DMC0 Data 5
DMC0 Data 6
DMC0 Data 7
DMC0 Data 8
DMC0 Data 9
DMC0 Data 10
DMC0 Data 11
DMC0 Data 12
DMC0 Data 13
DMC0 Data 14
DMC0 Data 15
DMC0 Data Mask for Lower Byte
DMC0 Data Strobe for Lower Byte
DMC0 Data Strobe for Lower Byte (Complement)
DMC0 On-Die Termination
DMC0 Row Address Strobe
DMC0 Reset (DDR3 Only)
DMC0 External Calibration Resistor Connection
DMC0 Data Mask for Upper Byte
DMC0 Data Strobe for Upper Byte
DMC0 Data Strobe for Upper Byte (Complement)
DMC0 Voltage Reference
DMC0 Write Enable
DMC1 Address 0
DMC1 Address 1
DMC1 Address 2
DMC1 Address 3
DMC1 Address 4
DMC1 Address 5
DMC1 Address 6
DMC1 Address 7
DMC1 Address 8
DMC1 Address 9
DMC1 Address 10
DMC1 Address 11
DMC1 Address 12
DMC1 Address 13
DMC1 Address 14
DMC1 Address 15
DMC1 Bank Address 0
DMC1 Bank Address 1
Rev. B |
Page 45 of 173 |
December 2018
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Pin Name
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
DMC1_A00
DMC1_A01
DMC1_A02
DMC1_A03
DMC1_A04
DMC1_A05
DMC1_A06
DMC1_A07
DMC1_A08
DMC1_A09
DMC1_A10
DMC1_A11
DMC1_A12
DMC1_A13
DMC1_A14
DMC1_A15
DMC1_BA0
DMC1_BA1
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC1_BA2
DMC1_CAS
DMC1_CK
DMC1_CKE
DMC1_CK
DMC1_CS0
DMC1_DQ00
DMC1_DQ01
DMC1_DQ02
DMC1_DQ03
DMC1_DQ04
DMC1_DQ05
DMC1_DQ06
DMC1_DQ07
DMC1_DQ08
DMC1_DQ09
DMC1_DQ10
DMC1_DQ11
DMC1_DQ12
DMC1_DQ13
DMC1_DQ14
DMC1_DQ15
DMC1_LDM
DMC1_LDQS
DMC1_LDQS
DMC1_ODT
DMC1_RAS
DMC1_RESET
DMC1_RZQ
DMC1_UDM
DMC1_UDQS
DMC1_UDQS
DMC1_VREF
DMC1_WE
ETH0_CRS
ETH0_MDC
ETH0_MDIO
ETH0_PTPAUXIN0
ETH0_PTPAUXIN1
ETH0_PTPAUXIN2
ETH0_PTPAUXIN3
ETH0_PTPCLKIN0
ETH0_PTPPPS0
ETH0_PTPPPS1
ETH0_PTPPPS2
ETH0_PTPPPS3
ETH0_RXCLK_REFCLK
ETH0_RXCTL_CRS
Description
DMC1 Bank Address 2
DMC1 Column Address Strobe
DMC1 Clock
DMC1 Clock Enable
DMC1 Clock (Complement)
DMC1 Chip Select 0
DMC1 Data 0
DMC1 Data 1
DMC1 Data 2
DMC1 Data 3
DMC1 Data 4
DMC1 Data 5
DMC1 Data 6
DMC1 Data 7
DMC1 Data 8
DMC1 Data 9
DMC1 Data 10
DMC1 Data 11
DMC1 Data 12
DMC1 Data 13
DMC1 Data 14
DMC1 Data 15
DMC1 Data Mask for Lower Byte
DMC1 Data Strobe for Lower Byte
DMC1 Data Strobe for Lower Byte (Complement)
DMC1 On-Die Termination
DMC1 Row Address Strobe
DMC1 Reset (DDR3 Only)
DMC1 External Calibration Resistor Connection
DMC1 Data Mask for Upper Byte
DMC1 Data Strobe for Upper Byte
DMC1 Data Strobe for Upper Byte (Complement)
DMC1 Voltage Reference
DMC1 Write Enable
ETH0 Carrier Sense/RMII Receive Data Valid
ETH0 Management Channel Clock
ETH0 Management Channel Serial Data
ETH0 PTP Auxiliary Trigger Input 0
ETH0 PTP Auxiliary Trigger Input 1
ETH0 PTP Auxiliary Trigger Input 2
ETH0 PTP Auxiliary Trigger Input 3
ETH0 PTP Clock Input 0
ETH0 PTP Pulse-Per-Second Output 0
ETH0 PTP Pulse-Per-Second Output 1
ETH0 PTP Pulse-Per-Second Output 2
ETH0 PTP Pulse-Per-Second Output 3
ETH0 RXCLK (10/100/1000) or REFCLK (10/100)
ETH0 RXCTL (10/100/1000) or CRS (10/100)
Rev. B |
Page 46 of 173 |
December 2018
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
A
A
A
B
B
B
B
B
B
B
A
A
A
A
Pin Name
DMC1_BA2
DMC1_CAS
DMC1_CK
DMC1_CKE
DMC1_CK
DMC1_CS0
DMC1_DQ00
DMC1_DQ01
DMC1_DQ02
DMC1_DQ03
DMC1_DQ04
DMC1_DQ05
DMC1_DQ06
DMC1_DQ07
DMC1_DQ08
DMC1_DQ09
DMC1_DQ10
DMC1_DQ11
DMC1_DQ12
DMC1_DQ13
DMC1_DQ14
DMC1_DQ15
DMC1_LDM
DMC1_LDQS
DMC1_LDQS
DMC1_ODT
DMC1_RAS
DMC1_RESET
DMC1_RZQ
DMC1_UDM
DMC1_UDQS
DMC1_UDQS
DMC1_VREF
DMC1_WE
PA_07
PA_02
PA_03
PB_03
PB_04
PB_05
PB_06
PB_02
PB_01
PB_00
PA_15
PA_14
PA_06
PA_07
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
ETH0_RXD0
ETH0_RXD1
ETH0_RXD2
ETH0_RXD3
ETH0_TXCLK
ETH0_TXCTL_TXEN
ETH0_TXD0
ETH0_TXD1
ETH0_TXD2
ETH0_TXD3
ETH0_TXEN
ETH1_CRS
ETH1_MDC
ETH1_MDIO
ETH1_REFCLK
ETH1_RXD0
ETH1_RXD1
ETH1_TXD0
ETH1_TXD1
ETH1_TXEN
HADC0_EOC_DOUT
HADC0_MUX0
HADC0_MUX1
HADC0_MUX2
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
Description
ETH0 Receive Data 0
ETH0 Receive Data 1
ETH0 Receive Data 2
ETH0 Receive Data 3
ETH0 Transmit Clock
ETH0 TXCTL (10/100/1000) or TXEN (10/100)
ETH0 Transmit Data 0
ETH0 Transmit Data 1
ETH0 Transmit Data 2
ETH0 Transmit Data 3
ETH0 Transmit Enable
ETH1 Carrier Sense/RMII Receive Data Valid
ETH1 Management Channel Clock
ETH1 Management Channel Serial Data
ETH1 Reference Clock
ETH1 Receive Data 0
ETH1 Receive Data 1
ETH1 Transmit Data 0
ETH1 Transmit Data 1
ETH1 Transmit Enable
HADC0 End of Conversion/Serial Data Out
HADC0 Controls to External Multiplexer
HADC0 Controls to External Multiplexer
HADC0 Controls to External Multiplexer
HADC0 Analog Input at Channel 0
HADC0 Analog Input at Channel 1
HADC0 Analog Input at Channel 2
HADC0 Analog Input at Channel 3
HADC0 Analog Input at Channel 4
HADC0 Analog Input at Channel 5
HADC0 Analog Input at Channel 6
HADC0 Analog Input at Channel 7
HADC0 Ground Reference for ADC
HADC0 External Reference for ADC
TAPC JTAG Clock
TAPC JTAG Serial Data In
TAPC JTAG Serial Data Out
TAPC JTAG Mode Select
TAPC JTAG Reset
LP0 Acknowledge
LP0 Clock
LP0 Data 0
LP0 Data 1
LP0 Data 2
LP0 Data 3
LP0 Data 4
LP0 Data 5
LP0 Data 6
Rev. B |
Page 47 of 173 |
Port
A
A
A
A
A
A
A
A
A
A
A
F
F
F
G
G
G
G
G
G
F
F
F
F
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
D
D
D
D
D
D
D
D
December 2018
Pin Name
PA_04
PA_05
PA_08
PA_09
PA_11
PA_10
PA_00
PA_01
PA_12
PA_13
PA_10
PF_13
PF_14
PF_15
PG_00
PG_04
PG_05
PG_02
PG_03
PG_01
PF_02
PF_05
PF_04
PF_03
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PD_11
PD_10
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
LP0_D7
LP1_ACK
LP1_CLK
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
MLB0_CLK
MLB0_DAT
MLB0_SIG
MLB0_CLKOUT
MSI0_CD
MSI0_CLK
MSI0_CMD
MSI0_D0
MSI0_D1
MSI0_D2
MSI0_D3
MSI0_D4
MSI0_D5
MSI0_D6
MSI0_D7
MSI0_INT
PA_00-15
PB_00-15
PCIE0_CLKM
PCIE0_CLKP
PCIE0_REF
PCIE0_RXM
PCIE0_RXP
PCIE0_TXM
PCIE0_TXP
PC_00-15
PD_00-15
PE_00-15
PF_00-15
PG_00-5
PPI0_CLK
Description
LP0 Data 7
LP1 Acknowledge
LP1 Clock
LP1 Data 0
LP1 Data 1
LP1 Data 2
LP1 Data 3
LP1 Data 4
LP1 Data 5
LP1 Data 6
LP1 Data 7
MLB0 Differential Clock (–)
MLB0 Differential Clock (+)
MLB0 Differential Data (–)
MLB0 Differential Data (+)
MLB0 Differential Signal (–)
MLB0 Differential Signal (+)
MLB0 Single-Ended Clock
MLB0 Single-Ended Data
MLB0 Single-Ended Signal
MLB0 Single-Ended Clock Out
MSI0 Card Detect
MSI0 Clock
MSI0 Command
MSI0 Data 0
MSI0 Data 1
MSI0 Data 2
MSI0 Data 3
MSI0 Data 4
MSI0 Data 5
MSI0 Data 6
MSI0 Data 7
MSI0 eSDIO Interrupt Input
PORTA Position 00 Through Position 15
PORTB Position 00 Through Position 15
PCIE0 CLK −
PCIE0 CLK +
PCIE0 Reference
PCIE0 RX −
PCIE0 RX +
PCIE0 TX −
PCIE0 TX +
PORTC Position 00 Through Position 15
PORTD Position 00 Through Position 15
PORTE Position 00 Through Position 15
PORTF Position 00 Through Position 15
PORTG Position 00 Through Position 5
EPPI0 Clock
Rev. B |
Page 48 of 173 |
Port
D
B
C
B
B
B
B
B
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
B
D
F
F
F
F
F
F
F
F
F
F
F
F
A
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
C
D
E
F
G
E
December 2018
Pin Name
PD_09
PB_15
PC_00
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PB_04
PB_06
PB_05
PD_14
PF_12
PF_11
PF_10
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_13
PA_00-15
PB_00-15
PCIE0_CLKM
PCIE0_CLKP
PCIE0_REF
PCIE0_RXM
PCIE0_RXP
PCIE0_TXM
PCIE0_TXP
PC_00-15
PD_00-15
PE_00-15
PF_00-15
PG_00-5
PE_03
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
PPI0_FS1
PPI0_FS2
PPI0_FS3
PWM0_AH
PWM0_AL
PWM0_BH
PWM0_BL
PWM0_CH
PWM0_CL
PWM0_DH
PWM0_DL
PWM0_SYNC
PWM0_TRIP0
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM1_TRIP0
PWM2_AH
Description
EPPI0 Data 0
EPPI0 Data 1
EPPI0 Data 2
EPPI0 Data 3
EPPI0 Data 4
EPPI0 Data 5
EPPI0 Data 6
EPPI0 Data 7
EPPI0 Data 8
EPPI0 Data 9
EPPI0 Data 10
EPPI0 Data 11
EPPI0 Data 12
EPPI0 Data 13
EPPI0 Data 14
EPPI0 Data 15
EPPI0 Data 16
EPPI0 Data 17
EPPI0 Data 18
EPPI0 Data 19
EPPI0 Data 20
EPPI0 Data 21
EPPI0 Data 22
EPPI0 Data 23
EPPI0 Frame Sync 1 (HSYNC)
EPPI0 Frame Sync 2 (VSYNC)
EPPI0 Frame Sync 3 (FIELD)
PWM0 Channel A High Side
PWM0 Channel A Low Side
PWM0 Channel B High Side
PWM0 Channel B Low Side
PWM0 Channel C High Side
PWM0 Channel C Low Side
PWM0 Channel D High Side
PWM0 Channel D Low Side
PWM0 PWMTMR Grouped
PWM0 Shutdown Input 0
PWM1 Channel A High Side
PWM1 Channel A Low Side
PWM1 Channel B High Side
PWM1 Channel B Low Side
PWM1 Channel C High Side
PWM1 Channel C Low Side
PWM1 Channel D High Side
PWM1 Channel D Low Side
PWM1 PWMTMR Grouped
PWM1 Shutdown Input 0
PWM2 Channel A High Side
Rev. B |
Port
E
E
E
E
E
E
E
E
E
E
D
D
B
B
B
B
B
B
D
D
E
E
E
D
E
E
C
B
B
B
C
B
B
B
B
E
B
D
D
D
D
D
D
D
D
D
D
F
Page 49 of 173 |
December 2018
Pin Name
PE_12
PE_11
PE_10
PE_09
PE_08
PE_07
PE_06
PE_05
PE_04
PE_00
PD_15
PD_14
PB_04
PB_05
PB_00
PB_01
PB_02
PB_03
PD_13
PD_12
PE_13
PE_14
PE_15
PD_00
PE_02
PE_01
PC_15
PB_07
PB_08
PB_06
PC_00
PB_13
PB_14
PB_11
PB_12
PE_09
PB_15
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_02
PF_07
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PWM2_AL
PWM2_BH
PWM2_BL
PWM2_CH
PWM2_CL
PWM2_DH
PWM2_DL
PWM2_SYNC
PWM2_TRIP0
GND
VDD_EXT
VDD_INT
RTC0_CLKIN
RTC0_XTAL
SINC0_CLK0
SINC0_D0
SINC0_D1
SINC0_D2
SINC0_D3
SMC0_A01
SMC0_A02
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A13
SMC0_A14
SMC0_A15
SMC0_A16
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_A24
SMC0_A25
SMC0_ABE0
SMC0_ABE1
SMC0_AMS0
SMC0_AMS1
Description
PWM2 Channel A Low Side
PWM2 Channel B High Side
PWM2 Channel B Low Side
PWM2 Channel C High Side
PWM2 Channel C Low Side
PWM2 Channel D High Side
PWM2 Channel D Low Side
PWM2 PWMTMR Grouped
PWM2 Shutdown Input 0
Ground
External Voltage Domain
Internal Voltage Domain
RTC0 Crystal Input/External Oscillator Connection
RTC0 Crystal Output
SINC0 Clock 0
SINC0 Data 0
SINC0 Data 1
SINC0 Data 2
SINC0 Data 3
SMC0 Address 1
SMC0 Address 2
SMC0 Address 3
SMC0 Address 4
SMC0 Address 5
SMC0 Address 6
SMC0 Address 7
SMC0 Address 8
SMC0 Address 9
SMC0 Address 10
SMC0 Address 11
SMC0 Address 12
SMC0 Address 13
SMC0 Address 14
SMC0 Address 15
SMC0 Address 16
SMC0 Address 17
SMC0 Address 18
SMC0 Address 19
SMC0 Address 20
SMC0 Address 21
SMC0 Address 22
SMC0 Address 23
SMC0 Address 24
SMC0 Address 25
SMC0 Byte Enable 0
SMC0 Byte Enable 1
SMC0 Memory Select 0
SMC0 Memory Select 1
Rev. B |
Page 50 of 173 |
December 2018
Port
F
F
F
D
E
E
E
E
D
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
A
A
B
B
B
B
B
B
D
D
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
C
E
E
C
E
Pin Name
PF_06
PF_09
PF_08
PD_15
PE_00
PE_04
PE_10
PE_05
PD_14
GND
VDD_EXT
VDD_INT
RTC0_CLKIN
RTC0_XTAL
PB_01
PA_14
PA_15
PB_00
PB_04
PB_05
PB_06
PB_03
PB_02
PD_13
PD_12
PB_01
PB_00
PA_15
PA_14
PA_09
PA_08
PA_13
PA_12
PA_11
PA_07
PA_06
PA_05
PA_04
PA_01
PA_00
PA_10
PA_03
PA_02
PC_12
PE_14
PE_15
PC_15
PE_13
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SMC0_AMS2
SMC0_AMS3
SMC0_AOE
SMC0_ARDY
SMC0_ARE
SMC0_AWE
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
SPI0_SS
SPI1_CLK
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPI2_CLK
SPI2_D2
Description
SMC0 Memory Select 2
SMC0 Memory Select 3
SMC0 Output Enable
SMC0 Asynchronous Ready
SMC0 Read Enable
SMC0 Write Enable
SMC0 Data 0
SMC0 Data 1
SMC0 Data 2
SMC0 Data 3
SMC0 Data 4
SMC0 Data 5
SMC0 Data 6
SMC0 Data 7
SMC0 Data 8
SMC0 Data 9
SMC0 Data 10
SMC0 Data 11
SMC0 Data 12
SMC0 Data 13
SMC0 Data 14
SMC0 Data 15
SPI0 Clock
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Output 5
SPI0 Slave Select Output 6
SPI0 Slave Select Output 7
SPI0 Slave Select Input
SPI1 Clock
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPI2 Clock
SPI2 Data 2
Rev. B |
Port
C
C
D
B
C
B
E
E
E
E
E
D
D
D
B
B
B
B
B
B
B
B
C
C
C
C
C
D
C
C
E
E
E
D
E
E
E
E
C
E
E
E
E
F
F
E
C
C
Page 51 of 173 |
December 2018
Pin Name
PC_07
PC_08
PD_01
PB_04
PC_00
PB_15
PE_12
PE_11
PE_10
PE_09
PE_00
PD_15
PD_14
PD_00
PB_14
PB_13
PB_12
PB_11
PB_10
PB_09
PB_08
PB_07
PC_09
PC_10
PC_11
PC_12
PC_07
PD_01
PC_12
PC_00
PE_01
PE_02
PE_03
PD_01
PE_13
PE_14
PE_15
PE_08
PC_13
PE_07
PE_11
PE_12
PE_08
PF_00
PF_01
PE_11
PC_01
PC_04
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SPI2_D3
SPI2_MISO
SPI2_MOSI
SPI2_RDY
SPI2_SEL1
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI2_SS
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TM0_ACI0
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TM0_TMR6
TM0_TMR7
TRACE0_CLK
TRACE0_CLK
TRACE0_D00
TRACE0_D00
TRACE0_D01
TRACE0_D01
TRACE0_D02
TRACE0_D02
Description
SPI2 Data 3
SPI2 Master In, Slave Out
SPI2 Master Out, Slave In
SPI2 Ready
SPI2 Slave Select Output 1
SPI2 Slave Select Output 2
SPI2 Slave Select Output 3
SPI2 Slave Select Output 4
SPI2 Slave Select Output 5
SPI2 Slave Select Input
Boot Mode Control 0
Boot Mode Control 1
Boot Mode Control 2
Clock/Crystal Input
Clock/Crystal Input
Processor Clock Output
Active High Fault Output
Active Low Fault Output
Processor Hardware Reset Control
Reset Output
Crystal Output
Crystal Output
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Clock
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TIMER0 Timer 6
TIMER0 Timer 7
TRACE0 Trace Clock (First Instance)
TRACE0 Trace Clock (Second Instance)
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 0 (Second Instance)
TRACE0 Trace Data 1 (First Instance)
TRACE0 Trace Data (Second Instance)
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 2 (Second Instance)
Rev. B |
Page 52 of 173 |
Port
C
C
C
E
C
E
E
E
E
C
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
C
B
D
C
B
D
D
B
B
C
E
B
B
B
B
B
F
F
G
D
F
D
D
F
F
D
December 2018
Pin Name
PC_05
PC_02
PC_03
PE_12
PC_06
PE_03
PE_04
PE_05
PE_06
PC_06
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
PC_14
PB_03
PD_13
PC_07
PB_10
PD_08
PD_09
PB_00
PB_01
PC_11
PE_09
PB_15
PB_10
PB_07
PB_08
PB_14
PF_00
PF_01
PG_00
PD_10
PF_13
PD_02
PD_03
PF_14
PF_15
PD_04
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
TRACE0_D03
TRACE0_D03
TRACE0_D04
TRACE0_D04
TRACE0_D05
TRACE0_D05
TRACE0_D06
TRACE0_D06
TRACE0_D07
TRACE0_D07
TRACE0_D08
TRACE0_D09
TRACE0_D10
TRACE0_D11
TRACE0_D12
TRACE0_D13
TRACE0_D14
TRACE0_D15
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
UART0_CTS
UART0_RTS
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX
UART2_CTS
UART2_RTS
UART2_RX
UART2_TX
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB0_XTAL
USB1_DM
USB1_DP
USB1_VBUS
VDD_DMC
VDD_HADC
Description
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 3 (Second Instance)
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 4 (Second Instance)
TRACE0 Trace Data 5 (First Instance)
TRACE0 Trace Data (Second Instance)
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 6 (Second Instance)
TRACE0 Trace Data (First Instance)
TRACE0 Trace Data 7 (Second Instance)
TRACE0 Trace Data 8
TRACE0 Trace Data 9
TRACE0 Trace Data 10
TRACE0 Trace Data 11
TRACE0 Trace Data 12
TRACE0 Trace Data 13
TRACE0 Trace Data 14
TRACE0 Trace Data 15
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
TWI2 Serial Clock
TWI2 Serial Data
UART0 Clear to Send
UART0 Request to Send
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1 Transmit
UART2 Clear to Send
UART2 Request to Send
UART2 Receive
UART2 Transmit
USB0 Clock/Crystal Input
USB0 Data −
USB0 Data +
USB0 OTG ID
USB0 VBUS Control
USB0 Bus Voltage
USB0 Crystal
USB1 Data −
USB1 Data +
USB1 Bus Voltage
DMC VDD
HADC/TMU VDD
Rev. B |
Page 53 of 173 |
Port
G
D
G
D
D
G
G
D
G
D
F
F
F
G
G
G
G
G
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
C
C
C
E
E
B
B
E
E
D
D
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
December 2018
Pin Name
PG_01
PD_05
PG_02
PD_06
PD_07
PG_03
PG_04
PD_08
PG_05
PD_09
PF_13
PF_14
PF_15
PG_01
PG_02
PG_03
PG_04
PG_05
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
PD_00
PC_15
PC_14
PC_13
PE_01
PE_02
PB_03
PB_02
PE_11
PE_10
PD_13
PD_12
USB_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB_XTAL
USB1_DM
USB1_DP
USB1_VBUS
VDD_DMC
VDD_HADC
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 19. ADSP-SC58x/ADSP-2158x 529-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
VDD_PCIE
VDD_PCIE_RX
VDD_PCIE_TX
VDD_RTC
VDD_USB
Description
PCIE Supply Voltage
PCIE RX Supply Voltage
PCIE TX Supply Voltage
RTC VDD
USB VDD
Rev. B |
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Page 54 of 173 |
December 2018
Pin Name
VDD_PCIE
VDD_PCIE_RX
VDD_PCIE_TX
VDD_RTC
VDD_USB
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
GPIO MULTIPLEXING FOR THE 529-BALL CSP_BGA PACKAGE
Table 20 through Table 26 identify the pin functions that are
multiplexed on the general-purpose I/O pins of the 529-ball
CSP_BGA package.
Table 20. Signal Multiplexing for Port A
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
Multiplexed
Function 0
ETH0_TXD0
ETH0_TXD1
ETH0_MDC
ETH0_MDIO
ETH0_RXD0
ETH0_RXD1
ETH0_RXCLK_REFCLK
ETH0_CRS
ETH0_RXD2
ETH0_RXD3
ETH0_TXEN
ETH0_TXCLK
ETH0_TXD2
ETH0_TXD3
ETH0_PTPPPS3
ETH0_PTPPPS2
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
SMC0_A21
SMC0_A20
SMC0_A24
SMC0_A23
SMC0_A19
SMC0_A18
SMC0_A17
SMC0_A16
SMC0_A12
SMC0_A11
SMC0_A22
SMC0_A15
SMC0_A14
SMC0_A13
SMC0_A10
SMC0_A09
Multiplexed
Function Input Tap
Multiplexed
Function 2
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D12
PPI0_D13
PWM0_BH
TM0_TMR3
TM0_TMR4
CAN1_TX
CAN1_RX
PWM0_DH
PWM0_DL
PWM0_CH
PWM0_CL
TM0_TMR1
Multiplexed
Function 3
SMC0_A08
SMC0_A07
SMC0_A04
SMC0_A03
SMC0_ARDY
SMC0_A01
SMC0_A02
SMC0_D15
SMC0_D14
SMC0_D13
SMC0_D12
SMC0_D11
SMC0_D10
SMC0_D09
SMC0_D08
SMC0_AWE
Multiplexed
Function Input Tap
TM0_ACLK3
TM0_ACLK4
SINC0_D0
SINC0_D1
Table 21. Signal Multiplexing for Port B
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
Multiplexed
Function 0
ETH0_PTPPPS1
ETH0_PTPPPS0
ETH0_PTPCLKIN0
ETH0_PTPAUXIN0
MLB0_CLK
MLB0_SIG
MLB0_DAT
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP1_ACK
Multiplexed
Function 1
SINC0_D2
SINC0_CLK0
UART1_TX
UART1_RX
SINC0_D3
PWM0_AH
PWM0_AL
TM0_TMR2
TM0_TMR5
PWM0_TRIP0
Rev. B |
Page 55 of 173 |
December 2018
TM0_ACI1
ETH0_PTPAUXIN1
ETH0_PTPAUXIN2
ETH0_PTPAUXIN3
TM0_ACI4
CNT0_ZM
CNT0_UD
CNT0_DG
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 22. Signal Multiplexing for Port C
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
Multiplexed
Function 0
LP1_CLK
SPI2_CLK
SPI2_MISO
SPI2_MOSI
SPI2_D2
SPI2_D3
SPI2_SEL1
CAN0_RX
CAN0_TX
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_SEL3
UART0_TX
UART0_RX
UART0_RTS
Multiplexed
Function 1
PWM0_BL
Multiplexed
Function 2
SPI0_SEL4
SPI0_SEL1
Multiplexed
Function 3
SMC0_ARE
SMC0_AMS2
SMC0_AMS3
Multiplexed
Function Input Tap
SPI2_SS
TM0_ACI3
TM0_CLK
SPI0_RDY
SPI1_SEL1
PPI0_FS3
ACM0_T0
ACM0_A0
ACM0_A1
ACM0_A2
SMC0_A25
Multiplexed
Function 2
ACM0_A3
ACM0_A4
TRACE0_D00
TRACE0_D01
TRACE0_D02
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
TRACE0_CLK
Multiplexed
Function 3
SMC0_D07
SMC0_AOE
PPI0_D19
PPI0_D18
MLB0_CLKOUT
SMC0_A06
SMC0_A05
SMC0_D06
SMC0_D05
Multiplexed
Function 2
Multiplexed
Function 3
SMC0_D04
C1_FLG0
C2_FLG0
TM0_ACI0
SMC0_AMS0
Table 23. Signal Multiplexing for Port D
Signal Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
Multiplexed
Function 0
UART0_CTS
SPI0_SEL2
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP0_CLK
LP0_ACK
UART2_TX
UART2_RX
PPI0_D11
PPI0_D10
Multiplexed
Function 1
PPI0_D23
PWM1_TRIP0
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM2_TRIP0
PWM2_CH
Multiplexed
Function Input Tap
SPI0_SS
TM0_ACLK1
TM0_ACLK2
TM0_ACI2
Table 24. Signal Multiplexing for Port E
Signal Name
PE_00
PE_01
PE_02
Multiplexed
Function 0
PPI0_D09
PPI0_FS2
PPI0_FS1
Multiplexed
Function 1
PWM2_CL
SPI0_SEL5
SPI0_SEL6
Rev. B |
UART1_CTS
UART1_RTS
Page 56 of 173 |
December 2018
Multiplexed
Function Input Tap
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 24. Signal Multiplexing for Port E (Continued)
Signal Name
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
Multiplexed
Function 0
PPI0_CLK
PPI0_D08
PPI0_D07
PPI0_D06
PPI0_D05
PPI0_D04
PPI0_D03
PPI0_D02
PPI0_D01
PPI0_D00
SPI1_CLK
SPI1_MISO
SPI1_MOSI
Multiplexed
Function 1
SPI0_SEL7
PWM2_DH
PWM2_SYNC
Multiplexed
Function 2
SPI2_SEL2
SPI2_SEL3
SPI2_SEL4
SPI2_SEL5
SPI1_SEL2
SPI1_RDY
TM0_TMR0
UART2_RTS
UART2_CTS
SPI2_RDY
PPI0_D20
PPI0_D21
PPI0_D22
Multiplexed
Function 3
C1_FLG1
C2_FLG1
C1_FLG2
C2_FLG2
C1_FLG3
C2_FLG3
SMC0_D03
SMC0_D02
SMC0_D01
SMC0_D00
SMC0_AMS1
SMC0_ABE0
SMC0_ABE1
Multiplexed
Function Input Tap
Multiplexed
Function 1
SPI1_SEL6
SPI1_SEL7
HADC0_EOC_DOUT
HADC0_MUX2
HADC0_MUX1
HADC0_MUX0
PWM2_AL
PWM2_AH
PWM2_BL
PWM2_BH
Multiplexed
Function 2
Multiplexed
Function 3
Multiplexed
Function Input Tap
TRACE0_D08
TRACE0_D09
TRACE0_D10
TRACE0_D00
TRACE0_D01
TRACE0_D02
MSI0_INT
Multiplexed
Function 1
TRACE0_CLK
TRACE0_D11
TRACE0_D12
TRACE0_D13
TRACE0_D14
TRACE0_D15
Multiplexed
Function 2
Multiplexed
Function 3
SPI1_SEL5
PWM0_SYNC
PWM2_DL
SPI1_SEL3
SPI1_SEL4
SPI1_SS
Table 25. Signal Multiplexing for Port F
Signal Name
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
Multiplexed
Function 0
TM0_TMR6
TM0_TMR7
MSI0_D0
MSI0_D1
MSI0_D2
MSI0_D3
MSI0_D4
MSI0_D5
MSI0_D6
MSI0_D7
MSI0_CMD
MSI0_CLK
MSI0_CD
ETH1_CRS
ETH1_MDC
ETH1_MDIO
Table 26. Signal Multiplexing for Port G
Signal Name
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
Multiplexed
Function 0
ETH1_REFCLK
ETH1_TXEN
ETH1_TXD0
ETH1_TXD1
ETH1_RXD0
ETH1_RXD1
Rev. B |
TRACE0_D03
TRACE0_D04
TRACE0_D05
TRACE0_D06
TRACE0_D07
Page 57 of 173 |
December 2018
Multiplexed
Function Input Tap
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADSP-SC58X/ADSP-2158X DESIGNER QUICK REFERENCE
Table 27 provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• The Reset Term column specifies the termination present
when the processor is in the reset state.
• The Reset Drive column specifies the active drive on the
signal when the processor is in the reset state.
• The Signal Name column includes the signal name for
every pin and the GPIO multiplexed pin function, where
applicable.
• The Power Domain column specifies the power supply
domain in which the signal resides.
• The Type column identifies the I/O type or supply type of
the pin. The abbreviations used in this column are a (analog), s (supply), g (ground) and Input, Output, and InOut.
• The Driver Type column identifies the driver type used by
the corresponding pin. The driver types are defined in the
Output Drive Currents section of this data sheet.
• The Internal Term column specifies the termination present when the processor is not in the reset state.
• The Description and Notes column identifies any special
requirements or characteristics for a signal. These recommendations apply whether or not the hardware block
associated with the signal is featured on the product. If no
special requirements are listed, the signal can be left unconnected if it is not used. For multiplexed general-purpose
I/O pins, this column identifies the functions available on
the pin.
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference
Signal Name
DAI0_PIN01
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
DAI0_PIN02
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN03
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN04
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN05
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN06
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN07
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN08
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN09
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN10
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN11
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN12
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN13
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN14
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN15
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 58 of 173 |
December 2018
Description and Notes
Desc: DAI0 Pin 1
Notes: No notes
Desc: DAI0 Pin 2
Notes: No notes
Desc: DAI0 Pin 3
Notes: No notes
Desc: DAI0 Pin 4
Notes: No notes
Desc: DAI0 Pin 5
Notes: No notes
Desc: DAI0 Pin 6
Notes: No notes
Desc: DAI0 Pin 7
Notes: No notes
Desc: DAI0 Pin 8
Notes: No notes
Desc: DAI0 Pin 9
Notes: No notes
Desc: DAI0 Pin 10
Notes: No notes
Desc: DAI0 Pin 11
Notes: No notes
Desc: DAI0 Pin 12
Notes: No notes
Desc: DAI0 Pin 13
Notes: No notes
Desc: DAI0 Pin 14
Notes: No notes
Desc: DAI0 Pin 15
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DAI0_PIN16
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
DAI0_PIN17
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN18
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN19
InOut
A
PullDown
none
none
VDD_EXT
DAI0_PIN20
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN01
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN02
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN03
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN04
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN05
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN06
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN07
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN08
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN09
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN10
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN11
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN12
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN13
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN14
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN15
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN16
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN17
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN18
InOut
A
PullDown
none
none
VDD_EXT
DAI1_PIN19
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 59 of 173 |
December 2018
Description and Notes
Desc: DAI0 Pin 16
Notes: No notes
Desc: DAI0 Pin 17
Notes: No notes
Desc: DAI0 Pin 18
Notes: No notes
Desc: DAI0 Pin 19
Notes: No notes
Desc: DAI0 Pin 20
Notes: No notes
Desc: DAI1 Pin 1
Notes: No notes
Desc: DAI1 Pin 2
Notes: No notes
Desc: DAI1 Pin 3
Notes: No notes
Desc: DAI1 Pin 4
Notes: No notes
Desc: DAI1 Pin 5
Notes: No notes
Desc: DAI1 Pin 6
Notes: No notes
Desc: DAI1 Pin 7
Notes: No notes
Desc: DAI1 Pin 8
Notes: No notes
Desc: DAI1 Pin 9
Notes: No notes
Desc: DAI1 Pin 10
Notes: No notes
Desc: DAI1 Pin 11
Notes: No notes
Desc: DAI1 Pin 12
Notes: No notes
Desc: DAI1 Pin 13
Notes: No notes
Desc: DAI1 Pin 14
Notes: No notes
Desc: DAI1 Pin 15
Notes: No notes
Desc: DAI1 Pin 16
Notes: No notes
Desc: DAI1 Pin 17
Notes: No notes
Desc: DAI1 Pin 18
Notes: No notes
Desc: DAI1 Pin 19
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DAI1_PIN20
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
DMC0_A00
Output
B
none
none
none
VDD_DMC
DMC0_A01
Output
B
none
none
none
VDD_DMC
DMC0_A02
Output
B
none
none
none
VDD_DMC
DMC0_A03
Output
B
none
none
none
VDD_DMC
DMC0_A04
Output
B
none
none
none
VDD_DMC
DMC0_A05
Output
B
none
none
none
VDD_DMC
DMC0_A06
Output
B
none
none
none
VDD_DMC
DMC0_A07
Output
B
none
none
none
VDD_DMC
DMC0_A08
Output
B
none
none
none
VDD_DMC
DMC0_A09
Output
B
none
none
none
VDD_DMC
DMC0_A10
Output
B
none
none
none
VDD_DMC
DMC0_A11
Output
B
none
none
none
VDD_DMC
DMC0_A12
Output
B
none
none
none
VDD_DMC
DMC0_A13
Output
B
none
none
none
VDD_DMC
DMC0_A14
Output
B
none
none
none
VDD_DMC
DMC0_A15
Output
B
none
none
none
VDD_DMC
DMC0_BA0
Output
B
none
none
none
VDD_DMC
DMC0_BA1
Output
B
none
none
none
VDD_DMC
DMC0_BA2
Output
B
none
none
none
VDD_DMC
DMC0_CAS
Output
B
none
none
none
VDD_DMC
DMC0_CK
Output
C
none
none
L
VDD_DMC
DMC0_CKE
Output
B
none
none
L
VDD_DMC
DMC0_CK
Output
C
none
none
L
VDD_DMC
Rev. B |
Page 60 of 173 |
December 2018
Description and Notes
Desc: DAI1 Pin 20
Notes: No notes
Desc: DMC0 Address 0
Notes: No notes
Desc: DMC0 Address 1
Notes: No notes
Desc: DMC0 Address 2
Notes: No notes
Desc: DMC0 Address 3
Notes: No notes
Desc: DMC0 Address 4
Notes: No notes
Desc: DMC0 Address 5
Notes: No notes
Desc: DMC0 Address 6
Notes: No notes
Desc: DMC0 Address 7
Notes: No notes
Desc: DMC0 Address 8
Notes: No notes
Desc: DMC0 Address 9
Notes: No notes
Desc: DMC0 Address 10
Notes: No notes
Desc: DMC0 Address 11
Notes: No notes
Desc: DMC0 Address 12
Notes: No notes
Desc: DMC0 Address 13
Notes: No notes
Desc: DMC0 Address 14
Notes: No notes
Desc: DMC0 Address 15
Notes: No notes
Desc: DMC0 Bank Address Input 0
Notes: No notes
Desc: DMC0 Bank Address Input 1
Notes: No notes
Desc: DMC0 Bank Address Input 2
Notes: No notes
Desc: DMC0 Column Address Strobe
Notes: No notes
Desc: DMC0 Clock
Notes: No notes
Desc: DMC0 Clock Enable
Notes: No notes
Desc: DMC0 Clock (Complement)
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC0_CS0
Type
Output
Driver
Type
B
Internal
Term
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_DMC
DMC0_DQ00
InOut
B
none
none
VDD_DMC
DMC0_DQ01
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 1
Notes: No notes
DMC0_DQ02
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 2
Notes: No notes
DMC0_DQ03
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 3
Notes: No notes
DMC0_DQ04
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 4
Notes: No notes
DMC0_DQ05
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 5
Notes: No notes
DMC0_DQ06
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 6
Notes: No notes
DMC0_DQ07
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 7
Notes: No notes
DMC0_DQ08
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 8
Notes: No notes
DMC0_DQ09
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 9
Notes: No notes
DMC0_DQ10
InOut
B
none
none
VDD_DMC
Desc: DMC0 Data 10
Notes: No notes
DMC0_DQ11
InOut
B
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
none
none
VDD_DMC
Desc: DMC0 Data 11
Notes: No notes
Rev. B |
Page 61 of 173 |
December 2018
Description and Notes
Desc: DMC0 Chip Select 0
Notes: No notes
Desc: DMC0 Data 0
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC0_DQ12
Type
InOut
Driver
Type
B
DMC0_DQ13
InOut
B
DMC0_DQ14
InOut
B
DMC0_DQ15
InOut
B
DMC0_LDM
Output
B
DMC0_LDQS
InOut
C
DMC0_LDQS
InOut
C
DMC0_ODT
Output
DMC0_RAS
Internal
Term
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_DMC
Description and Notes
Desc: DMC0 Data 12
Notes: No notes
none
none
VDD_DMC
Desc: DMC0 Data 13
Notes: No notes
none
none
VDD_DMC
Desc: DMC0 Data 14
Notes: No notes
none
none
VDD_DMC
Desc: DMC0 Data 15
Notes: No notes
none
none
VDD_DMC
Internal logic
none
ensures that
input signal does
not float
Internal logic
none
ensures that
input signal does
not float
none
VDD_DMC
Desc: DMC0 Data Mask for Lower
Byte
Notes: No notes
Desc: DMC0 Data Strobe for Lower
Byte (Complement)
Notes: No notes
none
VDD_DMC
B
none
none
none
VDD_DMC
Output
B
none
none
none
VDD_DMC
DMC0_RESET
Output
B
none
none
none
VDD_DMC
DMC0_RZQ
a
B
none
none
none
VDD_DMC
DMC0_UDM
Output
B
none
none
none
VDD_DMC
DMC0_UDQS
InOut
C
none
Internal logic
ensures that
input signal does
not float
none
VDD_DMC
DMC0_UDQS
InOut
C
none
VDD_DMC
DMC0_VREF
a
Internal logic
none
ensures that
input signal does
not float
none
none
none
VDD_DMC
Rev. B |
Page 62 of 173 |
December 2018
Desc: DMC0 Data Strobe for Lower
Byte
Notes: External weak pull-down
required in LPDDR mode
Desc: DMC0 On-Die Termination
Notes: No notes
Desc: DMC0 Row Address Strobe
Notes: No notes
Desc: DMC0 Reset (DDR3 Only)
Notes: No notes
Desc: DMC0 External Calibration
Resistor Connection
Notes: Applicable for DDR2 and
DDR3 only. External pull-down of
34 Ω need to be added.
Desc: DMC0 Data Mask for Upper
Byte
Notes: No notes
Desc: DMC0 Data Strobe for Upper
Byte
Notes: External weak pull-down
required in LPDDR mode
Desc: DMC0 Data Strobe for Upper
Byte (Complement)
Notes: No notes
Desc: DMC0 Voltage Reference
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC0_WE
Type
Output
Driver
Type
B
Internal
Term
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_DMC
DMC1_A00
Output
B
none
none
none
VDD_DMC
DMC1_A01
Output
B
none
none
none
VDD_DMC
DMC1_A02
Output
B
none
none
none
VDD_DMC
DMC1_A03
Output
B
none
none
none
VDD_DMC
DMC1_A04
Output
B
none
none
none
VDD_DMC
DMC1_A05
Output
B
none
none
none
VDD_DMC
DMC1_A06
Output
B
none
none
none
VDD_DMC
DMC1_A07
Output
B
none
none
none
VDD_DMC
DMC1_A08
Output
B
none
none
none
VDD_DMC
DMC1_A09
Output
B
none
none
none
VDD_DMC
DMC1_A10
Output
B
none
none
none
VDD_DMC
DMC1_A11
Output
B
none
none
none
VDD_DMC
DMC1_A12
Output
B
none
none
none
VDD_DMC
DMC1_A13
Output
B
none
none
none
VDD_DMC
DMC1_A14
Output
B
none
none
none
VDD_DMC
DMC1_A15
Output
B
none
none
none
VDD_DMC
DMC1_BA0
Output
B
none
none
none
VDD_DMC
DMC1_BA1
Output
B
none
none
none
VDD_DMC
DMC1_BA2
Output
B
none
none
none
VDD_DMC
DMC1_CAS
Output
B
none
none
none
VDD_DMC
DMC1_CK
Output
C
none
none
L
VDD_DMC
DMC1_CKE
Output
B
none
none
L
VDD_DMC
DMC1_CK
Output
C
none
none
L
VDD_DMC
Rev. B |
Page 63 of 173 |
December 2018
Description and Notes
Desc: DMC0 Write Enable
Notes: No notes
Desc: DMC1 Address 0
Notes: No notes
Desc: DMC1 Address 1
Notes: No notes
Desc: DMC1 Address 2
Notes: No notes
Desc: DMC1 Address 3
Notes: No notes
Desc: DMC1 Address 4
Notes: No notes
Desc: DMC1 Address 5
Notes: No notes
Desc: DMC1 Address 6
Notes: No notes
Desc: DMC1 Address 7
Notes: No notes
Desc: DMC1 Address 8
Notes: No notes
Desc: DMC1 Address 9
Notes: No notes
Desc: DMC1 Address 10
Notes: No notes
Desc: DMC1 Address 11
Notes: No notes
Desc: DMC1 Address 12
Notes: No notes
Desc: DMC1 Address 13
Notes: No notes
Desc: DMC1 Address 14
Notes: No notes
Desc: DMC1 Address 15
Notes: No notes
Desc: DMC1 Bank Address Input 0
Notes: No notes
Desc: DMC1 Bank Address Input 1
Notes: No notes
Desc: DMC1 Bank Address Input 2
Notes: No notes
Desc: DMC1 Column Address Strobe
Notes: No notes
Desc: DMC1 Clock
Notes: No notes
Desc: DMC1 Clock Enable
Notes: No notes
Desc: DMC1 Clock (Complement)
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC1_CS0
Type
Output
Driver
Type
B
Internal
Term
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_DMC
DMC1_DQ00
InOut
B
none
none
VDD_DMC
DMC1_DQ01
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 1
Notes: No notes
DMC1_DQ02
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 2
Notes: No notes
DMC1_DQ03
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 3
Notes: No notes
DMC1_DQ04
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 4
Notes: No notes
DMC1_DQ05
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 5
Notes: No notes
DMC1_DQ06
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 6
Notes: No notes
DMC1_DQ07
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 7
Notes: No notes
DMC1_DQ08
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 8
Notes: No notes
DMC1_DQ09
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 9
Notes: No notes
DMC1_DQ10
InOut
B
none
none
VDD_DMC
Desc: DMC1 Data 10
Notes: No notes
DMC1_DQ11
InOut
B
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
none
none
VDD_DMC
Desc: DMC1 Data 11
Notes: No notes
Rev. B |
Page 64 of 173 |
December 2018
Description and Notes
Desc: DMC1 Chip Select 0
Notes: No notes
Desc: DMC1 Data 0
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC1_DQ12
Type
InOut
Driver
Type
B
DMC1_DQ13
InOut
B
DMC1_DQ14
InOut
B
DMC1_DQ15
InOut
B
DMC1_LDM
Output
B
DMC1_LDQS
InOut
DMC1_LDQS
Internal
Term
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_DMC
Description and Notes
Desc: DMC1 Data 12
Notes: No notes
none
none
VDD_DMC
Desc: DMC1 Data 13
Notes: No notes
none
none
VDD_DMC
Desc: DMC1 Data 14
Notes: No notes
none
none
VDD_DMC
Desc: DMC1 Data 15
Notes: No notes
none
none
VDD_DMC
C
Internal logic
none
ensures that
input signal does
not float
none
VDD_DMC
InOut
C
none
VDD_DMC
DMC1_ODT
Output
B
Internal logic
none
ensures that
input signal does
not float
none
none
Desc: DMC1 Data Mask for Lower
Byte
Notes: No notes
Desc: DMC1 Data Strobe for Lower
Byte
Notes: External weak pull-down
required in LPDDR mode
Desc: DMC1 Data Strobe for Lower
Byte (Complement)
Notes: No notes
none
VDD_DMC
DMC1_RAS
Output
B
none
none
none
VDD_DMC
DMC1_RESET
InOut
B
none
none
none
VDD_DMC
DMC1_RZQ
a
B
none
none
none
VDD_DMC
DMC1_UDM
Output
B
none
none
none
VDD_DMC
DMC1_UDQS
InOut
C
none
Internal logic
ensures that
input signal does
not float
none
VDD_DMC
DMC1_UDQS
InOut
C
none
VDD_DMC
DMC1_VREF
a
Internal logic
none
ensures that
input signal does
not float
none
none
none
VDD_DMC
Rev. B |
Page 65 of 173 |
December 2018
Desc: DMC1 On-Die Termination
Notes: No notes
Desc: DMC1 Row Address Strobe
Notes: No notes
Desc: DMC1 Reset (DDR3 Only)
Notes: No notes
Desc: DMC1 External Calibration
Resistor Connection
Notes: Applicable for DDR2 and
DDR3 only. External pull-down of
34 Ω need to be added.
Desc: DMC1 Data Mask for Upper
Byte
Notes: No notes
Desc: DMC1 Data Strobe for Upper
Byte
Notes: External weak pull-down
required in LPDDR mode
Desc: DMC1 Data Strobe for Upper
Byte (Complement)
Notes: No notes
Desc: DMC1 Voltage Reference
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
DMC1_WE
Type
Output
Driver
Type
B
Internal
Term
none
Reset
Term
none
Reset
Drive
none
GND
g
NA
none
none
none
HADC0_VIN0
a
NA
none
none
none
VDD_HADC
HADC0_VIN1
a
NA
none
none
none
VDD_HADC
HADC0_VIN2
a
NA
none
none
none
VDD_HADC
HADC0_VIN3
a
NA
none
none
none
VDD_HADC
HADC0_VIN4
a
NA
none
none
none
VDD_HADC
HADC0_VIN5
a
NA
none
none
none
VDD_HADC
HADC0_VIN6
a
NA
none
none
none
VDD_HADC
HADC0_VIN7
a
NA
none
none
none
VDD_HADC
HADC0_VREFN
s
NA
none
none
none
VDD_HADC
HADC0_VREFP
s
NA
none
none
none
VDD_HADC
JTG_TCK
Input
PullUp
none
none
VDD_EXT
JTG_TDI
Input
PullUp
none
none
VDD_EXT
JTG_TDO
Output
none
none
none
VDD_EXT
A
Rev. B |
Page 66 of 173 |
Power Domain
December 2018
Description and Notes
Desc: DMC1 Write Enable
Notes: No notes
Desc: Ground
Notes: No notes
Desc: HADC0 Analog Input at
Channel 0
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 1
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 2
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 3
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 4
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 5
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 6
Notes: If Input not used connect to
GND
Desc: HADC0 Analog Input at
Channel 7
Notes: If Input not used connect to
GND
Desc: HADC0 Ground Reference for
ADC
Notes: Can be left floating if HADC
and TMU are not used
Desc: HADC0 External Reference for
ADC
Notes: Can be left floating if HADC
and TMU are not used
Desc: JTAG Clock
Notes: No notes
Desc: JTAG Serial Data In
Notes: No notes
Desc: JTAG Serial Data Out
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Driver
Type
A
Internal
Term
PullUp
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PullDown
none
none
VDD_EXT
none
none
VDD_EXT
none
none
VDD_EXT
Desc: MLB0 Differential Clock (+)
Notes: No notes
none
none
VDD_EXT
Desc: MLB0 Differential Data (−)
Notes: No notes
none
none
VDD_EXT
Desc: MLB0 Differential Data (+)
Notes: No notes
none
none
VDD_EXT
Desc: MLB0 Differential Signal (−)
Notes: No notes
none
none
VDD_EXT
Desc: MLB0 Differential Signal (+)
Notes: No notes
A
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
Internal logic
ensures that
input signal does
not float
PullDown
none
none
VDD_EXT
InOut
A
PullDown
none
none
VDD_EXT
PA_02
InOut
A
PullDown
none
none
VDD_EXT
PA_03
InOut
A
PullDown
none
none
VDD_EXT
PA_04
InOut
A
PullDown
none
none
VDD_EXT
PA_05
InOut
A
PullDown
none
none
VDD_EXT
Desc: PORTA Position 0 | EMAC0
Transmit Data 0 | SMC0 Address 21
Notes: No notes
Desc: PORTA Position 1 | EMAC0
Transmit Data 1 | SMC0 Address 20
Notes: No notes
Desc: PORTA Position 2 | EMAC0
Management Channel Clock | SMC0
Address 24
Notes: No notes
Desc: PORTA Position 3 | EMAC0
Management Channel Serial Data |
SMC0 Address 23
Notes: No notes
Desc: PORTA Position 4 | EMAC0
Receive Data 0 | SMC0 Address 19
Notes: No notes
Desc: PORTA Position 5 | EMAC0
Receive Data 1 | SMC0 Address 18
Notes: No notes
Signal Name
JTG_TMS
Type
InOut
JTG_TRST
Input
MLB0_CLKN
Input
NA
MLB0_CLKP
Input
NA
MLB0_DATN
InOut
I
MLB0_DATP
InOut
I
MLB0_SIGN
InOut
I
MLB0_SIGP
InOut
I
PA_00
InOut
PA_01
Rev. B |
Page 67 of 173 |
December 2018
Description and Notes
Desc: JTAG Mode Select
Notes: No notes
Desc: JTAG Reset
Notes: No notes
Desc: MLB0 Differential Clock (−)
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PA_06
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PA_07
InOut
A
PullDown
none
none
VDD_EXT
PA_08
InOut
A
PullDown
none
none
VDD_EXT
PA_09
InOut
A
PullDown
none
none
VDD_EXT
PA_10
InOut
A
PullDown
none
none
VDD_EXT
PA_11
InOut
A
PullDown
none
none
VDD_EXT
PA_12
InOut
A
PullDown
none
none
VDD_EXT
PA_13
InOut
A
PullDown
none
none
VDD_EXT
PA_14
InOut
A
PullDown
none
none
VDD_EXT
PA_15
InOut
A
PullDown
none
none
VDD_EXT
PB_00
InOut
A
PullDown
none
none
VDD_EXT
PB_01
InOut
A
PullDown
none
none
VDD_EXT
PB_02
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 68 of 173 |
December 2018
Description and Notes
Desc: PORTA Position 6 | EMAC0
RXCLK (10/100/1000) or REFCLK
(10/100) | SMC0 Address 17
Notes: No notes
Desc: EMAC0 RXCTL (10/100/1000)
or CRS (10/100) | PORTA Position 7 |
EMAC0 Carrier Sense/RMII Receive
Data Valid | SMC0 Address 16
Notes: No notes
Desc: PORTA Position 8 | EMAC0
Receive Data 2 | SMC0 Address 12
Notes: No notes
Desc: PORTA Position 9 | EMAC0
Receive Data 3 | SMC0 Address 11
Notes: No notes
Desc: EMAC0 TXCTL (10/100/1000)
or TXEN (10/100) | PORTA Position
10 | EMAC0 Transmit Enable | SMC0
Address 22
Notes: No notes
Desc: PORTA Position 11 | EMAC0
Transmit Clock | SMC0 Address 15
Notes: No notes
Desc: PORTA Position 12 | EMAC0
Transmit Data 2 | SMC0 Address 14
Notes: No notes
Desc: PORTA Position 13 | EMAC0
Transmit Data 3 | SMC0 Address 13
Notes: No notes
Desc: PORTA Position 14 | EMAC0
PTP Pulse-Per-Second Output 3 |
SINC0 Data 0 | SMC0 Address 10
Notes: No notes
Desc: PORTA Position 15 | EMAC0
PTP Pulse-Per-Second Output 2 |
SINC0 Data 1 | SMC0 Address 9
Notes: No notes
Desc: PORTB Position 0 | EMAC0 PTP
Pulse-Per-Second Output 1 | EPPI0
Data 14 | SINC0 Data 2 | SMC0
Address 8 | TIMER0 Alternate Clock 3
Notes: No notes
Desc: PORTB Position 1 | EMAC0 PTP
Pulse-Per-Second Output 0 | EPPI0
Data 15 | SINC0 Clock 0 | SMC0
Address 7 | TIMER0 Alternate Clock 4
Notes: No notes
Desc: PORTB Position 2 | EMAC0 PTP
Clock Input 0 | EPPI0 Data 16 | SMC0
Address 4 | UART1 Transmit
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PB_03
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PB_04
InOut
A
PullDown
none
none
VDD_EXT
PB_05
InOut
A
PullDown
none
none
VDD_EXT
PB_06
InOut
A
PullDown
none
none
VDD_EXT
PB_07
InOut
A
PullDown
none
none
VDD_EXT
PB_08
InOut
A
PullDown
none
none
VDD_EXT
PB_09
InOut
A
PullDown
none
none
VDD_EXT
PB_10
InOut
A
PullDown
none
none
VDD_EXT
PB_11
InOut
A
PullDown
none
none
VDD_EXT
PB_12
InOut
A
PullDown
none
none
VDD_EXT
PB_13
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 69 of 173 |
December 2018
Description and Notes
Desc: PORTB Position 3 | EMAC0 PTP
Auxiliary Trigger Input 0 | EPPI0 Data
17 | SMC0 Address 3 | UART1 Receive
| TIMER0 Alternate Capture Input 1
Notes: No notes
Desc: PORTB Position 4 | EPPI0 Data
12 | MLB0 Single-Ended Clock |
SINC0 Data 3 | SMC0 Asynchronous
Ready | EMAC0 PTP Auxiliary Trigger
Input 1
Notes: No notes
Desc: PORTB Position 5 | EPPI0 Data
13 | MLB0 Single-Ended Signal |
SMC0 Address 1 | EMAC0 PTP
Auxiliary Trigger Input 2
Notes: No notes
Desc: PORTB Position 6 | MLB0
Single-Ended Data | PWM0 Channel
B High Side | SMC0 Address 2 |
EMAC0 PTP Auxiliary Trigger Input 3
Notes: No notes
Desc: PORTB Position 7 | LP1 Data 0
| PWM0 Channel A High Side | SMC0
Data 15 | TIMER0 Timer 3
Notes: No notes
Desc: PORTB Position 8 | LP1 Data 1
| PWM0 Channel A Low Side | SMC0
Data 14 | TIMER0 Timer 4
Notes: No notes
Desc: PORTB Position 9 | CAN1
Transmit | LP1 Data 2 | SMC0 Data 13
Notes: No notes
Desc: PORTB Position 10 | CAN1
Receive | LP1 Data 3 | SMC0 Data 12
| TIMER0 Timer 2 | TIMER0 Alternate
Capture Input 4
Notes: No notes
Desc: PORTB Position 11 | LP1 Data 4
| PWM0 Channel D High Side | SMC0
Data 11 | CNT0 Count Zero Marker
Notes: No notes
Desc: PORTB Position 12 | LP1 Data 5
| PWM0 Channel D Low Side | SMC0
Data 10 | CNT0 Count Up and
Direction
Notes: No notes
Desc: PORTB Position 13 | LP1 Data 6
| PWM0 Channel C High Side | SMC0
Data 9
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PB_14
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PB_15
InOut
A
PullDown
none
none
VDD_EXT
PCIE0_CLKM
Input
NA
PullDown
none
none
VDD_PCIE
PCIE0_CLKP
Input
NA
PullDown
none
none
VDD_PCIE
PCIE0_REF
a
NA
PullDown
none
none
VDD_PCIE
PCIE0_RXM
Input
NA
PullDown
none
none
VDD_PCIE_RX
PCIE0_RXP
Input
NA
PullDown
none
none
VDD_PCIE_RX
PCIE0_TXM
InOut
J
PullDown
none
none
VDD_PCIE_TX
PCIE0_TXP
InOut
J
PullDown
none
none
VDD_PCIE_TX
PC_00
InOut
H
PullDown
none
none
VDD_EXT
PC_01
InOut
A
PullDown
none
none
VDD_EXT
PC_02
InOut
A
PullDown
none
none
VDD_EXT
PC_03
InOut
A
PullDown
none
none
VDD_EXT
PC_04
InOut
A
PullDown
none
none
VDD_EXT
PC_05
InOut
A
PullDown
none
none
VDD_EXT
PC_06
InOut
A
PullDown
none
none
VDD_EXT
PC_07
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 70 of 173 |
December 2018
Description and Notes
Desc: PORTB Position 14 | LP1 Data 7
| PWM0 Channel C Low Side | SMC0
Data 8 | TIMER0 Timer 5 | CNT0 Count
Down and Gate
Notes: No notes
Desc: PORTB Position 15 | LP1
Acknowledge | PWM0 Shutdown
Input 0 | SMC0 Write Enable | TIMER0
Timer 1
Notes: No notes
Desc: PCIE0 CLK –
Notes: No notes
Desc: PCIE0 CLK +
Notes: No notes
Desc: PCIE0 Reference
Notes: No notes
Desc: PCIE0 RX –
Notes: No notes
Desc: PCIE0 RX +
Notes: No notes
Desc: PCIE0 TX –
Notes: No notes
Desc: PCIE0 TX +
Notes: No notes
Desc: PORTC Position 0 | LP1 Clock |
PWM0 Channel B Low Side | SMC0
Read Enable | SPI0 Slave Select
Output 4
Notes: No notes
Desc: PORTC Position 1 | SPI2 Clock
Notes: No notes
Desc: PORTC Position 2 | SPI2 Master
In, Slave Out
Notes: No notes
Desc: PORTC Position 3 | SPI2 Master
Out, Slave In
Notes: No notes
Desc: PORTC Position 4 | SPI2 Data 2
Notes: No notes
Desc: PORTC Position 5 | SPI2 Data 3
Notes: No notes
Desc: PORTC Position 6 | SPI2 Slave
Select Output 1 | SPI2 Slave Select
Input
Notes: No notes
Desc: PORTC Position 7 | CAN0
Receive | SMC0 Memory Select 2 |
SPI0 Slave Select Output 1 | TIMER0
Alternate Capture Input 3
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PC_08
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PC_09
InOut
A
PullDown
none
none
VDD_EXT
PC_10
InOut
A
PullDown
none
none
VDD_EXT
PC_11
InOut
A
PullDown
none
none
VDD_EXT
PC_12
InOut
A
PullDown
none
none
VDD_EXT
PC_13
InOut
A
PullDown
none
none
VDD_EXT
PC_14
InOut
A
PullDown
none
none
VDD_EXT
PC_15
InOut
A
PullDown
none
none
VDD_EXT
PD_00
InOut
A
PullDown
none
none
VDD_EXT
PD_01
InOut
A
PullDown
none
none
VDD_EXT
PD_02
InOut
A
PullDown
none
none
VDD_EXT
PD_03
InOut
A
PullDown
none
none
VDD_EXT
PD_04
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 71 of 173 |
December 2018
Description and Notes
Desc: PORTC Position 8 | CAN0
Transmit | SMC0 Memory Select 3
Notes: No notes
Desc: PORTC Position 9 | SPI0 Clock
Notes: No notes
Desc: PORTC Position 10 | SPI0
Master In, Slave Out
Notes: No notes
Desc: PORTC Position 11 | SPI0
Master Out, Slave In | TIMER0 Clock
Notes: No notes
Desc: PORTC Position 12 | ACM0
External Trigger n | SMC0 Address 25
| SPI0 Ready | SPI0 Slave Select
Output 3
Notes: No notes
Desc: PORTC Position 13 | ACM0 ADC
Control Signals | SPI1 Slave Select
Output 1 | UART0 Transmit
Notes: No notes
Desc: PORTC Position 14 | ACM0 ADC
Control Signals | UART0 Receive |
TIMER0 Alternate Capture Input 0
Notes: No notes
Desc: PORTC Position 15 | ACM0 ADC
Control Signals | EPPI0 Frame Sync 3
(FIELD) | SMC0 Memory Select 0 |
UART0 Request to Send
Notes: No notes
Desc: PORTD Position 0 | ACM0 ADC
Control Signals | EPPI0 Data 23 |
SMC0 Data 7 | UART0 Clear to Send
Notes: No notes
Desc: PORTD Position 1 | ACM0 ADC
Control Signals | SMC0 Output
Enable | SPI0 Slave Select Output 2 |
SPI0 Slave Select Input
Notes: No notes
Desc: PORTD Position 2 | LP0 Data 0
| PWM1 Shutdown Input 0 | TRACE0
Trace Data 0
Notes: No notes
Desc: PORTD Position 3 | LP0 Data 1
| PWM1 Channel A High Side |
TRACE0 Trace Data 1
Notes: No notes
Desc: PORTD Position 4 | LP0 Data 2
| PWM1 Channel A Low Side |
TRACE0 Trace Data 2
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PD_05
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PD_06
InOut
A
PullDown
none
none
VDD_EXT
PD_07
InOut
A
PullDown
none
none
VDD_EXT
PD_08
InOut
A
PullDown
none
none
VDD_EXT
PD_09
InOut
A
PullDown
none
none
VDD_EXT
PD_10
InOut
H
PullDown
none
none
VDD_EXT
PD_11
InOut
A
PullDown
none
none
VDD_EXT
PD_12
InOut
A
PullDown
none
none
VDD_EXT
PD_13
InOut
A
PullDown
none
none
VDD_EXT
PD_14
InOut
A
PullDown
none
none
VDD_EXT
PD_15
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 72 of 173 |
December 2018
Description and Notes
Desc: PORTD Position 5 | LP0 Data 3
| PWM1 Channel B High Side |
TRACE0 Trace Data 3
Notes: No notes
Desc: PORTD Position 6 | LP0 Data 4
| PWM1 Channel B Low Side |
TRACE0 Trace Data 4
Notes: No notes
Desc: PORTD Position 7 | LP0 Data 5
| PWM1 Channel C High Side |
TRACE0 Trace Data 5
Notes: No notes
Desc: PORTD Position 8 | LP0 Data 6
| PWM1 Channel C Low Side |
TRACE0 Trace Data 6 | TIMER0
Alternate Clock 1
Notes: No notes
Desc: PORTD Position 9 | LP0 Data 7
| PWM1 Channel D High Side |
TRACE0 Trace Data 7 | TIMER0
Alternate Clock 2
Notes: No notes
Desc: PORTD Position 10 | LP0 Clock
| PWM1 Channel D Low Side |
TRACE0 Trace Clock
Notes: No notes
Desc: PORTD Position 11 | LP0
Acknowledge | PWM1 PWMTMR
Grouped
Notes: No notes
Desc: PORTD Position 12 | EPPI0
Data 19 | SMC0 Address 6 | UART2
Transmit
Notes: No notes
Desc: PORTD Position 13 | EPPI0
Data 18 | SMC0 Address 5 | UART2
Receive | TIMER0 Alternate Capture
Input 2
Notes: No notes
Desc: PORTD Position 14 | EPPI0
Data 11 | MLB0 Single-Ended Clock
Out | PWM2 Shutdown Input 0 |
SMC0 Data 6
Notes: No notes
Desc: PORTD Position 15 | EPPI0
Data 10 | PWM2 Channel C High Side
| SMC0 Data 5
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PE_00
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PE_01
InOut
A
PullDown
none
none
VDD_EXT
PE_02
InOut
A
PullDown
none
none
VDD_EXT
PE_03
InOut
A
PullDown
none
none
VDD_EXT
PE_04
InOut
A
PullDown
none
none
VDD_EXT
PE_05
InOut
A
PullDown
none
none
VDD_EXT
PE_06
InOut
A
PullDown
none
none
VDD_EXT
PE_07
InOut
A
PullDown
none
none
VDD_EXT
PE_08
InOut
A
PullDown
none
none
VDD_EXT
PE_09
InOut
A
PullDown
none
none
VDD_EXT
PE_10
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 73 of 173 |
December 2018
Description and Notes
Desc: PORTE Position 0 | EPPI0 Data
9 | PWM2 Channel C Low Side | SMC0
Data 4
Notes: No notes
Desc: PORTE Position 1 | EPPI0 Frame
Sync 2 (VSYNC) | SPI0 Slave Select
Output 5 | SHARC Core 1 Flag Pin |
UART1 Clear to Send
Notes: No notes
Desc: PORTE Position 2 | EPPI0 Frame
Sync 1 (HSYNC) | SPI0 Slave Select
Output 6 | SHARC Core 2 Flag Pin |
UART1 Request to Send
Notes: No notes
Desc: PORTE Position 3 | EPPI0 Clock
| SPI0 Slave Select Output 7 | SPI2
Slave Select Output 2 | SHARC Core
1 Flag Pin
Notes: No notes
Desc: PORTE Position 4 | EPPI0 Data
8 | PWM2 Channel D High Side | SPI2
Slave Select Output 3 | SHARC Core
2 Flag Pin
Notes: No notes
Desc: PORTE Position 5 | EPPI0 Data
7 | PWM2 PWMTMR Grouped | SPI2
Slave Select Output 4 | SHARC Core
1 Flag Pin
Notes: No notes
Desc: PORTE Position 6 | EPPI0 Data
6 | SPI2 Slave Select Output 5 |
SHARC Core 2 Flag Pin
Notes: No notes
Desc: PORTE Position 7 | EPPI0 Data
5 | SPI1 Slave Select Output 2 |
SHARC Core 1 Flag Pin
Notes: No notes
Desc: PORTE Position 8 | EPPI0 Data
4 | SPI1 Ready | SPI1 Slave Select
Output 5 | SHARC Core 2 Flag Pin
Notes: No notes
Desc: PORTE Position 9 | EPPI0 Data
3 | PWM0 PWMTMR Grouped | SMC0
Data 3 | TIMER0 Timer 0
Notes: No notes
Desc: PORTE Position 10 | EPPI0 Data
2 | PWM2 Channel D Low Side | SMC0
Data 2 | UART2 Request to Send
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PE_11
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PE_12
InOut
A
PullDown
none
none
VDD_EXT
PE_13
InOut
A
PullDown
none
none
VDD_EXT
PE_14
InOut
A
PullDown
none
none
VDD_EXT
PE_15
InOut
A
PullDown
none
none
VDD_EXT
PF_00
InOut
A
PullDown
none
none
VDD_EXT
PF_01
InOut
A
PullDown
none
none
VDD_EXT
PF_02
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_03
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_04
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_05
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_06
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_07
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
Rev. B |
Page 74 of 173 |
December 2018
Description and Notes
Desc: PORTE Position 11 | EPPI0 Data
1 | SMC0 Data 1 | SPI1 Slave Select
Output 3 | UART2 Clear to Send | SPI1
Slave Select Input
Notes: No notes
Desc: PORTE Position 12 | EPPI0 Data
0 | SMC0 Data 0 | SPI1 Slave Select
Output 4 | SPI2 Ready
Notes: No notes
Desc: PORTE Position 13 | EPPI0 Data
20 | SMC0 Memory Select 1 | SPI1
Clock
Notes: No notes
Desc: PORTE Position 14 | EPPI0 Data
21 | SMC0 Byte Enable 0 | SPI1 Master
In, Slave Out
Notes: No notes
Desc: PORTE Position 15 | EPPI0 Data
22 | SMC0 Byte Enable 1 | SPI1 Master
Out, Slave In
Notes: No notes
Desc: PORTF Position 0 | SPI1 Slave
Select Output 6 | TIMER0 Timer 6
Notes: No notes
Desc: PORTF Position 1 | SPI1 Slave
Select Output 7 | TIMER0 Timer 7
Notes: No notes
Desc: PORTF Position 2 | HADC0 End
of Conversion/Serial Data Out | MSI0
Data 0
Notes: No notes
Desc: PORTF Position 3 | HADC0
Controls to External Multiplexer |
MSI0 Data 1
Notes: No notes
Desc: PORTF Position 4 | HADC0
Controls to External Multiplexer |
MSI0 Data 2
Notes: No notes
Desc: PORTF Position 5 | HADC0
Controls to External Multiplexer |
MSI0 Data 3
Notes: No notes
Desc: PORTF Position 6 | MSI0 Data 4
| PWM2 Channel A Low Side
Notes: No notes
Desc: PORTF Position 7 | MSI0 Data 5
| PWM2 Channel A High Side
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PF_08
Type
InOut
Driver
Type
A
Internal
Term
PullDown/
Programmable
PullUp
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
PF_09
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_10
InOut
A
PullDown/
Programmable
PullUp
none
none
VDD_EXT
PF_11
InOut
A
PullDown
none
none
VDD_EXT
PF_12
InOut
A
PullDown
none
none
VDD_EXT
PF_13
InOut
A
PullDown
none
none
VDD_EXT
PF_14
InOut
A
PullDown
none
none
VDD_EXT
PF_15
InOut
A
PullDown
none
none
VDD_EXT
PG_00
InOut
A
PullDown
none
none
VDD_EXT
PG_01
InOut
A
PullDown
none
none
VDD_EXT
PG_02
InOut
A
PullDown
none
none
VDD_EXT
PG_03
InOut
A
PullDown
none
none
VDD_EXT
PG_04
InOut
A
PullDown
none
none
VDD_EXT
Rev. B |
Page 75 of 173 |
December 2018
Description and Notes
Desc: PORTF Position 8 | MSI0 Data 6
| PWM2 Channel B Low Side
Notes: No notes
Desc: PORTF Position 9 | MSI0 Data 7
| PWM2 Channel B High Side
Notes: No notes
Desc: PORTF Position 10 | MSI0
Command
Notes: No notes
Desc: PORTF Position 11 | MSI0 Clock
Notes: No notes
Desc: PORTF Position 12 | MSI0 Card
Detect
Notes: No notes
Desc: PORTF Position 13 | EMAC1
Carrier Sense/RMII Receive Data
Valid | MSI0 eSDIO Interrupt Input |
TRACE0 Trace Data | TRACE0 Trace
Data 8
Notes: No notes
Desc: PORTF Position 14 | EMAC1
Management Channel Clock |
TRACE0 Trace Data | TRACE0 Trace
Data 9
Notes: No notes
Desc: PORTF Position 15 | EMAC1
Management Channel Serial Data |
TRACE0 Trace Data | TRACE0 Trace
Data 10
Notes: No notes
Desc: PORTG Position 0 | EMAC1
Reference Clock | TRACE0 Trace
Clock
Notes: No notes
Desc: PORTG Position 1 | EMAC1
Transmit Enable | TRACE0 Trace Data
| TRACE0 Trace Data 11
Notes: No notes
Desc: PORTG Position 2 | EMAC1
Transmit Data 0 | TRACE0 Trace Data
| TRACE0 Trace Data 12
Notes: No notes
Desc: PORTG Position 3 | EMAC1
Transmit Data 1 | TRACE0 Trace Data
| TRACE0 Trace Data 13
Notes: No notes
Desc: PORTG Position 4 | EMAC1
Receive Data 0 | TRACE0 Trace Data
| TRACE0 Trace Data 14
Notes: No notes
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
PG_05
Type
InOut
Driver
Type
A
Internal
Term
PullDown
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
RTC0_CLKIN
a
NA
none
none
none
VDD_RTC
RTC0_XTAL
a
NA
none
none
none
VDD_RTC
SYS_BMODE0
Input
NA
PullDown
none
none
VDD_EXT
SYS_BMODE1
Input
NA
PullDown
none
none
VDD_EXT
SYS_BMODE2
Input
NA
PullDown
none
none
VDD_EXT
SYS_CLKIN0
a
NA
none
none
none
VDD_EXT
SYS_CLKIN1
a
NA
none
none
none
VDD_EXT
SYS_CLKOUT
a
A
none
none
none
SYS_FAULT
InOut
A
none
none
none
SYS_FAULT
InOut
A
none
none
none
SYS_HWRST
Input
NA
none
none
none
VDD_EXT
SYS_RESOUT
Output
A
none
none
L
VDD_EXT
SYS_XTAL0
a
NA
none
none
none
VDD_EXT
SYS_XTAL1
a
NA
none
none
none
VDD_EXT
TWI0_SCL
InOut
D
none
none
none
VDD_EXT
TWI0_SDA
InOut
D
none
none
none
VDD_EXT
TWI1_SCL
InOut
D
none
none
none
VDD_EXT
TWI1_SDA
InOut
D
none
none
none
VDD_EXT
Rev. B |
Page 76 of 173 |
December 2018
Description and Notes
Desc: PORTG Position 5 | EMAC1
Receive Data 1 | TRACE0 Trace Data
| TRACE0 Trace Data 15
Notes: No notes
Desc: RTC0 Crystal Input/External
Oscillator Connection
Notes: Connect to GND if not used
Desc: RTC0 Crystal output
Notes: No notes
Desc: Boot Mode Control n
Notes: No notes
Desc: Boot Mode Control n
Notes: No notes
Desc: Boot Mode Control n
Notes: No notes
Desc: Clock/Crystal Input
Notes: No notes
Desc: Clock/Crystal Input
Notes: Connect to GND if not used
Desc: Processor Clock Output
Notes: No notes
Desc: Active-High Fault Output
Notes: External pull-down required
to keep signal in de-asserted state
Desc: Active-Low Fault Output
Notes: External pull-up required to
keep signal in de-asserted state
Desc: Processor Hardware Reset
Control
Notes: No notes
Desc: Reset Output
Notes: No notes
Desc: Crystal Output
Notes: No notes
Desc: Crystal Output
Notes: No notes
Desc: TWI0 Serial Clock
Notes: Add external pull-up if used.
Can be pulled low when not used.
Desc: TWI0 Serial Data
Notes: Add external pull-up if used.
Can be pulled low when not used.
Desc: TWI1 Serial Clock
Notes: Add external pull-up if used.
Can be pulled low when not used.
Desc: TWI1 Serial Data
Notes: Add external pull-up if used.
Can be pulled low when not used.
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
Signal Name
TWI2_SCL
Type
InOut
Driver
Type
D
Internal
Term
none
Reset
Term
none
Reset
Drive
none
Power Domain
VDD_EXT
TWI2_SDA
InOut
D
none
none
none
VDD_EXT
USB0_DM
InOut
F
none
none
none
VDD_USB
USB0_DP
InOut
F
none
none
none
VDD_USB
USB0_ID
InOut
none
none
none
VDD_USB
USB0_VBC
InOut
E
none
none
none
VDD_USB
USB0_VBUS
InOut
G
none
none
none
VDD_USB
USB1_DM
InOut
F
none
none
none
VDD_USB
USB1_DP
InOut
F
none
none
none
VDD_USB
USB1_VBUS
InOut
G
none
none
none
VDD_USB
USB_CLKIN
a
none
none
none
USB_XTAL
a
none
none
none
VDD_DMC
s
NA
none
none
none
VDD_EXT
s
NA
none
none
none
VDD_HADC
s
NA
none
none
none
VDD_INT
s
NA
none
none
none
VDD_PCIE
s
NA
none
none
none
VDD_PCIE_RX
s
NA
none
none
none
VDD_PCIE_TX
s
NA
none
none
none
Rev. B |
Page 77 of 173 |
December 2018
Description and Notes
Desc: TWI2 Serial Clock
Notes: Add external pull-up if used.
Can be pulled low when not used.
Desc: TWI2 Serial Data
Notes: Add external pull-up if used.
Can be pulled low when not used.
Desc: USB0 Data −
Notes: Add external pull-down if not
used1
Desc: USB0 Data +
Notes: Add external pull-down if not
used1
Desc: USB0 OTG ID
Notes: Connect to GND when USB is
not used1
Desc: USB0 VBUS Control
Notes: Add external pull-down if not
used1
Desc: USB0 Bus Voltage
Notes: Connect to GND if not used1
Desc: USB1 Data −
Notes: Add external pull-down if not
used1
Desc: USB1 Data +
Notes: Add external pull-down if not
used1
Desc: USB1 Bus Voltage
Notes: Connect to GND if not used1
Desc: USB0/USB1 Clock/Crystal
Input
Notes: Services both USB0 and
USB1. Connect to GND if not used.1
Desc: USB0/USB1 Crystal
Notes: Services both USB0 and USB1
Desc: DMC VDD
Notes: No notes
Desc: External Voltage Domain
Notes: No notes
Desc: HADC/TMU VDD
Notes: Can be left floating if HADC
and TMU are not used
Desc: Internal Voltage Domain
Notes: No notes
Desc: PCIE Supply Voltage
Notes: Connect to GND if not used1, 2
Desc: PCIE RX Supply Voltage
Notes: Connect to GND if not used1, 2
Desc: PCIE TX Supply Voltage
Notes: Connect to GND if not used1, 2
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 27. ADSP-SC58x/ADSP-2158x Designer Quick Reference (Continued)
1
2
Signal Name
VDD_RTC
Type
s
Driver
Type
NA
Internal
Term
none
Reset
Term
none
Reset
Drive
none
VDD_USB
s
NA
none
none
none
Power Domain
Guidance also applies to models that do not feature the associated hardware block. See Table 2 or Table 3 for further information.
For boundary scan to work, PCIE power supplies must be connected as per Specifications.
Rev. B |
Page 78 of 173 |
December 2018
Description and Notes
Desc: RTC VDD
Notes: No notes
Desc: USB VDD
Notes: Connect to VDD_EXT when
USB is not used
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SPECIFICATIONS
Specifications are subject to change without notice. For information about product specifications, contact your Analog Devices, Inc.,
representative.
OPERATING CONDITIONS
Parameter
Internal (Core) Supply Voltage
Conditions
Min
Nominal
Max
Unit
CCLK ≤ 450 MHz
CCLK ≤ 500 MHz
1.05
1.10
3.13
3.13
1.7
1.425
3.13
2.0
1.05
1.05
3.13
0.49 × VDD_DMC
2.5
0
2.0
0.7 × VBUSTWI
1.10
1.15
3.3
3.3
1.8
1.5
3.3
3.3
1.1
1.1
3.3
0.50 × VDD_DMC
3.30
1.15
1.20
3.47
3.47
1.9
1.575
3.47
3.60
1.15
1.15
3.47
0.51 × VDD_DMC
VDD_HADC
VHADC_REF + 0.2
External (I/O) Supply Voltage
Analog Power Supply Voltage
DDR2/LPDDR Controller Supply Voltage
DDR3 Controller Supply Voltage
USB Supply Voltage
VDD_USB2
RTC Voltage
VDD_RTC
VDD_PCIE_TX PCIe Core Transmit Voltage
VDD_PCIE_RX PCIe Core Receive Voltage
PCIe Voltage
VDD_PCIE
VDDR_VREF3 DDR2/DDR3 Reference Voltage
VHADC_REF4 HADC Reference Voltage
VHADC0_VINx HADC Input Voltage
VIH5
High Level Input Voltage
6, 7
High Level Input Voltage
VIHTWI
VDD_EXT = 3.47 V
VDD_EXT = 3.47 V
VBUSTWI
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VIL5
VILTWI6, 7
Low Level Input Voltage
Low Level Input Voltage
VDD_EXT = 3.13 V
VDD_EXT = 3.13 V
0.8
0.3 × VBUSTWI
V
V
VIL_DDR28
VIL_DDR38
VIH_DDR28
VIH_DDR38
VIL_LPDDR9
VIH_LPDDR9
TJ
Low Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Voltage
Junction Temperature 349-Lead CSP_BGA
0.8 × VDD_DMC
0
VDDR_VREF – 0.25 V
VDDR_VREF – 0.175 V
V
V
0.2 × VDD_DMC
V
V
100
°C
TJ
Junction Temperature 349-Lead CSP_BGA
–40
+110
°C
TJ
Junction Temperature 349-Lead CSP_BGA
–40
+125
°C
TJ
Junction Temperature 529-Lead CSP_BGA
0
110
°C
TJ
Junction Temperature 529-Lead CSP_BGA
–40
+125
°C
TJ
Junction Temperature 349-Lead CSP_BGA
0
105
°C
TJ
Junction Temperature 349-Lead CSP_BGA
–40
+120
°C
TJ
Junction Temperature 349-Lead CSP_BGA
–40
+125
°C
TJ
Junction Temperature 529-Lead CSP_BGA
0
115
°C
TJ
Junction Temperature 529-Lead CSP_BGA
VDD_DMC = 1.7 V
VDD_DMC = 1.425 V
VDD_DMC = 1.9 V
VDD_DMC = 1.575 V
VDD_DMC = 1.7 V
VDD_DMC = 1.9 V
TAMBIENT = 0°C to 70°C
CCLK ≤ 450 MHz
TAMBIENT = –40°C to +85°C
CCLK ≤ 450 MHz
TAMBIENT = –40°C to +95°C
CCLK ≤ 450 MHz
TAMBIENT = 0°C to 70°C
CCLK ≤ 450 MHz
TAMBIENT = –40°C to +85°C
CCLK ≤ 450 MHz
TAMBIENT = 0°C to 70°C
CCLK ≤ 500 MHz
TAMBIENT = –40°C to +85°C
CCLK ≤ 500 MHz
TAMBIENT = –40°C to +90°C
CCLK ≤ 500 MHz
TAMBIENT = 0°C to 70°C
CCLK ≤ 500 MHz
TAMBIENT = –40°C to +80°C
CCLK ≤ 500 MHz
–40
+125
°C
VDD_INT
VDD_EXT
VDD_HADC
VDD_DMC1
Rev. B |
Page 79 of 173 |
VDDR_VREF + 0.25
VDDR_VREF + 0.175
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Parameter
Conditions
Min
AUTOMOTIVE USE ONLY
Junction Temperature 349-Lead CSP_BGA
TJ
(Automotive Grade)10
Junction Temperature 529-Lead CSP_BGA
TJ
(Automotive Grade)10
Junction Temperature 349-Lead CSP_BGA
TJ
(Automotive Grade)10
TJ
Junction Temperature 529-Lead CSP_BGA
(Automotive Grade)10
TAMBIENT = –40°C to +105°C
CCLK ≤ 450 MHz
TAMBIENT = –40°C to +90°C
CCLK ≤ 450 MHz
TAMBIENT = –40°C to +100°C
CCLK ≤ 500 MHz
TAMBIENT = –40°C to +85°C
CCLK ≤ 500 MHz
Nominal
Max
Unit
–40
+133
°C
–40
+133
°C
–40
+133
°C
–40
+133
°C
1
Applies to DDR2/DDR3/LPDDR signals.
If not used, VDD_USB must be connected to 3.3 V.
3
Applies to DMC0_VREF and DMC1_VREF pins.
4
VHADC_VREF must always be less than VDD_HADC.
5
Parameter value applies to all input and bidirectional pins except the TWI, DMC, USB, PCIe, and MLB pins.
6
Parameter applies to TWI signals.
7
TWI signals are pulled up to VBUSTWI. See Table 28.
8
This parameter applies to all DMC0/1 signals in DDR2/DDR3 mode.
9
This parameter applies to DMC0/1 signals in LPDDR mode.
10
Automotive application use profile only. Not supported for nonautomotive use. Contact Analog Devices for more information.
2
Table 28. TWIxVSEL1 Settings and VDD_EXT/VBUSTWI
VBUSTWI
TWIxVSEL
0
1
1
2
2
VDD_EXT Nominal
Min
Nominal
Max
Unit
3.30
3.13
3.30
4.75
3.30
3.47
V
5.00
5.25
V
TWIxVSEL are the TWI voltage select bits in the PADS_PCFG0 register. See the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference.
Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWIxVSEL setting for correct JTAG boundary scan operation during reset.
Rev. B |
Page 80 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Clock Related Operating Conditions
Table 29 describes the core clock, system clock, and peripheral clock timing requirements. The data presented in the table applies to all
speed grades except where noted.
Table 29. Clock Operating Conditions
Parameter
fCCLK
Core Clock Frequency
Restriction
Min
fCCLK ≥ fSYSCLK
Typ
Max
Unit
100
500
MHz
250
MHz
30
125
MHz
125
MHz
1
fSYSCLK
SYSCLK Frequency
fSCLK0
SCLK0 Frequency2
fSYSCLK ≥ fSCLK0
fSCLK1
SCLK1 Frequency
fSYSCLK ≥ fSCLK1
fDCLK
LPDDR Clock Frequency
200
MHz
fDCLK
DDR2 Clock Frequency
400
MHz
fDCLK
DDR3 Clock Frequency
450
MHz
250
MHz
fOCLK
Output Clock Frequency
3
fSYS_CLKOUTJ SYS_CLKOUT Period Jitter
4, 5
±2
%
fPCLKPROG
Programmed PPI Clock When Transmitting Data and Frame Sync
75
MHz
fPCLKPROG
Programmed PPI Clock When Receiving Data or Frame Sync
45
MHz
fPCLKEXT ≤ fSCLK1
75
MHz
fPCLKEXT ≤ fSCLK1
45
MHz
150
MHz
fPCLKEXT
External PPI Clock When Receiving Data and Frame Sync
fPCLKEXT
External PPI Clock Transmitting Data or Frame Sync6, 7
fLCLKTPROG
Programmed Link Port Transmit Clock
fLCLKREXT
External Link Port Receive Clock
6, 7
6, 7
150
MHz
fSPTCLKPROG Programmed SPT Clock When Transmitting Data and Frame Sync
fLCLKEXT ≤ fCLKO8
62.5
MHz
fSPTCLKPROG Programmed SPT Clock When Receiving Data or Frame Sync
31.25
MHz
fSPTCLKEXT
External SPT Clock When Receiving Data and Frame Sync
fSPTCLKEXT
External SPT Clock Transmitting Data or Frame Sync6, 7
fSPICLKPROG
Programmed SPI Clock When Transmitting Data
fSPICLKPROG
Programmed SPI Clock When Receiving Data
fSPICLKEXT
External SPI Clock When Receiving Data6, 7
fSPICLKEXT
External SPI Clock When Transmitting Data
fACLKPROG
Programmed ACM Clock
6, 7
6, 7
fSPTCLKEXT ≤ fSCLK0
62.5
MHz
fSPTCLKEXT ≤ fSCLK0
31.25
MHz
75
MHz
75
MHz
fSPICLKEXT ≤ fSCLK1
75
MHz
fSPICLKEXT ≤ fSCLK1
45
MHz
62.5
MHz
1
When using MLB, there is a requirement that the fSYSCLK value must be a minimum of 100 MHz for both 3-pin and 6-pin modes and for all supported speeds.
The minimum frequency for SCLK0 applies only when using the USB.
3
fOCLK must not exceed fSCLK0 when selected as SYS_CLKOUT.
4
SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source. Due
to the dependency on these factors, the measured jitter may be higher or lower than this typical specification for each end application.
5
The value in the Typ field is the percentage of the SYS_CLKOUT period.
6
The maximum achievable frequency for any peripheral in external clock mode is dependent on the ability to meet the setup and hold times in the ac timing specifications
section for that peripheral.
7
The peripheral external clock frequency must also be less than or equal to the fSCLK (fSCLK0 or fSCLK1) that clocks the peripheral.
2
Rev. B |
Page 81 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 30. Phase-Locked Loop (PLL) Operating Conditions
Parameter
fPLLCLK
Min
200
PLL Clock Frequency
CSEL
(1-31)
SYSSEL
(1-31)
SYS_CLKIN
PLL
Max
1000
CCLK
S0SEL
(1-7)
SCLK0
S1SEL
(1-7)
SCLK1
SYSCLK
PLLCLK
DSEL
(1-31)
DCLK
OSEL
(1-127)
OUTCLK
Figure 8. Clock Relationships and Divider Values
Rev. B |
Page 82 of 173 |
December 2018
Unit
MHz
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ELECTRICAL CHARACTERISTICS
Parameter
1
VOH
VOL1
VOH_DDR23
VOL_DDR23
VOH_DDR23
VOL_DDR23
VOH_DDR34
VOL_DDR34
VOH_DDR34
VOL_DDR34
VOH_LPDDR5
VOL_LPDDR5
IIH6, 7
IIL6
IIL_PU7
IIH_PD8
IOZH9
IOZL9
CIN10
IDD_IDLE
Conditions
Min
2
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
for DDR2 DS = 40 Ω
Low Level Output Voltage
for DDR2 DS = 40 Ω
High Level Output Voltage
for DDR2 DS = 60 Ω
Low Level Output Voltage
for DDR2 DS = 60 Ω
High Level Output Voltage
for DDR3 DS = 40 Ω
At VDD_EXT = minimum, IOH = –1.0 mA
At VDD_EXT = minimum, IOL = 1.0 mA2
At VDD_DDR = minimum, IOH = –5.8 mA
Low Level Output Voltage
for DDR3 DS = 40 Ω
High Level Output Voltage
for DDR3 DS = 60 Ω
Low Level Output Voltage
for DDR3 DS = 60 Ω
High Level Output Voltage
for LPDDR
Low Level Output Voltage
for LPDDR
High Level Input Current
At VDD_DDR = minimum, IOL = 5.8 mA
Low Level Input Current
Low Level Input Current
Pull-Up
High Level Input Current
Pull-Down
Three-State Leakage
Current
Three-State Leakage
Current
Input Capacitance
VDD_INT Current in Idle
Typ
At VDD_DDR = minimum, IOH = –3.4 mA
V
V
V
0.32
V
1.38
V
0.32
1.105
V
V
0.32
1.105
V
V
At VDD_DDR = minimum, IOL = 3.4 mA
At VDD_DDR = minimum, IOH = –6.0 mA
0.4
1.38
At VDD_DDR = minimum, IOL = 3.4 mA
At VDD_DDR = minimum, IOH = –5.8 mA
Unit
2.4
At VDD_DDR = minimum, IOL = 5.8 mA
At VDD_DDR = minimum, IOH = –3.4 mA
Max
0.32
1.38
V
V
At VDD_DDR = minimum, IOL = 6.0 mA
0.32
V
At VDD_EXT = maximum,
VIN = VDD_EXT maximum
At VDD_EXT = maximum, VIN = 0 V
At VDD_EXT = maximum, VIN = 0 V
10
μA
10
200
μA
μA
At VDD_EXT = maximum, VIN = VDD_EXT
maximum
At VDD_EXT/VDD_DDR = maximum,
VIN = VDD_EXT/VDD_DDR maximum
at VDD_EXT/VDD_DDR = maximum,
VIN = 0 V
TCASE = 25°C
fCCLK = 450 MHz
ASFSHARC1 = 0.31
ASFSHARC2 = 0.31
ASFA5 = 0.29
fSYSCLK = 225 MHz
fSCLK0/1 = 112.5 MHz
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.1 V
200
μA
10
μA
10
μA
Rev. B |
Page 83 of 173 |
December 2018
5
495
pF
mA
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Parameter
Conditions
IDD_IDLE
VDD_INT Current in Idle
IDD_TYP
VDD_INT Current
IDD_TYP
VDD_INT Current
IDD_INT11
VDD_INT Current
Min
fCCLK = 500 MHz
ASFSHARC1 = 0.31
ASFSHARC2 = 0.31
ASFA5 = 0.29
fSYSCLK = 250 MHz
fSCLK0/1 = 125 MHz
(Other clocks are disabled)
No peripheral or DMA activity
TJ = 25°C
VDD_INT = 1.15 V
fCCLK = 450 MHz
ASFSHARC1 = 1.0
ASFSHARC2 = 1.0
ASFA5 = 0.73
fSYSCLK = 225 MHz
fSCLK0/1 = 112.5 MHz
(Other clocks are disabled)
FFT accelerator operating at fSYSCLK/4
DMA data rate = 600 Mbps
TJ = 25°C
VDD_INT = 1.1 V
fCCLK = 500 MHz
ASFSHARC1 = 1.0
ASFSHARC2 = 1.0
ASFA5 = 0.73
fSYSCLK = 250 MHz
fSCLK0/1 = 125 MHz
(Other clocks are disabled)
FFT accelerator operating at fSYSCLK/4
DMA data rate = 600 Mbps
TJ = 25°C
VDD_INT = 1.15 V
fCCLK 0 MHz
fSCLK0/1 0 MHz
1
Typ
Max
Unit
575
mA
1112
mA
1185
mA
See IDD_INT_TOT mA
equation in the
Total Internal
Power Dissipation section
Applies to all output and bidirectional pins except TWI, DMC, USB, PCIe, and MLB.
See the Output Drive Currents section for typical drive current capabilities.
3
Applies to all DMC output and bidirectional signals in DDR2 mode.
4
Applies to all DMC output and bidirectional signals in DDR3 mode.
5
Applies to all DMC output and bidirectional signals in LPDDR mode.
6
Applies to input pins SYS_BMODE0-2, SYS_CLKIN0, SYS_CLKIN1, SYS_HWRST, JTG_TDI, JTG_TMS, and USB0_CLKIN.
7
Applies to input pins with internal pull-ups including JTG_TDI, JTG_TMS, and JTG_TCK.
8
Applies to signals JTAG_TRST, USB0_VBUS, USB1_VBUS.
9
Applies to signals PA0-15, PB0-15, PC0-15, PD0-15, PE0-15, PF0-15, PG0-5, DAI0_PINx, DAI1_PINx, DMC0_DQx, DMC0_LDQS, DMC0_UDQS, DMC0_LDQS,
DMC0_UDQS, SYS_FAULT, SYS_FAULT, JTG_TDO, USB0_ID, USBx_DM, USBx_DP, and USBx_VBC.
10
Applies to all signal pins.
11
See Estimating Power for ADSP-SC58x/2158x SHARC+ Processors (EE-392) for further information.
2
Rev. B |
Page 84 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Total Internal Power Dissipation
Application Dependent Current
Total power dissipation has two components:
The application dependent currents include the dynamic current in the core clock domain of the two SHARC+ cores and the
Arm Cortex-A5 core, as well as the dynamic current in the
accelerator block.
• Static, including leakage current
• Dynamic, due to transistor switching characteristics for
each clock domain
Many operating conditions can affect power dissipation, including temperature, voltage, operating frequency, and processor
activity. The following equation describes the internal current
consumption.
IDD_INT_TOT = IDD_INT_STATIC + IDD_INT_CCLK_SHARC1_DYN +
IDD_INT_CCLK_SHARC2_DYN + IDD_INT_CCLK_A5_DYN +
IDD_INT_DCLK_DYN + IDD_INT_SYSCLK_DYN +
IDD_INT_SCLK0_DYN + IDD_INT_SCLK1_DYN +
IDD_INT_OCLK_DYN + IDD_INT_ACCL_DYN +
IDD_INT_USB_DYN + IDD_INT_MLB_DYN +
IDD_INT_EMAC_DYN + IDD_INT_DMA_DR_DYN +
IDD_INT_PCIE_DYN
IDD_INT_STATIC is the sole contributor to the static power dissipation component and is specified as a function of voltage
(VDD_INT) and junction temperature (TJ) in Table 31.
Table 31. Static Current—IDD_INT_STATIC (mA)
Voltage (VDD_INT)
TJ (°C)
1.05
1.10
1.15
1.20
–40
7
8
10
12
–20
12
14
17
21
–10
16
19
23
27
Dynamic current consumed by the core is subject to an activity
scaling factor (ASF) that represents application code running on
the processor cores (see Table 32 and Table 33). The ASF is
combined with the CCLK frequency and VDD_INT dependent
dynamic current data in Table 34 and Table 35, respectively, to
calculate this portion of the total dynamic power dissipation
component.
IDD_INT_CCLK_SHARC1_DYN = Table 34 × ASFSHARC1
IDD_INT_CCLK_SHARC2_DYN = Table 34 × ASFSHARC2
IDD_INT_CCLK_A5_DYN = Table 35 × ASFA5
Table 32. Activity Scaling Factors for the SHARC+ Core1 and
Core2 (ASFSHARC1 and ASFSHARC2)
IDD_INT Power Vector
ASF
IDD-IDLE
0.31
IDD-NOP
0.53
IDD-TYP_3070
0.74
IDD-TYP_5050
0.87
IDD-TYP_7030
1.00
IDD-PEAK_100
1.14
Table 33. Activity Scaling Factors for the Arm Cortex-A5
Core (ASFA5)
+0
21
25
30
35
+10
28
33
39
46
IDD_INT Power Vector
ASF
+25
42
49
58
67
IDD-IDLE
0.29
+40
63
73
84
98
IDD-DHRYSTONE
0.73
+55
92
106
122
141
IDD-TYP_2575
0.57
+70
133
152
175
200
IDD-TYP_5050
0.80
+85
190
216
247
282
IDD-TYP_7525
1.00
+100
269
305
346
393
IDD-PEAK_100
1.21
+105
302
342
387
439
+115
376
425
480
544
+125
466
525
592
669
+133
552
621
700
789
The other 14 addends in the IDD_INT_TOT equation comprise the
dynamic power dissipation component and fall into four broad
categories: application-dependent currents, clock currents, currents from high speed peripheral operation, and data
transmission currents.
Rev. B |
Page 85 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Clock Current
Table 34. Dynamic Current for Each SHARC+ Core
(mA, with ASF = 1.00)1
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT),
operating frequency, and a unique scaling factor.
Voltage (VDD_INT)
1
fCCLK (MHz)
1.05
1.10
1.15
1.20
500
N/A
374
391
408
450
321
337
352
367
400
286
299
313
326
IDD_INT_SCLK0_DYN (mA) = 0.44 × fSCLK0 (MHz) × VDD_INT (V)
IDD_INT_SYSCLK_DYN (mA) = 0.78 × fSYSCLK (MHz) ×
VDD_INT (V)
350
250
262
274
286
IDD_INT_SCLK1_DYN (mA) = 0.06 × fSCLK1 (MHz) × VDD_INT (V)
300
214
224
235
245
IDD_INT_DCLK_DYN (mA) = 0.14 × fDCLK (MHz) × VDD_INT (V)
250
179
187
196
204
IDD_INT_OCLK_DYN (mA) = 0.02 × fOCLK (MHz) × VDD_INT (V)
200
143
150
156
163
Current from High Speed Peripheral Operation
150
107
112
117
122
100
71
75
78
82
The following modules contribute significantly to power dissipation, and a single term is added when the modules are used.
IDD_INT_USB_DYN = 20 mA (if both USBs are enabled in HS
mode)
N/A means not applicable.
Table 35. Dynamic Current for the Arm Cortex-A5 Core
(mA, with ASF = 1.00)1
IDD_INT_EMAC_DYN = 10 mA (if EMAC is enabled)
IDD_INT_PCIE_DYN = 240 mA (if PCIe is enabled in 5 Gbps mode)
Voltage (VDD_INT)
1
IDD_INT_MLB_DYN = 10 mA (if MLB 6-pin interface is enabled)
fCCLK (MHz)
1.05
1.10
1.15
1.20
Data Transmission Current
500
N/A
83
86
90
450
71
74
78
81
400
63
66
69
72
350
55
58
60
63
300
47
50
52
54
The data transmission current represents the power dissipated
when moving data throughout the system via direct memory
access (DMA). This current is proportional to the data rate.
Refer to the power calculator available with Estimating Power
for ADSP-SC58x/2158x SHARC+ Processors (EE-392) to estimate IDD_INT_DMA_DR_DYN based on the bandwidth of the data
transfer.
250
39
41
43
45
200
32
33
35
36
150
24
25
26
27
100
16
17
18
19
N/A means not applicable.
The following equation is used to compute the power dissipation when the FFT accelerator is used:
IDD_INT_ACCL_DYN (mA) = ASFACCL × fSYSCLK (MHz) ×
VDD_INT (V)
Table 36. Activity Scaling Factors for the FFT Accelerator
(ASFACCL)
IDD_INT Power Vector
ASFACCL
Unused
0.0
IDD-TYP
0.32
Rev. B |
Page 86 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
HADC
HADC Timing Specifications
HADC Electrical Characteristics
Table 39. HADC Timing Specifications
Table 37. HADC Electrical Characteristics
Parameter
IDD_HADC_IDLE
IDD_HADC_ACTIVE
Conditions
Current consumption on
VDD_HADC.
HADC is powered on, but not
converting.
Current consumption on
VDD_HADC during a conversion.
Typ Unit
2.0 mA
Parameter
Conversion Time
Throughput Range
TWAKEUP
Typ
20 × TSAMPLE
Max
1
100
Unit
μs
MSPS
μs
TMU
2.5 mA
IDD_HADC_POWERDOWN Current consumption on
10
VDD_HADC.
Analog circuitry of the HADC is
powered down.
μA
TMU Characteristics
Table 40. TMU Characteristics
Parameter
Resolution
Accuracy
Typ
1
±6
Unit
°C
°C
HADC DC Accuracy
Table 41. TMU Gain and Offset
Table 38. HADC DC Accuracy1
Parameter
Resolution
No Missing Codes (NMC)
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Gain Error
Gain Error Matching
1
2
Typ
12
10
±2
±2
±8
±10
±4
±4
Unit
Bits
Bits
LSB
LSB
LSB
LSB
LSB
LSB
2
Junction Temperature Range
–40°C to +40°C
40°C to 85°C
85°C to 133°C
See the Operating Conditions section for the HADC0_VINx specification.
LSB = HADC0_VREFP ÷ 4096.
Rev. B |
Page 87 of 173 |
December 2018
TMU_GAIN
TMU_OFFSET
Contact Analog Devices, Inc.
Contact Analog Devices, Inc.
Contact Analog Devices, Inc.
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ABSOLUTE MAXIMUM RATINGS
ESD CAUTION
Stresses at or above those listed in Table 42 may cause permanent damage to the product. This is a stress rating only;
functional operation of the product at these or any other conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 42. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDD_INT)
External (I/O) Supply Voltage (VDD_EXT)
DDR2/LPDDR Controller Supply Voltage
(VDD_DMC)
DDR3 Controller Supply Voltage
(VDD_DMC)
USB PHY Supply Voltage (VDD_USB)
Real-Time Clock Supply Voltage (VDD_RTC)
PCIe Transmit Supply Voltage (VDD_PCIE_TX)
PCIe Receive Supply Voltage (VDD_PCIE_RX)
PCIe Supply Voltage (VDD_PCIE)
HADC Supply Voltage (VDD_HADC)
HADC Reference Voltage (VHADC_REF)
DDR2/LPDDR Input Voltage1
DDR2 Reference Voltage (VDDR_VREF)
DDR3 Input Voltage1
Digital Input Voltage1, 2
TWI Input Voltage1, 3
USB0_Dx Input Voltage1, 4
USB0_VBUS Input Voltage1, 4
Output Voltage Swing
Analog Input Voltage5
IOH/IOL Current per Signal2
Storage Temperature Range
Junction Temperature While Biased
Rating
–0.33 V to +1.26 V
–0.33 V to +3.60 V
–0.33 V to +1.90 V
–0.33 V to +1.60 V
–0.33 V to +3.60 V
–0.33 V to +3.60 V
–0.33 V to +1.20 V
–0.33 V to +1.20 V
–0.33 V to +3.60 V
–0.33 V to +3.60 V
–0.33 V to +3.60 V
–0.33 V to +1.90 V
–0.33 V to +1.90 V
–0.33 V to +1.60 V
–0.33 V to +3.60 V
–0.33 V to +5.50 V
–0.33 V to +5.25 V
–0.33 V to +6 V
–0.33 V to VDD_EXT +0.5 V
–0.2 V to VDD_HADC +0.2 V
6 mA (maximum)
–65C to +150C
133C
1
Applies only when the related power supply (VDD_DMC, VDD_EXT, or VDD_USB) is within
specification. When the power supply is below specification, the range is the voltage
being applied to that power domain ± 0.2 V.
2
Applies to 100% transient duty cycle.
3
Applies to TWI_SCL and TWI_SDA.
4
If the USB is not used, connect these pins according to Table 27.
5
Applies only when VDD_HADC is within specifications and ≤ 3.4 V. When VDD_HADC is
within specifications and > 3.4 V, the maximum rating is 3.6 V. When VDD_HADC is
below specifications, the range is VDD_HADC ± 0.2 V.
Rev. B |
Page 88 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
TIMING SPECIFICATIONS
Power-Up Reset Timing
Table 43 and Figure 9 show the relationship between power supply startup and processor reset timing, related to the clock generation unit
(CGU) and reset control unit (RCU).
In Figure 9, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_HADC, VDD_RTC, VDD_PCI_TX, VDD_PCI_RX, and VDD_PCI_CORE.
Table 43. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT, VDD_EXT, VDD_DMC, VDD_USB,
VDD_HADC, VDD_RTC, VDD_PCI_TX, VDD_PCI_RX, VDD_PCI_CORE) and SYS_CLKINx are
Stable and Within Specification
11 × tCKIN
SYS_HWRST
tRST_IN_PWR
SYS_CLKIN0/1
V
DD_SUPPLIES
NOTE: V
REFER TO V
,V
,V
,V
,V
,V
,V
,V
, AND V
.
DD_SUPPLIES
DD_INT DD_EXT DD_DMC DD_USB DD_HADC DD_RTC DD_PCI_TX DD_PCI_RX
DD_PCI_CORE
Figure 9. Power-Up Reset Timing
Rev. B |
Page 89 of 173 |
December 2018
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Clock and Reset Timing
Table 44 and Figure 10 describe clock and reset operations related to the CGU and RCU. Per the CCLK, SYSCLK, SCLK, DCLK, and
OCLK timing specifications in Table 29, combinations of SYS_CLKIN and clock multipliers must not select clock rates in excess of the
maximum instruction rate of the processor.
Table 44. Clock and Reset Timing
Parameter
Min
Max
Unit
20
50
MHz
20
50
MHz
Timing Requirements
fCKIN
SYS_CLKINx Frequency (Crystal)1, 2, 3
SYS_CLKINx Frequency (External CLKIN)
tCKINL
1, 2, 3
CLKIN Low Pulse1
1
tCKINH
CLKIN High Pulse
tWRST
RESET Asserted Pulse Width Low4
10
ns
10
ns
11 × tCKIN
ns
1
Applies to PLL bypass mode and PLL nonbypass mode.
The tCKIN period (see Figure 10) equals 1/fCKIN.
3
If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz.
4
Applies after power-up sequence is complete. See Table 43 and Figure 9 for power-up reset timing.
2
fCKIN
SYS_CLKIN0/1
tCKINL
tCKINH
tWRST
SYS_HWRST
Figure 10. Clock and Reset Timing
Rev. B |
Page 90 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Asynchronous Read
Table 45 and Figure 11 show asynchronous memory read timing, related to the SMC.
Table 45. Asynchronous Read
Parameter
Min
Max
Unit
Timing Requirements
tSDATARE
DATA in Setup Before SMC0_ARE High
5.1
ns
tHDATARE
DATA in Hold After SMC0_ARE High
0.7
ns
tDARDYARE
SMC0_ARDY Valid After SMC0_ARE Low1, 2
(RAT – 2.5) × tSCLK0 – 17.5
ns
Switching Characteristics
tAMSARE
ADDR/SMC0_AMSx Assertion Before SMC0_ARE (PREST + RST + PREAT) × tSCLK0 – 2
Low3
ns
tAOEARE
SMC0_AOE Assertion Before SMC0_ARE Low
ns
4
(RST + PREAT) × tSCLK0 – 2
5
tHARE
Output Hold After SMC0_ARE High
RHT × tSCLK0 –2
ns
tWARE
SMC0_ARE Active Low Width6
RAT × tSCLK0 – 2
ns
tDAREARDY
SMC0_ARE High Delay After SMC0_ARDY
Assertion1
2.5 × tSCLK0
3.5 × tSCLK0 + 17.5
1
SMC0_BxCTL.ARDYEN bit = 1.
RAT value set using the SMC_BxTIM.RAT bits.
3
PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
2
SMC0_ARE
SMC0_AMSx
tWARE
tHARE
tAMSARE
SMC0_Ax
tAOEARE
SMC0_AOE
tDARDYARE
tDAREARDY
SMC0_ARDY
tSDATARE
SMC0_Dx (DATA)
Figure 11. Asynchronous Read
Rev. B |
Page 91 of 173 |
December 2018
tHDATARE
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SMC Read Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications (Table 46 and Figure 12) with respect to SYS_CLKOUT are given to accommodate the connection of
the SMC to programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3.
Table 46. SMC Read Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
SMC0_Dx Setup Before SYS_CLKOUT
4.3
ns
tHDAT
SMC0_Dx Hold After SYS_CLKOUT
5
ns
tSARDY
SMC0_ARDY Setup Before SYS_CLKOUT
14.4
ns
tHARDY
SMC0_ARDY Hold After SYS_CLKOUT
0.7
ns
Switching Characteristics
tDO
Output Delay After SYS_CLKOUT1
tHO
1
1
Output Hold After SYS_CLKOUT
7
ns
–2.5
ns
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE, and SMC0_ABEx.
SETUP
CYCLES
PROGRAMMED READ
ACCESS CYCLES
ACCESS EXTENDED
CYCLES
HOLD
CYCLE
SYS_CLKOUT
tDO
tHO
SMC0_AMSx
SMC0_ABEx
SMC0_Ax
SMC0_AOE
tDO
tHO
SMC0_ARE
tSARDY
tHARDY
SMC0_ARDY
tSARDY
tHARDY
DATA 15–0
Figure 12. Asynchronous Memory Read Cycle Timing
Rev. B |
Page 92 of 173 |
December 2018
tSDAT
tHDAT
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Asynchronous Flash Read
Table 47 and Figure 13 show asynchronous flash memory read timing, related to the SMC.
Table 47. Asynchronous Flash Read
Parameter
Min
Max
Unit
Switching Characteristics
tAMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV Low1
PREST × tSCLK0 – 2
ns
tWADV
SMC0_NORDV Active Low Width2
RST × tSCLK0 – 2
ns
PREAT × tSCLK0 – 2
ns
RHT × tSCLK0 – 2
ns
RAT × tSCLK0 – 2
ns
tDADVARE
SMC0_ARE Low Delay From SMC0_NORDV High
tHARE
Output4 Hold After SMC0_ARE High5
6
tWARE
SMC0_ARE Active Low Width
3
7
1
PREST value set using the SMC_BxETIM.PREST bits.
RST value set using the SMC_BxTIM.RST bits.
3
PREAT value set using the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
7
RAT value set using the SMC_BxTIM.RAT bits.
2
SMC0_Ax
(NOR_Ax)
SMC0_AMSx
(NOR_CE)
tAMSADV
tWADV
SMC0_AOE
(NOR_ADV)
tDADVARE
tWARE
tHARE
SMC0_ARE
(NOR_OE)
SMC0_Dx
(NOR_Dx)
READ LATCHED
DATA
Figure 13. Asynchronous Flash Read
Rev. B |
Page 93 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Asynchronous Page Mode Read
Table 48 and Figure 14 show asynchronous memory page mode read timing, related to the SMC.
Table 48. Asynchronous Page Mode Read
Parameter
Min
Max
Unit
Switching Characteristics
tAV
SMC0_Axx (Address) Valid for First Address Minimum Width1
tAV1
SMC0_Axx (Address) Valid for Subsequent SMC0_Ax (Address) PGWS × tSCLK0 – 2
Minimum Width
tWADV
SMC0_NORDV Active Low Width2
RST × tSCLK0 – 2
ns
tHARE
Output3 Hold After SMC0_ARE High4
RHT × tSCLK0 – 2
ns
tWARE5
SMC0_ARE Active Low Width6, 7
(RAT + (Nw – 1) × PGWS) × tSCLK0 – 2
ns
(PREST + RST + PREAT + RAT) × tSCLK0 – 2
ns
ns
1
PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
2
RST value set using the SMC_BxTIM.RST bits.
3
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4
RHT value set using the SMC_BxTIM.RHT bits.
5
SMC_BxCTL.ARDYEN bit = 0.
6
RAT value set using the SMC_BxTIM.RAT bits.
7
Nw = Number of 16-bit data words read.
READ
LATCHED
DATA
SMC0_Ax
(NOR_Ax)
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
tAV
tAV1
tAV1
tAV1
A0
A0 + 1
A0 + 2
A0 + 3
SMC0_AMSx
(NOR_CE)
SMC0_AOE
NOR_ADV
tWADV
tWARE
SMC0_ARE
(NOR_OE)
tHARE
SMC0_Dx
(NOR_Dx)
D0
D1
Figure 14. Asynchronous Page Mode Read
Rev. B |
Page 94 of 173 |
December 2018
D2
D3
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Asynchronous Write
Table 49 and Figure 15 show asynchronous memory write timing, related to the SMC.
Table 49. Asynchronous Memory Write
Parameter
Min
Max
Unit
Timing Requirement
tDARDYAWE1
SMC0_ARDY Valid After SMC0_AWE Low 2
(WAT – 2.5) × tSCLK0 – 17.5 ns
Switching Characteristics
tENDAT
DATA Enable After SMC0_AMSx Assertion
tDDAT
DATA Disable After SMC0_AMSx Deassertion
tAMSAWE
ADDR/SMC0_AMSx Assertion Before SMC0_AWE Low3 (PREST + WST + PREAT) × tSCLK0 – 2
4
–3.5
ns
2.5
5
ns
ns
tHAWE
Output Hold After SMC0_AWE High
WHT × tSCLK0 – 3.5
ns
tWAWE6
SMC0_AWE Active Low Width2
WAT × tSCLK0 – 2
ns
tDAWEARDY1
SMC0_AWE High Delay After SMC0_ARDY Assertion
2.5 × tSCLK0
3.5 × tSCLK0 + 17.5
1
SMC_BxCTL.ARDYEN bit = 1.
2
WAT value set using the SMC_BxTIM.WAT bits.
3
PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
SMC0_AWE
SMC0_ABEx
SMC0_Ax
(ADDRESS)
tAMSAWE
tWAWE
tHAWE
SMC0_ARDY
tDARDYAWE
tDAWEARDY
SMC0_AMSx
SMC0_Dx (DATA)
tDDAT
tENDAT
Figure 15. Asynchronous Write
Rev. B |
Page 95 of 173 |
December 2018
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SMC Write Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications (Table 50 and Figure 16) with respect to SYS_CLKOUT are given to accommodate the connection of
the SMC to programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3.
Table 50. SMC Write Cycle Timing With Reference to SYS_CLKOUT (BxMODE = b#00)
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
SMC0_ARDY Setup Before SYS_CLKOUT
14.4
ns
tHARDY
SMC0_ARDY Hold After SYS_CLKOUT
0.7
ns
Switching Characteristics
tDDAT
SMC0_Dx Disable After SYS_CLKOUT
tENDAT
SMC0_Dx Enable After SYS_CLKOUT
tDO
Output Delay After SYS_CLKOUT1
tHO
1
1
Output Hold After SYS_CLKOUT
7
–2.5
7
–2.5
Output pins/balls include SMC0_AMSx, SMC0_ABEx, SMC0_Ax, SMC0_Dx, SMC0_AOE, and SMC0_AWE.
PROGRAMMED
WRITE
ACCESS
ACCESS
EXTEND HOLD
CYCLES
CYCLE CYCLE
SETUP
CYCLES
SYS_CLKOUT
tDO
tHO
SMC0_AMSx
SMC0_ABEx
SMC0_Ax
tHO
tDO
SMC0_AWE
tSARDY
tHARDY
SMC0_ARDY
tENDAT
tSARDY
tHARDY
tDDAT
SMC0_Dx
Figure 16. SMC Write Cycle Timing With Reference to SYS_CLKOUT Timing
Rev. B |
Page 96 of 173 |
December 2018
ns
ns
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Asynchronous Flash Write
Table 51 and Figure 17 show asynchronous flash memory write timing, related to the SMC.
Table 51. Asynchronous Flash Write
Parameter
Min
Max
Unit
Switching Characteristics
tAMSADV
SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1
PREST × tSCLK0 – 2
ns
tDADVAWE
SMC0_AWE Low Delay From ADV High2
PREAT × tSCLK0 – 2
ns
WST × tSCLK0 – 2
ns
WHT × tSCLK0 – 3.5
ns
WAT × tSCLK0 – 2
ns
3
tWADV
NR_ADV Active Low Width
tHAWE
Output4 Hold After SMC0_AWE High5
tWAWE
6
SMC0_AWE Active Low Width
7
1
PREST value set using the SMC_BxETIM.PREST bits.
PREAT value set using the SMC_BxETIM.PREAT bits.
3
WST value set using the SMC_BxTIM.WST bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
7
WAT value set using the SMC_BxTIM.WAT bits.
2
NOR_A 25-1
(SMC0_Ax)
NOR_CE
(SMC0_AMSx)
tAMSADV
tWADV
NOR_ADV
(SMC0_AOE)
tWAWE
tDADVAWE
tHAWE
NOR_WE
(SMC0_AWE)
NOR_DQ 15-0
(SMC0_Dx)
Figure 17. Asynchronous Flash Write
All Accesses
Table 52 describes timing that applies to all memory accesses, related to the SMC.
Table 52. All Accesses
Parameter
Min
Max
Unit
Switching Characteristic
tTURN
SMC0_AMSx Inactive Width
(IT + TT) × tSCLK0 – 2
Rev. B |
Page 97 of 173 |
December 2018
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DDR2 SDRAM Clock and Control Cycle Timing
Table 53 and Figure 18 show DDR2 SDRAM clock and control cycle timing, related to the DMC.
Table 53. DDR2 SDRAM Clock and Control Cycle Timing, VDD_DMC, Nominal 1.8 V1
400 MHz2
Parameter
Min
Max
Unit
Switching Characteristics
Clock Cycle Time (CL = 2 Not Supported)
2.5
3
Minimum Clock Pulse Width
0.44
0.56
tCK
tCL (abs)3
Maximum Clock Pulse Width
0.44
0.56
tCK
tIS
Control/Address Setup Relative to DMCx_CK Rise
175
ps
tIH
Control/Address Hold Relative to DMCx_CK Rise
250
ps
tCK
tCH (abs)
ns
1
Specifications apply to both DMC0 and DMC1.
2
In order to ensure proper operation of the DDR2, all the DDR2 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
3
As per JESD79-2E definition.
tCK
tCH
tCL
DMCx_CK
DMCx_CK
tIS
tIH
DMCx_Ax
DMCx CONTROL
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A0-A15 AND DMCx_BA0-BA2.
Figure 18. DDR2 SDRAM Clock and Control Cycle Timing
Rev. B |
Page 98 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DDR2 SDRAM Read Cycle Timing
Table 54 and Figure 19 show DDR2 SDRAM read cycle timing, related to the DMC.
Table 54. DDR2 SDRAM Read Cycle Timing, VDD_DMC, Nominal 1.8 V1
400 MHz2
Parameter
Min
Max
Unit
0.2
ns
Timing Requirements
tDQSQ
DMCx_DQS to DMCx_DQ Skew for DMCx_DQS and Associated
DMCx_DQxx Signals
tQH
DMCx_DQxx, DMCx_DQS Output Hold Time From DMCx_DQS
0.8
ns
tRPRE
Read Preamble
0.9
tCK
tRPST
Read Postamble
0.4
tCK
1
Specifications apply to both DMC0 and DMC1.
2
In order to ensure proper operation of the DDR2, all the DDR2 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
tCK
tCH
tCL
DMCx_CKx
DMCx_CKx
DMCx_Ax
DMCx CONTROL
tRPRE
DMCx_LDQS/DMCx_UDQS
DMCx_LDQS/DMCx_UDQS
tDQSQ
tDQSQ
tRPST
tQH
tQH
DMCx_DQxx
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13 AND DMCx_BA0-1.
Figure 19. DDR2 SDRAM Controller Input AC Timing
Rev. B |
Page 99 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DDR2 SDRAM Write Cycle Timing
Table 55 and Figure 20 show DDR2 SDRAM write cycle timing, related to the DMC.
Table 55. DDR2 SDRAM Write Cycle Timing, VDD_DMC, Nominal 1.8 V1
400 MHz2
Parameter
Min
Max
Unit
+0.15
tCK
Switching Characteristics
tDQSS
DMCx_DQS Latching Rising Transitions to Associated Clock Edges3
–0.15
tDS
Last Data Valid to DMCx_DQS Delay
0.1
ns
tDH
DMCx_DQS to First Data Invalid Delay
0.15
ns
tDSS
DMCx_DQS Falling Edge to Clock Setup Time
0.2
tCK
tDSH
DMCx_DQS Falling Edge Hold Time From DMCx_CK
0.2
tCK
tDQSH
DMCx_DQS Input High Pulse Width
0.35
tCK
tDQSL
DMCx_DQS Input Low Pulse Width
0.35
tCK
tWPRE
Write Preamble
0.35
tCK
tWPST
Write Postamble
0.4
tCK
tIPW
Address and Control Output Pulse Width
0.6
tCK
tDIPW
DMCx_DQ and DMCx_DM Output Pulse Width
0.35
tCK
1
Specifications apply to both DMC0 and DMC1.
To ensure proper operation of the DDR2, all the DDR2 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
3
Write command to first DMCx_DQS delay = WL × tCK + tDQSS.
2
DMCx_CK
DMCx_CK
tIPW
DMCx_Ax
DMCx CONTROL
tDSH
tDSS
tDQSS
DMCx_LDQS/DMCx_UDQS
DMCx_LDQS/DMCx_UDQS
DMC0_DQSn
DMC0_DQSn
tWPRE
tDQSL
tDS
tDH
tDQSH
tDIPW
DMCx_LDM
DMCx_UDM
DMCx_DQx
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13 AND DMCx_BA0-1.
Figure 20. DDR2 SDRAM Controller Output AC Timing
Rev. B |
Page 100 of 173 |
December 2018
tWPST
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing
Table 56 and Figure 21 show mobile DDR SDRAM clock and control cycle timing, related to the DMC.
Table 56. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMC, Nominal 1.8 V1
200 MHz2
Parameter
Min
Max
Unit
Switching Characteristics
tCK
Clock Cycle Time (CL = 2 Not Supported)
5
ns
tCH
Minimum Clock Pulse Width
0.45
0.55
tCK
tCL
Maximum Clock Pulse Width
0.45
0.55
tCK
tIS
Control/Address Setup Relative to DMCx_CK Rise
1
ns
tIH
Control/Address Hold Relative to DMCx_CK Rise
1
ns
1
Specifications apply to both DMC0 and DMC1.
2
To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
tCK
tCH
tCL
DMCx_CK
DMCx_CK
tIS
tIH
DMCx_Ax
DMCx CONTROL
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A0-A15 AND DMCx_BA0-BA2.
Figure 21. Mobile DDR SDRAM Clock and Control Cycle Timing
Rev. B |
Page 101 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Mobile DDR SDRAM Read Cycle Timing
Table 57 and Figure 22 show mobile DDR SDRAM read cycle timing, related to the DMC.
Table 57. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC, Nominal 1.8 V1
200 MHz2
Parameter
Min
Max
Unit
Timing Requirements
tQH
DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS
tDQSQ
DMCx_DQS to DMCx_DQ Skew for DMCx_DQS and Associated
DMCx_DQ Signals
tRPRE
Read Preamble
tRPST
Read Postamble
1.75
ns
0.4
ns
0.9
1.1
tCK
0.4
0.6
tCK
1
Specifications apply to both DMC0 and DMC1.
2
To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
DMCx_CK
tRPRE
tRPST
DMCx_LDQS/DMCx_HDQS
tQH
DMCx_DQx
(DATA)
Dn
Dn+1
Dn+2
tDQSQ
Figure 22. Mobile DDR SDRAM Controller Input AC Timing
Rev. B |
Page 102 of 173 |
December 2018
Dn+3
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Mobile DDR SDRAM Write Cycle Timing
Table 58 and Figure 23 show mobile DDR SDRAM write cycle timing, related to the DMC.
Table 58. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC, Nominal 1.8 V1
200 MHz2
Parameter
Min
Max
Unit
1.25
tCK
Switching Characteristics
tDQSS3
DMCx_DQS Latching Rising Transitions to Associated Clock Edges
0.75
tDS
Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns)
0.48
ns
tDH
DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns)
0.48
ns
tDSS
DMCx_DQS Falling Edge to Clock Setup Time
0.2
tCK
tDSH
DMCx_DQS Falling Edge Hold Time From DMCx_CK
0.2
tCK
tDQSH
DMCx_DQS Input High Pulse Width
0.4
tCK
tDQSL
DMCx_DQS Input Low Pulse Width
0.4
tCK
tWPRE
Write Preamble
0.25
tCK
tWPST
Write Postamble
0.4
tCK
tIPW
Address and Control Output Pulse Width
2.3
ns
tDIPW
DMCx_DQ and DMCx_DM Output Pulse Width
1.8
ns
1
Specifications apply to both DMC0 and DMC1.
To ensure proper operation of LPDDR, all the LPDDR requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
3
Write command to first DMCx_DQS delay = WL × tCK + tDQSS.
2
DMCx_CK
tDSS
tDSH
tDQSS
DMCx_LDQS/DMCx_HDQS
tWPRE
tDS
tDQSL
tDH
tDQSH
tWPST
tDIPW
DMCx_DQ0-15/
DMCx_LDQM/DMCx_HDQM
Dn
Dn+1
Dn+2
Dn+3
tDIPW
DMCx CONTROL
Write CMD
NOTE: CONTROL = DMCx_CSx, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13, AND DMCx_BA0-1.
tIPW
Figure 23. Mobile DDR SDRAM Controller Output AC Timing
Rev. B |
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ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DDR3 SDRAM Clock and Control Cycle Timing
Table 59 and Figure 24 show mobile DDR3 SDRAM clock and control cycle timing, related to the DMC.
Table 59. DDR3 SDRAM Clock and Control Cycle Timing, VDD_DMC, Nominal 1.5 V1
450 MHz2
Parameter
Min
Max
Unit
Switching Characteristics
Clock Cycle Time (CL = 2 Not Supported)
tCK
2.22
ns
3
Minimum Clock Pulse Width
0.43
0.57
tCK
tCL(abs)3
Maximum Clock Pulse Width
0.43
0.57
tCK
tIS
Control/Address Setup Relative to DMCx_CK Rise
0.2
ns
tIH
Control/Address Hold Relative to DMCx_CK Rise
0.275
ns
tCH(abs)
1
Specifications apply to both DMC0 and DMC1.
2
To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
3
As per JESD79-3F definition.
tCK
tCH
tCL
DMCx_CK
DMCx_CK
tIS
tIH
DMCx_Ax
DMCx CONTROL
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A0-A15 AND DMCx_BA0-BA2.
Figure 24. DDR3 SDRAM Clock and Control Cycle Timing
Rev. B |
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DDR3 SDRAM Read Cycle Timing
Table 60 and Figure 25 show mobile DDR3 SDRAM read cycle timing, related to the DMC.
Table 60. DDR3 SDRAM Read Cycle Timing, VDD_DMC, Nominal 1.5 V1
450 MHz2
Parameter
Min
Max
Unit
0.15
ns
Timing Requirements
tDQSQ
DMCx_DQS to DMCx_DQ Skew for DMCx_DQS and Associated DMCx_DQ
Signals
tQH
DMCx_DQ, DMCx_DQS Output Hold Time From DMCx_DQS
0.38
tCK
tRPRE
Read Preamble
0.9
tCK
tRPST
Read Postamble
0.3
tCK
1
Specifications apply to both DMC0 and DMC1.
2
To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
tCK
tCH
tCL
DMCx_CKx
DMCx_CKx
DMCx_Ax
DMCx CONTROL
tRPRE
DMCx_LDQS/DMCx_UDQS
DMCx_LDQS/DMCx_UDQS
tDQSQ
tDQSQ
tRPST
tQH
tQH
DMCx_DQxx
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13 AND DMCx_BA0-1.
Figure 25. DDR3 SDRAM Controller Input AC Timing
Rev. B |
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DDR3 SDRAM Write Cycle Timing
Table 61 and Figure 26 show mobile DDR3 SDRAM output ac timing, related to the DMC.
Table 61. DDR3 SDRAM Write Cycle Timing, VDD_DMC, Nominal 1.5 V1
450 MHz2
Parameter
Min
Max
Unit
0.25
tCK
Switching Characteristics
tDQSS
DMCx_DQS Latching Rising Transitions to Associated Clock Edges3
–0.25
tDS
Last Data Valid to DMCx_DQS Delay (Slew > 1 V/ns)
0.125
ns
tDH
DMCx_DQS to First Data Invalid Delay (Slew > 1 V/ns)
0.150
ns
tDSS
DMCx_DQS Falling Edge to Clock Setup Time
0.2
tCK
tDSH
DMCx_DQS Falling Edge Hold Time From DMCx_CK
0.2
tDQSH
DMCx_DQS Input High Pulse Width
0.45
0.55
tCK
tDQSL
DMCx_DQS Input Low Pulse Width
0.45
0.55
tCK
tWPRE
Write Preamble
0.9
tWPST
Write Postamble
0.3
tCK
tIPW
Address and Control Output Pulse Width
0.840
ns
tDIPW
DMCx_DQ and DMCx_DM Output Pulse Width
0.550
ns
tCK
tCK
1
Specifications apply to both DMC0 and DMC1.
To ensure proper operation of the DDR3, all the DDR3 requirements must be strictly followed. See Interfacing DDR3/DDR2/LPDDR Memory to ADSP-SC5xx/215xx
Processors (EE-387).
3
Write command to first DMCx_DQS delay = WL × tCK + tDQSS.
2
DMCx_CK
DMCx_CK
tIPW
DMCx_Ax
DMCx CONTROL
tDSH
tDSS
tDQSS
DMCx_LDQS/DMCx_UDQS
DMCx_LDQS/DMCx_UDQS
DMC0_DQSn
DMC0_DQSn
tDQSL
tWPRE
tDS
tDH
DMCx_LDM
DMCx_UDM
DMCx_DQx
NOTE: CONTROL = DMCx_CS0, DMCx_CKE, DMCx_RAS, DMCx_CAS, AND DMCx_WE.
ADDRESS = DMCx_A00-13, AND DMCx_BA0-1.
Figure 26. DDR3 SDRAM Controller Output AC Timing
Rev. B |
Page 106 of 173 |
December 2018
tDQSH
tDIPW
tWPST
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Enhanced Parallel Peripheral Interface (EPPI) Timing
Table 62 and Table 63 and Figure 27 through Figure 35 describe enhanced parallel peripheral interface (EPPI) timing operations. In
Figure 27 through Figure 35, POLC[1:0] represents the setting of the EPPI_CTL register, which sets the sampling/driving edges of the
EPPI clock.
When internally generated, the programmed PPI clock (fPCLKPROG) frequency in MHz is set by the following equation where VALUE is a
field in the EPPI_CLKDIV register that can be set from 0 to 65,535:
f SCLK0
f PCLKPROG = -------------------- VALUE + 1
1
t PCLKPROG = ----------------f PCLKPROG
When externally generated, the EPPI_CLK is called fPCLKEXT:
1
t PCLKEXT = -------------f PCLKEXT
Table 62. Enhanced Parallel Peripheral Interface (EPPI)—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSPI
External FS Setup Before EPPI_CLK
6.5
ns
tHFSPI
External FS Hold After EPPI_CLK
0
ns
tSDRPI
Receive Data Setup Before EPPI_CLK
6.5
ns
tHDRPI
Receive Data Hold After EPPI_CLK
0
ns
tSFS3GI
External FS3 Input Setup Before EPPI_CLK Fall Edge in Clock
Gating Mode
14
ns
tHFS3GI
External FS3 Input Hold Before EPPI_CLK Fall Edge in Clock
Gating Mode
0
ns
0.5 × tPCLKPROG – 1.5
ns
tPCLKPROG – 1.5
ns
Switching Characteristics
tPCLKW
1
EPPI_CLK Width1
tPCLK
EPPI_CLK Period
1
tDFSPI
Internal FS Delay After EPPI_CLK
tHOFSPI
Internal FS Hold After EPPI_CLK
tDDTPI
Transmit Data Delay After EPPI_CLK
tHDTPI
Transmit Data Hold After EPPI_CLK
3.5
–0.5
3.5
–0.5
See Table 29 for details on the minimum period that can be programmed for tPCLKPROG.
Rev. B |
Page 107 of 173 |
December 2018
ns
ns
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
FRAME SYNC
DRIVEN
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPI
tPCLKW
tHOFSPI
tPCLK
EPPI_FS1/2
tSDRPI
tHDRPI
EPPI_D00-23
Figure 27. EPPI Internal Clock GP Receive Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPI
tPCLKW
tHOFSPI
EPPI_FS1/2
tHDTPI
tDDTPI
EPPI_D00-23
Figure 28. EPPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPI
tPCLKW
tHFSPI
tPCLK
EPPI_FS1/2
tSDRPI
tHDRPI
EPPI_D00-23
Figure 29. EPPI Internal Clock GP Receive Mode with External Frame Sync Timing
Rev. B |
Page 108 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPI
tHFSPI
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPI
tHDTPI
EPPI_D00-23
Figure 30. EPPI Internal Clock GP Transmit Mode with External Frame Sync Timing
EPPI_CLK
tHFS3GI
tSFS3GI
EPPI_FS3
Figure 31. Clock Gating Mode with Internal Clock and External Frame Sync Timing
Table 63. Enhanced Parallel Peripheral Interface (EPPI)—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tPCLKW
EPPI_CLK Width1
0.5 × tPCLKEXT – 0.5
ns
tPCLK
EPPI_CLK Period1
tPCLKEXT – 1
ns
tSFSPE
External FS Setup Before EPPI_CLK
2
ns
tHFSPE
External FS Hold After EPPI_CLK
3.7
ns
tSDRPE
Receive Data Setup Before EPPI_CLK
2
ns
tHDRPE
Receive Data Hold After EPPI_CLK
3.7
ns
Switching Characteristics
1
tDFSPE
Internal FS Delay After EPPI_CLK
tHOFSPE
Internal FS Hold After EPPI_CLK
tDDTPE
Transmit Data Delay After EPPI_CLK
tHDTPE
Transmit Data Hold After EPPI_CLK
15.3
2.4
ns
15.3
2.4
ns
ns
ns
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency see the fPCLKEXT specification in Table 29.
Rev. B |
Page 109 of 173 |
December 2018
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FRAME SYNC
DRIVEN
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPE
tPCLKW
tHOFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 32. EPPI External Clock GP Receive Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPE
tPCLKW
tHOFSPE
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 33. EPPI External Clock GP Transmit Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPE
tPCLKW
tHFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 34. EPPI External Clock GP Receive Mode with External Frame Sync Timing
Rev. B |
Page 110 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPE
tHFSPE
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 35. EPPI External Clock GP Transmit Mode with External Frame Sync Timing
Rev. B |
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Link Ports (LP)
In LP receive mode, the link port clock is supplied externally and is called fLCLKREXT, therefore the period can be represented by:
1
t LCLKREXT = --------------f LCLKREXT
In link port transmit mode, the programmed link port clock (fLCLKTPROG) frequency in MHz is set by the following equation where
VALUE is a field in the LP_DIV register that can be set from 1 to 255:
f CLKO8
f LCLKTPROG = -------------------- VALUE 2
In the case where VALUE = 0, fLCLKTPROG = fCLKO8. For all settings of VALUE, the following equation is true:
1
t LCLKTPROG = -----------------f LCLKTPROG
Calculation of the link receiver data setup and hold relative to the link clock is required to determine the maximum allowable skew that
can be introduced in the transmission path length difference between LPx_Dx and LPx_CLK. Setup skew is the maximum delay that can
be introduced in LPx_Dx relative to LPx_CLK (setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can
be introduced in LPx_CLK relative to LPx_Dx (hold skew = tLCLKTWL min – tHLDCH – tHLDCL).
Table 64. Link Ports—Receive1
Parameter
Min
Max
Unit
150
MHz
Timing Requirements
fLCLKREXT
LPx_CLK Frequency
tSLDCL
Data Setup Before LPx_CLK Low
tHLDCL
Data Hold After LPx_CLK Low
1.4
ns
tLCLKEW
LPx_CLK Period2
tLCLKREXT – 0.42
ns
tLCLKRWL
LPx_CLK Width Low2
0.5 × tLCLKREXT
ns
tLCLKRWH
LPx_CLK Width High2
0.5 × tLCLKREXT
ns
0.9
ns
Switching Characteristic
tDLALC
LPx_ACK Low Delay After LPx_CLK Low3
1.5 × tCLKO8 + 4
1
2.5 × tCLKO8 + 12
ns
Specifications apply to LP0 and LP1.
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LPx_CLK. For the external
LPx_CLK ideal maximum frequency see the fLCLKTEXT specification in Table 29.
3
LPx_ACK goes low with tDLALC relative to rise of LPx_CLK after first byte, but does not go low if the link buffer of the receiver is not about to fill.
2
Rev. B |
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December 2018
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tLCLKEW
tLCLKRWH
tLCLKRWL
LPx_CLK
tHLDCL
tSLDCL
LPx_D7–0
IN
tDLALC
LPx_ACK (OUT)
Figure 36. Link Ports—Receive
Rev. B |
Page 113 of 173 |
December 2018
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Table 65. Link Ports—Transmit1
Parameter
Min
Max
Unit
Timing Requirements
tSLACH
LPx_ACK Setup Before LPx_CLK Low
2 × tCLKO8 + 13.5
ns
tHLACH
LPx_ACK Hold After LPx_CLK Low
–5.5
ns
Switching Characteristics
tDLDCH
Data Delay After LPx_CLK High
tHLDCH
Data Hold After LPx_CLK High
–0.8
tLCLKTWL2
LPx_CLK Width Low
0.33 × tLCLKTPROG
0.6 × tLCLKTPROG
0.66 × tLCLKTPROG
2
1
2
1.6
ns
ns
tLCLKTWH
LPx_CLK Width High
0.45 × tLCLKTPROG
tLCLKTW2
LPx_CLK Period
N × tLCLKTPROG – 0.5
tDLACLK
LPx_CLK Low Delay After LPx_ACK High
tCLKO8 + 4
LAST BYTE
TRANSMITTED
tLCLKTWL
2 × tCLKO8 + 1 × tLPCLK + 10
FIRST BYTE
TRANSMITTED1
LPx_CLK
tDLDCH
tHLDCH
LPx_Dx
(DATA)
OUT
tSLACH
tHLACH
tDLACLK
LPx_ACK (IN)
NOTES
The tSLACH and tHLACH specifications apply only to the LPx_CLK falling edge. If these specifications are met,
LPx_CLK would extend and the dotted LPx_CLK falling edge would not occur as shown. The position of the
dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min should be used for tSLACH
and tLCLKTWH Max for tHLACH.
Figure 37. Link Ports—Transmit
Rev. B |
Page 114 of 173 |
December 2018
ns
ns
Specifications apply to LP0 and LP1.
See Table 29 for details on the minimum period that can be programmed for tLCLKTPROG.
tLCLKTWH
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Serial Ports (SPORT)
To determine whether a device is compatible with the SPORT at clock speed n, the following specifications must be confirmed: frame sync
delay and frame sync setup and hold; data delay and data setup and hold; and serial clock (SPTx_CLK) width. In Figure 38, either the rising edge or the falling edge of SPTx_CLK (external or internal) can be used as the active sampling edge.
When externally generated, the SPORT clock is called fSPTCLKEXT:
1
t SPTCLKEXT = ----------------------f SPTCLKEXT
When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in MHz is set by the following equation where
CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535:
f SCLK0
f SPTCLKPROG = ---------------------- CLKDIV + 1
1
t SPTCLKPROG = -------------------------f SPTCLKPROG
Table 66. Serial Ports—External Clock1
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
Frame Sync Setup Before SPTx_CLK
2
(Externally Generated Frame Sync in either Transmit or Receive
Mode)2
ns
tHFSE
Frame Sync Hold After SPTx_CLK
2.7
(Externally Generated Frame Sync in either Transmit or Receive
Mode)2
ns
tSDRE
Receive Data Setup Before Receive SPTx_CLK2
2
ns
tHDRE
Receive Data Hold After SPTx_CLK2
2.7
ns
3
tSPTCLKW
SPTx_CLK Width
tSPTCLK
SPTx_CLK Period3
0.5 × tSPTCLKEXT – 1.5
ns
tSPTCLKEXT – 1.5
ns
Switching Characteristics
tDFSE
Frame Sync Delay After SPTx_CLK
(Internally Generated Frame Sync in either Transmit or Receive
Mode)4
14.5
tHOFSE
Frame Sync Hold After SPTx_CLK
2
(Internally Generated Frame Sync in either Transmit or Receive
Mode)4
tDDTE
Transmit Data Delay After Transmit SPTx_CLK4
tHDTE
Transmit Data Hold After Transmit SPTx_CLK4
ns
14
2
1
ns
ns
ns
Specifications apply to all eight SPORTs.
Referenced to sample edge.
3
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPTx_CLK. For the external
SPTx_CLK ideal maximum frequency see the fSPTCLKEXT specification in Table 29.
4
Referenced to drive edge.
2
Rev. B |
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Table 67. Serial Ports—Internal Clock1
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
tHFSI
tSDRI
tHDRI
Frame Sync Setup Before SPTx_CLK
(Externally Generated Frame Sync in either Transmit or
Receive Mode)2
12
Frame Sync Hold After SPTx_CLK
(Externally Generated Frame Sync in either Transmit or
Receive Mode)2
–0.5
Receive Data Setup Before SPTx_CLK2
3.4
ns
1.5
ns
Receive Data Hold After SPTx_CLK
2
ns
ns
Switching Characteristics
tDFSI
Frame Sync Delay After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
3.5
tHOFSI
Frame Sync Hold After SPTx_CLK (Internally Generated
Frame Sync in Transmit or Receive Mode)3
tDDTI
Transmit Data Delay After SPTx_CLK3
tHDTI
Transmit Data Hold After SPTx_CLK3
–2.5
ns
tSCLKIW
SPTx_CLK Width4
0.5 × tSPTCLKPROG – 1.5
ns
tSPTCLK
SPTx_CLK Period4
tSPTCLKPROG – 1.5
ns
–2.5
Specifications apply to all eight SPORTs.
Referenced to the sample edge.
3
Referenced to drive edge.
4
See Table 29 for details on the minimum period that can be programmed for tSPTCLKPROG.
2
Rev. B |
Page 116 of 173 |
ns
3.5
1
December 2018
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
DATA RECEIVE—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
tSCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tSFSI
tHOFSI
tHFSI
tSFSE
tHFSE
tSDRE
tHDRE
tHOFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tSDRI
tHDRI
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
tSCLKW
SPTx_A/BCLK
(SPORT CLOCK)
SPTx_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tSFSE
tHOFSE
SPTx_A/BFS
(FRAME SYNC)
SPTx_A/BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
tHDTE
SPTx_A/BDx
(DATA CHANNEL A/B)
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 38. Serial Ports
Rev. B |
Page 117 of 173 |
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tHFSE
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Table 68. Serial Ports—Enable and Three-State1
Parameter
Min
Max
Unit
Switching Characteristics
tDDTEN
tDDTTE
Data Disable from External Transmit SPTx_CLK
tDDTIN
Data Enable from Internal Transmit SPTx_CLK2
tDDTTI
1
2
Data Enable from External Transmit SPTx_CLK2
Data Disable from Internal Transmit SPTx_CLK
1
ns
2
14
–2.5
ns
2
2.8
Specifications apply to all eight SPORTs.
Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK EXTERNAL)
tDDTEN
tDDTTE
SPTx_A/BDx
(DATA CHANNEL A/B)
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK INTERNAL)
tDDTIN
tDDTTI
SPTx_A/BDx
(DATA CHANNEL A/B)
Figure 39. Serial Ports—Enable and Three-State
Rev. B |
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ns
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The SPTx_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active channel selection
registers) the SPTx_TDV is asserted for communication with external devices.
Table 69. Serial Ports—TDV (Transmit Data Valid)1
Parameter
Min
Max
Unit
Switching Characteristics
tDRDVEN
1
2
Data Valid Enable Delay from Drive Edge of External Clock2
2
2
tDFDVEN
Data Valid Disable Delay from Drive Edge of External Clock
tDRDVIN
Data Valid Enable Delay from Drive Edge of Internal Clock
2
tDFDVIN
Data Valid Disable Delay from Drive Edge of Internal Clock2
14
–2.5
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK EXTERNAL)
tDRDVEN
tDFDVEN
SPTx_A/BTDV
DRIVE EDGE
DRIVE EDGE
SPTx_CLK
(SPORT CLOCK INTERNAL)
tDRDVIN
tDFDVIN
SPTx_A/BTDV
Figure 40. Serial Ports—Transmit Data Valid Internal and External Clock
Rev. B |
Page 119 of 173 |
December 2018
ns
ns
3.5
Specifications apply to all eight SPORTs.
Referenced to drive edge.
DRIVE EDGE
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 70. Serial Ports—External Late Frame Sync1
Parameter
Min
Max
Unit
14
ns
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit Frame Sync or External Receive Frame
Sync with MCE = 1, MFD = 02
tDDTENFS
Data Enable for MCE = 1, MFD = 02
0.5
ns
1
Specifications apply to all eight SPORTs.
2
The tDDTLFSE and tDDTENFS parameters apply to left justified as well as standard serial mode and MCE = 1, MFD = 0.
DRIVE
SAMPLE
DRIVE
SPTx_A/BCLK
(SPORT CLOCK)
tHFSE/I
tSFSE/I
SPTx_A/BFS
(FRAME SYNC)
tDDTE/I
tDDTENFS
SPTx_A/BDx
(DATA CHANNEL A/B)
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 41. External Late Frame Sync
Rev. B |
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Sample Rate Converter—Serial Input Port
The ASRC input signals are routed from the DAIx_PINx pins using the SRU. Therefore, the timing specifications provided in Table 71 are
valid at the DAIx_PINx pins.
Table 71. ASRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
1
tSRCHFS
4
ns
Frame Sync Hold After Serial Clock Rising Edge
5.5
ns
Data Setup Before Serial Clock Rising Edge
4
ns
tSRCHD1
Data Hold After Serial Clock Rising Edge
5.5
ns
tSRCCLKW
Clock Width
tSCLK0 – 1
ns
tSRCCLK
Clock Period
2 × tSCLK0
ns
tSRCSD
1
1
Frame Sync Setup Before Serial Clock Rising Edge
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of
the PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
tSRCCLKW
DAIx_PIN20–1
(SCLK)
tSRCSFS
tSRCHFS
DAIx_PIN20–1
(FS)
tSRCSD
tSRCHD
DAIX_PIN20–1
(SDATA)
Figure 42. ASRC Serial Input Port Timing
Rev. B |
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Sample Rate Converter—Serial Output Port
For the serial output port, the frame sync is an input and it must meet setup and hold times with regard to SCLK on the output port. The
serial data output has a hold time and delay specification with regard to serial clock. The serial clock rising edge is the sampling edge, and
the falling edge is the drive edge.
Table 72. ASRC, Serial Output Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
Frame Sync Setup Before Serial Clock Rising Edge
4
ns
tSRCHFS
Frame Sync Hold After Serial Clock Rising Edge
5.5
ns
tSRCCLKW
Clock Width
tSCLK0 – 1
ns
tSRCCLK
Clock Period
2 × tSCLK0
ns
1
Switching Characteristics
tSRCTDD1
1
tSRCTDH
1
Transmit Data Delay After Serial Clock Falling Edge
13
Transmit Data Hold After Serial Clock Falling Edge
1
ns
ns
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of
the PCG can be either CLKIN, SCLK0, or any of the DAI pins.
SAMPLE EDGE
tSRCCLK
tSRCCLKW
DAIx_PIN20–1
(SCLK)
tSRCSFS
tSRCHFS
DAIx_PIN20–1
(FS)
tSRCTDD
tSRCTDH
DAIx_PIN20–1
(SDATA)
Figure 43. ASRC Serial Output Port Timing
Rev. B |
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SPI Port—Master Timing
Table 73 and Figure 44 describe SPI port master operations.
When internally generated, the programmed SPI clock (fSPICLKPROG) frequency in MHz is set by the following equation where BAUD is a
field in the SPIx_CLK register that can be set from 0 to 65,535:
f SCLK1
f SPICLKPROG = -------------------- BAUD + 1
1
t SPICLKPROG = ------------------------f SPICLKPROG
Note that
• In dual-mode data transmit, the SPIx_MISO signal is an output.
• In quad-mode data transmit, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are outputs.
• In dual-mode data receive, the SPIx_MOSI signal is an input.
• In quad-mode data receive, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are inputs.
• Quad-mode is supported by SPI2 only.
• CPHA is a configuration bit in the SPI_CTL register.
Table 73. SPI Port—Master Timing1
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
3.2
ns
tHSPIDM
SPIx_CLK Sampling Edge to Data Input Invalid
1.2
ns
Switching Characteristics
tSDSCIM
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 1
tSCLK1 – 2
ns
SPIx_SEL Low to First SPI_CLK Edge for CPHA = 0
1.5 × tSCLK1 – 2
ns
tSPICHM
SPIx_CLK High Period2
0.5 × tSPICLKPROG – 1
ns
2
tSPICLM
SPIx_CLK Low Period
0.5 × tSPICLKPROG – 1
ns
tSPICLK
SPIx_CLK Period2
tSPICLKPROG – 1
ns
tHDSM
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 1
1.5 × tSCLK1 – 2
ns
Last SPIx_CLK Edge to SPIx_SEL High for CPHA = 0
tSCLK1 – 2
ns
tSPITDM
Sequential Transfer Delay3
tSCLK1 – 1
ns
tDDSPIDM
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
2.6
–1.5
1
All specifications apply to all three SPIs.
See Table 29 for details on the minimum period that can be programmed for tSPICLKPROG.
3
Applies to sequential mode with STOP ≥ 1.
2
Rev. B |
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SPIx_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIx_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(SPIx_MISO)
tDDSPIDM
tHDSPIDM
DATA OUTPUTS
(SPIx_MOSI)
CPHA = 0
tSSPIDM
tHSPIDM
DATA INPUTS
(SPIx_MISO)
Figure 44. SPI Port—Master Timing
Rev. B |
Page 124 of 173 |
December 2018
tSPITDM
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SPI Port—Slave Timing
Table 74 and Figure 45 describe SPI port slave operations. Note that
• In dual-mode data transmit, the SPIx_MOSI signal is an output.
• In quad-mode data transmit, the SPIx_MOSI, SPIx_D2, and SPIx_D3 signals are outputs.
• In dual-mode data receive, the SPIx_MISO signal is an input.
• In quad-mode data receive, the SPIx_MISO, SPIx_D2, and SPIx_D3 signals are inputs.
• In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT, as follows:
1
t SPICLKEXT = ----------------------f SPICLKEXT
• Quad mode is supported by SPI2 only.
• CPHA is a configuration bit in the SPI_CTL register.
Table 74. SPI Port—Slave Timing1
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
SPIx_CLK High Period2
2
0.5 × tSPICLKEXT – 1
ns
tSPICLS
SPIx_CLK Low Period
0.5 × tSPICLKEXT – 1
ns
tSPICLK
SPIx_CLK Period2
tSPICLKEXT – 1
ns
tHDS
Last SPIx_CLK Edge to SPIx_SS Not Asserted
5
ns
tSPITDS
Sequential Transfer Delay
tSPICLK – 1
ns
tSDSCI
SPIx_SS Assertion to First SPIx_CLK Edge
10.5
ns
tSSPID
Data Input Valid to SPIx_CLK Edge (Data Input Setup)
2
ns
tHSPID
SPIx_CLK Sampling Edge to Data Input Invalid
1.6
ns
Switching Characteristics
tDSOE
SPIx_SS Assertion to Data Out Active
0
14
ns
tDSDHI
SPIx_SS Deassertion to Data High Impedance
0
12.5
ns
tDDSPID
SPIx_CLK Edge to Data Out Valid (Data Out Delay)
14
ns
tHDSPID
SPIx_CLK Edge to Data Out Invalid (Data Out Hold)
0
1
ns
All specifications apply to all three SPIs.
2
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPIx_CLK. For the external
SPIx_CLK ideal maximum frequency, see the fSPICLKTEXT specification in Table 29.
Rev. B |
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SPIx_SS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPIx_CLK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
CPHA = 1
tSSPID
tHSPID
DATA INPUTS
(SPIx_MOSI)
tDSOE
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPIx_MISO)
tHSPID
CPHA = 0
tSSPID
DATA INPUTS
(SPIx_MOSI)
Figure 45. SPI Port—Slave Timing
Rev. B |
Page 126 of 173 |
December 2018
tSPITDS
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SPI Port—SPI Ready (SPIx_RDY) Slave Timing
SPIx_RDY is used to provide flow control. CPOL, CPHA, and FCCH are configuration bits in the SPIx_CTL register.
Table 75. SPI Port—SPIx_RDY Slave Timing1
Parameter
Conditions
Min
Max
Unit
FCCH = 0
3 × tSCLK1
4 × tSCLK1 + 10
ns
FCCH = 1
4 × tSCLK1
5 × tSCLK1 + 10
ns
Switching Characteristic
tDSPISCKRDYS SPIx_RDY Deassertion from Last Valid Input SPIx_CLK Edge
1
All specifications apply to all three SPIs.
tDSPISCKRDYS
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
SPIx_RDY (O)
Figure 46. SPIx_RDY Deassertion from Valid Input SPIx_CLK Edge in Slave Mode
Rev. B |
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SPI Port—Open Drain Mode (ODM) Timing
In Figure 47 and Figure 48 and Table 77 and Table 78, the outputs can be SPIx_MOSI, SPIx_MISO, SPIx_D2, and/or SPIx_D3, depending
on the mode of operation. CPOL and CPHA are configuration bits in the SPI_CTL register.
Table 76. SPI Port—ODM Master Mode 1
Parameter
Min
Max
Unit
Switching Characteristics
1
tHDSPIODMM
SPIx_CLK Edge to High Impedance from Data Out Valid
–1
tDDSPIODMM
SPIx_CLK Edge to Data Out Valid from High Impedance
–1
ns
+6
ns
Max
Unit
All specifications apply to all three SPIs.
tHDSPIODMM
tHDSPIODMM
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMM
tDDSPIODMM
Figure 47. ODM Master Mode
Table 77. SPI Port—ODM Slave Mode1
Parameter
Min
Timing Requirements
1
tHDSPIODMS
SPIx_CLK Edge to High Impedance from Data Out Valid
tDDSPIODMS
SPIx_CLK Edge to Data Out Valid from High Impedance
0
ns
11
All specifications apply to all three SPIs.
tHDSPIODMS
tHDSPIODMS
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMS
tDDSPIODMS
Figure 48. ODM Slave Mode
Rev. B |
Page 128 of 173 |
December 2018
ns
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SPI Port—SPIx_RDY Master Timing
SPIx_RDY provides flow control. CPOL and CPHA are configuration bits in the SPIx_CTL register, whereas LEADX, LAGX, and STOP
are configuration bits in the SPIx_DLY register.
Table 78. SPI Port—SPIx_RDY Master Timing1
Parameter
Conditions
Min
Max
Unit
Timing Requirement
tSRDYSCKM
(2 + 2 × BAUD2) × tSCLK1 + 10
Setup Time for SPIx_RDY Deassertion
Before Last Valid Data SPIx_CLK Edge
ns
Switching Characteristic
tDRDYSCKM3 Assertion of SPIx_RDY to First SPIx_CLK Baud = 0, CPHA = 0
Edge of Next Transfer
4.5 × tSCLK1
5.5 × tSCLK1 + 10
ns
Baud = 0, CPHA = 1
4 × tSCLK1
5 × tSCLK1 + 10
ns
Baud > 0, CPHA = 0
(1 + 1.5 × BAUD2) × tSCLK1
(2 + 2.5 × BAUD2) × tSCLK1 + 10 ns
Baud > 0, CPHA = 1
(1 + 1 × BAUD2) × tSCLK1
(2 + 2 × BAUD2) × tSCLK1 + 10 ns
1
All specifications apply to all three SPIs.
BAUD value is set using the SPIx_CLK.BAUD bits. BAUD value = SPIx_CLK.BAUD bits + 1.
3
Specification assumes the LEADX, LAGX, and STOP bits in the SPI_DLY register are zero.
2
tSRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
SPIx_CLK
(CPOL = 1)
Figure 49. SPIx_RDY Setup Before SPIx_CLK
Rev. B |
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tDRDYSCKM
SPIx_RDY
SPIx_CLK
(CPOL = 0)
CPHA = 0
SPIx_CLK
(CPOL = 1)
SPIx_CLK
(CPOL = 0)
CPHA = 1
SPIx_CLK
(CPOL = 1)
Figure 50. SPIx_CLK Switching Diagram After SPIx_RDY Assertion
Rev. B |
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Precision Clock Generator (PCG) (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes inputs directly from the DAI
pins (via pin buffers) and sends outputs directly to the DAI pins. For the other cases, where the PCG inputs and outputs are not directly
routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteristics apply to
external DAI pins (DAIx_PINx).
Table 79. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIP
Input Clock Period
tSCLK × 2
ns
tSTRIG
PCG Trigger Setup Before Falling Edge of PCG Input Clock
4.5
ns
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input Clock
3
ns
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge Delay After 2.5
PCG Input Clock
13.5
ns
tDTRIGCLK
PCG Output Clock Delay After PCG Trigger
2.5 + (2.5 × tPCGIP)
13.5 + (2.5 × tPCGIP)
ns
tDTRIGFS1
PCG Frame Sync Delay After PCG Trigger
2.5 + ((2.5 + D – PH) × tPCGIP) 13.5 + ((2.5 + D – PH) × tPCGIP) ns
tPCGOW2
Output Clock Period
2 × tPCGIP – 1
ns
1
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference.
2
Normal mode of operation.
tSTRIG
tHTRIG
DAIx_PIN20–1
PCG_TRIGx_I
DAIx_PIN20–1
PCG_EXTx_I
(CLKIN)
tPCGIP
tDPCGIO
DAIx_PIN20–1
PCG_CLKx_O
tDTRIGCLK
tDPCGIO
DAIx_PIN20–1
PCG_FSx_O
tDTRIGFS
Figure 51. PCG (Direct Pin Routing)
Rev. B |
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tPCGOW
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General-Purpose I/O Port Timing
Table 80 and Figure 52 describe I/O timing, related to the general-purpose I/O port.
Table 80. General-Purpose Port Timing
Parameter
Min
Max
Unit
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
2 × tSCLK0 – 1.5
ns
tWFI
GPIO INPUT
Figure 52. General-Purpose Port Pin Timing
General-Purpose I/O Timer Cycle Timing
Table 81, Table 82, and Figure 53 describe timer expired operations related to the general-purpose timer. The input signal is asynchronous
in Width Capture Mode and External Clock Mode and has an absolute maximum input frequency of fSCLK/4 MHz. The Width Value
value is the timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. When externally generated, the
TMx_CLK clock is called fTMRCLKEXT, as follows:
1
t TMRCLKEXT = -----------------------f TMRCLKEXT
Table 81. Timer Cycle Timing (Internal Mode)
Parameter
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)1
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)2
1
2
Min
Max
2 × tSCLK
2 × tSCLK
tSCLK × WIDTH – 1.5
Unit
ns
ns
tSCLK × WIDTH + 1.5
ns
The minimum pulse width applies for TMRx signals in width capture and external clock modes.
WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).
Table 82. Timer Cycle Timing (External Mode)
Parameter
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1
tWH
Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1
tEXT_CLK
Timer External Clock Period2
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In EXT_CLK Cycles)3
Min
Max
2 × tEXT_CLK
2 × tEXT_CLK
tTMRCLKEXT
tEXT_CLK × WIDTH – 1.5
1
Unit
ns
ns
ns
tEXT_CLK × WIDTH + 1.5
ns
The minimum pulse width applies for TMRx signals in width capture and external clock modes.
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external
TMR_CLK maximum frequency see the fTMRCLKEXT specification in Table 29.
3
WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).
2
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TMR OUTPUT
tHTO
TMR INPUT
tWH, tWL
Figure 53. Timer Cycle Timing
DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block)
Table 83 and Figure 54 describe I/O timing related to the digital audio interface (DAI) for direct pin connections only (for example,
DAIx_PB01_I to DAIx_PB02_O).
Table 83. DAI Pin to DAI Pin Routing
Parameter
Switching Characteristic
tDPIO
Delay DAI Pin Input Valid to DAI Output Valid
Min
Max
Unit
1.5
12
ns
DAIx_PINn
tDPIO
DAIx_PINm
Figure 54. DAI Pin to DAI Pin Direct Routing
Up/Down Counter/Rotary Encoder Timing
Table 84 and Figure 55 describe timing related to the general-purpose counter (CNT).
Table 84. Up/Down Counter/Rotary Encoder Timing
Parameter
Min
Max
Unit
Timing Requirement
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
CNT0_UD
CNT0_DG
CNT0_ZM
tWCOUNT
Figure 55. Up/Down Counter/Rotary Encoder Timing
Rev. B |
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2 × tSCLK0
ns
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Pulse Width Modulator (PWM) Timing
Table 85 and Figure 56 describe timing, related to the PWM.
Table 85. PWM Timing1
Parameter
Min
Max
Unit
Timing Requirement
tES
External Sync Pulse Width
2 × tSCLK0
ns
Switching Characteristics
tDODIS
Output Inactive (off ) After Trip Input2
tDOE
Output Delay After External Sync2, 3
2 × tSCLK0 + 5.5
15
ns
5 × tSCLK0 + 14
ns
1
All specifications apply to all three PWMs.
PWM outputs are PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
3
When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock.
2
PWMx_SYNC
(AS INPUT)
tES
tDOE
OUTPUT
tDODIS
PWMx_TRIP
Figure 56. PWM Timing
Rev. B |
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PWM — Medium Precision (MP) Mode Timing
Table 86 and Figure 57 describe medium precision (MP) PWM operations.
Table 86. PWM—MP Mode, Output Pulse
Parameter
Switching Characteristic
tMPWMW
MP PWM Output Pulse Width1, 2
1
2
Min
Max
Unit
(N + m × 0.25) × tSCLK – 1.0
(N + m × 0.25) × tSCLK + 1.0
ns
N is the DUTY bit field (coarse duty) from the duty register. m is the ENHDIV (Enhanced Precision Divider bits) value from the HP duty register.
Applies to individual PWM channel with 50% duty cycle. Other PWM channels within the same unit are toggling at the same time. No other GPIO pins toggle.
PWMOUTPUT
t MPWMW
Figure 57. PWM MP Mode Timing, Output Pulse
PWM — Heightened Precision (HP) Mode Timing
Table 87, Table 88, and Figure 58 through Figure 61 describe heightened precision (HP) PWM operations.
Table 87. PWM—HP Mode (HPPWM), Output Pulse Width Accuracy
Parameter
HPPWM Pulse Width Accuracy
Resolution1, 2
Conditions
Min
Maximum allowed heightened precision divider bits for
fractional duty cycles within system clock period
Guaranteed monotonic
Differential Nonlinearity (DNL)1, 3
Integral Nonlinearity (INL)1, 4
RMS Jitter1
–0.99
–1.0
RMS jitter of any given pulse width code step
200
1
This specification applies when the system clock SCLK0 is running at 112.5 and 125 MHz.
2
See Figure 58 for an example of 4-bit resolution of fractional duty cycle edge placement.
3
DNL definition. See Figure 59 for an example of DNL calculation. For each heightened precision duty register value (n) is as follows:
PW n – PW n – 1
DNL n = -------------------------------------------------- – 1
IdealLSBStepWidth
4
INL definition. See Figure 60 for an example of INL calculation. For each heightened precision duty register value (n) is as follows:
PW n – PW 0
INL n = ------------------------------------------------------ – n
IdealLSBPulseWidth
SYSCLK
0
8
16
PWMOUT
HP DUTY CYCLE CONTROL CODE n
PWMOUT
HP DUTY CYCLE CONTROL CODE n + 1
Figure 58. Fractional Duty Cycle Edge Placement (4-Bit Resolution)
Rev. B |
Page 135 of 173 |
December 2018
Typ
Max
Unit
4
Bits
+1.0
+1.0
LSB
LSB
ps
…
7
7
PWM OUTPUT EDGE PLACEMENT (LSB)
15
PWM OUTPUT EDGE PLACEMENT (LSB)
15
…
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
IDEAL PULSE WIDTH
6
5
4
DNL = 0.5
3
DNL = 0
2
DNL = 0.5
IDEAL PULSE WIDTH
6
5
INL = -0.3
4
INL = 0
3
2
INL = 0.5
1
1
DNL = 0
0
0
1
2
3
4
5
6
7
…
0
0
15
1
2
3
4
5
6
7
… 15
HEIGHTENED PRECISION DUTY CYCLE CODE
(ONLY THE FIRST 8 CODES ARE SHOWN)
HEIGHTENED PRECISION DUTY CYCLE CODE
(ONLY THE FIRST 8 CODES ARE SHOWN)
Figure 60. HPPWM Pulse Width Accuracy: INL Calculation
Figure 59. HPPWM Pulse Width Accuracy: DNL Calculation
Note that Figure 59 and Figure 60 show sample data for calculating DNL and INL, respectively. They do not reflect actual
measured performance.
Table 88. PWM—HP and MP Modes, Output Skew
Parameter
Switching Characteristic
tPWMS
HP and MP PWM Output Skew 1
1
Min
Max
Unit
1.0
ns
Output edge difference between any two PWM channels (AH, AL, BH, BL, CH, CL, DH and DL) in the same PWM unit (a unit is PWMx where x = 0, 1, 2), with the same
HP/MP edge placement.
PWM OUTPUTS
t PWMS
PWM OUTPUTS
Figure 61. PWM HP and MP Modes Timing, Output Skew
Rev. B |
Page 136 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADC Controller Module (ACM) Timing
Table 89 and Figure 62 describe ACM operations.
When internally generated, the programmed ACM clock (fACLKPROG) frequency in MHz is set by the following equation where CKDIV is
a field in the ACM_TC0 register and ranges from 1 to 255:
f SCLK1
f ACLKPROG = ------------------
CKDIV + 1
1
t ACLKPROG = ----------------f ACLKPROG
Setup cycles (SC) in Table 89 is also a field in the ACM0_TC0 register and ranges from 0 to 4095. Hold cycles (HC) is a field in the
ACM0_TC1 register that ranges from 0 to 15.
Table 89. ACM Timing
Parameter
Min
Max
Unit
Timing Requirements
tSDR
SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK
3.5
ns
tHDR
SPORT DRxPRI/DRxSEC Hold After ACMx_CLK
1.5
ns
Switching Characteristics
1
tSCTLCS
ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS
(SC + 1) × tSCLK1 – 3
ns
tHCTLCS
ACM Control (ACMx_A[4:0]) Hold After Deassertion of CS
HC × tACLKPROG – 1
ns
1
tACLKW
ACM Clock Pulse Width
(0.5 × tACLKPROG) – 1.5
ns
tACLK
ACM Clock Period1
tACLKPROG – 1.5
ns
tHCSACLK
CS Hold to ACMx_CLK Edge
–2.5
ns
tSCSACLK
CS Setup to ACMx_CLK Edge
tACLKPROG – 3.5
ns
See Table 29 for details on the minimum period that can be programmed for tACLKPROG.
DAIx_PIN20–1
(ACM0_FS/CS)
CSPOL = 1/0
tSCSACLK
DAIx_PIN20–1
(ACM0_CLK)
CLKPOL = 1/0
tACLK
tACLKW
tHCSACLK
DAIx_PIN20–1
(ACM0_A0-4)
tSDR
t SCTLCS
DAIx_PIN20–1
(ACM0_T0)
Figure 62. ACM Timing
Rev. B |
Page 137 of 173 |
December 2018
tHDR
t HCTLCS
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described in the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware
Reference.
Controller Area Network (CAN) Interface
The CAN interface timing is described in the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference.
Universal Serial Bus (USB)
Table 90 describes the universal serial bus (USB) clock timing. Refer to the USB 2.0 Specification for timing and dc specifications for USB
pins (including output characteristics for driver types E, F, and G listed in the ADSP-SC58x/ADSP-2158x Designer Quick Reference).
Table 90. USB Clock Timing1
Parameter
Min
Max
Unit
Timing Requirements
1
fUSBS
USB_CLKIN Frequency
24
24
MHz
fsUSB
USB_CLKIN Clock Frequency Stability
–50
+50
ppm
This specification is supported by USB0.
PCI Express (PCIe)
The PCIe interface complies with the Gen1 and Gen2 x1 lane data rate specification and supports up to 3.0 PCIe base functionality.
For more information about PCIe, see the following standards:
• PCI Express Base 3.0 Specification, Revision 1.0, PCI-SIG
• PCI Express 2.0 Card Electromechanical Specification, Revision 2.0, PCI-SIG
• PHY Interface for the PCI Express Architecture, Revision 2.0, Intel Corporation
• PCI-SIG Engineering Change Request: L1 Substates, February 1, 2012, PCI-SIG
• IEEE Standard 1149.1-2001, IEEE
• IEEE Standard 1149.6-2003, IEEE
Rev. B |
Page 138 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
10/100 EMAC Timing (ETH0 and ETH1)
Table 91 through Table 93 and Figure 63 through Figure 65 describe the RMII EMAC operations.
Table 91. 10/100 EMAC Timing—RMII Receive Signal1
Parameter2
Min
Max
Unit
50 + 1%
MHz
tREFCLKF × 65%
ns
Timing Requirements
1
2
tREFCLKF
ETHx_REFCLK Frequency (fSCLK0 = SCLK0 Frequency)
tREFCLKW
ETHx_REFCLK Width (tREFCLKF = ETHx_REFCLK Period)
tREFCLKF × 35%
tREFCLKIS
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data Input Setup)
1.75
ns
tREFCLKIH
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data Input Hold)
1.6
ns
These specifications apply to ETH0 and ETH1.
RMII inputs synchronous to RMII ETHx_REFCLK are ETHx_RXD1–0, RMII ETHx_CRS, and ERxER.
tREFCLKF
ETHx_REFCLK
tREFCLKW
tREFCLKW
ETHx_RXD1–0
ETHx_CRS
tREFCLKIS
tREFCLKIH
Figure 63. 10/100 EMAC Controller Timing—RMII Receive Signal
Table 92. 10/100 EMAC Timing—RMII Transmit Signal1
Parameter2
Min
Max
Unit
11.9
ns
Switching Characteristics
1
2
tREFCLKOV
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)
tREFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold)
2
These specifications apply to ETH0 and ETH1.
RMII outputs synchronous to RMII ETHx_REFCLK are ETHx_TXD1 and TXD0.
tREFCLKF
ETHx_REFCLK
tREFCLKOH
ETHx_TXD1–0
ETHx_TXEN
tREFCLKOV
Figure 64. 10/100 EMAC Controller Timing—RMII Transmit Signal
Rev. B |
Page 139 of 173 |
December 2018
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 93. EMAC Timing— Station Management1
Parameter2
Min
Max
Unit
Timing Requirements
tMDIOS
ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup)
10.8
ns
tMDCIH
ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold)
0
ns
Switching Characteristics
tMDCOV
ETHx_MDC Falling Edge to ETHx_MDIO Output Valid
tSCLK0 + 2
tMDCOH
ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold)
tSCLK0 –2.9
ns
ns
1
These specifications apply to ETH0 and ETH1.
2
ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock with a minimum period that is
programmable as a multiple of the system clock SCLK0. ETHx_MDIO is a bidirectional data line.
ETHx_MDC
(OUTPUT)
tMDCOH
ETHx_MDIO
(OUTPUT)
tMDCOV
ETHx_MDIO
(INPUT)
tMDIOS
tMDCIH
Figure 65. Ethernet MAC Controller Timing— Station Management
Rev. B |
Page 140 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
10/100/1000 EMAC Timing (ETH0 Only)
Table 94 and Figure 66 describe the RGMII EMAC timing.
Table 94. 10/100/1000 EMAC Timing—RGMII Receive and Transmit Signals 1
Parameter
Min
Max
Unit
Timing Requirements
tSETUPR
Data to Clock Input Setup at Receiver
1
ns
tHOLDR
Data to Clock Input Hold at Receiver
1
ns
tGREFCLKF
RGMII Receive Clock Period
8
ns
tGREFCLKW
RGMII Receive Clock Pulse Width
4
ns
Switching Characteristics
1
tSKEWT
Data to Clock Output Skew at Transmitter
–0.5
0.5
ns
tCYC
Clock Cycle Duration
7.2
8.8
ns
tDUTY_G
Duty Cycle for RGMII Minimum
tGREFCLKF × 45%
tGREFCLKF × 55%
ns
This specification is supported by ETH0 only (10/100/1000 EMAC controller).
ETH_TXCLK
(AT TRANSMITTER)
tSKEWT
tDUTY_G
tCYC
tDUTY_G
ETH_TXD3–0
ETH_TXCTL_TXEN
ETH_RXCLK_REFCLK
(AT RECEIVER)
t
tSETUPR
GREFCLKW
tGREFCLKW
t
HOLDR
ETH_RXD3–0
ETH_RXCTL_CRS
Figure 66. Gigabit EMAC Controller Timing—RGMII
Rev. B |
Page 141 of 173 |
December 2018
t
GREFCLKF
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Sinus Cardinalis (SINC) Filter Timing
The programmed SINC filter clock (fSINCLKPROG) frequency in MHz is set by the following equation where MDIV is a field in the CLK
control register that can be set from 4 to 63:
f SCLK
f SINCLKPROG = --------MDIV
1
t SINCLKPROG = -------------------------f SINCLKPROG
Table 95. SINC Timing
Parameter
Timing Requirements
tSSINC
SINC0_Dx Setup Before SINC0_CLKx Rise
tHSINC
SINC0_Dx Hold After SINC0_CLKx Rise
Switching Characteristics
tSINCLK
SINC0_CLKx Period1
tSINCLKW
SINC0_CLKx Width1
1
Min
Max
13.5
0
ns
ns
tSINCLKPROG – 2.5
0.5 × tSINCLKPROG – 2.5
ns
ns
See Table 29 for details on the minimum period that may be programmed for tSINCLKPROG.
tSINCLK
tSINCLKW
tSINCLKW
SINC0_CLKx
tSSINC
tHSINC
SINC_Dx
Figure 67. SINC Timing
Rev. B |
Page 142 of 173 |
Unit
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Sony/Philips Digital Interface (S/PDIF) Transmitter
Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16, 18, 20, or 24 bits.
The following sections provide timing for the transmitter.
S/PDIF Transmitter Serial Input Waveforms
Figure 68 and Table 96 show the right justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on
the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a
frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is right justified to the next
frame sync transition.
Table 96. S/PDIF Transmitter Right Justified Mode
Parameter
Timing Requirement
tRJD
Frame Sync to MSB Delay in Right Justified Mode
Conditions
Nominal
Unit
16-bit word mode
18-bit word mode
20-bit word mode
24-bit word mode
16
14
12
8
SCLK
SCLK
SCLK
SCLK
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
tRJD
DAI_P20–1
SDATA
LSB
MSB
MSB–1
MSB–2
Figure 68. Right Justified Mode
Rev. B |
Page 143 of 173 |
December 2018
LSB+2
LSB+1
LSB
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Figure 69 and Table 97 show the default I2S justified mode. The frame sync is low for the left channel and high for the right channel. Data
is valid on the rising edge of serial clock. The MSB is left justified to the frame sync transition but with a delay.
Table 97. S/PDIF Transmitter I2S Mode
Parameter
Timing Requirement
tI2SD
Frame Sync to MSB Delay in I2S Mode
Nominal
Unit
1
SCLK
LEFT/RIGHT CHANNEL
DAI_P20–1
FS
DAI_P20–1
SCLK
tI2SD
DAI_P20–1
SDATA
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 69. I2S Justified Mode
Figure 70 and Table 98 show the left justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left justified to the frame sync transition with no delay.
Table 98. S/PDIF Transmitter Left Justified Mode
Parameter
Timing Requirement
tLJD
Frame Sync to MSB Delay in Left Justified Mode
DAI_P20–1
FS
LEFT/RIGHT CHANNEL
DAI_P20–1
SCLK
tLJD
DAI_P20–1
SDATA
MSB
MSB–1
MSB–2
LSB+2
LSB+1
LSB
Figure 70. Left Justified Mode
Rev. B |
Page 144 of 173 |
December 2018
Nominal
Unit
0
SCLK
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given in Table 99. Input signals are routed to the DAIx_PINx pins using the SRU.
Therefore, the timing specifications provided below are valid at the DAIx_PINx pins.
Table 99. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
3
ns
tSIHFS
Frame Sync Hold After Serial Clock Rising Edge
3
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
3
ns
1
tSIHD
1
1
Data Hold After Serial Clock Rising Edge
3
ns
tSITXCLKW
Transmit Clock Width
9
ns
tSITXCLK
Transmit Clock Period
20
ns
tSISCLKW
Clock Width
36
ns
tSISCLK
Clock Period
80
ns
The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The input of the
PCG can be either CLKIN or any of the DAI pins.
SAMPLE EDGE
tSITXCLKW
tSITXCLK
DAIx_PIN20–1
(TxCLK)
tSISCLK
tSISCLKW
DAIx_PIN20–1
(SCLK)
tSISFS
tSIHFS
DAIx_PIN20–1
(FS)
tSISD
tSIHD
DAIx_PIN20–1
(SDATA)
Figure 71. S/PDIF Transmitter Input Timing
Oversampling Clock (TxCLK) Switching Characteristics
The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the
internal biphase clock.
Table 100. Oversampling Clock (TxCLK) Switching Characteristics
Parameter
Switching Characteristics
fTXCLK_384
Frequency for TxCLK = 384 × Frame Sync
fTXCLK_256
Frequency for TxCLK = 256 × Frame Sync
fFS
Frame Rate (FS)
Rev. B |
Max
Unit
Oversampling ratio × frame sync ≤ 1/tSITXCLK
49.2
192.0
MHz
MHz
kHz
Page 145 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
S/PDIF Receiver
The following section describes timing as it relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital PLL mode, the internal digital PLL generates the 512 × FS clock.
Table 101. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Max
Unit
5
ns
5
ns
Switching Characteristics
tDFSI
Frame Sync Delay After Serial Clock
tHOFSI
Frame Sync Hold After Serial Clock
tDDTI
Transmit Data Delay After Serial Clock
tHDTI
Transmit Data Hold After Serial Clock
–2
–2
SAMPLE EDGE
DRIVE EDGE
DAIx_PIN20–1
(SCLK)
tDFSI
tHOFSI
DAIx_PIN20–1
(FS)
tDDTI
tHDTI
DAIx_PIN20–1
(DATA CHANNEL
A/B)
Figure 72. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. B |
Page 146 of 173 |
December 2018
ns
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Media LB (MLB)
All the numbers shown in Table 102 are applicable for all MLB speed modes (1024 FS, 512 FS, and 256 FS) for the 3-pin protocol, unless
otherwise specified. Refer to the Media Local Bus Specification version 4.2 for more details.
Table 102. 3-Pin MLB Interface Specifications
Parameter
tMLBCLK
tMCKL
tMCKH
tMCKR
tMCKF
tMPWV1
tDSMCF
tDHMCF
tMCFDZ
tMCDRV
tMDZH2
CMLB
1
2
Min
MLB Clock Period
1024 FS
512 FS
256 FS
MLBCLK Low Time
1024 FS
512 FS
256 FS
MLBCLK High Time
1024 FS
512 FS
256 FS
MLBCLK Rise Time (VIL to VIH)
1024 FS
512 FS/256 FS
MLBCLK Fall Time (VIH to VIL)
1024 FS
512 FS/256 FS
MLBCLK Pulse Width Variation
1024 FS
512 FS/256
DAT/SIG Input Setup Time
DAT/SIG Input Hold Time
DAT/SIG Output Time to Three-State
DAT/SIG Output Data Delay From MLBCLK Rising Edge
Bus Hold Time
1024 FS
512 FS/256
DAT/SIG Pin Load
1024 FS
512 FS/256
Typ
Max
20.3
40
81
Unit
ns
ns
ns
6.1
14
30
ns
ns
ns
9.3
14
30
ns
ns
ns
1
2
0
1
3
ns
ns
1
3
ns
ns
0.7
2.0
nspp
nspp
15
8
ns
ns
ns
ns
2
4
ns
ns
40
60
pf
pf
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak.
Board designs must ensure the high impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while
meeting the maximum capacitive load listed.
Rev. B |
Page 147 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
MLB_SIG/
MLB_DAT
(Rx, Input)
VALID
tDHMCF
tDSMCF
tMCKH
MLB_CLK
tMCKR
tMCKL
tMCKF
tMLBCLK
tMCFDZ
tMCDRV
tMDZH
MLB_SIG/
MLB_DAT
(Tx, Output)
VALID
Figure 73. MLB Timing (3-Pin Interface)
The ac timing specifications of the 6-pin MLB interface is detailed in Table 103. Refer to the Media Local Bus Specification version 4.2 for
more details.
Table 103. 6-Pin MLB Interface Specifications
Parameter
tMT
Differential Transition Time at the Input Pin (See Figure 74)
1
2
fMCKE
MLBCP/N External Clock Operating Frequency (See Figure 75)1
fMCKR
Recovered Clock Operating Frequency (Internal, not Observable
at Pins, Only for Timing References) (See Figure 75)
tDELAY
Transmitter MLBSP/N (MLBDP/N) Output Valid From Transition of
MLBCP/N (Low to High) (See Figure 76)
tPHZ
Conditions
20% to 80% VIN+/VIN–
80% to 20% VIN+/VIN–
2048 × FS at 44.0 kHz
2048 × FS at 50.0 kHz
2048 × FS at 44.0 kHz
2048 × FS at 50.0 kHz
fMCKR = 2048 × FS
Min
Typ
Max
1
90.112
Unit
ns
0.6
102.4
5
MHz
MHz
MHz
MHz
ns
Disable Turnaround Time From Transition of MLBCP/N (Low to High) fMCKR = 2048 × FS
(See Figure 77)
0.6
7
ns
tPLZ
Enable Turnaround Time From Transition of MLBCP/N (Low to High)
(See Figure 77)
fMCKR = 2048 × FS
0.6
11.2
ns
tSU
MLBSP/N (MLBDP/N) Valid to Transition of MLBCP/N (Low to High)
(See Figure 76)
fMCKR = 2048 × FS
1
ns
tHD
MLBSP/N (MLBDP/N) Hold From Transition of MLBCP/N (Low to High)
(See Figure 76)2
0.6
ns
102.4
90.112
fMCKE (maximum) and fMCKR (maximum) include maximum cycle to cycle system jitter (tJITTER) of 600 ps for a bit error rate of 10E-9.
Receivers must latch MLBSP/N (MLBDP/N) data within tHD (min) of the rising edge of MLBCP/N.
Rev. B |
Page 148 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
tMT
MLBCP/N
MLBDP/N
MLBSP/N
tMT
80%
20%
Figure 74. MLB 6-Pin Transition Time
MLBCP/N
1/fMCKE
RECOVERED
CLOCK (1:1)
T1:1
NOTE: T1:1 = 1/fMCKE
Figure 75. MLB 6-Pin Clock Definitions
1/fMCKE
MLBCP/N
1/fMCKR
RECOVERED
CLOCK
tDELAY
tDELAY
MLBSP/N
MLBDP/N
(TRANSMIT)
tSU
MLBSP/N
MLBDP/N
(RECEIVE)
VALID
VALID
tHD
tHD
Figure 76. MLB 6-Pin Delay, Setup, and Hold Times
MLBCP/N
RECOVERED
CLOCK (1:1)
tPHZ
MLBDP/N
MLNSP/N
tPLZ
Figure 77. MLB 6-Pin Disable and Enable Turnaround Times
Rev. B |
Page 149 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Mobile Storage Interface (MSI) Controller Timing
Table 104 and Figure 78 show I/O timing related to the MSI.
Table 104. MSI Controller Timing
Parameter
Min
Max
Unit
Timing Requirements
tISU
Input Setup Time
4.8
ns
tIH
Input Hold Time
–0.5
ns
Switching Characteristics
1
fPP
Clock Frequency Data Transfer Mode1
tWL
Clock Low Time
8
tWH
Clock High Time
8
tTLH
Clock Rise Time
tTHL
Clock Fall Time
3
ns
tODLY
Output Delay Time During Data Transfer Mode
2
ns
tOH
Output Hold Time
50
MHz
ns
ns
3
ns
–1.8
ns
tPP = 1/fPP.
VOH (MIN)
tPP
MSI_CLK
tTHL
tISU
tTLH
tWL
tIH
VOL (MAX)
tWH
INPUT
tODLY
tOH
OUTPUT
NOTES:
1 INPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS.
2 OUTPUT INCLUDES MSI_Dx AND MSI_CMD SIGNALS.
Figure 78. MSI Controller Timing
Rev. B |
Page 150 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Program Trace Macrocell (PTM) Timing
Table 105 and Figure 79 provide I/O timing related to the PTM.
Table 105. Trace Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDTRD
Trace Data Delay From Trace Clock Maximum
tHTRD
Trace Data Hold From Trace Clock Minimum
0.5 × tSCLK0 – 1.2
0.5 × tSCLK0 + 2
ns
tPTRCK
Trace Clock Period Minimum
2 × tSCLK0 – 1
ns
tPTRCK
TRACE0_CLK
tHTRD
D0
TRACE0_DX
tDTRD
D1
tDTRD
Figure 79. Trace Timing
Rev. B |
Page 151 of 173 |
tHTRD
December 2018
ns
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Debug Interface (JTAG Emulation Port) Timing
Table 106 and Figure 80 provide I/O timing related to the debug interface (JTAG Emulator Port).
Table 106. JTAG Emulation Port Timing
Parameter
Min
Max
Unit
Timing Requirements
tTCK
JTG_TCK Period
20
ns
tSTAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
4
ns
tHTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High
4
ns
tSSYS
System Inputs Setup Before JTG_TCK High1
12
ns
tHSYS
System Inputs Hold After JTG_TCK High1
5
ns
4
TCK
JTG_TRST Pulse Width (measured in JTG_TCK cycles)
tTRSTW
2
Switching Characteristics
tDTDO
JTG_TDO Delay From JTG_TCK Low
13.5
ns
tDSYS
System Outputs Delay After JTG_TCK Low3
17
ns
1
System Inputs = MLB0_CLKP, MLB0_DATP, MLB0_SIGP, DAI0_PIN20-01, DAI1_PIN20-01, DMC0_A15-0, DMC1_A15-0, DMC0_DQ15-0, DMC1_DQ15-0,
DMC0_RESET, DMC1_RESET, PA_15-0, PB_15-0, PC_15-0, PD_15-0, PE_15-0, PF_15-0, PG_5-0, SYS_BMODE2-0, SYS_FAULT, SYS_FAULT, SYS_RESOUT,
TWI2-0_SCL, TWI2-0_SDA2.
2
50 MHz maximum.
3
System Outputs = DMC0_A15-0, DMC0_BA2-0, DMC0_CAS, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ15-0, DMC0_LDM, DMC0_LDQS, DMC0_ODT,
DMC0_RAS, DMC0_RESET, DMC0_UDM, DMC0_UDQS, DMC0_WE, DMC1_A15-0, DMC1_BA2-0, DMC1_CAS, DMC1_CK, DMC1_CKE, DMC1_CS0,
DMC1_DQ15-0, DMC1_LDM, DMC1_LDQS, DMC1_ODT, DMC1_RAS, DMC1_RESET, DMC1_UDM, DMC1_UDQS, DMC1_WE, MLB0_DATP, MLB0_SIGP,
PA_15-0, PB_15-0, PC_15-0, PCIE_TXP, PD_15-0, PE_15-0, PF_15-0, PG_5-0, SYS_BMODE2-0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT, SYS_RESOUT.
tTCK
JTG_TCK
tSTAP
tHTAP
JTG_TMS
JTG_TDI
tDTDO
JTG_TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 80. JTAG Port Timing
Rev. B |
Page 152 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
OUTPUT DRIVE CURRENTS
50
Output drive currents for PCIe pins are compliant with PCIe
Gen1 and Gen2 x1 lane data rate specifications. Output drive
currents for MLB pins are compliant with MOST150 LVDS
specifications. Output drive currents for USB pins are compliant with the USB 2.0 specifications.
VOH
40
VDD_EXT = 3.47V AT –40°C
VDD_EXT = 3.30V AT +25°C
VDD_EXT = 3.13V AT +133°C
30
SOURCE CURRENT (mA)
Figure 81 through Figure 93 show typical current-voltage characteristics for the output drivers of the ADSP-SC58x and ADSP2158x processors. The curves represent the current drive capability of the output drivers as a function of output voltage.
20
10
0
VOL
–10
VDD_EXT = 3.13V AT +133°C
VDD_EXT = 3.30V AT +25°C
VDD_EXT = 3.47V AT –40°C
–20
–30
–40
50
VOH
40
VDD_EXT = 3.47V AT –40°C
VDD_EXT = 3.30V AT +25°C
VDD_EXT = 3.13V AT +133°C
–50
0
0.5
1.0
20
1.5
2.0
2.5
SOURCE VOLTAGE (V)
3.0
3.5
4.0
Figure 83. Driver Type H Current (3.3 V VDD_EXT)
10
0
0
VOL
–10
VDD_EXT = 3.13V AT +133°C
VDD_EXT = 3.30V AT +25°C
VDD_EXT = 3.47V AT –40°C
–20
–30
–40
–50
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
3.0
3.5
VDD_DMC = 1.425V AT +133°C
VDD_DMC = 1.500V AT +25°C
VDD_DMC = 1.575V AT –40°C
–5
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
30
4.0
Figure 81. Driver Type A Current (3.3 V VDD_EXT)
–10
–15
–20
0
–5
VOL
VDD_EXT = 3.13V AT +133°C
VDD_EXT = 3.30V AT +25°C
VDD_EXT = 3.47V AT –40°C
–25
0
0.2
0.4
0.6
0.8
1.0
SOURCE VOLTAGE (V)
1.2
1.4
1.6
Figure 84. Driver Type B and Driver Type C (DDR3 Drive Strength 40 Ω)
–15
–20
0
–25
–2
–30
–35
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
–10
–40
–45
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
2.5
3.0
Figure 82. Driver Type D Current (3.3 V VDD_EXT)
VDD_DMC = 1.425V AT +133°C
VDD_DMC = 1.500V AT +25°C
VDD_DMC = 1.575V AT –40°C
–4
–6
–8
–10
–12
–14
–16
0
0.2
0.4
0.6
0.8
SOURCE VOLTAGE (V)
1.0
1.2
Figure 85. Driver Type B and Driver Type C (DDR3 Drive Strength 60 Ω)
Rev. B |
Page 153 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
0
25
–2
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
VDD_DMC = 1.7V AT +133°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.9V AT –40°C
–4
20
15
10
VDD_DMC = 1.575V AT –40°C
VDD_DMC = 1.500V AT +25°C
VDD_DMC = 1.425V AT +133°C
5
–6
v8
–10
–12
–14
–16
v18
–20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
0.2
0.4
SOURCE VOLTAGE (V)
0.6
0.8
1.0
1.2
1.4
SOURCE VOLTAGE (V)
Figure 86. Driver Type B and Driver Type C (DDR3 Drive Strength 40 Ω)
Figure 89. Driver Type B and Driver Type C (DDR2 Drive Strength 60Ω)
16
30
14
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
25
12
10
8
6
VDD_DMC = 1.575V AT –40°C
VDD_DMC = 1.500V AT +25°C
VDD_DMC = 1.425V AT +133°C
4
2
0.2
0.4
0.6
0.8
1.0
15
10
VDD_DMC = 1.9V AT –40°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.7V AT +133°C
5
0
0
20
1.2
1.4
1.6
0
1.8
0
0.2
0.4
SOURCE VOLTAGE (V)
Figure 87. Driver Type B and Driver Type C (DDR3 Drive Strength 60 Ω)
0.8
1.0
1.2
1.4
SOURCE VOLTAGE (V)
1.6
1.8
2.0
Figure 90. Driver Type B and Driver Type C (DDR2 Drive Strength 40Ω)
0
20
18
–5
16
VDD_DMC = 1.7V AT +133°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.9V AT –40°C
–10
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
0.6
–15
–20
–25
14
12
10
8
6
VDD_DMC = 1.9V AT –40°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.7V AT +133°C
4
–30
2
–35
0
0
0.2
0.4
0.6
0.8
1.0
1.2
SOURCE VOLTAGE (V)
1.4
1.6
1.8
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE(V)
Figure 88. Driver Type B and Driver Type C (DDR2 Drive Strength 40 Ω)
Rev. B |
Page 154 of 173 |
Figure 91. Driver Type B and Driver Type C (DDR2 Drive Strength 60 Ω)
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Output Enable Time Measurement
0
VDD_DMC = 1.7V AT +133°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.9V AT –40°C
–5
Output pins are considered enabled when they make a transition from a high impedance state to the point when they start
driving.
SOURCE CURRENT (mA)
–10
The output enable time, tENA, is the interval from the point
when a reference signal reaches a high or low voltage level to the
point when the output starts driving, as shown on the right side
of Figure 95. If multiple pins are enabled, the measurement
value is that of the first pin to start driving.
–15
–20
–25
–30
–35
REFERENCE
SIGNAL
–40
–45
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
SOURCE VOLTAGE (V)
tDIS
tENA
Figure 92. Driver Type B and Device Driver C (LPDDR)
45
40
SOURCE CURRENT (mA)
35
OUTPUT STOPS DRIVING
30
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
25
Figure 95. Output Enable/Disable
20
Output Disable Time Measurement
15
Output pins are considered disabled when they stop driving,
enter a high impedance state, and start to decay from the output
high or low voltage. The output disable time, tDIS, is the interval
from when a reference signal reaches a high or low voltage level
to the point when the output stops driving, as shown on the left
side of Figure 95.
10
VDD_DMC = 1.9V AT –40°C
VDD_DMC = 1.8V AT +25°C
VDD_DMC = 1.7V AT +133°C
5
0
0
0.5
1.0
1.5
2.0
2.5
SOURCE VOLTAGE (V)
Figure 93. Driver Type B and Device Driver C (LPDDR)
Capacitive Loading
TEST CONDITIONS
All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 94
shows the measurement point for ac measurements (except output enable/disable). The measurement point, VMEAS, is
VDD_EXT/2 for VDD_EXT (nominal) = 3.3 V.
INPUT
OR
OUTPUT
VMEAS
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 96). VLOAD is equal
to VDD_EXT/2. Figure 97 through Figure 101 show how output
rise time varies with capacitance. The delay and hold specifications given must be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
VMEAS
Figure 94. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Rev. B |
Page 155 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
TESTER PIN ELECTRONICS
3.0
50:
T1
DUT
OUTPUT
45:
70:
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
REFERENCE
50:
SIGNAL
0.5pF
2pF
4pF
tDIS_MEASURED
400:
tDIS
VOH
(MEASURED)
tENA_MEASURED
tENA
VOH
(MEASURED)
VOH (MEASURED) - ΔV
2.5
RISE AND FALL TIMES (ns)
VLOAD
VOL (MEASURED) + ΔV
VTRIP (LOW)
NOTES:
VOL
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND V
CAN
OL BE USED
(MEASURED)
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION
LINE
(MEASURED)
t
DECAY
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE
tTRIP(TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
tFALL = 3.3V AT 25°C
1.0
5
10
15
20
25
30
35
40
LOAD CAPACITANCE (pF)
Figure 98. Driver Type H Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VDD_EXT = 3.3 V)
0.9
RISE AND FALL TIMES (ns)
0.8
5.0
4.5
4.0
RISE AND FALL TIMES (ns)
1.5
00
Figure 96. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
3.5
tRISE = 3.3V AT 25°C
3.0
2.5
tRISE = 3.3V AT 25°C
0.5
VTRIP (HIGH)
ANALOG
DEVICES
RECOMMENDS
OUTPUT
STOPS
DRIVING USING THE IBIS MODEL TIMING FOR A GIVEN
OUTPUT
DRIVING
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM
MAYSTARTS
INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
HIGH IMPEDANCE STATE
2.0
tFALL = 3.3V AT 25°C
0.7
tRISE = 1.8V AT 25°C
0.6
0.5
tFALL = 1.8V AT 25°C
0.4
0.3
0.2
2.0
0.1
1.5
0
0
1.0
2
4
6
8
LOAD CAPACITANCE (pF)
10
12
0.5
Figure 99. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) for LPDDR
0
0
5
10
15
20
25
30
35
40
LOAD CAPACITANCE (pF)
Figure 97. Driver Type A Typical Rise and Fall Times (10% to 90%) vs. Load
Capacitance (VDD_EXT = 3.3 V)
0.9
RISE AND FALL TIMES (ns)
0.8
0.7
tRISE = 1.8V AT 25°C
0.6
0.5
tFALL = 1.8V AT 25°C
0.4
0.3
0.2
0.1
0
0
2
4
6
8
LOAD CAPACITANCE (pF)
10
12
Figure 100. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance (VDD_DMC = 1.8 V) for DDR2
Rev. B |
Page 156 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Table 107. Thermal Characteristics for 349 CSP_BGA
0.9
Parameter
JA
JA
JA
JC
JT
JT
JT
RISE AND FALL TIMES (ns)
0.8
0.7
tRISE = 1.5V AT 25°C
0.6
0.5
tFALL = 1.5V AT 25°C
0.4
0.3
0.2
Conditions
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typ
13.3
12.1
11.6
3.65
0.08
0.12
0.14
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 108. Thermal Characteristics for 529 CSP_BGA
0.1
0
0
2
4
6
8
LOAD CAPACITANCE (pF)
10
12
Figure 101. Driver Type B and Driver Type C Typical Rise and Fall Times
(10% to 90%) vs. Load Capacitance (VDD_DMC = 1.5 V) for DDR3
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application PCB,
use the following equation:
Parameter
JA
JA
JA
JC
JT
JT
JT
T = T
+ P
J
CASE
JT
D
where:
TJ = junction temperature (°C).
TCASE = case temperature (°C) measured at top center of
package.
JT = from Table 107 and Table 108.
PD = power dissipation (see the Total Internal Power Dissipation section for the method to calculate PD).
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first order approximation of TJ by the following equation:
T J = T A + JA P D
where TA = ambient temperature (°C).
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
In Table 107 and Table 108, airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6. The junction to case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 6-layer PCB with
101.6 mm × 152.4 mm dimensions.
Rev. B |
Page 157 of 173 |
December 2018
Conditions
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typ
13.4
12.1
11.6
3.63
0.08
0.11
0.13
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS
The ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments
(Numerical by Ball Number) table lists the 349-ball BGA package by ball number.
The ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments
(Alphabetical by Pin Name) table lists the 349-ball BGA package
by pin name.
ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
Pin Name
GND
DMC0_A06
DMC0_A04
DMC0_RAS
DMC0_CKE
DMC0_DQ15
DMC0_DQ13
DMC0_UDQS
DMC0_UDQS
DMC0_DQ09
DMC0_VREF
DMC0_CK
DMC0_CK
DMC0_DQ06
DMC0_LDQS
DMC0_LDQS
DMC0_DQ01
GND
PD_00
PD_03
PD_06
GND
DMC0_A07
GND
DMC0_A02
DMC0_A00
DMC0_ODT
DMC0_DQ14
DMC0_DQ12
GND
DMC0_DQ11
DMC0_DQ10
DMC0_DQ08
DMC0_DQ07
DMC0_DQ05
DMC0_DQ04
DMC0_DQ03
DMC0_DQ02
DMC0_DQ00
PC_13
PD_02
Ball No.
B20
B21
B22
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D01
D02
D03
D11
D12
D20
D21
D22
E01
E02
E03
E05
E20
E21
E22
F01
Pin Name
PD_05
GND
PD_08
DMC0_A10
DMC0_A09
GND
DMC0_A08
DMC0_A03
DMC0_CAS
DMC0_BA0
DMC0_A01
DMC0_RZQ
DMC0_WE
DMC0_CS0
GND
DMC0_LDM
DMC0_UDM
PD_01
PC_14
SYS_CLKOUT
PC_15
PD_04
GND
PD_07
PD_11
DMC0_A11
DMC0_A12
DMC0_BA2
VDD_INT
VDD_INT
PD_10
PD_09
PD_12
DMC0_A14
DMC0_A15
DMC0_A13
DMC0_A05
VDD_INT
PD_13
PD_14
DMC0_RESET
Rev. B |
Ball No.
F02
F03
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F20
F21
F22
G01
G02
G03
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
H01
H02
H03
H06
H07
H16
Page 158 of 173 |
Pin Name
PC_11
DMC0_BA1
VDD_DMC
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_DMC
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
PD_15
PE_00
PC_12
PC_10
PC_04
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
PE_01
PE_02
PC_08
PC_07
SYS_FAULT
VDD_DMC
VDD_DMC
GND
December 2018
Ball No.
H17
H20
H21
H22
J01
J02
J03
J06
J09
J10
J11
J12
J13
J14
J17
J20
J21
J22
K01
K02
K03
K06
K08
K09
K10
K11
K12
K13
K14
K15
K17
K20
K21
K22
L01
L02
L03
L04
L06
L08
L09
Pin Name
VDD_DMC
VDD_INT
PE_03
PE_04
PC_05
PC_06
JTG_TDI
VDD_DMC
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_05
PE_06
PC_03
PC_02
SYS_FAULT
VDD_INT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_08
PE_07
PC_01
SYS_HWRST
PC_09
VDD_INT
VDD_INT
GND
GND
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Ball No.
L10
L11
L12
L13
L14
L15
L17
L19
L20
L21
L22
M01
M02
M03
M04
M06
M08
M09
M10
M11
M12
M13
M14
M15
M17
M19
M20
M21
M22
N01
N02
N03
N06
N08
N09
N10
N11
N12
N13
N14
N15
N17
N20
N21
N22
P01
P02
Pin Name
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_11
PE_10
PE_09
JTG_TRST
JTG_TMS
JTG_TCK
VDD_INT
VDD_INT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_13
PE_15
PE_12
SYS_XTAL1
SYS_BMODE0
PC_00
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
DAI1_PIN04
DAI1_PIN02
PE_14
SYS_CLKIN1
SYS_BMODE1
Ball No.
P03
P06
P09
P10
P11
P12
P13
P14
P17
P20
P21
P22
R01
R02
R03
R06
R07
R16
R17
R20
R21
R22
T01
T02
T03
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
U01
U02
U03
U06
U07
U08
U09
Pin Name
JTG_TDO
VDD_EXT
GND
GND
GND
GND
GND
GND
VDD_EXT
DAI1_PIN01
DAI1_PIN05
DAI1_PIN03
GND
PB_15
PB_14
VDD_EXT
GND
GND
VDD_EXT
DAI1_PIN08
DAI1_PIN07
DAI1_PIN06
SYS_XTAL0
SYS_BMODE2
DAI0_PIN07
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
DAI1_PIN12
DAI1_PIN10
DAI1_PIN09
SYS_CLKIN0
SYS_RESOUT
PB_07
VDD_EXT
VDD_EXT
VDD_USB
VDD_INT
Rev. B |
Ball No.
U10
U11
U12
U13
U14
U15
U16
U17
U20
U21
U22
V01
V02
V03
V20
V21
V22
W01
W02
W03
W11
W12
W20
W21
W22
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Page 159 of 173 |
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
DAI1_PIN20
DAI1_PIN11
DAI1_PIN19
PB_13
PB_12
DAI0_PIN20
PA_00
PA_01
PA_02
PB_10
PB_11
DAI0_PIN19
VDD_INT
VDD_INT
PA_05
PA_03
PA_04
PB_09
PB_08
DAI0_PIN12
DAI0_PIN06
DAI0_PIN02
DAI0_PIN03
DAI0_PIN01
USB0_VBC
TWI0_SCL
TWI1_SDA
VDD_HADC
GND
HADC0_VIN6
PB_06
PB_00
PB_04
PB_01
PA_10
PA_15
GND
PA_06
PA_08
December 2018
Ball No.
AA01
AA02
AA03
AA04
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Pin Name
DAI0_PIN11
GND
DAI0_PIN10
DAI0_PIN04
DAI0_PIN05
USB0_ID
USB0_VBUS
TWI2_SCL
TWI2_SDA
TWI0_SDA
HADC0_VIN2
HADC0_VIN5
HADC0_VIN4
HADC0_VIN7
PB_05
PB_02
PA_14
PB_03
PA_12
PA_11
GND
PA_09
GND
DAI0_PIN09
DAI0_PIN08
USB_CLKIN
USB_XTAL
USB0_DP
USB0_DM
TWI1_SCL
HADC0_VREFP
HADC0_VREFN
HADC0_VIN0
HADC0_VIN1
HADC0_VIN3
MLB0_SIGP
MLB0_SIGN
MLB0_DATP
MLB0_DATN
MLB0_CLKP
MLB0_CLKN
PA_13
PA_07
GND
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADSP-SC58x/ADSP-2158x 349-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
Ball No.
Y07
Y05
Y06
AA04
AA05
Y04
T03
AB03
AB02
AA03
AA01
Y03
W03
V03
P20
N21
P22
N20
P21
R22
R21
R20
T22
T21
U21
T20
U22
U20
B04
C08
B03
C05
A03
E05
A02
B01
C04
C02
C01
D01
D02
E03
E01
E02
C07
F03
D03
Pin Name
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
C06
A13
A05
A12
C11
B17
A17
B16
B15
B14
B13
A14
B12
B11
A10
B10
B09
B07
A07
B06
A06
C13
A16
A15
B05
A04
F01
C09
C14
A09
A08
A11
C10
A01
A18
A22
AA02
AA21
AB01
AB22
B02
B08
B21
C03
C12
C20
H16
Rev. B |
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Page 160 of 173 |
December 2018
Ball No.
J09
J10
J11
J12
J13
J14
K08
K09
K10
K11
K12
K13
K14
K15
L08
L09
L10
L11
L12
L13
L14
L15
M08
M09
M10
M11
M12
M13
M14
M15
N08
N09
N10
N11
N12
N13
N14
N15
P09
P10
P11
P12
P13
P14
R01
R07
R16
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
Ball No.
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
Y12
Y20
AB11
AB12
AA11
AB13
AA13
AA12
Y13
AA14
AB10
AB09
M03
J03
P03
M02
M01
AB19
AB18
AB17
AB16
AB15
AB14
V20
V21
V22
W21
W22
W20
Y21
AB21
Y22
AA22
Y18
AA20
AA19
AB20
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Pin Name
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
Ball No.
AA17
Y19
Y15
Y17
AA16
AA18
Y16
AA15
Y14
U03
Y02
Y01
W01
W02
V02
V01
R03
R02
N03
L01
K02
K01
G03
J01
J02
H02
H01
L03
G02
F02
G01
B18
C16
C18
A19
C15
B19
A20
C19
B20
A21
C21
B22
D21
D20
C22
D22
E21
Pin Name
PD_14
PD_15
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB_CLKIN
USB_XTAL
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Ball No.
E22
F21
F22
G21
G22
H21
H22
J21
J22
K22
K21
L22
L21
L20
M22
M20
N22
M21
N02
P02
T02
U01
P01
C17
H03
K03
L02
U02
T01
N01
Y09
AA10
AB08
Y10
AA08
AA09
AB07
AB06
AA06
Y08
AA07
AB04
AB05
F06
F11
G06
G07
G08
Rev. B |
Pin Name
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_HADC
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Page 161 of 173 |
December 2018
Ball No.
G09
G10
G11
G12
G13
G14
G15
G16
G17
H06
H07
H17
J06
J17
K17
L17
M17
N06
N17
P06
P17
R06
R17
T06
T17
U06
U07
U14
U15
U16
U17
Y11
D11
D12
E20
F07
F08
F09
F10
F12
F13
F14
F15
F16
F17
F20
G20
H20
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_USB
Ball No.
J20
K06
K20
L04
L06
L19
M04
M06
M19
U09
U10
U11
U12
U13
W11
W12
U08
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
CONFIGURATION OF THE 349-BALL CSP_BGA
Figure 102 shows an overview of signal placement on the 349-ball CSP_BGA.
TOP VIEW
A1 BALL
CORNER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
A
B
C
D
E
F
GND
G
I/O SIGNALS
H
J
VDD_EXT
K
VDD_INT
L
VDD_DDR
M
U
VDD_USB
N
H
VDD_HADC
P
R
T
U
U
V
W
Y
H
AA
AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
A1 BALL
CORNER
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
U
V
W
Y
H
AA
AB
BOTTOM VIEW
Figure 102. 349-Ball CSP_BGA Configuration
Rev. B |
Page 162 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS
The ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments
(Numerical by Ball Number) table lists the 529-ball BGA package by ball number.
The ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments
(Alphabetical by Pin Name) table lists the 529-ball BGA package
by pin name.
ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
Pin Name
GND
DMC0_UDQS
DMC0_CK
DMC0_CK
DMC0_DQ09
DMC0_LDQS
DMC0_LDQS
DMC0_DQ05
DMC0_DQ03
DMC0_DQ01
DMC1_DQ03
DMC1_DQ00
DMC1_LDQS
DMC1_LDQS
DMC1_VREF
DMC1_CK
DMC1_CK
DMC1_DQ09
DMC1_UDQS
DMC1_UDQS
DMC1_DQ13
DMC1_DQ15
GND
DMC0_UDQS
DMC0_DQ12
DMC0_DQ11
DMC0_DQ10
DMC0_DQ08
DMC0_DQ06
DMC0_DQ07
DMC0_DQ04
DMC0_DQ02
DMC0_DQ00
DMC1_DQ01
DMC1_DQ02
DMC1_DQ04
DMC1_DQ05
DMC1_DQ06
DMC1_DQ07
DMC1_DQ08
DMC1_DQ10
Ball No.
B19
B20
B21
B22
B23
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
Pin Name
DMC1_DQ11
DMC1_DQ12
DMC1_DQ14
PD_00
PD_04
DMC0_DQ14
DMC0_DQ13
DMC0_CS0
DMC0_CKE
DMC0_LDM
DMC1_RESET
DMC1_A03
DMC1_A00
DMC1_A01
DMC1_A04
DMC1_A06
DMC1_BA1
DMC1_ODT
DMC1_CS0
DMC1_LDM
DMC1_UDM
DMC1_A14
DMC1_A12
DMC1_A13
PC_13
PD_01
PD_06
PD_05
DMC0_VREF
DMC0_DQ15
DMC0_BA0
DMC0_BA2
DMC0_ODT
DMC0_UDM
DMC1_A05
DMC1_WE
DMC1_A07
DMC1_A02
DMC1_BA0
DMC1_A08
DMC1_CKE
Rev. B |
Ball No.
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
F01
F02
F03
F04
F05
F06
F07
F08
Page 163 of 173 |
Pin Name
DMC1_BA2
DMC1_CAS
DMC1_RAS
DMC1_A09
DMC1_A15
DMC1_A10
DMC1_A11
PC_14
PD_10
PD_09
DMC0_A04
DMC0_RAS
DMC0_BA1
DMC0_WE
DMC0_RZQ
GND
GND
GND
GND
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
DMC1_RZQ
PC_15
PD_08
PD_14
PD_11
DMC0_A01
DMC0_A06
DMC0_CAS
DMC0_A02
DMC0_A07
GND
VDD_INT
VDD_INT
December 2018
Ball No.
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
H01
H02
H03
Pin Name
GND
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
GND
VDD_INT
VDD_INT
VDD_INT
PE_06
PD_02
PD_13
PD_12
DMC0_A13
DMC0_A09
DMC0_A03
DMC0_A11
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
PE_04
PE_13
PE_01
PE_00
DMC0_A14
DMC0_A12
DMC0_A05
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Ball No.
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
K01
K02
K03
K04
Pin Name
DMC0_A00
VDD_INT
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_INT
SYS_CLKOUT
PE_12
PE_05
PE_02
DMC0_A15
DMC0_A10
DMC0_A08
PC_08
VDD_INT
VDD_DMC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
PD_03
PD_07
PF_14
PF_01
PE_07
DMC0_RESET
PC_11
PC_06
PC_09
Ball No.
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
M01
M02
M03
M04
M05
Pin Name
VDD_INT
VDD_DMC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PD_15
PF_11
PF_06
PE_10
PC_04
PC_12
PC_07
PC_10
VDD_INT
VDD_DMC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_03
PF_09
PE_09
PE_14
PC_01
PC_05
PC_02
SYS_FAULT
VDD_INT
Rev. B |
Ball No.
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
P01
P02
P03
P04
P05
P06
Page 164 of 173 |
Pin Name
VDD_DMC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
PE_08
PE_11
PF_03
PF_00
PF_02
JTG_TMS
JTG_TRST
SYS_HWRST
PC_03
VDD_INT
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PE_15
PF_04
PF_05
PF_07
JTG_TDO
JTG_TDI
SYS_FAULT
JTG_TCK
VDD_INT
VDD_EXT
December 2018
Ball No.
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
T01
T02
T03
T04
T05
T06
T07
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
PF_10
PF_08
PF_15
PF_12
PG_00
SYS_XTAL1
SYS_BMODE1
SYS_BMODE2
SYS_BMODE0
VDD_INT
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
PG_01
PG_05
PG_04
PF_13
SYS_CLKIN1
PB_15
GND
PB_14
VDD_INT
VDD_EXT
GND
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Ball No.
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
V01
V02
V03
V04
V05
V06
V07
V08
V09
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
VDD_INT
DAI1_PIN03
PG_03
PG_02
DAI1_PIN01
SYS_XTAL0
SYS_RESOUT
PC_00
DAI0_PIN20
VDD_INT
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_EXT
DAI1_PIN08
DAI1_PIN07
DAI1_PIN04
DAI1_PIN05
DAI1_PIN02
SYS_CLKIN0
PB_13
DAI0_PIN19
DAI0_PIN12
VDD_INT
VDD_EXT
VDD_PCIE_RX
VDD_PCIE_TX
VDD_EXT
Ball No.
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Pin Name
VDD_EXT
VDD_EXT
HADC0_VIN4
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
DAI1_PIN16
DAI1_PIN06
DAI1_PIN12
DAI1_PIN09
PB_12
PB_09
DAI0_PIN18
DAI0_PIN11
VDD_INT
VDD_INT
VDD_PCIE
VDD_INT
VDD_INT
VDD_INT
VDD_INT
HADC0_VIN6
VDD_INT
VDD_RTC
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
DAI1_PIN20
DAI1_PIN11
DAI1_PIN10
DAI1_PIN13
PB_11
PB_10
DAI0_PIN17
DAI0_PIN08
DAI0_PIN05
DAI0_PIN10
USB0_ID
VDD_USB
USB0_VBC
TWI0_SCL
TWI2_SDA
Rev. B |
Ball No.
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA01
AA02
AA03
AA04
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
Page 165 of 173 |
Pin Name
HADC0_VIN0
HADC0_VIN7
GND
PB_05
PA_14
PA_13
PA_12
PA_10
PA_00
DAI1_PIN14
DAI1_PIN17
DAI1_PIN15
PB_08
PB_07
DAI0_PIN16
DAI0_PIN07
DAI0_PIN06
DAI0_PIN01
PCIE0_REF
USB1_VBUS
USB0_VBUS
TWI1_SCL
TWI1_SDA
HADC0_VIN1
HADC0_VIN5
PB_06
PB_02
PB_04
PB_03
PB_00
PA_09
PA_05
PA_01
DAI1_PIN19
DAI1_PIN18
DAI0_PIN15
DAI0_PIN14
DAI0_PIN09
DAI0_PIN13
DAI0_PIN04
DAI0_PIN02
DAI0_PIN03
USB_XTAL
USB_CLKIN
TWI2_SCL
TWI0_SDA
HADC0_VREFN
HADC0_VIN2
December 2018
Ball No.
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC01
AC02
AC03
AC04
AC05
AC06
AC07
AC08
AC09
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
Pin Name
HADC0_VIN3
RTC0_XTAL
MLB0_SIGN
MLB0_DATN
MLB0_CLKN
PA_15
PA_11
PA_06
PA_04
PA_02
GND
PCIE0_RXP
PCIE0_RXM
PCIE0_CLKM
PCIE0_CLKP
PCIE0_TXP
PCIE0_TXM
USB1_DM
USB1_DP
USB0_DP
USB0_DM
HADC0_VREFP
VDD_HADC
GND
RTC0_CLKIN
MLB0_SIGP
MLB0_DATP
MLB0_CLKP
PB_01
PA_07
PA_08
PA_03
GND
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ADSP-SC58x/ADSP-2158x 529-BALL BGA BALL ASSIGNMENTS (ALPHABETICAL BY PIN NAME)
Pin Name
DAI0_PIN01
DAI0_PIN02
DAI0_PIN03
DAI0_PIN04
DAI0_PIN05
DAI0_PIN06
DAI0_PIN07
DAI0_PIN08
DAI0_PIN09
DAI0_PIN10
DAI0_PIN11
DAI0_PIN12
DAI0_PIN13
DAI0_PIN14
DAI0_PIN15
DAI0_PIN16
DAI0_PIN17
DAI0_PIN18
DAI0_PIN19
DAI0_PIN20
DAI1_PIN01
DAI1_PIN02
DAI1_PIN03
DAI1_PIN04
DAI1_PIN05
DAI1_PIN06
DAI1_PIN07
DAI1_PIN08
DAI1_PIN09
DAI1_PIN10
DAI1_PIN11
DAI1_PIN12
DAI1_PIN13
DAI1_PIN14
DAI1_PIN15
DAI1_PIN16
DAI1_PIN17
DAI1_PIN18
DAI1_PIN19
DAI1_PIN20
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
Ball No.
AA06
AB06
AB07
AB05
Y05
AA05
AA04
Y04
AB03
Y06
W04
V04
AB04
AB02
AB01
AA03
Y03
W03
V03
U04
T23
U23
T20
U21
U22
V21
U20
U19
V23
W22
W21
V22
W23
Y21
Y23
V20
Y22
AA23
AA22
W20
H04
F01
F04
G03
E01
H03
Pin Name
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_A14
DMC0_A15
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_RESET
DMC0_RZQ
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_VREF
DMC0_WE
Ball No.
F02
F05
J03
G02
J02
G04
H02
G01
H01
J01
D03
E03
D04
F03
A04
C04
A03
C03
B10
A10
B09
A09
B08
A08
B06
B07
B05
A05
B04
B03
B02
C02
C01
D02
C05
A07
A06
D05
E02
K01
E05
D06
B01
A02
D01
E04
Rev. B |
Pin Name
DMC1_A00
DMC1_A01
DMC1_A02
DMC1_A03
DMC1_A04
DMC1_A05
DMC1_A06
DMC1_A07
DMC1_A08
DMC1_A09
DMC1_A10
DMC1_A11
DMC1_A12
DMC1_A13
DMC1_A14
DMC1_A15
DMC1_BA0
DMC1_BA1
DMC1_BA2
DMC1_CAS
DMC1_CK
DMC1_CKE
DMC1_CK
DMC1_CS0
DMC1_DQ00
DMC1_DQ01
DMC1_DQ02
DMC1_DQ03
DMC1_DQ04
DMC1_DQ05
DMC1_DQ06
DMC1_DQ07
DMC1_DQ08
DMC1_DQ09
DMC1_DQ10
DMC1_DQ11
DMC1_DQ12
DMC1_DQ13
DMC1_DQ14
DMC1_DQ15
DMC1_LDM
DMC1_LDQS
DMC1_LDQS
DMC1_ODT
DMC1_RAS
DMC1_RESET
Page 166 of 173 |
December 2018
Ball No.
C08
C09
D10
C07
C10
D07
C11
D09
D12
D17
D19
D20
C18
C19
C17
D18
D11
C12
D14
D15
A16
D13
A17
C14
A12
B11
B12
A11
B13
B14
B15
B16
B17
A18
B18
B19
B20
A21
B21
A22
C15
A13
A14
C13
D16
C06
Pin Name
DMC1_RZQ
DMC1_UDM
DMC1_UDQS
DMC1_UDQS
DMC1_VREF
DMC1_WE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
E19
C16
A20
A19
A15
D08
A01
A23
E06
E07
E08
E09
F06
F09
F16
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
L07
L08
L09
L10
L11
L12
L13
L14
L15
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
L16
L17
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
T03
T07
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HADC0_VIN0
HADC0_VIN1
HADC0_VIN2
HADC0_VIN3
HADC0_VIN4
HADC0_VIN5
HADC0_VIN6
HADC0_VIN7
HADC0_VREFN
HADC0_VREFP
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
MLB0_CLKN
MLB0_CLKP
MLB0_DATN
MLB0_DATP
MLB0_SIGN
MLB0_SIGP
PA_00
PA_01
Rev. B |
Ball No.
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
Y14
AC01
AC14
AC23
Y12
AA12
AB13
AB14
V12
AA13
W12
Y13
AB12
AC12
P04
P02
P01
N01
N02
AB18
AC18
AB17
AC17
AB16
AC16
Y20
AA21
Pin Name
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PCIE0_CLKM
PCIE0_CLKP
PCIE0_REF
PCIE0_RXM
PCIE0_RXP
PCIE0_TXM
PCIE0_TXP
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
Page 167 of 173 |
December 2018
Ball No.
AB23
AC22
AB22
AA20
AB21
AC20
AC21
AA19
Y19
AB20
Y18
Y17
Y16
AB19
AA18
AC19
AA15
AA17
AA16
Y15
AA14
AA02
AA01
W02
Y02
Y01
W01
V02
T04
T02
AC04
AC05
AA07
AC03
AC02
AC07
AC06
U03
M01
M03
N04
L01
M02
K03
L03
J04
K04
L04
Pin Name
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
Ball No.
K02
L02
C20
D21
E20
B22
C21
F21
J19
B23
C23
C22
J20
E21
D23
D22
E23
F23
F22
E22
K20
G23
G22
H23
L20
G20
H22
F20
J23
M19
L22
K23
M20
H21
G21
L23
N20
M22
J22
M23
M21
N21
N22
K22
N23
P20
L21
P19
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Pin Name
PF_11
PF_12
PF_13
PF_14
PF_15
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
RTC0_CLKIN
RTC0_XTAL
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN0
SYS_CLKIN1
SYS_CLKOUT
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_RESOUT
SYS_XTAL0
SYS_XTAL1
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
TWI2_SCL
TWI2_SDA
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
USB1_DM
USB1_DP
USB1_VBUS
USB_CLKIN
USB_XTAL
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Ball No.
K21
P22
R23
J21
P21
P23
R20
T22
T21
R22
R21
AC15
AB15
R04
R02
R03
V01
T01
H20
P03
M04
N03
U02
U01
R01
Y10
AB11
AA10
AA11
AB10
Y11
AC11
AC10
Y07
Y09
AA09
AC08
AC09
AA08
AB09
AB08
G06
G07
G08
G09
G10
G11
G12
Pin Name
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_HADC
Ball No.
G13
G14
G15
G16
G17
G18
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
J06
K06
L06
M06
J18
K18
L18
M18
N06
N18
P06
P18
R06
R18
T06
T18
U06
U18
V06
V09
V10
V11
V13
V14
V15
V16
V17
V18
AC13
Rev. B |
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Page 168 of 173 |
December 2018
Ball No.
E10
E11
E12
E13
E14
E15
E16
E17
E18
F07
F08
F10
F11
F12
F13
F14
F15
F17
F18
F19
G05
G19
H05
H19
J05
K05
K19
L05
L19
M05
N05
N19
P05
R05
R19
T05
T19
U05
V05
V19
W05
W06
W08
W09
W10
W11
W13
W15
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_PCIE
VDD_PCIE_RX
VDD_PCIE_TX
VDD_RTC
VDD_USB
Ball No.
W16
W17
W18
W19
W07
V07
V08
W14
Y08
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
CONFIGURATION OF THE 529-BALL CSP_BGA
Figure 103 shows an overview of signal placement on the 529-ball CSP_BGA.
TOP VIEW
A1 BALL
CORNER
1
2
3
4
5
6
7
8
V
C
T
W
P
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Y
R
U
AA
AB
AC
H
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
A1 BALL
CORNER
1
A
B
C
D
E
F
GND
G
I/O SIGNALS
H
VDD_EXT
J
VDD_INT
K
L
VDD_DDR
U
VDD_USB
R
VDD_RTC
P
VDD_PCIE
H
VDD_HADC
T
C
VDD_CORE_PCIRX
U
T
VDD_CORE_PCITX
M
N
P
R
T
R
C
V
P
W
U
Y
AA
AB
H
AC
BOTTOM VIEW
Figure 103. 529-Ball CSP_BGA Configuration
Rev. B |
Page 169 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
OUTLINE DIMENSIONS
Dimensions for the 19 mm × 19 mm 349-ball CSP_BGA package in Figure 104 are shown in millimeters.
A1 BALL
CORNER
19.10
19.00 SQ
18.90
A1 BALL
CORNER
22 20 18 16 14 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
A
C
G
16.80
BSC SQ
J
F
H
K
L
M
N
0.80
BSC
B
D
E
P
R
T
U
W
AA
TOP VIEW
1.50
1.36
1.21
V
Y
AB
BOTTOM VIEW
1.10 REF
DETAIL A
DETAIL A
1.11
1.01
0.91
0.35 NOM
0.30 MIN
SEATING
PLANE
0.50
COPLANARITY
0.20
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.
Figure 104. 349-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-349-1)
Dimensions shown in millimeters
Rev. B |
Page 170 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
Dimensions for the 19 mm × 19 mm 529-ball CSP_BGA package in Figure 105 are shown in millimeters.
A1 BALL
CORNER
19.10
19.00 SQ
18.90
A1 BALL
CORNER
22 20 18 16 14 12 10 8 6 4 2
23 21 19 17 15 13 11 9 7 5 3 1
A
C
17.60
REF SQ
0.80
BSC
TOP VIEW
1.50
1.36
1.21
0.70 REF
B
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
BOTTOM VIEW
DETAIL A
DETAIL A
1.11
1.01
0.91
0.39
0.35
0.30
SEATING
PLANE
0.50
COPLANARITY
0.2
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-RRAB-2.
Figure 105. 529-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-529-1)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 109 is an aid for PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for SurfaceMount Design and Land Pattern Standard.
Table 109. CSP_BGA Data for Use with Surface-Mount Design
Package
BC-349-1
BC-529-1
Package Ball Attach Type
Solder Mask Defined
Solder Mask Defined
Rev. B |
Package Solder Mask Opening
0.4 mm Diameter
0.4 mm Diameter
Page 171 of 173 |
December 2018
Package Ball Pad Size
0.5 mm Diameter
0.5 mm Diameter
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
AUTOMOTIVE PRODUCTS
The following models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models
may have specifications that differ from the nonautomotive
models; therefore designers should review the Specifications
section of this data sheet carefully. Only the automotive grade
products shown in Table 110 are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these
models.
Table 110. Automotive Products
Model 1, 2
AD21583WCBCZ4Axx
AD21584WCBCZ4Axx
AD21584WCBCZ5Axx
ADSC582WCBCZ4Axx
ADSC583WCBCZ3Axx
ADSC583WCBCZ4Axx
ADSC584WCBCZ3Axx
ADSC584WCBCZ4Axx
ADSC584WCBCZ5Axx
ADSC587WCBCZ4Bxx
ADSC587WBBCZ5Bxx
Processor Instruction
Rate (Max)
450 MHz
450 MHz
500 MHz
450 MHz
300 MHz
450 MHz
300 MHz
450 MHz
500 MHz
450 MHz
500 MHz
Temperature
Range3
–40°C to +105°C
–40°C to +105°C
–40°C to +100°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +100°C
–40°C to +105°C
–40°C to +85°C
Arm
Cores4
N/A
N/A
N/A
1
1
1
1
1
1
1
1
SHARC+
Cores
2
2
2
1
2
2
2
2
2
2
2
1
SHARC+
SRAM
384 kB
640 kB
640 kB
640 kB
384 kB
384 kB
640 kB
640 kB
640 kB
640 kB
640 kB
PCIe
Lanes4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Package
Description
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
Package
Option
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-529-1
BC-529-1
Z = RoHS Compliant Part.
xx denotes the current die revision.
3
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see the Operating Conditions section for the junction temperature
(TJ) specification which is the only temperature specification.
4
N/A means not applicable.
2
Rev. B |
Page 172 of 173 |
December 2018
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
ORDERING GUIDE
Model1
ADSP-21583KBCZ-4A
ADSP-21583BBCZ-4A
ADSP-21583CBCZ-4A
ADSP-21584KBCZ-4A
ADSP-21584KBCZ-5A
ADSP-21584BBCZ-4A
ADSP-21584BBCZ-5A
ADSP-21584CBCZ-4A
ADSP-21584CBCZ-5A
ADSP-21587KBCZ-4B
ADSP-21587KBCZ-5B
ADSP-21587BBCZ-4B
ADSP-21587BBCZ-5B
ADSP-SC582KBCZ-4A
ADSP-SC582BBCZ-4A
ADSP-SC582CBCZ-4A
ADSP-SC583KBCZ-3A
ADSP-SC583BBCZ-3A
ADSP-SC583CBCZ-3A
ADSP-SC583KBCZ-4A
ADSP-SC583BBCZ-4A
ADSP-SC583CBCZ-4A
ADSP-SC584KBCZ-3A
ADSP-SC584BBCZ-3A
ADSP-SC584CBCZ-3A
ADSP-SC584KBCZ-4A
ADSP-SC584KBCZ-5A
ADSP-SC584BBCZ-4A
ADSP-SC584BBCZ-5A
ADSP-SC584CBCZ-4A
ADSP-SC584CBCZ-5A
ADSP-SC587KBCZ-4B
ADSP-SC587KBCZ-5B
ADSP-SC587BBCZ-4B
ADSP-SC587BBCZ-5B
ADSP-SC589KBCZ-4B
ADSP-SC589KBCZ-5B
ADSP-SC589BBCZ-4B
ADSP-SC589BBCZ-5B
Processor Instruction
Rate (Max)
450 MHz
450 MHz
450 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
450 MHz
450 MHz
300 MHz
300 MHz
300 MHz
450 MHz
450 MHz
450 MHz
300 MHz
300 MHz
300 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
450 MHz
500 MHz
Temperature
Range2
0°C to +70°C
–40°C to +85°C
–40°C to +95°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +95°C
–40°C to +90°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +80°C
0°C to +70°C
–40°C to +85°C
–40°C to +95°C
0°C to +70°C
–40°C to +85°C
–40°C to +95°C
0°C to +70°C
–40°C to +85°C
–40°C to +95°C
0°C to +70°C
–40°C to +85°C
–40°C to +95°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +95°C
–40°C to +90°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +80°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +80°C
Arm
Cores3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SHARC+
Cores
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SHARC+
SRAM
384 kB
384 kB
384 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
384 kB
384 kB
384 kB
384 kB
384 kB
384 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
640 kB
1
PCIe
Lanes3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
Package
Description
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
349-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
529-Ball cspBGA
Package
Option
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
BC-529-1
Z =RoHS Compliant Part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see the Operating Conditions section for the junction temperature
(TJ) specification which is the only temperature specification.
3
N/A means not applicable.
2
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13317-0-12/18(B)
Rev. B |
Page 173 of 173 |
December 2018
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