ADV7175KS

a Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder ADV7175/ADV7176 Close Captioning Support Teletext Support (Passthrough Mode) On-Board Color Bar Generation On-Board Voltage Reference 2-Wire Serial MPU Interface (I2C Compatible) +5 V CMOS Monolithic Construction 44-Pin PQFP Thermally Enhanced Package APPLICATIONS MPEG-1 and MPEG-2 Video DVD Digital Satellite/Cable Systems (Set Top Boxes/IRDs) Video Games CD Video/Karaoke Professional Studio Quality PC Video/Multimedia GENERAL DESCRIPTION FEATURES CCIR-601 YCrCb to PAL/NTSC Video Encoder Single 27 MHz Clock Required ( 2 Oversampling) Pixel Port Supports: CCIR-656 4:2:2 8-Bit Parallel Input Format 4:2:2 16-Bit Parallel Input Format SMPTE 170M NTSC Compatible Composite Video Output CCIR624/CCIR601 PAL Compatible Composite Video Output SCART/PeriTV Support YUV Output Mode Simultaneous Composite and S-VHS Y/C or RGB YUV Video Outputs Programmable Luma Filters (Low-Pass/Notch) Square Pixel Support (Slave Mode) Allows Subcarrier Phase Locking with External Video Source 10-Bit DAC Resolution for Encoded Video Channels 8-Bit DAC Resolution for RGB Output YUV Interpolation for Accurate Subcarrier Construction Programmable Subcarrier Frequency and Phase Programmable LUMA Delay Color Signal Control/Burst Signal Control Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Master/Slave Operation Supported Master Mode Timing Programmability Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)* The ADV7175/ADV7176 is an integrated digital video encoder that converts Digital CCIR-601 4:2:2 component video data into a standard analog baseband television signal compatible with world wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In addition to the composite output signal, there is the facility to output S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or RGB format is simultaneously available at the analog outputs with the composite video signal. Each analog output generates a standard video-level signal into a doubly terminated 75 Ω load. (Continued on page 6) FUNCTIONAL BLOCK DIAGRAM 8 YUV TO RBG MATRIX 8 M U 10 L T I P 10 L E X 10 E R VAA 10-BIT DAC 10-BIT DAC 10-BIT DAC RESET 8 GREEN/ LUMA/ Y RED/ CHROMA/ V BLUE/ COMPOSITE/ U 8 COLOR DATA P7–P0 P15–P8 4:2:2 TO 4:4:4 INTERPOLATOR 8 YCrCb TO YUV MATRIX 8 ADD SYNC 8 INTERPOLATOR 8 Y LOW-PASS FILTER U LOW-PASS FILTER 10 8 ADD BURST 8 INTERPOLATOR 8 10 10 10-BIT DAC COMPOSITE 8 8 ADD BURST 8 INTERPOLATOR 8 10 V LOW-PASS FILTER 10 10 ADV7175/ADV7176 VOLTAGE REFERENCE CIRCUIT VREF RSET COMP HSYNC FIELD/VSYNC BLANK VIDEO TIMING GENERATOR I2C MPU PORT REAL-TIME CONTROL CIRCUIT SIN/COS DDS BLOCK CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND *This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADV7175/ADV7176–SPECIFICATIONS Model Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance ANALOG OUTPUTS Output Current3 Output Current4 Full-Scale DAC Output LSB Size DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Voltage Reference Range, VREF POWER REQUIREMENTS VAA IDAC6 ICCT7 Power Supply Rejection Ratio DYNAMIC PERFORMANCE Luma Bandwidth9 (Low-Pass Filter) Stopband Cutoff Pass Band Cutoff Chroma Bandwidth Stopband Cutoff Pass Band Cutoff Luma Bandwidth9 (Low-Pass Filter) Stopband Cutoff Pass Band Cutoff Chroma Bandwidth Stopband Cutoff Pass Band Cutoff Differential Gain Differential Phase Differential Gain Differential Phase SNR SNR Hue Accuracy Color Saturation Accuracy 8 5 (VAA = +5 V1, VREF = 1.235 V RSET = 150 TMIN to TMAX2 unless otherwise noted) . All specifications Conditions1 ADV7175/ADV7176 Min Typ Max 10 Units Bits LSB LSB V V µA pF V V µA pF mA mA IRE µA % V kΩ pF V V mA mA %/% Guaranteed Monotonic 2 VIN = 0.4 V or 2.4 V 10 ISOURCE = 400 µA ISINK = 3.2 mA 2.4 ±1 ±1 0.8 ±1 0.4 10 10 33 34.7 8 182.5 33.9 2 15 37 0 IOUT = 0 mA IVREFOUT = 20 µA 1.112 1.235 5 140 110 0.02 5 +1.4 30 1.359 COMP = 0.1 µF NTSC Mode >50 dB Attenuation 50 dB Attenuation 50 >51.3 >27.6 >29.3 >40 >54 >50.3 Figure 3. Y Filter Specifications PASSBAND CUT OFF (MHz) 1.0 1.3 PASSBAND RIPPLE (dB) 0.085 0.04 STOPBAND CUT OFF (MHz) 3.6 4.0 STOPBAND ATTENUATION (dB) ATTENUATION @ 1.3MHz (dB) 0.3 0.02 F3dB 2.05 2.45 FILTER SELECTION NTSC PAL >40 >40 Figure 4. UV Filter Specifications –6– REV. A ADV7175/ADV7176 0 TYPE A –20 –20 0 TYPE A AMPLITUDE – dB TYPE B –60 AMPLITUDE – dB –40 –40 TYPE B –60 –80 –80 –100 –100 –120 0 2 4 6 8 FREQUENCY – MHz 10 12 –120 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 5. NTSC Low-Pass Filter Figure 7. PAL Low-Pass Filter 0 0 –20 –20 AMPLITUDE – dB AMPLITUDE – dB –40 –40 –60 –60 –80 –80 –100 –100 –120 0 2 4 6 8 FREQUENCY – MHz 10 12 –120 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 6. NTSC Notch Filter Figure 8. PAL Notch Filter 0 –20 AMPLITUDE – dB –40 –60 –80 –100 –120 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 9. NTSC/PAL Extended Mode Filter REV. A –7– ADV7175/ADV7176 0 –10 –20 0 –10 –20 –30 AMPLITUDE – dB AMPLITUDE – dB –30 –40 –50 –60 –70 –80 –90 –100 0 2 4 6 8 FREQUENCY – MHz 10 12 –40 –50 –60 –70 –80 –90 –100 0 2 4 6 8 FREQUENCY – MHz 10 12 Figure 10. NTSC UV Filter COLOR BAR GENERATION Figure 11. PAL UV Filter The ADV7175/ADV7176 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75% amplitude, 100% saturation (100/0/75/0) for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic “1.” SQUARE PIXEL MODE CLOCK COMPOSITE VIDEO e.g. VCR OR CABLE VIDEO DECODER (e.g.SAA7110) M U X MPEG DECODER SCRESET/RTC GREEN/LUMA/Y P7–P0 RED/CHROMA/V BLUE/COMPOSITE/U HSYNC FIELD/VSYNC COMPOSITE The ADV7175/ADV7176 can be used to operate in square pixel mode. For NTSC operation an input clock of 24.54 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal filters scale accordingly for square pixel mode operation. COLOR SIGNAL CONTROL ADV7175/ADV7176 Figure 12. RTC Connections PIXEL TIMING DESCRIPTION The color information can be switched on and off the video output using Bit MR24 of Mode Register 2. BURST SIGNAL CONTROL The ADV7175/ADV7176 can operate in either 8-bit or 16-bit YCrCb Mode. 8-Bit YCrCb Mode The burst information can be switched on and off the video output using Bit MR25 of Mode Register 2. NTSC PEDESTAL CONTROL The pedestal information on both odd and even fields can be controlled on a line by line basis using the NTSC Pedestal Control Registers. This allows the pedestals to be controlled during the vertical blanking interval (Lines 10 to 25). SUBCARRIER RESET This default mode accepts multiplexed YCrCb inputs through the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a rising clock edge. 16-Bit YCrCb Mode Together with the SCRESET/RTC PIN and Bits MR22 and MR21 of Mode Register 2, the ADV7175/ADV7176 can be used in subcarrier reset mode. The subcarrier will reset to field 0 at the start of the following field when a high to low transition occurs on this input pin. REAL TIME CONTROL This mode accepts Y inputs through the P7-P0 pixel inputs and multiplexed CrCb inputs through the P15-P8 pixel inputs. The data is loaded on every second rising clock edge of CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc. VIDEO TIMING DESCRIPTION Together with the SCRESET/RTC PIN and Bits MR22 and MR21 of Mode Register 2, the ADV7175/ADV7176 can be used to lock an external video source. The real time control mode allows the ADV7175/ADV7176 to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs out a digital datastream in the RTC format (such as a Phillips SAA7110 video decoder), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This digital datastream is 67 bits wide and the subcarrier is contained in bits 0 to 21. Each bit is 2 clock cycles long. –8– The ADV7175/ADV7176 is intended to interface to off the shelf MPEG1 and MPEG2 Decoders. As a consequence the ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a CCIR-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. The ADV7175/ADV7176 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7175/ADV7176 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required. (Continued on page 15) REV. A ADV7175/ADV7176 Mode 0 (CCIR-656): Slave Option. (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The HSYNC, FIELD/VSYNC and BLANK (if not used) pins should be tied high in this mode. ANALOG VIDEO EAV CODE INPUT PIXELS F00X8181 CC Y F00Y0000 rb 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 PIXELS 4 PIXELS PAL SYSTEM END OF ACTIVE VIDEO LINE 280 PIXELS SAV CODE 8 1 8 1 F 0 0X CY CCYC CYC rb r rb 0000F00Yb 4 PIXELS NTSC SYSTEM 4 PIXELS 1440 PIXELS 4 PIXELS 1440 PIXELS START OF ACTIVE VIDEO LINE Figure 13. Timing Mode 0 (Slave Mode) Mode 0 (CCIR-656): Master Option. (Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions relative to the video waveform are illustrated in Figure 16. DISPLAY VERTICAL BLANK DISPLAY 522 H 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 V F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 H 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 V F ODD FIELD EVEN FIELD Figure 14. Timing Mode 0 (NTSC Master Mode) REV. A –9– ADV7175/ADV7176 DISPLAY VERTICAL BLANK DISPLAY 622 H V 623 624 625 1 2 3 4 5 6 7 21 22 23 F EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 309 H 310 311 312 313 314 315 316 317 318 319 320 334 335 336 V F ODD FIELD EVEN FIELD Figure 15. Timing Mode 0 (PAL Master Mode) ANALOG VIDEO H F V Figure 16. Timing Mode 0 Data Transitions (Master Mode) –10– REV. A ADV7175/ADV7176 Mode 1: Slave Option. HSYNC, BLANK, FIELD. (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 17. Timing Mode 1 (NTSC) DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 18. Timing Mode 1 (PAL) REV. A –11– ADV7175/ADV7176 Mode 1: Master Option. HSYNC, BLANK, FIELD. (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NTSC) and Figure 18 (PAL). Figure 19 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data. HSYNC FIELD PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PIXEL DATA Cb Y Cr Y PAL = 132 * CLOCK/2 NTSC = 118 * CLOCK/2 Figure 19. Timing Mode 1 Odd/Even Field Transitions Mode 2: Slave Option. HSYNC, VSYNC, BLANK. (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK VSYNC 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK VSYNC ODD FIELD EVEN FIELD Figure 20. Timing Mode 2 (NTSC) –12– REV. A ADV7175/ADV7176 DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK VSYNC 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK VSYNC 310 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD EVEN FIELD Figure 21. Timing Mode 2 (PAL) Mode 2: Master Option. HSYNC, VSYNC, BLANK. (Timing Register 0 TR0 = X X X X X 1 0 1 ) In this mode the ADV7175/ADV7176 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NTSC) and Figure 21 (PAL). Figure 22 illustrates the HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 23 illustrates the HSYNC, BLANK and VSYNC for an odd to even field transition relative to the pixel data. HSYNC VSYNC BLANK PAL = 12* CLOCK/2 NTSC = 16 * CLOCK/2 PIXEL DATA PAL = 132* CLOCK/2 NTSC = 118 * CLOCK/2 LINE 3 LINE 4 Cb Y Cr Y Figure 22. Timing Mode 2 Even-to-Odd Field Transition REV. A –13– ADV7175/ADV7176 HSYNC VSYNC PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 BLANK PAL = 864 * CLOCK/2 NTSC = 858 * CLOCK/2 PIXEL DATA PAL = 132 * CLOCK/2 NTSC = 118 * CLOCK/2 LINE 265 LINE 266 Cb Y Cr Y Cb Figure 23. Timing Mode 2 Odd-to-Even Field Transition Mode 3: Master/Slave Option. HSYNC, BLANK, FIELD. (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). DISPLAY VERTICAL BLANK DISPLAY 522 HSYNC BLANK FIELD 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 EVEN FIELD ODD FIELD DISPLAY VERTICAL BLANK DISPLAY 260 HSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 BLANK FIELD ODD FIELD EVEN FIELD Figure 24. Timing Mode 3 (NTSC) –14– REV. A ADV7175/ADV7176 DISPLAY VERTICAL BLANK DISPLAY 622 HSYNC BLANK FIELD 623 624 625 1 2 3 4 5 6 7 21 22 23 EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 HSYNC BLANK FIELD 310 311 312 313 314 315 316 317 318 319 320 334 335 336 EVEN FIELD ODD FIELD Figure 25. Timing Mode 3 (PAL) (Continued from page 8) In addition the ADV7175/ADV7176 supports a PAL or NTSC square pixel operation in slave mode. The part requires an input pixel clock of 24.54 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7175/ADV7176 has 8 distinct master or slave timing configurations. These are divided into 4 timing modes which operate at one discrete clock frequency (27 MHz). Timing control is established with the bidirectional SYNC, BLANK and FIELD/VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulse widths and the where they occur in relation to each other. OUTPUT VIDEO TIMING PAL–Interlaced: Scan lines 1–6, 311–318 and 624–625 are always blanked and vertical sync pulses are included in Fields 1, 2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always blanked and vertical sync pulses are included in Fields 3, 4, 7 and 8. The remaining scan lines in the vertical interval are also blanked and can be used for close captioning data. Burst is disabled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and 6. Burst is disabled on lines 1–5, 311–319 and 623–625 in Fields 3, 4, 7 and 8. PAL–Noninterlaced: Scan lines 1–6 and 311–312 are always blanked and vertical sync pulses are included. The remaining scan lines in the vertical interval are also blanked and can be used for close captioning data. Burst is disabled on lines 1–5, 310–312. POWER-ON RESET The video timing generator generates the appropriate SYNC, BLANK and BURST sequence that controls the output analog waveforms. These sequences are summarized below. In slave modes the following sequences are synchronized with the input timing control signals. In master modes the timing generator free runs and generates the following sequences in addition to the output timing control signals. NTSC–Interlaced: Scan lines 1–9 and 264–272 are always blanked and vertical sync pulses are included. Scan lines 525, 10–21 and 262, 263, 273–284 are also blanked and can be used for close captioning data. Burst is disabled on lines 1–6, 261– 269 and 523–525. NTSC–Noninterlaced: Scan lines 1–9 are always blanked and vertical sync pulses are included. Scan lines 10–21 are also blanked and can be used for close captioning data. Burst is disabled on lines 1–6, 261–262. After power-up, it is necessary to execute a reset operation. A reset occurs on the falling edge of a high to low transition on the RESET pin. This initializes the pixel port such that the pixel inputs P7–P0 are selected. After reset, the ADV7175/ADV7176 is automatically set up to operate in NTSC mode. Subcarrier frequency code 21F07C16 HEX is loaded into the subcarrier frequency registers. All other registers, with the exception of Mode Register 0, are set to 00H. All bits in Mode Register 0 are set to Logic Level “0” except Bit MR02. Bit MR02 of Mode Register 0 is set to Logic “1.” This enables the 7.5 IRE pedestal. REV. A –15– ADV7175/ADV7176 MPU PORT DESCRIPTION The ADV7175 and ADV7176 support a two wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs serial data (SDATA) and serial clock (SCLOCK) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7175 and ADV7176 each have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 26 and Figure 27. The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or Logic Level “1.” 1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X will write information to the peripheral. A Logic “1” on the LSB of the first byte means that the master will read information from the peripheral. The ADV7175/ADV7176 acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. The ADV7175 has 33 subaddresses and the ADV7176 has 19 subaddresses to enable access to the internal registers. It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto increment allowing data to be written to or from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one by one basis without having to update all the registers. There is one exception. The Subcarrier Frequency Registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The auto increment function should be then used to increment and access subcarrier frequency registers 1, 2 and 3. The subcarrier frequency registers should not be accessed independently. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then these cause an immediate jump to the idle condition. During a given SCLOCK high period the user should only issue one start condition, one stop condition or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7175/ADV7176 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode, the user exceeds the highest subaddress then the following action will be taken: 1. In Read Mode the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7175/ADV7176 and the part will return to the idle condition. Figure 28 illustrates an example of data transfer for a read sequence and the start and stop conditions. SDATA Fig 26. ADV7175 Slave Address 0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X Fig 27. ADV7176 Slave Address To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high to low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic “0” on the LSB of the first byte means that the master WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 READ SEQUENCE S SLAVE ADDR S = START BIT P = STOP BIT A(S) SUB ADDR A(S) S SUB ADDR DATA SCLOCK S 1-7 8 9 1-7 8 9 1-7 DATA 8 9 ACK P STOP START ADDR R/ W ACK SUBADDRESS ACK Figure 28. Bus Data Transfer Figure 29 shows bus write and read sequences. A(S) LSB = 1 DATA A(S) P A(S) SLAVE ADDR A(S) DATA A(M) DATA A(M) P A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 29. Write and Read Sequences –16– REV. A ADV7175/ADV7176 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 SR7–SR5 (000) ZERO SHOULD BE WRITTEN TO THESE BITS SUBADDRESS REGISTER SR4 SR3 SR2 SR1 SR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 • • 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 • • 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 • • 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 • • 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 • • 1 MODE REGISTER 0 MODE REGISTER 1 SUB CARRIER FREQ REGISTER 0 SUB CARRIER FREQ REGISTER 1 SUB CARRIER FREQ REGISTER 2 SUB CARRIER FREQ REGISTER 3 SUB CARRIER PHASE REGISTER TIMING MODE REGISTER 0 CLOSED CAPTIONING EXTENDED DATA – BYTE 0 CLOSED CAPTIONING EXTENDED DATA – BYTE 1 CLOSED CAPTIONING DATA – BYTE 0 CLOSED CAPTIONING DATA – BYTE 1 TIMING MODE REGISTER 1 MODE REGISTER 2 NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3) NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3) NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4) NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4) MODE REGISTER 3 MACROVISION REGISTERS (ADV7175 ONLY) " " " " " " MACROVISION REGISTERS (ADV7175 ONLY) Figure 30. Subaddress Register REGISTER ACCESSES Subaddress Register (SR7–SR0) The MPU can write to or read from all of the registers of the ADV7175/ADV7176 except the subaddress register which is a write only register. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. Then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed. REGISTER PROGRAMMING The communications register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress set up. The subaddress register determines to/from which register the operation takes place. Figure 30 shows the various operations under the control of the subaddress register. Zero should always be written to SR7– SR5. Register Select (SR4–SR0): The following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers and NTSC pedestal control registers in terms of its configuration. These bits are setup to point to the required starting address. MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Mode Register 0 is a 8-bit wide register. Figure 31 shows the various operations under the control of Mode Register 0. This register can be read from as well written to. MR07 MR06 MR05 MR04 MR03 MR02 MR01 MR00 OUTPUT SELECT MR06 0 1 YC OUTPUT RGB/YUV OUTPUT FILTER SELECT MR04 MR03 0 0 1 1 0 1 0 1 LOW PASS FILTER (A) NOTCH FILTER EXTENDED MODE LOW PASS FILTER (B) 0 0 1 1 OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 1 0 1 NTSC PAL (B, D, G, H, I) PAL (M) RESERVED MR07 (0) ZERO SHOULD BE WRITTEN TO THIS BIT RGB SYNC MR05 0 1 DISABLE ENABLE PEDESTAL CONTROL MR02 0 1 PEDESTAL OFF PEDESTAL ON Figure 31. Mode Register 0 REV. A –17– ADV7175/ADV7176 MODE REGISTER 0 (MR07–MR00) BIT DESCRIPTION Encode Mode Control (MR01–MR00): MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) These bits are used to set up the encode mode. The ADV7175/ ADV7176 can be set up to output NTSC, PAL (B, D, G, H, I), PAL (M) and PAL (N) standard video. Pedestal Control (MR02) Mode Register 1 is a 8-bit wide register. Figure 32 shows the various operations under the control of Mode Register 1. This register can be read from as well written to. MODE REGISTER 1 (MR17–MR10) BIT DESCRIPTION Interlaced Mode Control (MR10): This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid if the ADV7175/ADV7176 is configured in PAL mode. Luminance Filter Control (MR04–MR03) This bit is used to setup the output to interlaced or non-interlaced mode. This mode is only relevant when the part is in composite video mode. Closed Captioning Field Control (MR12–MR11) These bits are used for selecting between a filter for the luminance signal. These filters automatically are set to the cutoff frequency for the low-pass filters and the subcarrier frequency for the notch filter. The extended mode filter is a 5.5 MHz low-pass filter. The filters are illustrated in Figures 3 to 11. RGB Sync (MR05) These bits control the field that close captioning data is displayed on close captioning information can be displayed on an odd field, even field or both fields. DAC Control (MR16–MR13) This bit is used to set up the RGB outputs with the sync information encoded. Output Control (MR06) These bits can be used to power down the DACs. This can be used to reduce the power consumption of the ADV7175/ADV7176 if any of the DACs are not required in the application. Color Bar Control (MR17) This bit specifies if the part is in composite video or RGB/YUV mode. Please note that in RGB/YUV mode the main composite signal is still available. This bit can be used to generate and output an internal color bar. The color bar configuration is 75/75/75/7.5 for NTSC and 100/0/75/0 for PAL. MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10 COMPOSITE DAC CONTROL MR16 0 1 NORMAL POWER DOWN 0 1 GREEN/LUMA DAC CONTROL MR14 NORMAL POWER DOWN CLOSED CAPTIONING FIELD SELECTION MR12 MR11 0 0 1 1 0 1 0 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS) INTERLACE CONTROL MR10 NORMAL POWER DOWN 0 1 INTERLACED NON-INTERLACED COLOR BAR CONTROL MR17 0 1 DISABLE ENABLE BLUE/COMPOSITE DAC CONTROL MR15 0 1 NORMAL POWER DOWN 0 1 RED/CHROMA DAC CONTROL MR13 Figure 32. Mode Register 1 –18– REV. A ADV7175/ADV7176 SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0) (Address (SR4–SR0) = 05H–02H) TIMING REGISTER 0 (TR07–TR00) (Address (SR4-SR0) = 07H) These 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers are calculated by using the following equation: Subcarrier Frequency Register = 232 –1 * F SCF FCLK Timing Register 0 is a 8-bit wide register. Figure 34 shows the various operations under the control of Timing Register 0. This register can be read from as well written to. TIMING REGISTER 0 (TR07–TR00) BIT DESCRIPTION Master/Slave Control (TR00) i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5796 MHz Subcarrier Frequency Register = 232 – 1 * 3.579545 × 10 6 27 × 10 6 This bit controls whether the ADV7175/ADV7176 is in master or slave mode. Timing Mode Control (TR02–TR01) Subcarrier Frequency Register = 21F07C16 HEX Figure 33 shows how the frequency is set up by the 4 registers. SUBCARRIER FREQUENCY REG 0 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 3 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24 These bits control the timing mode of the ADV7175/ADV7176 These modes are described in the Timing and Control section of the data sheet. BLANK Control (TR03) FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 This bit controls whether the BLANK input is used when the part is in slave mode. Luma Delay Control (TR05–TR04) FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0 These bits control the addition of a luminance delay. Each bit represents a delay of 74 ns. Pixel Port Select (TR06) Figure 33. Subcarrier Frequency Register SUBCARRIER PHASE REGISTER (FP7–FP0): (Address (SR4–SR0) = 06H) This bit is used to set the pixel port to accept 8-bit or 16-bit data. If an 8-bit input is selected the data will be set up on Pins P7–P0. Timing Register Reset (TR07) This 8-bit wide register is used to set up the subcarrier phase. Each bit represents 1.41°. Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after setting up a new timing mode. TR07 TR06 TR05 TR04 TR03 TR02 TR01 TR00 TIMING REGISTER RESET TR07 BLACK INPUT CONTROL TR03 0 1 ENABLE DISABLE TIMING MODE SELECTION TR02 TR01 0 0 1 1 0 1 0 1 MODE 0 MODE 1 MODE 2 MODE 3 0 1 MASTER/SLAVE CONTROL TR00 SLAVE TIMING MASTER TIMING PIXEL PORT CONTROL TR06 0 1 8-BIT 16-BIT LUMA DELAY TR05 TR04 0 0 1 1 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY Figure 34. Timing Register 0 REV. A –19– ADV7175/ADV7176 CLOSED CAPTIONING EXTENDED DATA REGISTERS 1–0 (CED15–CED00) (Address (SR4–SR0) = 09–08H) HSYNC to VSYNC/FIELD Delay Control (TR13–TR12) These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output. HSYNC to FIELD Delay Control (TR15–TR14) When the ADV7175/ADV7176 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15–TR14) When the ADV7175/ADV7176 is in Timing Mode 2, these bits adjust the VSYNC pulse width. HSYNC to Pixel Data Adjust (TR17–TR16) This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped. This adjustment is available in both master and slave timing modes. MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4-SR0) = 0DH) These 8-bit wide registers are used to set up the closed captioning extended data bytes. Figure 35 shows how the high and low bytes are set up in the registers. BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED7 CED6 CED5 CED4 CED3 CED2 CED9 CED8 BYTE 0 CED1 CED0 Figure 35. Closed Captioning Extended Data Register CLOSED CAPTIONING DATA REGISTERS 1–0 (CCD15–CCD00) (Subaddress (SR4–SR0) = 0B–0AH) These 8-bit wide registers are used to set up the closed captioning data bytes. Figure 36 shows how the high and low bytes are set up in the registers. BYTE 1 Mode Register 2 is an 8-bit wide register. CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD8 Figure 38 shows the various operations under the control of Mode Register 2. This register can be read from as well written to. MODE REGISTER 2 (MR27–MR20) BIT DESCRIPTION Square Pixel Mode Control (MR20) BYTE 0 CCD0 Figure 36. Closed Captioning Data Register TIMING REGISTER 1 (TR17–TR10) (Address (SR4–SR0) = 0CH) This bit is used to setup square pixel mode. This is available in slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. Genlock Control (MR22–MR21) Timing Register 1 is an 8-bit wide register. Figure 37 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals. TIMING REGISTER 1 (TR17–TR10) BIT DESCRIPTION HSYNC Width (TR11–TR10) These bits adjust the HSYNC pulse width. These bits control the genlock feature of the ADV7175/ ADV7176 Setting MR21 to a Logic “1” configures the SCRESET/RTC pin as an input. Setting MR22 to logic level “0” configures the SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0 following a low to high transition on the SCRESET/RTC pin. Setting MR22 to Logic Level “1” configures the SCRESET/RTC pin as a real time control input. TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 HSYNC TO PIXEL DATA ADJUSTMENT TR17 TR16 0 0 1 1 0 1 0 1 0 x TPCLK 1 x TPCLK 2 x TPCLK 3 x TPCLK HSYNC TO FIELD RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 x x 0 1 Tc Tb Tb + 32µs HSYNC TO FIELD/VSYNC DELAY TR13 TR12 0 0 1 1 0 1 0 1 1 x TPCLK 3 x TPCLK 16 x TPCLK 64 x TPCLK HSYNC WIDTH TR11 TR10 0 0 1 1 0 1 0 1 Ta 1 x TPCLK 4 x TPCLK 16 x TPCLK 128 x TPCLK VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 0 1 0 1 1 x TPCLK 4 x TPCLK 16 x TPCLK 64 x TPCLK TIMING MODE 1 (MASTER/PAL) LINE 1 HSYNC Ta Tb FIELD/VSYNC Tc LINE 313 LINE 314 Figure 37. Timing Register 1 –20– REV. A ADV7175/ADV7176 MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20 RGB/YUV CONTROL MR26 0 1 RGB OUTPUT YUV OUTPUT 0 1 CHROMINANCE CONTROL MR24 ENABLE COLOR DISABLE COLOR GENLOCK SELECTION MR22 MR21 x 0 1 0 1 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN ENABLE RTC PIN SQUARE PIXEL CONTROL MR20 CCIR624 OUTPUT CCIR601 OUTPUT 0 1 DISABLE ENABLE LOWER POWER MODE MR27 0 1 DISABLE ENABLE MR25 0 1 BURST CONTROL ENABLE BURST DISABLE BURST 0 1 CCIR624/CCIR601 CONTROL MR23 Figure 38. Mode Register 2 CCIR624/CCIR601 Control (MR23) LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 1/3 This bit switches the video output between CCIR624 and CCIR601 video standard. Chrominance Control (MR24) PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8 This bit enables the color information to be switched on and off the video output. Burst Control (MR25) FIELD 2/4 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0 This bit enables the burst information to be switched on and off the video output. RGB/YUV Control (MR26) LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8 This bit enables the output from the RGB DACs to be set to YUV output video standard. Bit MR06 of Mode Register 0 must be set to Logic Level “1” before MR26 is set. Lower Power Control (MR27) Figure 39. Pedestal Control Registers MODE REGISTER 3 MR3 (MR37–30) (Address (SR4–SR0) = 12H) This bit enables the lower power mode of the ADV7175/ ADV7176. NTSC PEDESTAL CONTROL REGISTERS 3–0 (PCE15–0, PCO15–0) (Subaddress (SR4–SR0) = 11-0EH) Mode Register 3 is an 8-bit wide register. Figure 34 shows the various operations under the control of Mode Register 3. Bits MR36–MR30 are reserved and Logic “0” should be written to them. MODE REGISTER 3 (MR37–MR30) DESCRIPTION DAC Switching Control (MR37) These 8-bit wide registers are used to set up the NTSC pedestal on a line by line basis in the vertical blanking interval for both odd and even fields. Figure 39 shows the four control registers. A Logic “1” in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line. This bit is used to switch the luminance signal onto the composite DAC. Figure 40 illustrates the DAC outputs and how they switch when MR 37 is set to Logic “1”. MR37 MR36 MR35 MR34 MR33 MR32 MR31 MR30 MR36-MR30 (RESERVED) ZERO SHOULD BE WRITTEN TO THESE BITS DAC OUTPUT SWITCHING MR37 0 1 DAC A DAC B DAC C DAC D COMPOSITE BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE Figure 40. Mode Register 3 REV. A –21– ADV7175/ADV7176 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7175/ADV7176 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7175/ADV7176 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing. Ground Planes operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA pins on the ADV7175/ADV7176 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7175/ADV7176 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The ground plane should encompass all ADV7175/ADV7176 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7175/ADV7176, the analog output traces, and all the digital signal traces leading up to the ADV7175/ ADV7176. The ground plane is the board’s common ground plane. Power Planes The digital inputs to the ADV7175/ADV7176 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7175/ADV7176 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV7175/ADV7176 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7175/ADV7176. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7175/ADV7176 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling The ADV7175/ADV7176 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7175/ADV7176 so as to minimize reflections. The ADV7175/ADV7176 should have no inputs left floating. Any inputs that are not required should be tied to ground. For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable –22– REV. A ADV7175/ADV7176 POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 0.1µF 0.01µF +5V (VAA) +5V (VAA) 0.1µF +5V (VAA) 1, 11, 20, 28, 30, 37 0.1µF 25 COMP 33 VREF 38–42, 2–9, 12–14 P15–P0 VAA GREEN/ LUMA/ 27 Y 10µF 33µF GND L1 (FERRITE BEAD) +5V (VCC) ADV7175 ADV7176 75Ω RED/ CHROMA/ 26 V BLUE/ COMPOSITE/ 31 U 75Ω S VIDEO “UNUSED INPUTS SHOULD BE GROUNDED” 35 SCRESET/RTC 15 HSYNC 16 FIELD/VSYNC 17 BLANK 75Ω COMPOSITE 32 75Ω +5V (VCC) 5kΩ +5V (VCC) 5kΩ 22 RESET 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) 44 CLOCK +5V (VAA) 10kΩ ALSB 18 SCLOCK 23 MPU BUS SDATA 24 RSET 34 GND 10, 19, 21 29, 36, 43 150Ω Figure 41. Recommended Analog Circuit Layout The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if 13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the ADV7175/ADV7176 in the correct sequence. D CLOCK CK Q D CK Q 13.5MHz HSYNC Figure 42. Circuit to Generate 13.5 MHz REV. A –23– ADV7175/ADV7176 APPENDIX 2 CLOSED CAPTIONING The ADV7175/ADV7176 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of line 21 of the odd fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run in signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes. The data for these bytes is stored in closed captioning data registers 0 and 1. The ADV7175/ADV7176 also supports the extended closed captioning operation which is active during even fields and is encoded on scan line 284. The data for this operation is stored in closed captioning extended data registers 0 and 1. All clock run-in signals and timing to support closed captioning on lines 21 and 282 are generated automatically by the ADV7175/ ADV7176. All pixels inputs are ignored during lines 21 and 282. FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA208 describe the closed captioning information for lines 21 and 284. 13.407µs S T A R T P A R I T Y P A R I T Y D6–D0 D6–D0 50 IRE 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003µs 17.379µs 33.764µs Figure 43. Closed Captioning Waveform (NTSC) –24– REV. A ADV7175/ADV7176 APPENDIX 3 NTSC WAVEFORMS (With Pedestal) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 44. NTSC Composite Video Levels 100 IRE REF WHITE 1048.4mV 714.2mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 45. NTSC Luma Video Levels 1067.7mV 835mV (pk-pk) PEAK CHROMA 286mV (pk-pk) 650mV BLANK/BLACK LEVEL 232.2mV PEAK CHROMA 0mV Figure 46. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 720.8mV 7.5 IRE 0 IRE –40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV Figure 47. NTSC RGB Video Levels REV. A –25– ADV7175/ADV7176 NTSC WAVEFORMS (Without Pedestal) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 48. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE –40 IRE BLANK /BLACK LEVEL SYNC LEVEL 338mV 52.1mV Figure 49. NTSC Luma Video Levels 1101.6mV 903.2mV (pk-pk) PEAK CHROMA 307mV (pk-pk) 650mV BLANK/BLACK LEVEL 198.4mV PEAK CHROMA 0mV Figure 50. NTSC Chroma Video Levels 100 IRE REF WHITE 1052.2mV 715.7mV 0 IRE –40 IRE BLANK/BLACK LEVEL SYNC LEVEL 336.5mV 51mV Figure 51. NTSC RGB Video Levels –26– REV. A ADV7175/ADV7176 PAL WAVEFORMS 1284.2mV PEAK COMPOSITE 1047.1mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 52. PAL Composite Video Levels 1047mV REF WHITE 696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL Figure 53. PAL Luma Video Levels 1092.5mV 885mV (pk-pk) PEAK CHROMA 300mV (pk-pk) 650mV BLANK/BLACK LEVEL 207.5mV PEAK CHROMA 0mV Figure 54. PAL Chroma Video Levels 1050.2mV REF WHITE 698.4mV 351.8mV 51mV BLANK /BLACK LEVEL SYNC LEVEL Figure 55. PAL RGB Video Levels REV. A –27– ADV7175/ADV7176 APPENDIX 4 REGISTER VALUES The ADV7175/ADV7176 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. In the examples shown the timing mode is set to Mode 0 in slave format. TR02–TR00 of the timing register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the register programming section of the data sheet. TR07 should be toggled after setting up a new timing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples this register is programmed in default mode. NTSC PAL (M) Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 PAL (B, D, G, H, I) 04 Hex 00 Hex 16 Hex 7C Hex F0 Hex 21 Hex 00 Hex 08 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 PAL (N) 06 Hex 00 Hex A3 Hex EF Hex E6 Hex 21 Hex 00 Hex 08 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 01 Hex 00 Hex CB Hex 8A Hex 09 Hex 2A Hex 00 Hex 08 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex Mode Register 0 Mode Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Timing Register 0 Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Timing Register 1 Mode Register 2 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 Mode Register 3 05 Hex 00 Hex CB Hex 8A Hex 09 Hex 2A Hex 00 Hex 08 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex 00 Hex –28– REV. A ADV7175/ADV7176 APPENDIX 5 OUTPUT FILTER If an output filter is required for the composite output of the ADV7175/ADV7176. The following filter can be used. Plots of the filter characteristics can be produced on request. L 1µH IN C 470pF C 330pF C 56pF L 2.7µH L 0.7µH OUT Figure 56. Output Filter REV. A –29– ADV7175/ADV7176 APPENDIX 6 OUTPUT WAVEFORMS Figure 57. 100/75% Color Bars NTSC Figure 58. 100/75% Color Bars NTSC (Chrominance Only) –30– REV. A ADV7175/ADV7176 Figure 59. 100/75% Color Bars NTSC (Luminance Only) Figure 60. 100/75% Color Bars PAL REV. A –31– ADV7175/ADV7176 Figure 61. Differential Phase and Gain Measurements (PAL) Figure 62. Vectorscope Measurements (PAL) –32– REV. A ADV7175/ADV7176 Figure 63. Modulated Ramp Measurements (PAL) REV. A –33– ADV7175/ADV7176 INDEX Contents Page No. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1 ADV7175/ADV7176 SPECIFICATIONS . . . . . . . . . . . . . . 2 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 4 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN DESCRIPTION/PIN CONFIGURATION . . . . . . . . . 5 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 6 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 6 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 8 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 8 COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8 BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 8 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 8 SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 REAL TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 8 Timing Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . 15 POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . 16 Contents Page No. REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 17 Subaddress Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . 19 Subcarrier Phase Register . . . . . . . . . . . . . . . . . . . . . . . . 19 Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Closed Captioning Extended Data Registers 1-0 . . . . . . 20 Closed Captioning Data Registers 1-0 . . . . . . . . . . . . . . 20 Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 NTSC Pedestal Control Registers 3-0 . . . . . . . . . . . . . . 21 APPENDIX 1. BOARD DESIGN AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 22 APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . 24 APPENDIX 3. VIDEO WAVEFORMS . . . . . . . . . . . . . . 25 APPENDIX 4. REGISTER VALUES . . . . . . . . . . . . . . . 28 APPENDIX 5. OUTPUT FILTER . . . . . . . . . . . . . . . . . 29 APPENDIX 6. OUTPUT WAVEFORMS . . . . . . . . . . . . 30 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 35 –34– REV. A ADV7175/ADV7176 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE TOP VIEW (PINS DOWN) 0.546 (13.875) 0.398 (10.11) 0.390 (9.91) 8° 0.8° 34 33 23 22 4 4 12 1 11 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) 0.083 (2.11) 0.077 (1.96) REV. A –35– –36– C213a–4– /96 PRINTED IN U.S.A.