a
Professional Extended-10 ™
Video Encoder with 54 MHz Oversampling
ADV7194
FEATURES
10-Bit Extended CCIR-656 Input Data Port
Six High-Quality 10-Bit Video DACs
10-Bit Internal Digital Video Processing
Multistandard Video Input
Multistandard Video Output
4ⴛ Oversampling with Internal 54 MHz PLL
Programmable Video Control Includes:
Digital Noise Reduction
Gamma Correction
Black Burst
LUMA Delay
CHROMA Delay
Multiple Luma and Chroma Filters
Luma SSAF™ (Super Sub-Alias Filter)
Average Brightness Detection
Field Counter
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface (I2C Compatible and
Fast I 2C)
Supply Voltage 5 V and 3.3 V Operation
80-Lead LQFP Package
APPLICATIONS
Professional DVD Playback Systems
PC Video/Multimedia Playback Systems
Progressive Scan Playback Systems
Professional Studio Equipment
GENERAL DESCRIPTION
The ADV7194 is part of the new generation of video encoders
from Analog Devices. The device builds on the performance of
previous video encoders and provides new features like interfacing progressive scan devices, digital noise reduction, gamma
correction, 4× oversampling and 54 MHz operation, average
brightness detection, black burst signal generation, chroma delay,
an additional Chroma Filter, etc.
The ADV7194 supports NTSC-M, NTSC-N (Japan), PAL N,
PAL-B/D/G/H/I and PAL-60 standards. Input standards supported include ITU-R.BT656 4:2:2 YCrCb in 8-, 10-, 16- or
20-bit format and 3× 10-bit YCrCb progressive scan format.
The ADV7194 can output composite video (CVBS), S-Video
(Y/C), Component YUV or RGB and analog progressive scan in
YPrPb format. The analog component output is also compatible
with Betacam, MII and SMPTE/EBU N10 levels, SMPTE 170M
NTSC and ITU-R.BT 470 PAL.
For more information about the ADV7194’s features refer to
Detailed Description of Features section.
SIMPLIFIED BLOCK DIAGRAM
DIGITAL
INPUT
27MHz
CLOCK
VIDEO
INPUT
PROCESSING
10-BIT YCrCb
IN 4:2:2 FORMAT
ANALOG
OUTPUT
PLL
AND
54MHz
CHROMA
LPF
DEMUX
ITU–R.BT
656/601
VIDEO
OUTPUT
PROCESSING
VIDEO
SIGNAL
PROCESSING
AND
YCrCbTOYUV
MATRIX
COLOR CONTROL
DNR
GAMMA
CORRECTION
VBI
TELETEXT
CLOSED CAPTION
CGMS/WSS
10-BIT
DAC
2ⴛ
OVERSAMPLING
SSAF
LPF
LUMA
LPF
10-BIT
DAC
10-BIT
DAC
OR
10-BIT
DAC
4ⴛ
OVERSAMPLING
COMPOSITE VIDEO
Y [S-VIDEO]
C [S-VIDEO]
RGB
YUV
YPrPb
TV SCREEN
OR
PROGRESSIVE
SCAN DISPLAY
10-BIT
DAC
10-BIT
DAC
I2C INTERFACE
ADV7194
Extended-10 is a trademark of Analog Devices, Inc. This technology combines 10-bit conversion, 10-bit digital video data processing, and 10-bit external interfacing.
SSAF is a trademark of Analog Devices Inc.
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
I2C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADV7194
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29
MODE REGISTERS 0–9 . . . . . . . . . . . . . . . . . . . . . . . 30–35
TIMING REGISTERS 0–1 . . . . . . . . . . . . . . . . . . . . . . . . 36
SUBCARRIER FREQUENCY AND
PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TELETEXT REQUEST CONTROL REGISTER . . . . . . 38
CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38
CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39
COLOR CONTROL REGISTERS . . . . . . . . . . . . . . . . . . 39
HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40
HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40
BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40
BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40
SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41
PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 41
GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43
BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44
OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44
OCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 44
APPENDIX 1
Board Design and Layout Considerations . . . . . . . . . . . . 45
APPENDIX 2
Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX 3
Copy Generation Management System (CGMS) . . . . . . . 48
APPENDIX 4
Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
APPENDIX 5
Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
APPENDIX 6
Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX 7
DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
APPENDIX 8
Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53
Power-On Reset Register Values . . . . . . . . . . . . . . . . . . . 55
APPENDIX 9
NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 56
NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 57
PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 64
APPENDIX 10
Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69
CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS
5 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3 V Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 V Dynamic Specifications . . . . . . . . . . . . . . . . . . . . . . . 5
5 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 V Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10
DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13
FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17
BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17
BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17
CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CSO, HSO, AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . 17
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17
COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17
COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17
UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18
DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18
DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18
REAL-TIME CONTROL, SUBCARRIER RESET, AND
TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VERTICAL BLANKING DATA INSERTION
AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
20-/16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20
RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 28
–2–
REV. A
ADV7194
SPECIFICATIONS (V
1
5 V SPECIFICATIONS
= 5 V, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX2 unless
otherwise noted.)
AA
Parameter
Min
Typ
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity3
Differential Nonlinearity3
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
Input Leakage Current4
Input Leakage Current5
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current6
Three-State Leakage Current7
Three-State Output Capacitance
ANALOG OUTPUTS
Output Current (Max)
Output Current (Min)
DAC-to-DAC Matching3
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Max
Unit
10
Bits
± 1.0
± 1.0
LSB
LSB
2
0.8
±1
10
0
6
1
200
2.4
4.125
0.8
10
200
6
0.4
4.33
2.16
0.4
4.625
10
2.5
1.4
0
100
6
V
V
µA
pF
µA
µA
POWER REQUIREMENTS
VAA
Normal Power Mode
IDAC9
ICCT (2× Oversampling)10, 11
ICCT (4× Oversampling)10, 11
IPLL
Sleep Mode
IDAC
ICCT
mA
mA
%
V
kΩ
pF
RL = 300 Ω
RL = 600 Ω, RSET1,2 = 2400 Ω
1.235
1.359
V
4.75
5.0
5.25
V
29
80
120
6
35
120
170
10
mA
mA
mA
mA
µA
µA
NOTES
1
All measurements are made in 4× Oversampling Mode unless otherwise specified.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
Guaranteed by characterization.
4
For all inputs but PAL_NTSC and ALSB.
5
For PAL_NTSC and ALSB inputs.
6
For all outputs but VSO/TTX/CLAMP.
7
For VSO/TTX/CLAMP outputs.
8
Measurement made in 2× Oversampling Mode.
9
IDAC is the total current required to supply all DACs including the V REF circuitry.
10
All six DACs on.
11
ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL.
Specifications subject to change without notice.
REV. A
–3–
VIN = 0.4 V or 2.4 V
ISOURCE = 400 µA
ISINK = 3.2 mA
1.112
0.01
85
Guaranteed Monotonic
V
V
µA
µA
pF
8
VOLTAGE REFERENCE
Reference Range, VREF
Test Conditions
IOUT = 0 mA
ADV7194–SPECIFICATIONS
2
1 (VAA = 3.0 V, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX
3.3 V SPECIFICATIONS
unless otherwise noted.)
Parameter
Min
Typ
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
Input Leakage Current3
Input Leakage Current4
6
1
200
10
Bits
± 1.0
± 1.0
LSB
LSB
±1
10
V
V
µA
pF
µA
µA
4.125
3.15
Test Conditions
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V
V
V
µA
µA
pF
ISOURCE = 400 µA
ISINK = 3.2 mA
RL = 300 Ω
RL = 600 Ω, RSET1,2 = 2400 Ω
100
6
mA
mA
%
V
kΩ
pF
1.235
V
2.4
0.4
10
200
6
VOLTAGE REFERENCE
Reference Range7
POWER REQUIREMENTS
VAA
Normal Power Mode
IDAC8
ICCT (2× Oversampling)9, 10
ICCT (4× Oversampling)9, 10
IPLL
Sleep Mode
IDAC
ICCT
Unit
2
0.8
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current5
Three-State Leakage Current6
Three-State Output Capacitance
ANALOG OUTPUTS
Output Current (Max)
Output Current (Min)
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Max
10
4.33
2.16
0.4
4.625
2.5
1.4
3.3
3.6
V
29
42
68
6
54
86
mA
mA
mA
mA
IOUT = 0 mA
µA
µA
0.01
85
NOTES
1
All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. For 2 × Oversampling Mode, the power
requirements for the ADV7194 are typically 3.0 V.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
For all inputs but PAL_NTSC and ALSB.
4
For PAL_NTSC and ALSB inputs.
5
For all outputs but VSO/TTX/CLAMP.
6
For VSO/TTX/CLAMP outputs.
7
Measurement made in 2× Oversampling Mode.
8
IDAC is the total current required to supply all DACs including the V REF circuitry.
9
All six DACs on.
10
ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL.
Specifications subject to change without notice.
–4–
REV. A
ADV7194
5 V DYNAMIC SPECIFICATIONS1
Parameter
(VAA = 5 V ⴞ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
Min
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermod
Chroma/Luma Gain Ineq
Chroma/Luma Delay Ineq
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Differential Gain3
Differential Phase3
SNR (Pedestal)3
Typ
Max
0.5
0.7
0.7
0.5
0.1
1.7
2.2
0.6
82
72
0.1 (0.4)
0.4 (0.15)
78.5 (78)
78 (78)
61.7 (61.7)
62 (63)
SNR (Ramp)3
0.9
0.7
0.3 (0.5)
0.5 (0.3)
Unit
Degrees
%
±%
± Degrees
±%
±%
ns
±%
dB
dB
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Test Conditions
Referenced to 40 IRE
RMS
Peak Periodic
RMS
Peak Periodic
NOTES
1
All measurements are made in 4× Oversampling Mode unless otherwise specified.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
Values in parentheses apply to 2× Oversampling Mode.
Specifications subject to change without notice.
3.3 V DYNAMIC SPECIFICATIONS1
Parameter
Hue Accuracy
Color Saturation Accuracy
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermod
Differential Gain3
Differential Phase3
SNR (Pedestal)3
SNR (Ramp)3
Min
(VAA = 3.3 V ⴞ 150 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All
specifications TMIN to TMAX2 unless otherwise noted.)
Typ
Max
0.5
0.8
0.6
83
71
0.7
0.5
0.1
0.2 (0.5)
0.5 (0.2)
78.5 (78)
78 (78)
62.3 (62)
61 (62.5)
NOTES
1
All measurements are made in 4× Oversampling Mode unless otherwise specified.
2
Temperature range T MIN to TMAX: 0°C to 70°C.
3
Values in brackets apply to 2× Oversampling Mode.
Specifications subject to change without notice.
REV. A
–5–
Unit
Degrees
%
±%
dB
dB
±%
± Degrees
±%
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Test Conditions
Referenced to 40 IRE
RMS
Peak Periodic
RMS
Peak Periodic
ADV7194
5 V TIMING CHARACTERISTICS
Parameter
(VAA = 5 V ⴞ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted.)
Min
MPU PORT2
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
300
300
0.6
Test Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
2
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL
PORT3
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15 (2× Oversampling)
Pipeline Delay, t15 (4× Oversampling)
8
0.1
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
8
8
6
5
6
4
13
12
57
67
TELETEXT PORT4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
11
3
6
RESET CONTROL
Reset Low Time
3
24
ns
ns
ns
20
ns
2
PLL
PLL Output Frequency
54
MHz
NOTES
1
Temperature range T MIN to TMAX: 0°C to 70°C.
2
Guaranteed by characterization.
3
Pixel Port consists of the following:
Data: P0–P9, Y0/P10–Y9/P19,
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN Input.
4
Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
–6–
REV. A
ADV7194
3.3 V TIMING CHARACTERISTICS
Parameter
Max
Unit
400
2
kHz
µs
µs
µs
µs
ns
ns
ns
µs
8
0.1
ns
ns
27
13
12
37
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
TELETEXT PORT4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
11
3
6
ns
ns
ns
RESET CONTROL
RESET Low Time
3
PLL
PLL Output Frequency
54
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
Min
(VAA = 3.3 V ⴞ 150 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All
specifications TMIN to TMAX1 unless otherwise noted.)2
0
0.6
1.3
0.6
0.6
100
300
300
0.6
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL
PORT3
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15, 2× Oversampling
Typ
8
8
6
4
2.5
3
20
ns
MHz
NOTES
1
Temperature range T MIN to TMAX: 0°C to 70°C.
2
Guaranteed by characterization.
3
Pixel Port consists of the following:
Data: P0–P9, Y0/P10–Y9/P19,
Control: HSYNC, VSYNC, BLANK
Clock: CLKIN Input.
4
Teletext Port consists of:
Digital Output: TTXRQ,
Data: TTX.
Specifications subject to change without notice.
REV. A
–7–
Test Conditions
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
ADV7194
t5
t3
t3
SDA
t6
t1
SCL
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
PIXEL INPUT
DATA
CONTROL
O/PS
t12
t10
HSYNC,
VSYNC,
BLANK
CONTROL
I/PS
Cb
Y
Cr
Y
t11
HSYNC,
VSYNC,
BLANK,
CSO_HSO,
VSO, CLAMP
Cb
Y
t13
t14
Figure 2. Pixel and Control Data Timing Diagram
TTXREQ
t16
CLOCK
t17
t18
TTX
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
CLOCK
t9
Y0 – Y9
INCLUDING
SYNC INFORMATION
t 12
t 10
Y0
Y1
Y2
Y3
Y4
Y5
Cb0 – Cb9
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cr0 – Cr9
Cr0
Cr1
Cr2
Cr3
PROGRESSIVE
SCAN INPUT
Cr4
Cr5
t 11
Figure 4. Progressive Scan Input Timing
–8–
REV. A
ADV7194
ABSOLUTE MAXIMUM RATINGS 1
PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C
Analog Outputs to GND2 . . . . . . . . . . . . . . GND – 0.5 to VAA
The 80-lead package is used for this device. The junction-toambient (θJA) thermal resistance in still air on a four-layer PCB
is 24.7°C.
To reduce power consumption when using this part the user
can run the part on a 3.3 V supply, turn off any unused DACs.
The user must at all times stay below the maximum junction
temperature of 110°C. The following equation shows how to
calculate this junction temperature:
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
Junction Temperature = (VAA × (IDAC + ICCT)) × θJA + 70°C (TAMB)
IDAC = 10 mA + (sum of the average currents consumed by
each powered-on DAC)
Average current consumed by each powered-on DAC =
(VREF × K )/RSET
VREF = 1.235 V
K = 4.2146
CSO_HSO
VSO/ TTX/CLAMP
Cr[0]
Cr[3]
Cr[2]
Cr[1]
DGND
VDD
Cr[4]
Cr[5]
Cr[6]
Cr[8]
Cr[7]
Cb[0]
Cr[9]
Cb[2]
Cb[1]
VDD
Cb[3]
DGND
PIN CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P0 1
P1 2
60 RESET
PIN 1
IDENTIFIER
59 PAL_NTSC
P2 3
P3 4
58 RSET1
57 V
REF
56 COMP 1
P4 5
P5 6
P6 7
55 DAC A
54 DAC B
P7 8
53 VAA
52 AGND
ADV7194
LQFP
P8 9
P9 10
Y[0]/P10 11
51 DAC C
TOP VIEW
(Not to Scale)
50 DAC D
Y[1]/P11 12
49 AGND
Y[2]/P12 13
Y[3]/P13 14
Y[4]/P14 15
48 VAA
47 DAC E
Y[5]/P15 16
Y[6]/P16 17
Y[7]/P17 18
45 COMP 2
Y[8]/P18 19
Y[9]/P19 20
42 ALSB
46 DAC F
44 RSET2
43 DGND
41 SCRESET/RTC/TR
SCL
SDA
AGND
CLKIN
CLKOUT
VAA
DGND
VDD
TTXREQ
Cb[9]
Cb[8]
Cb[7]
Cb[6]
Cb[5]
VSYNC
BLANK
Cb[4]
HSYNC
VDD
DGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADV7194KST
0°C to 70°C
80-Lead Quad Flatpack
ST-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7194 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–9–
WARNING!
ESD SENSITIVE DEVICE
ADV7194
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Input/
Output
1–10
P0–P9
I
11–20
Y0/P10–Y9/P19
I
10-Bit or 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up
on Pin P0 (Pin Number 1) in 10-bit input mode.
20-Bit or 16-Bit Multiplexed YCrCb Pixel Port or 1× 10-bit progressive scan input for Y data.
P
G
Digital Power Supply (3.3 V to 5 V).
Digital Ground.
I/O
HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output
(Master Mode) or an input (Slave Mode) and accept Sync Signals.
21, 34, 68, 79 VDD
22, 33, 43, 69, DGND
80
23
HSYNC
Function
24
VSYNC
I/O
VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input
(Slave Mode) and accept VSYNC as a Control Signal.
25
BLANK
I/O
Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking and Data Insertion Blanking Input section.
26–31, 75–78
32
Cb0–Cb9
TTXREQ
I
O
1 × 10-Bit Progressive Scan Input Port for Cb Data.
Teletext Data Request Output Signal, used to control teletext data transfer.
35, 49, 52
36
AGND
CLKIN
G
I
37
CLKOUT
O
Analog Ground.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
Clock Output Pin.
38, 48, 53
39
VAA
SCL
P
I
Analog Power Supply (3.3 V to 5 V).
MPU Port Serial Interface Clock Input.
40
41
SDA
SCRESET/RTC/TR
I/O
I
42
ALSB
I
MPU Port Serial Data Input/Output.
Multifunctional Input: Real-Time Control (RTC) input, Timing Reset input, Subcarrier
Reset input.
TTL Address Input. This signal sets up the LSB of the MPU address.
44
RSET2
I
A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC D, E, F.
45
COMP 2
O
Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP 2 to
VAA.
46
47
DAC F
DAC E
O
O
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
50
51
DAC D
DAC C
O
O
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
54
55
DAC B
DAC A
O
O
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
Composite/Y/Y/GREEN Analog Output. This DAC is capable of providing 4.33 mA output.
56
COMP 1
O
Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP 1 to
VAA.
57
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external
VREF can not be used in 4× oversampling mode.
58
RSET1
I
A 1200 Ω resistor connected from this pin to AGND is used to control full-scale amplitudes
of the Video Signals from the DAC A, B, C.
59
60
PAL_NTSC
RESET
I
I
61
CSO_HSO
O
Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
The input resets the on-chip timing generator and sets the ADV7194 into default mode
See Appendix 8 for Default Register settings.
Dual function CSO or HSO output Sync Signal at TTL level.
62
VSO/TTX/CLAMP
I/O
63–67, 70–74
Cr0–Cr9
I
Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin.
CLAMP TTL Output Signals can be used to drive external circuitry to enable clamping
of all Video Signals.
1 × 10-Bit Progressive Scan Input Port for Cr Data.
–10–
REV. A
ADV7194
There are six DACs available on the ADV7194, each of which
is capable of providing 4.33 mA of current. In addition to the
composite output signal there is the facility to output S-Video
(Y/C Video), RGB Video, and YUV Video. All YUV formats
(SMPTE/EBU N10, MII, or Betacam) are supported.
DETAILED DESCRIPTION OF FEATURES
Clocking
Single 27 MHz Clock Required to Run the Device
4ⴛ Oversampling with Internal 54 MHz PLL
Square Pixel Operation
Advanced Power Management
Programmable Video Control Features
Digital Noise Reduction
Black Burst Signal Generation
Pedestal Level
Hue, Brightness, Contrast and Saturation
Clamping Output signal
VBI (Vertical Blanking Interval)
Subcarrier Frequency and Phase
LUMA Delay
CHROMA Delay
Gamma Correction
Luma and Chroma Filters
Luma SSAF (Super Subalias Filter)
Average Brightness Detection
Field Counter
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
CGMS (Copy Generation Management System)
WSS (Wide Screen Signaling)
Closed Captioning Support
Teletext Insertion Port (PAL-WST)
2-Wire Serial MPU Interface
(I 2C Compatible and Fast I2C)
I2C Registers Synchronized to VSYNC
The on-board SSAF (Super Subalias Filter) with extended
luminance frequency response and sharp stopband attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution. An additional sharpness
control feature allows high-frequency enhancement on the luminance signal.
DNR MODE
DNR CONTROL
NOISE SIGNAL PATH
HSYNC
VSYNC
BLANK
DNR CONTROL
TTXREQ
10
10
YCrCb- Y
TO10
YUV
U
MATRIX 10
DNR
Y
AND
10
GAMMA
U
CORRECTION 10
V
V
10 10 10
P0
BRIGHTNESS
CONTROL
AND
ADD SYNC
AND
INTERPOLATOR
SATURATION
CONTROL
AND
ADD BURST
AND
INTERPOLATOR
INPUT FILTER
BLOCK
FILTER OUTPUT
>THRESHOLD?
Y DATA
INPUT
FILTER OUTPUT<
THRESHOLD
ADV7194
Figure 6. Block Diagram for DNR Mode and DNR Sharpness Mode
SCL
SDA ALSB
Cr0–Cr9
Cb0–Cb9 Y0–Y9
I2C MPU PORT
PROGRAMMABLE
LUMA FILTER
AND
SHARPNESS
FILTER
PROGRAMMABLE
CHROMA
FILTER
YUV-TO-RGB
MATRIX
AND
YUV LEVEL
CONTROL
BLOCK
MODULATOR
AND
HUE CONTROL
REAL-TIME
CONTROL
CIRCUIT
SIN/COS
DDS
BLOCK
CLKOUT
SCRESET/RTC/TR
Figure 5. Detailed Functional Block Diagram
REV. A
DNR OUT
MAIN SIGNAL PATH
DEMUX
PLL
ADD SIGNAL ABOVE THRESHOLD
RANGE TO ORIGINAL SIGNAL
NOISE SIGNAL PATH
P15
CLKIN
GAIN
BLOCK SIZE CONTROL CORING GAIN DATA
BORDER AREA
CORING GAIN BORDER
BLOCK OFFSET
CGMS/WSS
AND
CLOSED CAPTIONING
CONTROL
TELETEXT
INSERTION
BLOCK
DNR OUT
DNR SHARPNESS MODE
RESET
TTX
FILTER OUTPUT>
THRESHOLD
MAIN SIGNAL PATH
CSO_HSO
VIDEO TIMING
GENERATOR
FILTER OUTPUT
THRESHOLD
MAIN SIGNAL PATH
In DNR mode, it is possible to subtract a fraction of the signal
which lies below the set threshold, assumed to be noise, from
the original signal. The threshold is set in DNR Register 1.
DNR
SHARPNESS
MODE
When DNR Sharpness mode is enabled it is possible to add a
fraction of the signal which lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect being that the signal will be boosted
(similar to using Extended SSAF Filter).
FILTER BLOCK
FILTER OUTPUT
> THRESHOLD ?
Y DATA
INPUT
FILTER D
FILTER OUTPUT
< THRESHOLD
0.8
MAGNITUDE – dB
MAIN SIGNAL PATH
0.6
0.2
Four bits are assigned to this control which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
FILTER A
1
DNR
OUT
Block Offset (DNR24–DNR27)
FILTER B
0
ADD
SIGNAL
ABOVE
THRESHOLD
RANGE
TO
ORIGINAL
SIGNAL
Figure 88. Block Diagram for DNR Mode and DNR Sharpness Mode
FILTER C
0.4
0
DNR
OUT
GAIN CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
CORING GAIN DATA
CORING GAIN BORDER
NOISE SIGNAL PATH
1
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE
FROM
ORIGINAL
SIGNAL
2
3
4
FREQUENCY – MHz
5
6
APPLY DATA
CORING GAIN
Figure 87. Filter Response of Filters Selectable
APPLY BORDER
CORING GAIN
OXXXXXXO OXXXXXXO
OXXXXXXO OXXXXXXO
DNR27-DNR24
= 01HEX
OFFSET CAUSED BY
VARIATIONS IN INPUT
TIMING
OXXXXXXO OXXXXXXO
Figure 89.
–42–
REV. A
ADV7194
DNR27
DNR26
DNR25
DNR24
0
0
0
•
•
•
1
1
1
0
0
0
•
•
•
1
1
1
0
0
1
•
•
•
0
1
1
0
1
0
•
•
•
1
0
1
0 PIXEL OFFSET
1 PIXEL OFFSET
2 PIXEL OFFSET
•
•
•
13 PIXEL OFFSET
14 PIXEL OFFSET
15 PIXEL OFFSET
DNR22
DNR MODE
CONTROL
BLOCK OFFSET CONTROL
DNR DNR DNR DNR
27 26 25 24
DNR23
DNR21
DNR20
DNR INPUT SELECT CONTROL
DNR DNR DNR
22 21 20
DNR23
0
DNR MODE
1
DNR
SHARPNESS
MODE
0
0
0
1
0
1
1
0
1
0
1
0
FILTER A
FILTER B
FILTER C
FILTER D
Figure 90. DNR Register 2
GAMMA CORRECTION REGISTERS 0–13 (GAMMA
CORRECTION 0–13)
(Address (SR5–SR0) = 26H–32H)
The Gamma Correction Registers are fourteen 8-bit-wide registers. They are used to program the gamma correction Curves A
and B.
Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.
y32
y64
y96
y128
= [(16/224)0.5 × 224] + 16 = 76*
= [(48/224)0.5 × 224] + 16 =120*
= [(80/224)0.5 × 224] + 16 = 150*
= [(112/224)0.5 × 224] + 16 = 174*
*Rounded to the nearest integer.
The above will result in a gamma curve shown below, assuming
a ramp signal as an input.
300
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT
GAMMA-CORRECTED AMPLITUDE
Gamma correction uses the function:
SignalOUT = (SignalIN)γ
where
γ = gamma power factor
Gamma correction is performed on the luma data only. The
user has the choice to use two different curves, Curve A or
Curve B. At any one time only one of these curves can be used.
The response of the curve is programmed at seven predefined
locations. In changing the values at these locations the gamma
curve can be modified. Between these points linear interpolation
is used to generate intermediate values. Considering the curve
to have a total length of 256 points, the seven locations are at:
32, 64, 96, 128, 160, 192, and 224.
300
SIGNAL OUTPUT
200
250
0.5
150 200
150
100
100
SIGNAL INPUT
50
50
0
0
50
100
150
LOCATION
200
250
Figure 91. Signal Input (Ramp) and Signal Output for
Gamma 0.5
Location 0, 16, 240 and 255 are fixed and can not be changed.
For the length of 16 to 240 the gamma correction curve has to
be calculated as below:
y = xγ
where
300
GAMMA-CORRECTED AMPLITUDE
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
y = gamma corrected output
x = linear input signal
γ = gamma power factor
To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:
yn = [x(n–16) /(240–16)]γ × (240–16) + 16
where
x(n-16) = Value for x along x-axis at points n = 32, 64, 96, 128,
160, 192 or 224
yn
250
250
SIGNAL OUTPUTS
200
0.3
0.5
150
1.8
50
0
= Value for y along the y-axis, which has to be written
into the gamma correction register
T
PU
IN
L
A
1.5
GN
SI
100
0
50
100
150
LOCATION
200
250
Figure 92. Signal Input (Ramp) and Selectable Gamma
Output Curves
Example:
The gamma curves shown above are examples only, any user
defined curve is acceptable in the range of 16–240.
REV. A
–43–
ADV7194
BRIGHTNESS DETECT REGISTER
(Address (SR5–SR0) = 34H)
OCR BIT DESCRIPTION
Reserved (OCR00)
The Brightness Detect Register is an 8-bit-wide register used only
to read back data in order to monitor the brightness/darkness of
the incoming video data on a field-by-field basis. The brightness
information is read from the I2C and based on this information,
the color controls or the gamma correction controls may be
adjusted.
A Logic 0 must be written to this bit.
The luma data is monitored in the active video area only. The
average brightness I2C register is updated on the falling edge of
every VSYNC signal.
Reserved (OCR02–OCR03)
OUTPUT CLOCK REGISTER (OCR9–0)
(Address (SR4–SR0) = 35H)
A Logic 1 must be written to these bits.
The Output Clock Register is an 8-bit-wide register. Figure 93
shows the various operations under the control of this register.
A Logic 0 must be written to this bit.
OCR07
OCR06
CLKOUT Pin Control (OCR01)
This bit enables the CLKOUT pin when set to 1 and, therefore, outputs a 54 MHz clock generated by the internal PLL.
The PLL and 4× Oversampling have to be enabled for this control to take effect, (MR61 = 0; MR16 = 1).
A Logic 0 must be written to these bits.
Reserved (OCR04–OCR06)
Reserved (OCR07)
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR07
OCR06 – OCR04
OCR03 – OCR02
OCR00
ZERO MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THESE BITS
ZERO MUST BE
WRITTEN TO
THESE BITS
ZERO MUST BE
WRITTEN TO
THIS BIT
CLKOUT
PIN CONTROL
OCR01
0
ENSABLED
1
DISABLED
Figure 93. Mode Register 10 (MR10)
–44–
REV. A
ADV7194
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
Supply Decoupling
The ADV7194 is a highly integrated circuit containing both
precision analog and high-speed digital circuitry. It has been
designed to minimize interference effects on the integrity of the
analog circuitry by the high-speed digital circuitry. It is imperative that these same design and layout techniques be applied
to the system level design such that high-speed, accurate performance is achieved. The Recommended Analog Circuit Layout
shows the analog interface between the device and monitor.
For optimum performance, bypass capacitors should be installed
using the shortest leads possible, consistent with reliable operation,
to reduce the lead inductance. Best performance is obtained
with 0.1 µF ceramic capacitor decoupling. Each group of VAA
pins on the ADV7194 must have at least one 0.1 µF decoupling
capacitor to AGND. The same applies to groups of VDD and
DGND. These capacitors should be placed as close as possible
to the device.
The layout should be optimized for lowest noise on the ADV7194
power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of
VAA, AGND, VDD, and DGND pins should be minimized so as
to minimize inductive ringing.
Ground Planes
The ground plane should encompass all ADV7194 ground pins,
voltage reference circuitry, power supply bypass circuitry for
the ADV7194, the analog output traces, and all the digital signal
traces leading up to the ADV7194. This should be as substantial
as possible to maximize heat spreading and power dissipation on
the board.
Power Planes
It is important to note that while the ADV7194 contains circuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator
for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7194 should be isolated as much
as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog
power plane.
Due to the high clock rates involved, long clock lines to the
ADV7194 should be avoided to reduce noise pickup.
The ADV7194 and any associated analog circuitry should have
its own power plane, referred to as the analog power plane (VAA).
This power plane should be connected to the regular PCB power
plane (VCC) at a single point through a ferrite bead. This bead
should be located within three inches of the ADV7194.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC), and not the
analog power plane.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general board.
The ADV7194 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to
impedance mismatch.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7194 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common-mode.
Analog Signal Interconnect
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals
should never overlay any of the analog signal circuitry and should
be kept as far away as possible.
For best performance, the outputs should each have a 300 Ω load
resistor connected to AGND. These resistors should be placed
as close as possible to the ADV7194 so as to minimize reflections.
The ADV7194 should have no inputs left floating. Any inputs
that are not required should be tied to ground.
REV. A
–45–
ADV7194
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
5V (VAA)
10nF
5V (VAA)
0.1F
5V (VAA)
5V (VAA)
COMP2
53,
48, 38
0.1F
0.1F
COMP1
VAA
VREF
79, 68,
34, 21
0.1F
VDD
DAC A
300
Cb0 – Cb9
Cr0 – Cr9
10nF
DAC B
300
ADV7194
Y0/P10 – Y9/P19
DAC C
300
UNUSED
INPUTS
SHOULD BE
GROUNDED
P9 – P0
DAC D
300
CSO_HSO
VSO/TTX/CLAMP
DAC E
PAL_NTSC
300
SCRESET/RTC/TR
DAC F
HSYNC
5V (VAA)
100
BLANK
4.7k
27MHz CLOCK
(SAME CLOCK AS
USED BY MPEG2
DECODER)
5k
5V (VCC)
5k
SCL
RESET
4.7F
6.3V
5V (VCC)
300
VSYNC
100
MPU BUS
SDATA
TTXREQ
RSET2
CLKIN
ALSB
5V (VAA)
4.7k
1.2k
RSET1
AGND
DGND
52, 49,
35
1.2k
80, 69, 43,
33, 22
Figure 94. Recommended Analog Circuit Layout
–46–
REV. A
ADV7194
APPENDIX 2
CLOSED CAPTIONING
FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA608 describe the closed captioning information for Lines
21 and 284.
The ADV7194 supports closed captioning conforming to the
standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active
line time of Line 21 of the odd fields and Line 284 of even fields.
The ADV7194 uses a single buffering method. This means that
the closed captioning buffer is only one byte deep, therefore,
there will be no frame delay in outputting the closed captioning
data unlike other two byte deep buffering systems. The data
must be loaded one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of
this method is to use VSYNC to interrupt a microprocessor, which
in turn will load the new data (two bytes) every field. If no new
data is required for transmission, 0s must be inserted in both
data registers, this is called NULLING. It is also important to
load control codes all of which are double bytes on Line 21 or a TV
will not recognize them. If there is a message like Hello World
which has an odd number of characters, it is important to pad it
out to even in order to get end of caption 2-byte control code to
land in the same field.
Closed captioning consists of a seven-cycle sinusoidal burst
that is frequency and phase locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by a Logic Level 1 start bit. Sixteen bits of data
follow the start bit. These consist of two eight-bit bytes, seven
data bits, and one odd parity bit. The data for these bytes is
stored in Closed Captioning Data Registers 0 and 1.
The ADV7194 also supports the extended closed captioning
operation which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in Closed
Captioning Extended Data Registers 0 and 1.
All clock run-in signals and timing to support Closed Captioning
on Lines 21 and 284 are generated automatically by the ADV7194
All pixels inputs are ignored during Lines 21 and 284 if closed
captioning is enabled.
10.5 0.25s
12.91s
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
P
A
R
I
T
Y
D0–D6
BYTE 0
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003s
33.764s
27.382s
Figure 95. Closed Captioning Waveform (NTSC)
REV. A
–47–
D0–D6
BYTE 1
P
A
R
I
T
Y
ADV7194
APPENDIX 3
COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7194 supports Copy Generation Management System
(CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields.
Bits C/W05 and C/W06 control whether or not CGMS data is
put out on ODD and EVEN fields. CGMS data can only be
transmitted when the ADV7194 is configured in NTSC mode.
The CGMS data is 20 bits long, the function of each of these
bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see
Figure 96. These bits are put out from the configuration registers in
the following order: C/W00 = C16, C/W01 = C17, C/W02 =
C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 =
C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 =
C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2,
C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27
= C7. If the bit C/W04 is set to a Logic 1, the last six bits C19–C14
which comprise the 6-bit CRC check sequence are calculated automatically on the ADV7194 based on the lower 14 bits (C0–C13)
of the data in the data registers and output with the remaining
14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1
with a preset value of 111111. If C/W04 is set to a Logic 0 then
all 20 bits (C0–C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user).
Function of CGMS Bits
Word 0 – 6 Bits
Word 1 – 4 Bits
Word 2 – 6 Bits
CRC – 6 Bits CRC Polynomial = X6 + X + 1 (Preset to
111111)
WORD 0
B1
B2
B3
Aspect Ratio
Display Format
Undefined
WORD 0
B4, B5, B6
WORD 1
B7, B8, B9,
B10
WORD 2
B11, B12,
B13, B14
1
16:9
Letterbox
0
4:3
Normal
Identification Information About Video and
Other Signals (e.g., Audio)
Identification Signal Incidental to Word 0
Identification Signal and Information
Incidental to Word 0
100 IRE
CRC SEQUENCE
REF
70 IRE
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
49.1s 0.5s
–40 IRE
11.2s
2.235s 20ns
Figure 96. CGMS Waveform Diagram
–48–
REV. A
ADV7194
APPENDIX 4
WIDE SCREEN SIGNALING
The ADV7194 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS
data can only be transmitted when the ADV7194 is configured in
PAL mode. The WSS data is 14 bits long, the function of each
of these bits is as shown below. The WSS data is preceded by a
run-in sequence and a Start Code, see Figure 97. The bits are
output from the configuration registers in the following order:
C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3,
C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7,
C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11,
C/W14 = W12, C/W15 = W13. If the bit C/W07 is set to a
Logic 1, it enables the WSS data to be transmitted on Line 23.
The latter portion of Line 23 (42.5 µs from the falling edge of
HSYNC) is available for the insertion of video.
Function of CGMS Bits
Bit 0–Bit 2
Bit 3
B0,
0
1
0
1
0
1
0
1
B1,
0
0
1
1
0
0
1
1
Aspect Ratio/Format/Position
Is Odd Parity Check of Bit 0–Bit 2
B2,
0
0
0
0
1
1
1
1
B3
1
0
0
1
0
1
1
0
Aspect
Ratio
4:3
14:9
14:9
16:9
16:9
>16:9
14:9
16:9
Format
Format
Full Format
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full Format
Nonapplicable
Position
Position
Nonapplicable
Center
Top
Center
Top
Center
Center
Nonapplicable
B4
0
1
Camera Mode
Film Mode
B5
0
1
Standard Coding
Motion Adaptive Color Plus
B6
0
1
No Helper
Modulated Helper
B7
RESERVED
B9
0
1
0
1
B10
0
0
1
1
No Open Subtitles
Subtitles in Active Image Area
Subtitles Out of Active Image Area
RESERVED
B11
0
No Surround Sound Information
1
Surround Sound Mode
B12 RESERVED
B13 RESERVED
500mV
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0s
38.4s
42.5s
Figure 97. WSS Waveform Diagram
REV. A
–49–
ADV7194
APPENDIX 5
TELETEXT INSERTION
Time, tPD, is the time needed by the ADV7194 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears TSYNTTXOUT = 10.2 µs after the leading edge of
the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to deliver
TTX data.
With the programmability that is offered with TTXREQ signal
on the Rising/Falling edges, the TTX data is always inserted at
the correct position of 10.2 µs after the leading edge of Horizontal
Sync pulse, thus this enables a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained
such that it allows the insertion of 360 (in order to comply with
the Teletext Standard PAL-WST) teletext bits at a text data rate
of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to 0.
The insertion window is not open if the Teletext Enable bit
(MR33) is set to 0.
Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit
has a width of almost four clock cycles. The ADV7194 uses
an internal sequencer and variable phase interpolation filter
to minimize the phase jitter and thus generate a bandlimited
signal which can be output on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that
TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are Bits 47, 56, 65, and 74. This scheme
holds for all following cycles of 37 TTX bits, until all 360 TTX
bits are completed. All teletext lines are implemented in the
same way. Individual control of teletext lines are controlled
by Teletext Setup Registers.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27 MHz/4) = 6.75 MHz
(6.9375 × 106/6.75 × 106) = 1.027777
45 BYTES (360 BITS) – PAL
TELETEXT VBI LINE
ADDRESS & DATA
RUN-IN CLOCK
Figure 98. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
tPD
HSYNC
tPD
10.2s
TTXDATA
TTXDEL
TTXREQ
PROGRAMMABLE PULSE EDGES
TTXST
tSYNTTXOUT = 10.2s
tPD = PIPELINE DELAY THROUGH ADV7194
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 99. Teletext Functionality Diagram
–50–
REV. A
ADV7194
APPENDIX 6
OPTIONAL OUTPUT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and
RGB outputs of the ADV7194, the following filter in Figure 100
can be used in 2× Oversampling Mode. In 4× Oversampling
Mode the filter in Figure 102 is recommended. The plot of the
filter characteristics are shown in Figures 101 and 103. An output
22H
22H
filter is not required if the outputs of the ADV7194 are connected to most analog monitors or TVs, however, if the output
signals are applied to a system where sampling is used (e.g.,
Digital TVs) then a filter is required to prevent aliasing.
22H
6.8H
FILTER I/P
600R
22pF
68pF
56pF
10H
FILTER I/P
FILTER O/P
FILTER O/P
600R
600R
27pF
68pF
600R
Figure 101. Output Filter for 4 × Oversampling Mode
Figure 100. Output Filter for 2 × Oversampling Mode
0
0
–7
–10
–14
MAGNITUDE – dB
MAGNITUDE – dB
–20
–30
–40
–21
–28
–35
–42
–49
–50
–56
–60
–63
–70
100k
1M
10M
FREQUENCY – Hz
–70
100k
100M
1M
10M
FREQUENCY – Hz
Figure 103. Output Filter Plot for 4× Oversampling Filter
Figure 102. Output Filter Plot for 2× Oversampling Filter
2 FILTER
REQUIREMENTS
0
dB
4 FILTER
REQUIREMENTS
–30
6.75
13.5
27.0
FREQUENCY – MHz
40.5
Figure 104. Output Filter Requirements in 4× Oversampling Mode
REV. A
100M
–51–
54.0
ADV7194
APPENDIX 7
DAC BUFFERING
External buffering is needed on the ADV7194 DAC outputs.
The configuration in Figure 105 is recommended.
+VCC
When calculating absolute output full-scale current and voltage
use the following equations:
INPUT/
OPTIONAL
FILTER O/P
VOUT = IOUT × RLOAD
AD8051
OUTPUT TO
TV MONITOR
–VCC
IOUT = (VREF × K)/RSET
Figure 106. Recommended DAC Output Buffer Using an
Op Amp
K = 4.2146 constant, VREF = 1.235 V
VAA
ADV7194
VREF
RSET1
1.2k
PIXEL
PORT
DAC A
OUTPUT
BUFFER
CVBS
DAC B
OUTPUT
BUFFER
LUMA
DAC C
OUTPUT
BUFFER
CHROMA
DAC D
OUTPUT
BUFFER
G
DAC E
OUTPUT
BUFFER
B
DAC F
OUTPUT
BUFFER
R
DIGITAL
CORE
RSET2
1.2k
Figure 105. Output DAC Buffering Configuration
–52–
REV. A
ADV7194
APPENDIX 8
RECOMMENDED REGISTER VALUES
The ADV7194 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards.
PAL B, D, G, H, I (FSC = 4.43361875 MHz)
NTSC (FSC = 3.5795454 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
1DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
35Hex
REV. A
Data
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Output Clock Register
10Hex
3FHex
62Hex
00Hex
00Hex
00Hex
00Hex
00Hex
04Hex
00Hex
08Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
44Hex
20Hex
00Hex
70Hex
Address
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
1DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
35Hex
–53–
Data
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Output Clock Register
11Hex
3FHex
62Hex
00Hex
00Hex
00Hex
00Hex
00Hex
04Hex
00Hex
08Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
44Hex
20Hex
00Hex
70Hex
ADV7194
PAL 60 (FSC = 4.43361875 MHz)
PAL N (FSC = 4.43361875 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
4Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
35Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Output Clock Register
Data
Address
13Hex
3FHex
62Hex
00Hex
00Hex
00Hex
00Hex
00Hex
04Hex
00Hex
08Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
44Hex
20Hex
00Hex
70Hex
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
1DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
35Hex
–54–
Data
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Output Clock Register
12Hex
3FHex
62Hex
00Hex
00Hex
00Hex
00Hex
00Hex
04Hex
00Hex
08Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
44Hex
20Hex
00Hex
70Hex
REV. A
ADV7194
POWER-ON RESET REGISTER VALUES
POWER-ON RESET REG VALUES
(PAL_NTSC = 0, NTSC Selected)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
1DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
26Hex
27Hex
28Hex
29Hex
2AHex
2BHex
2CHex
2DHex
2EHex
2FHex
30Hex
31Hex
32Hex
33Hex
34Hex
35Hex
REV. A
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Gamma 0
Gamma 1
Gamma 2
Gamma 3
Gamma 4
Gamma 5
Gamma 6
Gamma 7
Gamma 8
Gamma 9
Gamma 10
Gamma 11
Gamma 12
Gamma 13
Brightness Detect Register
Output Clock Register
POWER-ON RESET REG VALUES
(PAL_NTSC = 1, PAL Selected)
Data
Address
00Hex
07Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
08Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
72Hex
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
1AHex
1BHex
1CHex
1DHex
1EHex
1FHex
20Hex
21Hex
22Hex
23Hex
24Hex
25Hex
26Hex
27Hex
28Hex
29Hex
2AHex
2BHex
2CHex
2DHex
2EHex
2FHex
30Hex
31Hex
32Hex
33Hex
34Hex
35Hex
–55–
Data
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Mode Register 7
Mode Register 8
Mode Register 9
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Reg 0
CGMS_WSS Reg 1
CGMS_WSS Reg 2
Teletext Control Register
Contrast Control Register
Color Control Register 1
Color Control Register 2
Hue Control Register
Brightness Control Register
Sharpness Response Register
DNR 0
DNR 1
DNR 2
Gamma 0
Gamma 1
Gamma 2
Gamma 3
Gamma 4
Gamma 5
Gamma 6
Gamma 7
Gamma 8
Gamma 9
Gamma 10
Gamma 11
Gamma 12
Gamma 13
Brightness Detect Register
Output Clock Register
00Hex
07Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
08Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
xxHex
72Hex
ADV7194
APPENDIX 9
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
Figure 107. NTSC Composite Video Levels
100 IRE
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
Figure 108. NTSC Luma Video Levels
PEAK CHROMA
963.8mV
629.7mV (pk-pk)
286mV (pk-pk)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
335.2mV
0mV
Figure 109. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
–40 IRE
SYNC LEVEL
45.9mV
Figure 110. NTSC RGB Video Levels
–56–
REV. A
ADV7194
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
Figure 111. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
338mV
52.1mV
Figure 112. NTSC Luma Video Levels
PEAK CHROMA
978mV
694.9mV (pk-pk)
286mV (pk-pk)
650mV
BLANK/BLACK LEVEL
283mV
PEAK CHROMA
0mV
Figure 113. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
BLANK/BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
Figure 114. NTSC RGB Video Levels
REV. A
–57–
336.5mV
51mV
ADV7194
PAL WAVEFORMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
Figure 115. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
350.7mV
SYNC LEVEL
50.8mV
Figure 116. PAL Luma Video Levels
PEAK CHROMA
990mV
672mV (pk-pk)
300mV (pk-pk)
650mV
BLANK/BLACK LEVEL
318mV
PEAK CHROMA
0mV
Figure 117. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
351.8mV
SYNC LEVEL
51mV
Figure 118. PAL RGB Video Levels
–58–
REV. A
ADV7194
PARADE SMPTE/EBU PAL
mV
Y(A)
Pb(B)
mV
Pr(C)
mV
700
250
250
600
200
200
500
150
150
400
100
100
300
50
50
200
0
0
–50
–50
0
–100
–100
100
–150
–150
200
–200
–200
–250
–250
100
300
Figure 119. PAL YUV Parade Plot
mV
GREEN (A)
mV
BLUE (B)
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
mV
RED (C)
700
600
500
400
300
200
100
0
0
100
100
100
200
200
200
300
300
300
Figure 120. PAL RGB Waveforms
REV. A
–59–
ADV7194
505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
UV WAVEFORMS
505mV
423mV
334mV
171mV
BETACAM LEVEL
BETACAM LEVEL
82mV
0mV
0mV
0mV
0mV
–82mV
171mV
334mV
–423mV
505mV
–505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 124. NTSC 100% Color Bars No Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Figure 121. NTSC 100% Color Bars No Pedestal U Levels
467mV
467mV
391mV
309mV
158mV
BETACAM LEVEL
BETACAM LEVEL
76mV
0mV
0mV
0mV
0mV
–76mV
–158mV
–309mV
–391mV
–467mV
–467mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Figure 125. NTSC 100% Color Bars with Pedestal V
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 122. NTSC 100% Color Bars with Pedestal U Levels
350mV
350mV
293mV
232mV
SMPTE LEVEL
SMPTE LEVEL
118mV
57mV
0mV
0mV
0mV
0mV
–57mV
–118mV
–232mV
–293mV
–350mV
–350mV
Figure 126. PAL 100% Color Bars V Levels
Figure 123. PAL 100% Color Bars U Levels
–60–
REV. A
ADV7194
OUTPUT WAVEFORMS
0.6
VOLTS
0.4
0.2
0.0
0.2
L608
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 0.00 dB
APL = 39.1%
625 LINE PAL
NO FILTERING
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
SOUND-IN-SYNC OFF
SYNC = SOURCE
FRAMES SELECTED: 1 2 3 4
Figure 127. 100/0/75/0 PAL Color Bars
VOLTS
0.5
0.0
L575
0.0
10.0
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
20.0
30.0
40.0
50.0
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
–61–
70.0
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 128. 100/0/75/0 PAL Color Bars Luminance
REV. A
60.0
ADV7194
VOLTS
0.5
0.0
–0.5
L575
10.0
20.0
30.0
40.0
MICROSECONDS
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
50.0
60.0
NO BRUCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 129. 100/0/75/0 PAL Color Bars Chrominance
100.0
VOLTS
IRE:FLT
0.5
50.0
0.0
0.0
–50.0
0.0
F1
L76
10.0
20.0
30.0
40.0
MICROSECONDS
APL = 44.6%
525 LINE NTSC
50.0
60.0
PRECISION MODE OFF
NO FILTERING
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
SYNC = A
FRAMES SELECTED: 1 2
Figure 130. 100/7.5/75/7.5 NTSC Color Bars
–62–
REV. A
ADV7194
100.0
0.6
0.4
VOLTS
IRE:FLT
50.0
0.2
0.0
0.0
–0.2
F2
L238
10.0
20.0
30.0
40.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.7%
525 LINE NTSC
NO FILTERING
50.0
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
60.0
SYNC = SOURCE
FRAMES SELECTED: 1 2
Figure 131. 100/7.5/75/7.5 NTSC Color Bars Luminance
0.4
50.0
0.0
IRE:FLT
VOLTS
0.2
–0.2
–50.0
–0.4
F1
L76
0.0
10.0
20.0
30.0
40.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE!
525 LINE NTSC
50.0
60.0
PRECISION MODE OFF
NO FILTERING
SYNCHRONOUS
SLOW CLAMP TO 0.00 V AT 6.72 s
SYNC = B
FRAMES SELECTED: 1 2
Figure 132. 100/7.5/75/7.5 NTSC Color Bars Chrominance
REV. A
–63–
ADV7194
VIDEO MEASUREMENT PLOTS
COLOR BAR (NTSC)
FIELD = 1
LINE = 21
WFM
FCC COLOR BAR
LUMINANCE LEVEL (IRE)
99.6
69.0
55.9
48.1
36.3
28.3
15.7
7.7
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
100
50
0
CHROMINANCE LEVEL (IRE)
0.0
62.1
87.6
81.8
81.8
87.8
62.1
0.0
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
167.3
283.8
240.9
60.8
103.6
347.1
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
100
50
0
CHROMINANCE PHASE (DEGREE)
400
200
0
GRAY
AVERAGE 32
BLACK
32
Figure 133. NTSC Color Bar Measurement
COLOR BAR (PAL)
LINE = 570
WFM
COLOR BAR
LUMINANCE LEVEL (mV)
1000
695.7
464.8
366.6
305.7
217.3
156.4
61.2
–0.4
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
500
0
CHROMINANCE LEVEL (mV)
1000
0.0
474.4
669.1
623.5
624.7
669.6
475.2
0.0
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
166.7
283.3
240.4
60.4
103.2
346.7
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
500
0
CHROMINANCE PHASE (DEGREE)
400
300
200
100
0
GRAY
AVERAGE 32
BLACK
32
Figure 134. PAL Color Bar Measurement
–64–
REV. A
ADV7194
DG DP (NTSC)
MOD 5 STEP
WFM
DG DP (PAL)
FIELD = 1, LINE = 21
2.5
0.21
0.02
0.07
0.27
MIN = 0.00, MAX = 0.32, p-p = 0.32
DIIFFERENTIAL GAIN (PERCENT)
MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27
DIIFFERENTIAL GAIN (PERCENT)
0.00
MOD 5 STEP
WFM
LINE = 570
0.08
2.5
0.00
0.30
0.15
0.24
0.32
0.26
1st
2nd
3rd
4th
5th
6th
1.5
1.5
0.5
0.5
–0.5
–0.5
–1.5
–1.5
–2.5
1st
2nd
3rd
4th
2.5
0.10
–2.5
6th
0.12
0.15
0.13
MIN = 0.00, MAX = 0.16, p-p = 0.16
DIFFERENTIAL PHASE (DEGREE)
MIN = 0.00, MAX = 0.20, p-p = 0.20
DIFFERENTIAL PHASE (DEGREE)
0.00
5th
0.10
2.5
0.00
0.09
1st
2nd
0.13
0.16
3rd
4th
0.12
0.14
5th
6th
1.5
1.5
0.5
0.5
–0.5
–0.5
–1.5
–1.5
–2.5
1st
2nd
AVERAGE 32
3rd
4th
5th
–2.5
6th
AVERAGE 32
32
Figure 135. NTSC DG DP Measurement
LUMINANCE NONLINEARITY (NTSC)
Figure 137. PAL DG DP Measurement
LUMINANCE NONLINEARITY (PAL)
MOD 5 STEP
WFM
99.9
99.9
99.6
100.0
MOD 5 STEP
p-p = 0.8
LUMINANCE NONLINEARITY (PERCENT)
p-p = 0.4
LUMINANCE NONLINEARITY (PERCENT)
WFM
LINE = 570
FIELD = 2, LINE = 77
111
32
113
99.9
99.6
99.9
100.0
2nd
3rd
99.6
99.9
111
109
109
107
107
105
105
103
101
103
99
101
97
99
95
97
93
95
91
93
89
91
1st
AVERAGE 32
2nd
3rd
4th
5th
1st
32
AVERAGE 32
Figure 136. NTSC Luminance Nonlinearity
REV. A
4th
5th
32
Figure 138. PAL Luminance Nonlinearity
–65–
ADV7194
CHROMINANCE NONLINEARITY(NTSC)
WFM
FIELD = 2, LINE = 217
CHROMINANCE AMPLITUDE ERROR (PERCENT)
0.5
NTSC–7 COMBINATION
CHROMINANCE NONLINEARITY(PAL)
WFM
LINE = 572
CHROMINANCE AMPLITUDE ERROR (PERCENT)
REF = 40IRE PACKET
0.0
–0.3
MOD 3 STEP
REF = 420mV PACKET
0.6
0.0
–0.4
140mV
420mV
700mV
10
10
0
0
–10
–10
20IRE
40IRE
80IRE
CHROMINANCE PHASE ERROR (DEGREE)
–0.0
5
REF = 40IRE PACKET
0.0
CHROMINANCE PHASE ERROR (DEGREE)
0.0
0
0
–5
–5
20IRE
40IRE
80IRE
CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV)
0.0
0.1
REF = 420mV PACKET
–0.3
0.0
–0.3
140mV
420mV
700mV
CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 700mV)
0.1
0.0
0.0
0.1
420mV
700mV
0.2
0.1
0.2
0.0
0.0
–0.1
–0.2
–0.2
20IRE
AVERAGE 32
40IRE
80IRE
140mV
AVERAGE 32
32
Figure 139. NTSC Chrominance Nonlinearity
CHROMINANCE AM/PM (NTSC)
FIELD = 2, LINE = 217
WFM
Figure 141. PAL Chrominance Nonlinearity
RED FIELD
CHROMINANCE AM/PM (PAL)
LINE = 572
BANDWIDTH 10kHz TO 100kHz
–86.5dB RMS
–90
–85
–80
–75
PM NOISE
–70
AM NOISE
–65
–60
dB RMS
–90
–85
APPROPRIATE
–80
–75
–70
–84.2dB RMS
–95
–82.7dB RMS
–95
WFM
BANDWIDTH 10kHz TO 100kHz
AM NOISE
–95
32
–90
–85
–80
–75
PM NOISE
–65
–60
dB RMS
–65
–60
dB RMS
–65
–60
dB RMS
–80.5dB RMS
–95
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
–70
–90
–85
–80
–75
–70
(0dB = 700mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 140. NTSC Chrominance AM/PM
Figure 142. PAL Chrominance AM/PM
–66–
REV. A
ADV7194
NOISE SPECTRUM (NTSC)
PEDESTAL
WFM
NOISE SPECTRUM (PAL)
PEDESTAL
WFM
LINE = 511
FIELD = 2, LINE = 223
NOISE LEVEL = –79.7dB RMS
AMPLITUDE (0dB = 714mV p-p)
NOISE LEVEL = –79.1dB RMS
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 10kHz TO FULL
BANDWIDTH 10kHz TO FULL
20
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–100
1
2
3
MHz
4
5
6
1
RAMP
WFM
5
6
7
NOISE SPECTRUM (PAL)
RAMP
WFM
LINE = 572
NOISE LEVEL = –63.1dB RMS
AMPLITUDE (0dB = 714mV p-p)
BANDWIDTH 100kHz TO FULL (TILT NULL)
0
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
2
3
MHz
NOISE LEVEL = –62.3dB RMS
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 100kHz TO FULL (TILT NULL)
4
5
6
1
2
3
4
5
6
MHz
Figure 144. NTSC Noise Spectrum: Ramp
REV. A
4
Figure 145. PAL Noise Spectrum: Pedestal
FIELD = 2, LINE = 217
1
3
MHz
Figure 143. NTSC Noise Spectrum: Pedestal
NOISE SPECTRUM (NTSC)
2
Figure 146. PAL Noise Spectrum: Ramp
–67–
7
ADV7194
APPENDIX 10
VECTOR PLOTS
V
APL = 39.6%
SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN 1.000 0.000dB
625 LINE PAL
BURST FROM SOURCE
DISPLAY +V AND –V
cy
R
g
M
g
75%
100%
YI
b
U
yl
B
G
Cy
m
g
r
SOUND IN SYNC OFF
Figure 147. PAL Vector Plot
R-Y
APL = 45.1%
SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN 1.000 0.000dB
525 LINE NTSC
BURST FROM SOURCE
cy
I
R
M
g
YI
Q
b
100%
B-Y
75%
B
G
Cy
–Q
–I
SETUP 7.5%
Figure 148. NTSC Vector Plot
–68–
REV. A
ADV7194
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.063 (1.60)
MAX
0.030 (0.75)
0.020 (0.50)
C00231–0–2/01 (rev. A)
80-Lead LQFP
(ST-80)
0.640 (16.25)
SQ
0.620 (15.75)
0.553 (14.05)
SQ
0.549 (13.95)
80
1
61
60
SEATING
PLANE
0.486
(12.35)
TYP
SQ
TOP VIEW
(PINS DOWN)
20
21
41
40
0.029 (0.73)
0.022 (0.57)
0.014 (0.35)
0.010 (0.25)
PRINTED IN U.S.A.
0.004 (0.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.057 (1.45)
0.053 (1.35)
REV. A
–69–
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