Data Sheet
10-Bit, 4× Oversampled SDTV Video Decoder
with Differential Inputs and Deinterlacer
ADV7283
FEATURES
GENERAL DESCRIPTION
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
6 analog video input channels with on-chip antialiasing
filters
Video input support for CVBS (composite), Y/C (S-Video), and
YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
time-base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive peak
white mode
Fast switching capability
Integrated interlaced-to-progressive (I2P) video output
converter (deinterlacer)
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi® (Macrovision) copy protection detection
8-bit ITU-R BT.656 YCrCb 4:2:2 output
Full featured vertical blanking interval (VBI) data slicer with
world system teletext (WST) support
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C automotive temperature grade
−40°C to +85°C industrial qualified temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
The ADV7283 is a versatile one-chip, multiformat video
decoder that automatically detects standard analog baseband
video signals compatible with worldwide NTSC, PAL, and
SECAM standards in the form of composite, S-Video, and
component video.
The ADV7283 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The six analog video inputs of the ADV7283 can accept singleended, pseudo differential, and fully differential signals.
The ADV7283 contains a deinterlacer (I2P converter) that
allows the device to output video in a progressive format.
The ADV7283 is programmed via a 2-wire, serial bidirectional
port (I2C compatible) and is fabricated in a 1.8 V CMOS
process.
The ADV7283 is provided in a space-saving LFCSP surfacemount, RoHS-compliant package.
The ADV7283 is available in an automotive grade rated over the
−40°C to +105°C temperature range, as well as a −40°C to +85°C
temperature range, making the device ideal for both automotive
and industrial applications.
APPLICATIONS
Automotive infotainment
Smartphone/multimedia handsets
DVRs for video security
Media players
Rev. A
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ADV7283
Data Sheet
TABLE OF CONTENTS
Features .....................................................................................1
Power-Down Sequence........................................................ 12
Applications...............................................................................1
DVDDIO Supply Voltage.......................................................... 12
General Description ..................................................................1
Power Supply Requirements ................................................ 12
Revision History ........................................................................2
Input Networks........................................................................ 13
Functional Block Diagram.........................................................3
Single-Ended Input Network ............................................... 13
Specifications.............................................................................4
Differential Input Network .................................................. 13
Electrical Specifications .........................................................4
Short-to-Battery Protection ................................................. 13
Video Specifications...............................................................5
Applications Information ........................................................ 14
Analog Specifications.............................................................6
Input Configuration............................................................. 14
Clock and I C Timing Specifications......................................6
Adaptive Contrast Enhancement......................................... 15
Pixel Port Timing Specifications ............................................7
I2P Function ........................................................................ 15
Absolute Maximum Ratings ......................................................8
ITU-R BT.656 Transmitter Configuration ........................... 15
Thermal Resistance ................................................................8
I2C Port Description ............................................................ 16
ESD Caution ..........................................................................8
Register Maps ...................................................................... 17
Pin Configuration and Function Descriptions...........................9
PCB Layout Recommendations ........................................... 18
Theory of Operation................................................................10
Typical Circuit Connection ..................................................... 20
Analog Front End ................................................................10
Outline Dimensions ................................................................ 21
Standard Definition Processor .............................................11
Ordering Guide ................................................................... 21
Power Supply Sequencing ........................................................12
Automotive Products ........................................................... 21
2
Optimal Power-Up Sequence...............................................12
Simplified Power-Up Sequence............................................12
REVISION HISTORY
10/2016—Rev. 0 to Rev. A
Changes to Ordering Guide.....................................................21
5/2014—Revision 0: Initial Version
Rev. A | Page 2 of 21
Data Sheet
ADV7283
FUNCTIONAL BLOCK DIAGRAM
ADV7283
CLOCK PROCESSING BLOCK
LLC
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
I2P
REFERENCE
ACE
DOWN
DITHER
I2C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
NOTES
1. SHA IS A SAMPLE-AND-HOLD AMPLIFIER CIRCUIT.
Figure 1.
Rev. A | Page 3 of 21
8-BIT
PIXEL DATA
P0 TO P7
INTRQ
12347-001
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
ADV7283
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
ADC Resolution
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Symbol
N
INL
DNL
VIH
Input Low Voltage
VIL
Input Leakage Current
I IN
Input Capacitance
CRYSTAL INPUT
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS
Output High Voltage
CIN
Output Low Voltage
VOL
High Impedance Leakage Current
Output Capacitance
POWER REQUIREMENTS 1, 2, 3
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Power Supply
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Single-Ended CVBS Input
Differential CVBS Input
Y/C Input
YPrPb Input
Digital Supply Current
Single-Ended CVBS Input
Differential CVBS Input
Test Conditions/Comments
Min
CVBS mode
CVBS mode
DVDDIO = 3.3 V
DVDDIO = 1.8 V
DVDDIO = 3.3 V
DVDDIO = 1.8 V
RESET pin
SDATA, SCLK pins
PWRDWN , ALSB pins
Typ
10
Bits
LSB
LSB
2
1.2
−10
−10
−10
XTALN pin
XTALN pin
1.2
VOH
DVDDIO = 3.3 V, I SOURCE = 0.4 mA
DVDDIO = 1.8 V, I SOURCE = 0.4 mA
DVDDIO = 3.3 V, I SINK = 3.2 mA
DVDDIO = 1.8 V, I SINK = 1.6 mA
2.4
1.4
I LEAK
COUT
1.62
1.71
1.71
1.71
Fully differential and pseudo
differential CVBS
Unit
2
±0.6
VIH
VIL
DVDDIO
PVDD
AVDD
DVDD
I DVDDIO
I PVDD
I AVDD
Max
3.3
1.8
1.8
1.8
5
12
0.8
0.4
+10
+15
+50
10
V
V
V
V
µA
µA
µA
pF
0.4
V
V
0.4
0.2
10
20
V
V
V
V
µA
pF
3.63
1.89
1.89
1.89
V
V
V
V
mA
mA
47
69
mA
mA
60
75
mA
mA
70
70
mA
mA
70
70
mA
mA
I DVDD
Fully differential and pseudo
differential CVBS
Y/C Input
YPrPb Input
Rev. A | Page 4 of 21
Data Sheet
Parameter
POWER-DOWN CURRENTS1
Digital I/O Supply Power-Down
Current
PLL Supply Power-Down Current
Analog Supply Power-Down Current
Digital Supply Power-Down Current
Total Power Dissipation in PowerDown Mode
ADV7283
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
I DVDDIO_PD
73
µA
I PVDD_PD
I AVDD_PD
I DVDD_PD
46
0.2
420
1
µA
µA
µA
mW
Guaranteed by characterization.
Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern.
3 All specifications apply when the I2P core is activated, unless otherwise stated.
1
2
VIDEO SPECIFICATIONS
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 2.
Parameter
NONLINEAR SPECIFICATIONS 1
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
Signal-to-Noise Ratio (SNR),
Unweighted
Analog Front-End Crosstalk
Common-Mode Rejection Ratio 2
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
Subcarrier Lock Range
Color Lock-In Time
Synchronization Depth Range
Color Burst Range
Fast Switch Speed 3
Symbol
Test Conditions/Comments
Min
DP
DG
LNL
CVBS input, modulated five-step
CVBS input, modulated five-step
CVBS input, five-step
0.9
0.5
2.0
Degrees
%
%
SNR
Luma ramp
57.1
dB
Luma flat field
58
60
73
dB
dB
dB
CMRR
Typ
−5
40
fSC
Max
+5
70
±1.3
60
20
5
200
200
100
1
Unit
%
Hz
kHz
Lines
%
%
ms
These specifications apply for all CVBS input types (NTSC, PAL, and SECAM), as well as for single-ended and differential CVBS inputs.
The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Networks section). The CMRR measurement
was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz.
3 Fast switch speed is the time required for the ADV7283 to switch from one analog input (single-ended or differential) to another, for example, switching from A 1 to A 2.
IN
IN
2
Rev. A | Page 5 of 21
ADV7283
Data Sheet
ANALOG SPECIFICATIONS
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 3.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions/Comments
Min
Typ
Max
0.1
10
0.4
0.4
10
10
Clamps switched off
Unit
µF
MΩ
mA
mA
µA
µA
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, and PVDD= 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 4.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I 2 C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
RESET INPUT
Symbol
Min
Typ
Max
Unit
±50
MHz
ppm
28.63636
400
t1
t2
t3
t4
t5
t6
t7
t8
kHz
µs
µs
µs
µs
ns
ns
ns
µs
0.6
1.3
0.6
0.6
100
300
300
0.6
RESET Pulse Width
5
ms
t3
t5
t3
SDATA
t2
t4
t7
Figure 2. I C Timing Diagram
2
Rev. A | Page 6 of 21
t8
12347-002
t1
t6
SCLK
Data Sheet
ADV7283
PIXEL PORT TIMING SPECIFICATIONS
AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 5.
Parameter
CLOCK OUTPUTS
LLC Output Frequency
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
55:45
MHz
% duty cycle
3.8
ns
6.9
ns
27
t 16 :t 17
45:55
Negative clock edge to start of valid data
(t SETUP = t 17 − t 18 )
End of valid data to negative clock edge
(t HOLD = t 16 − t 19 )
t 18
t 19
t16
t17
OUTPUT LLC
t18
12347-201
t19
P0 TO P7 OUTPUTS
Figure 3. Pixel Port and Control Output Timing Diagram
Rev. A | Page 7 of 21
ADV7283
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
1
Parameter
AVDD to GND
DVDD to GND
PVDD to GND
DVDDIO to GND
PVDD to DVDD
AVDD to DVDD
Digital Inputs (RESET , ALSB,
SDATA, SCLK, PWRDWN )
Voltage
Digital Outputs (P7 to P0,
INTRQ , LLC) Voltage
Analog Inputs (XTALN, AIN 1 to
AIN 6) to Ground
Maximum Junction Temperature
(TJ max)
Storage Temperature Range
1
Rating
2.2 V
2.2 V
2.2 V
4V
−0.9 V to +0.9 V
−0.9 V to +0.9 V
GND − 0.3 V to DVDDIO + 0.3 V
GND − 0.3 V to DVDDIO + 0.3 V
The thermal resistance values in Table 7 are specified for the
device soldered onto a 4-layer printed circuit board (PCB) with
a common ground plane (GND) and with the exposed pad of
the device connected to DGND. The values in Table 7 are
maximum values.
Table 7. Thermal Resistance for the 32-Lead LFCSP
Thermal Characteristic
Junction to Ambient Thermal
Resistance (Still Air)
Junction to Case Thermal
Resistance
GND − 0.3 V to AVDD + 0.3 V
ESD CAUTION
140°C
−65°C to +150°C
The absolute maximum ratings assume that the DGND pins and the exposed
pad of the ADV7283 are connected together to a common ground plane
(GND). This is part of the recommended layout scheme. See the PCB Layout
Recommendations section for more information. The absolute maximum
ratings are stated in relation to this common ground plane.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 8 of 21
Symbol
θJA
Value
32.5
Unit
°C/W
θJC
2.3
°C/W
Data Sheet
ADV7283
32
31
30
29
28
27
26
25
LLC
PWRDWN
SCLK
SDATA
ALSB
RESET
INTRQ
AIN6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADV7283
LFCSP
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
AIN5
AIN4
AIN3
AVDD
VREFN
VREFP
AIN2
AIN1
NOTES
1. THE EXPOSED PAD AND DGND PINS MUST BE
CONNECTED TOGETHER TO A COMMON GROUND
PLANE (GND).
12347-057
P3 9
P2 10
P1 11
P0 12
DVDD 13
XTALP 14
XTALN 15
PVDD 16
DGND
DVDDIO
DVDD
DGND
P7
P6
P5
P4
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1, 4
Mnemonic
DGND
Type
Ground
2
3, 13
5 to 12
14
DVDDIO
DVDD
P7 to P0
XTALP
Power
Power
Output
Output
15
XTALN
Input
16
17,18, 22 to
25
19
20
21
26
PVDD
AIN 1 to AIN 6
Power
Input
VREFP
VREFN
AVDD
INTRQ
Output
Output
Power
Output
27
RESET
Input
28
ALSB
Input
29
30
31
SDATA
SCLK
PWRDWN
LLC
Input/output
Input
Input
32
EPAD (EP)
Output
Description
Ground for Digital Supply. The exposed pad and DGND pins must be connected together
to a common ground plane (GND).
Digital Input/Output Power Supply (1.8 V or 3.3 V).
Digital Power Supply (1.8 V).
Video Pixel Output Ports.
Output for the External 28.63636 MHz Crystal. Connect this pin to the external
28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock
oscillator source is used to clock the ADV7283. The crystal used with the ADV7283 must be
a fundamental crystal.
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7283 must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used
to clock the ADV7283, the output of the oscillator is fed into the XTALN pin.
PLL Power Supply (1.8 V).
Analog Video Input Channels.
Internal Voltage Reference Output.
Internal Voltage Reference Output.
Analog Power Supply (1.8 V).
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7283 circuitry.
Selector for the I 2 C Write Address. When ALSB is set to Logic 0, the write address is 0x40;
when ALSB is set to Logic 1, the write address is 0x42.
I 2 C Port Serial Data Input/Output.
I 2 C Port Serial Clock Input. The maximum clock rate is 400 kHz.
Power-Down Pin. A logic low on this pin places the ADV7283 in power-down mode.
Line-Locked Output Clock for Output Pixel Data. The clock output is typically 27 MHz, but it
increases or decreases according to the video line length.
Exposed Pad. The exposed pad and DGND pins must be connected together to a common
ground plane (GND).
Rev. A | Page 9 of 21
ADV7283
Data Sheet
THEORY OF OPERATION
The ADV7283 is a versatile one-chip, multiformat video
decoder. The device automatically detects standard analog
baseband video signals compatible with worldwide NTSC, PAL,
and SECAM standards in the form of composite, S-Video, and
component video.
The ADV7283 converts the analog video signals into an 8-bit
YCrCb 4:2:2 video data stream that is compatible with the 8-bit
ITU-R BT.656 interface standard.
The analog video inputs of the ADV7283 accept single-ended,
pseudo differential, and fully differential composite video signals,
as well as S-Video and YPrPb video signals, supporting a wide
range of consumer and automotive video sources.
In differential CVBS mode, the ADV7283, along with an
external resistor divider, provides a common-mode input range
of up to 4 V, enabling the removal of large signal, common-mode
transients present on the video lines.
The advanced I2P function allows the ADV7283 to convert an
interlaced video input into a progressive video output. This
function is performed without the need for external memory.
The ADV7283 uses edge adaptive technology to minimize
video defects on low angle lines.
The AGC and clamp restore circuitry allow an input video
signal peak-to-peak range of 1.0 V p-p at the analog video input
pins of the ADV7283. Alternatively, the AGC and clamp restore
circuitry can be bypassed for manual settings.
The external ac coupling capacitors protect the ADV7283 from
short-to-battery (STB) events on the analog video input pins.
The ADV7283 supports a number of other functions, including
8-bit to 6-bit down dither mode and ACE.
The ADV7283 is programmed via a 2-wire, serial bidirectional
port (I2C compatible) and is fabricated in a 1.8 V CMOS
process. The monolithic CMOS construction of the ADV7283
ensures greater functionality with lower power dissipation.
The ADV7283 is provided in a space-saving LFCSP surfacemount, RoHS-compliant package.
ANALOG FRONT END
The analog front end (AFE) of the ADV7283 comprises a single
high speed, 10-bit ADC that digitizes the analog video signal
before applying it to the standard definition processor (SDP).
The AFE uses differential channels to the ADC to ensure high
performance in mixed-signal applications and to enable differential
CVBS inputs to connect directly to the ADV7283.
The AFE also includes an input mux that enables the
application of multiple video signals to the ADV7283. The input
mux allows the application of up to six composite video signals to
the ADV7283.
Current clamps are positioned in front of the ADC to ensure
that the video signal remains within the range of the converter.
A resistor divider network is required before each analog input
channel to ensure that the input signal is kept within the range
of the ADC (see the Input Networks section). Fine clamping of
the video signal is performed downstream by digital fine
clamping within the ADV7283.
Table 9 lists the three ADC clock rates that are determined by
the video input format to be processed. These clock rates ensure
4× oversampling per channel for CVBS, Y/C, and YPrPb modes.
Table 9. ADC Clock Rates
Input Format
CVBS (Composite)
Y/C (S-Video)
YPrPb (Component)
1
ADC Clock Rate
(MHz)1
57.27
114
172
Oversampling
Rate per
Channel
4×
4×
4×
Based on a 28.63636 MHz crystal between the XTALP and XTALN pins.
The fully differential AFE of the ADV7283 provides inherent
small and large signal noise rejection, improved
electromagnetic interference (EMI) protection, and the ability
to absorb ground bounce. Support is provided for both true
differential and pseudo differential signals.
The ADV7283 is available in an automotive grade that is rated
over the−40°C to +105°C temperature range, making the device
ideal for automotive applications.
The ADV7283 is also available in a −40°C to +85°C temperature
range, making it ideal for industrial applications.
Rev. A | Page 10 of 21
Data Sheet
ADV7283
STANDARD DEFINITION PROCESSOR
The ADV7283 can decode a large selection of baseband video
signals in composite (both single-ended and differential),
S-Video, and component formats. The video processor supports
the following standards:
•
•
•
PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,
PAL Nc, PAL 60
NTSC J, NTSC M, NTSC 4.43
SECAM B, SECAM D, SECAM G, SECAM K, SECAM L
Using the SDP, the ADV7283 can automatically detect the video
standard and process it accordingly.
The ADV7283 has a five-line adaptive 2D comb filter that
provides superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to the
video standard and signal quality without user intervention.
Video user controls such as brightness, contrast, saturation, and
hue are also available with the ADV7283.
The ADV7283 implements the patented Adaptive Digital Line
Length Tracking (ADLLT™) algorithm to track varying video line
lengths from sources such as VCRs. ADLLT enables the
ADV7283 to track and decode poor quality video sources such as
VCRs and noisy sources from tuner outputs and camcorders.
The ADV7283 contains a chroma transient improvement (CTI)
processor that sharpens the edge rate of chroma transitions,
resulting in sharper vertical transitions.
The ACE feature of the ADV7283 offers improved visual detail
using an algorithm that automatically varies contrast levels to
enhance picture detail. ACE increases the contrast in dark areas
of an image without saturating the bright areas of the image.
This feature is particularly useful in automotive applications,
where it can be important to discern objects in shaded areas.
Down dithering converts the output of the ADV7283 from an
8-bit to a 6-bit output, enabling ease of design for standard LCD
panels.
The I2P block converts the interlaced video input into a
progressive video output without the need for external memory.
The SDP can process a variety of VBI data services, such as closed
captioning (CCAP), wide screen signaling (WSS), copy generation
management systems (CGMS), and teletext data slicing for
world system teletext (WST).
The ADV7283 is fully Rovi® (Macrovision) compliant; detection
circuitry enables Type I, Type II, and Type III protection levels
to be identified and reported to the user. The decoder is also
fully robust to all Rovi signal inputs.
Rev. A | Page 11 of 21
ADV7283
Data Sheet
POWER SUPPLY SEQUENCING
OPTIMAL POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7283 is to first
power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies
(DVDD, PVDD, and AVDD).
When powering up the ADV7283, follow these steps (during
power-up, all supplies must adhere to the specifications listed in
the Absolute Maximum Ratings section):
1.
2.
3.
4.
5.
6.
Assert the PWRDWN and RESET pins (pull the pins low).
Power up the DVDDIO supply.
After DVDDIO is fully asserted, power up the 1.8 V supplies.
After the 1.8 V supplies are fully asserted, pull
the PWRDWN pin high.
Wait 5 ms and then pull the RESET pin high.
After all power supplies and the PWRDWN and RESET pins
are powered up and stable, wait an additional 5 ms before
initiating I2C communication with the ADV7283.
SIMPLIFIED POWER-UP SEQUENCE
Alternatively, the ADV7283 can be powered up by asserting all
supplies and the PWRDWN and RESET pins simultaneously.
After this operation, perform a software reset, then wait 10 ms
before initiating I2C communication with the ADV7283.
While the supplies are being established, ensure that a lower
rated supply does not go above a higher rated supply level.
During power-up, all supplies must adhere to the specifications
listed in the Absolute Maximum Ratings section.
POWER-DOWN SEQUENCE
operate with a nominal DVDDIO voltage of 1.8 V. When operating
with a nominal voltage of 1.8 V, apply the power-up sequences
described in the Optimal Power-Up Sequence and Simplified
Power-Up Sequence sections. The only changes are that DVDDIO
is powered up to 1.8 V instead of 3.3 V, and the PWRDWN
and RESET pins of the ADV7283 are powered up to 1.8 V
instead of 3.3 V.
Note that when the ADV7283 operates with a nominal DVDDIO
voltage of 1.8 V, then set the drive strength of all digital outputs
to a maximum.
Note that when DVDDIO is set to a nominal voltage of 1.8 V, no
pins can be pulled up to 3.3 V. For example, pull the I2C pins of
the ADV7283 (SCLK and SDATA) up to 1.8 V instead of
3.3 V.
POWER SUPPLY REQUIREMENTS
Table 10 shows the current rating recommendations for power
supply design. Use these values when designing a power supply
section to ensure that an adequate current is supplied to the
ADV7283.
Table 10. Current Rating Recommendations for Power
Supply Design
Current
I DVDDIO
I DVDD
I AVDD
I PVDD
Rating
20 mA
110 mA
100 mA
20 mA
The ADV7283 supplies can be deasserted simultaneously as
long as DVDDIO does not go below a lower rated supply.
DVDDIO SUPPLY VOLTAGE
Under normal operating conditions, the ADV7283 operates
with a nominal DVDDIO voltage of 3.3 V. The device can also
1.8V
1.8V SUPPLIES
PWRDWN PIN
POWER-UP
3.3V SUPPLY
POWER-UP
RESET PIN
PWRDWN PIN
3.3V SUPPLY
1.8V SUPPLIES
POWER-UP
RESET PIN
POWER-UP
5ms
RESET
OPERATION
Figure 5. Optimal Power-Up Sequence
Rev. A | Page 12 of 21
5ms
WAIT
TIME
12347-005
VOLTAGE
3.3V
Data Sheet
ADV7283
INPUT NETWORKS
An input network (external resistor and capacitor circuit) is
required on the AINx input pins of the ADV7283. The
components of the input network depend on the video format
selected for the analog input.
transmission involves transmitting a CVBS signal and a source
ground signal.
SINGLE-ENDED INPUT NETWORK
•
•
•
Figure 6 shows the input network to use on each AINx input pin
of the ADV7283 when any of the following video input formats
are used:
Single-ended CVBS
Y/C (S-Video)
YPrPb
INPUT
CONNECTOR
VIDEO INPUT
FROM SOURCE
100nF
24Ω
EXT
ESD
AIN3
51Ω
12347-006
•
•
•
Figure 6. Single-Ended Input Network
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to the
ADC range of the ADV7283. This allows an input range of up to
1.47 V p-p. Note that amplifiers within the ADC restore the
amplitude of the input signal so SNR performance is
maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the AINx pins of the ADV7283.
The clamping circuitry within the ADV7283 restores the dc bias
of the input signal to the optimal level before it is fed into the
ADC of the ADV7283.
DIFFERENTIAL INPUT NETWORK
Figure 7 shows the input network to use when differential
CVBS video is input on the AINx input pins of the ADV7283.
POSITIVE
INPUT
CONNECTOR
1.3kΩ
100nF
AIN1
430Ω
EXT
ESD
R1
1.3kΩ
NEGATIVE
INPUT
CONNECTOR
AIN2
Inherent small signal and large signal noise rejection
Improved EMI performance
An ability to absorb ground bounce
Resistor R1 provides the RF end termination for the differential
CVBS input lines. For a pseudo differential CVBS input, a value
of 75 Ω is recommended for R1. For a fully differential CVBS
input, a value of 150 Ω is recommended for R1.
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
of the ADV7283 to 4 V p-p. Note that amplifiers within the
ADC restore the amplitude of the input signal so that SNR
performance is maintained.
The 100 nF ac coupling capacitors remove the dc bias of the
analog input video before it is fed into the AINx pins of the
ADV7283. The clamping circuitry within the ADV7283 restores
the dc bias of the input signal to the optimal level before it is fed
into the ADC of the ADV7283.
The combination of the 1.3 kΩ and 430 Ω resistors and the
100 nF ac coupling capacitors limits the current flow into the
ADV7283 during STB events (see the Short-to-Battery
Protection section).
To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors
must be closely matched; that is, all 1.3 kΩ and 430 Ω resistors
must have the same resistance tolerance, and this tolerance must
be as low as possible.
SHORT-TO-BATTERY PROTECTION
In differential mode, the ADV7283 is protected against STB
events by the external 100 nF ac coupling capacitors (see
Figure 7). The external input network resistors are sized to be
large enough to reduce the current flow during an STB event,
but small enough to avoid affecting the operation of the
ADV7283.
The power rating of the input network resistors must be chosen
withstand the high voltages of STB events. Similarly, ensure that
the breakdown voltage of the ac coupling capacitors is robust
enough to handle STB events.
430Ω
100nF
12347-007
VIDEO INPUT
FROM SOURCE
Differential video transmission has several key advantages over
single-ended transmission, including
Figure 7. Differential Input Network
Fully differential video transmission involves transmitting two
complementary CVBS signals. Pseudo differential video
The R1 resistor is protected because no current or limited current
flows through it during an STB event.
Rev. A | Page 13 of 21
ADV7283
Data Sheet
APPLICATIONS INFORMATION
INPUT CONFIGURATION
The input format of the ADV7283 is specified using the
INSEL[4:0] bits (see Table 11). These bits also configure the SDP
core to process CVBS, differential CVBS, Y/C (S-Video), or
component (YPrPb) format. The INSEL[4:0] bits are located in
the user sub map of the register space at Address 0x00[4:0]. For
more information about the registers, see the Register Maps
section.
The INSEL[4:0] bits specify predefined analog input routing
schemes, eliminating the need for manual mux programming
and allowing the user to route the various video signal types to
the decoder. For example, if the CVBS input is selected, the
remaining channels are powered down.
Table 11. Input Format Specified by the INSEL[4:0] Bits
INSEL[4:0] Bit Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
Video Format
CVBS
CVBS
CVBS
CVBS
Reserved
Reserved
CVBS
CVBS
Y/C (S-Video)
01001
Y/C (S-Video)
01010
01011
Reserved
Y/C (S-Video)
01100
YPrPb
01101
01110
Reserved
Differential CVBS
01111
Differential CVBS
10000
10001
Reserved
Differential CVBS
10010 to 11111
Reserved
Rev. A | Page 14 of 21
Analog Inputs
CVBS input on AIN 1
CVBS input on AIN 2
CVBS input on AIN 3
CVBS input on AIN 4
Reserved
Reserved
CVBS input on AIN 5
CVBS input on AIN 6
Y input on AIN 1
C input on AIN 2
Y input on AIN 3
C input on AIN 4
Reserved
Y input on AIN 5
C input on AIN 6
Y input on AIN 1
Pb input on AIN 2
Pr input on AIN 3
Reserved
Positive input on AIN 1
Negative input on AIN 2
Positive input on AIN 3
Negative input on AIN 4
Reserved
Positive input on AIN 5
Negative input on AIN 6
Reserved
Data Sheet
ADV7283
ADAPTIVE CONTRAST ENHANCEMENT
The ADV7283 can increase the contrast of an image depending
on the content of the picture, making bright areas brighter and
dark areas darker. The optional ACE feature increases the
contrast within dark areas without significantly affecting the
bright areas. The ACE feature is particularly useful in
automotive applications, where it is important to discern objects
in shaded areas.
The ACE function is disabled by default. To enable the ACE
function, execute the following register writes:
1.
2.
3.
Write 0x40 to Register 0x0E in User Sub Map (0x40 or
0x42). This enters User Sub Map 2.
Write 0x80 to Register 0x80 in User Sub Map 2 (0x40 or
0x42). This enables ACE.
Write 0x00 to Register 0x0E in User Sub Map 2 (0x40 or
0x42). This reenters User Sub Map.
To disable the ACE function, execute the following register
writes:
2.
3.
Write 0x40 to Register 0x0E in User Sub Map (0x40 or
0x42). This enters User Sub Map 2.
Write 0x00 to Register 0x80 in User Sub Map 2 (0x40 or
0x42). This disables ACE.
Write 0x00 to Register 0x0E in User Sub Map 2 (0x40 or
0x42). This reenters User Sub Map.
VIDEO
DECODER
The I2P function of the ADV7283 allows the device to convert
an interlaced video input into a progressive video output. This
function is performed without the need for external memory.
The ADV7283 use edge adaptive technology to minimize video
defects on low angle lines.
The I2P function is disabled by default. To enable the I2P function, use the recommended scripts from Analog Devices, Inc.
ITU-R BT.656 TRANSMITTER CONFIGURATION
The ADV7283 receives analog video and outputs digital video
according to the ITU-R BT.656 specification. The ADV7283
outputs the ITU-R BT.656 video data stream over the P0 to P7
data pins, and has a line-locked clock (LLC) pin.
Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format.
Synchronization signals are automatically embedded in the video
data signal in accordance with the ITU-R BT.656 specification.
The LLC output clocks the output data on the P0 to P7 pins at a
nominal frequency of 27 MHz.
ADV7283
P0
P1
P2
P3
ANALOG
VIDEO
INPUT
ANALOG
FRONT
END
STANDARD
DEFINITION
PROCESSOR
ITU-R BT.656
DATA
STREAM
P4
P5
P6
P7
LLC
12347-018
1.
I2P FUNCTION
Figure 8. ITU-R BT.656 Output Stage
Rev. A | Page 15 of 21
ADV7283
Data Sheet
I2C PORT DESCRIPTION
the SDATA and SCLK lines for the start condition and the
correct transmitted address.
The ADV7283 supports a 2-wire, I2C-compatible serial
interface. Two inputs, serial data (SDATA) and serial clock
(SCLK), carry information between the ADV7283 and the
system I2C master controller. The I2C port of the ADV7283
allows the user to set up and configure the decoder and to read
back captured VBI data.
The R/W bit determines the direction of the data. Logic 0 on the
LSB of the first byte means that the master writes information
to the peripheral. Logic 1 on the LSB of the first byte means that
the master reads information from the peripheral.
The ADV7283 has a number of possible I2C slave addresses and
subaddresses (see the Register Maps section). The main map of
the ADV7283 has four possible slave addresses for read and write
operations, depending on the logic level of the ALSB pin (see
Table 12).
The ADV7283 acts as a standard I2C slave device on the bus.
The data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/W bit. The device has subaddresses to enable
access to the internal registers; therefore, it interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto-increment, allowing data to
be written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also access
any unique subaddress register individually without updating
all the registers.
Table 12. Main Map I 2 C Address
R/ W Bit
0
1
0
1
Slave Address
0x40 (write)
0x41 (read)
0x42 (write)
0x43 (read)
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, issue
only one start condition, one stop condition, or a single stop
condition followed by a single start condition. If the user issues
an invalid subaddress, the ADV7283 does not issue an
acknowledge and returns to the idle condition.
The ALSB pin controls Bit 1 of the slave address. By changing
the logic level of the ALSB pin, it is possible to control two
ADV7283 devices in an application without using the same I2C
slave address. The LSB (Bit 0) specifies either a read or write
operation: Logic 1 corresponds to a read operation, and Logic 0
corresponds to a write operation.
To control the device on the bus, a specific protocol is followed.
2.
3.
4.
If the highest subaddress is exceeded in auto-increment mode,
one of the following actions is taken:
The master initiates a data transfer by establishing a start
condition, which is defined as a high to low transition on
SDATA while SCLK remains high, and indicates that an
address/data stream follows.
All peripherals respond to the start condition and shift the
next eight bits (the 7-bit address plus the R/W bit). The bits
are transferred from MSB to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth
clock pulse; this is known as an acknowledge (ACK) bit.
All other devices withdraw from the bus and maintain an
idle condition. In the idle condition, the device monitors
•
•
In read mode, the register contents of the highest subaddress continue to be output until the master device issues
a no acknowledge, which indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is not
pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded into
a subaddress register. The ADV7283 issues a no
acknowledge, and the device returns to the idle condition.
SDATA
SCLK
S
1–7
8
1–7
9
START ADDR R/W ACK
8
9
SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
Figure 9. Bus Data Transfer
WRITE
SEQUENCE
DATA
S SLAVE ADDR A(S) SUBADDRESS A(S)
LSB = 0
READ
SEQUENCE
DATA
A(S) P
LSB = 1
S SLAVE ADDR A(S) SUBADDRESS A(S) S
S = START BIT
P = STOP BIT
A(S)
SLAVE ADDR A(S)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
DATA
A(M)
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
Figure 10. Read and Write Sequence
Rev. A | Page 16 of 21
DATA
A(M) P
12347-011
1.
12347-010
ALSB Pin
0
0
1
1
Data Sheet
ADV7283
MAIN MAP
VPP MAP
DEVICE ADDRESS
DEVICE ADDRESS
WRITE: 0x84 (RECOMMENDED
READ: 0x85 SETTINGS)
ALSB PIN HIGH
WRITE: 0x42
READ: 0x43
0x0E[6:5] = 00
0x0E[6:5] = 01
0x0E[6:5] = 10
USER
SUB MAP
INTERRUPT/VDP
SUB MAP
USER SUB
MAP 2
VPP MAP DEVICE ADDRESS IS
PROGRAMMABLE AND SET BY
REGISTER 0xFD IN THE USER
SUB MAP
12347-012
ALSB PIN LOW
WRITE: 0x40
READ: 0x41
Figure 11. Register Map and Sub Map Access
REGISTER MAPS
User Sub Map 2
The ADV7283 contains two register maps: the main register
map and the VPP register map.
User Sub Map 2 contains registers that control the ACE, down
dither, and fast lock functions. It also contains controls that set
the acceptable input luma and chroma limits before the
ADV7283 enters free run and color kill modes.
Note that the main map of the ADV7283 contains three sub
maps: the user sub map, the interrupt/VDP map, and User Sub
Map 2.
Main Map
The ALSB pin sets the I2C slave address of the main map of the
ADV7283 (see Table 12). The main map allows the user to
program the I2C slave addresses of the VPP map. The main map
contains three sub maps: the user sub map, the interrupt/VDP
sub map, and User Sub Map 2. These three sub maps are accessed
by writing to the SUB_USR_EN bits (Address 0x0E[6:5]) within
the main map (see Figure 11 and Table 13).
User Sub Map
The user sub map contains registers that program the analog
front end and digital core of the ADV7283. The user sub map
has the same I2C slave address as the main map. To access the
user sub map, set the SUB_USR_EN bits in the main map
(Address 0x0E[6:5]) to 00.
Interrupt/VDP Sub Map
The interrupt/VDP sub map contains registers that can be used to
program internal interrupts, control the INTRQ pin, and decode
VBI data.
The interrupt/VDP sub map has the same I2C slave address as
the main map. To access the interrupt/VDP sub map, set the
SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01.
User Sub Map 2 has the same I2C slave address as the main map.
To access User Sub Map 2, set the SUB_USR_EN bits in the main
map (Address 0x0E[6:5]) to 10.
VPP Map
The video postprocessor (VPP) map contains registers that
control the I2P core (interlaced-to-progressive converter).
The VPP map has a programmable I2C slave address, which is
programmed using Register 0xFD in the user sub map of the
main map. The default value for the VPP map address is 0x00;
however, the VPP map cannot be accessed until the I2C slave
address is set. The recommended I2C slave address for the VPP
map is 0x84.
To set the I2C slave address of the VPP map, write to the
VPP_SLAVE_ADDRESS[7:1] bits of the user sub map (Address
0xFD[7:1]).
It is recommended to set the VPP_SLAVE_ADDRESS[7:1] bits
to a value of 0x84. This sets the VPP map I2C write address to
0x84 and the I2C read address to 0x85.
SUB_USR_EN Bits, Address 0x0E[6:5]
The ADV7283 main map contains three sub maps: the user sub
map, the interrupt/VDP sub map, and User Sub Map 2 (see
Figure 11). The user sub map is available by default. The other
two sub maps are accessed using the SUB_USR_EN bits. When
programming of the interrupt/VDP map or User Sub Map 2 is
completed, write to the SUB_USR_EN bits to return to the user
sub map.
Rev. A | Page 17 of 21
ADV7283
Data Sheet
Table 13. I 2 C Register Map and Sub Map Addresses
ALSB Pin
0
0
0
0
0
0
1
1
1
1
1
1
X1
X1
1
R/ W Bit
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
0 (write)
1 (read)
SUB_USR_EN Bits
(Address 0x0E[6:5])
00
00
01
01
10
10
00
00
01
01
10
10
XX1
XX1
Slave Address
0x40
0x41
0x40
0x41
0x40
0x41
0x42
0x43
0x42
0x43
0x42
0x43
0x84
0x85
Register Map or Sub Map
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
User sub map
User sub map
Interrupt/VDP sub map
Interrupt/VDP sub map
User Sub Map 2
User Sub Map 2
VPP map
VPP map
X and XX mean don’t care.
PCB LAYOUT RECOMMENDATIONS
The ADV7283 is a high precision, high speed, mixed-signal
device. To achieve maximum performance from the device, it is
important to use a well designed PCB. This section provides
guidelines for designing a PCB for use with the ADV7283.
Analog Interface Inputs
When routing the analog interface inputs on the PCB, keep
track lengths to a minimum. Use 75 Ω trace impedances when
possible; trace impedances other than 75 Ω increase the chance
of reflections.
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 100 nF and 10 nF capacitors. The basic principle is to place
a decoupling capacitor within approximately 0.5 cm of each
power pin. Avoid placing the decoupling capacitors on the
opposite side of the PCB from the ADV7283 because doing so
introduces inductive vias in the path.
Place the decoupling capacitors between the power plane and
the power pin. Current must flow from the power plane to the
capacitor and then to the power pin. Do not apply the power
connection between the capacitor and the power pin. The best
approach is to place a via close to or beneath the decoupling
capacitor pads down to the power plane (see Figure 12).
VIA TO SUPPLY
SUPPLY
VIA TO GND
NOTES
1. GND REFERS TO THE COMMON GROUND PLANE
OF THE PCB.
Figure 12. Recommended Power Supply Decoupling
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This disparity can
result in a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the
regulated analog supply voltage. To mitigate this problem,
regulate the analog supply, or at least the PVDD supply, from a
different, cleaner power source, for example, from a 12 V supply.
Using a single ground plane for the entire board is recommended.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and can result in long ground
loops. Therefore, using a single ground plane can improve noise
performance.
VREFN and VREFP Pins
Place the circuit associated with the VREFN and VREFP pins as
close as possible to the ADV7283 and on the same side of the
PCB as the device.
Digital Outputs
The ADV7283 digital outputs are INTRQ, LLC, and P0 to P7.
Minimize the trace length that the digital outputs must drive.
Longer traces have higher capacitance, requiring more current
and, in turn, causing more internal digital noise. Shorter traces
reduce the possibility of reflections.
100nF
12347-013
10nF
GROUND
It is especially important to maintain low noise and good
stability for the PVDD pin. Pay careful attention to regulation,
filtering, and decoupling. It is highly desirable to provide
separate regulated supplies for each circuit group (AVDD, DVDD,
DVDDIO, and PVDD).
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce current spikes inside the ADV7283. If
series resistors are used, place them as close as possible to the
Rev. A | Page 18 of 21
Data Sheet
ADV7283
pins of the ADV7283. However, do not add vias or extra length
to the output trace in an attempt to place the resistors closer.
If possible, limit the capacitance that each digital output must
drive to less than 15 pF. This recommendation can be easily
accommodated by keeping traces short and by connecting the
outputs to only one device. Loading the outputs with excessive
capacitance increases the current transients inside the
ADV7283, creating more digital noise on the power supplies.
Exposed Metal Pad
The ADV7283 has an exposed metal pad on the bottom of the
package. This pad must be soldered to ground. The exposed
pad is used for proper heat dissipation, noise suppression, and
mechanical strength.
Digital Inputs
The digital inputs of the ADV7283 are designed to work with
1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V
signals. Extra components are required if 5 V logic signals must
be applied to the decoder.
Rev. A | Page 19 of 21
ADV7283
Data Sheet
TYPICAL CIRCUIT CONNECTION
Figure 13 provides an example of how to connect ADV7283. For detailed schematics of the ADV7283 evaluation board, contact a local
Analog Devices field applications engineer or an Analog Devices distributor.
0.1µF
AIN1
DIFF1+
1.3kΩ
FULLY
150Ω
DIFFERENTIAL
CVBS INPUT
430Ω
430Ω
0.1µF
AIN2
DIFF1–
1.3kΩ
D VDD _1.8V
0.1µF
D VDDIO _3.3V
10nF
A VDD _1.8V
0.1µF
0.1µF
0.1µF
10nF
10nF
10nF
0.1µF
D VDD _1.8V
AIN4
1.3kΩ
0.1µF
10nF
16
21
13
2
0.1µF
3
A VDD _1.8V
A IN 2
17
A IN 1
18
A IN 2
0.1µF
AIN6
24kΩ
51Ω
22
A IN 3
23
A IN 4
A IN 5
A IN 6
ADV7283
A IN 4
24
A IN 5
25
A IN 6
19
LOCATE VREFP AND VREFN CAPACITOR AS
CLOSE AS POSSIBLE TO THE ADV7283 AND ON
THE SAME SIDE OF THE PCB AS THE ADV7283
A IN 3
P0 TO P7
P VDD
A IN 1
A VDD
51Ω
D VDD
AIN5
24kΩ
P0
P1
P2
P3
P4
P5
P6
P7
12
11
10
9
8
7
6
5
P0
P1
P2
P3
P4
P5
P6
P7
YCrCb
8-BIT
ITU-R BT.656 DATA
VREFP
0.1µF
20
VREFN
LLC
INTRQ
32
26
LLC
INTRQ
LOCATE CLOSE TO, AND ON THE
SAME SIDE OF THE PCB AS, THE ADV7283
14
47pF
XTALP
28.63636MHz
15
47pF
XTALN
D VDDIO
4kΩ
28
ALSB
2C
ALSB TIED HIGH: I
ADDRESS = 0x42
ALSB TIED LOW: I 2 C ADDRESS = 0x40
SCLK
SDATA
30
29
PWRDWN
RESET
SCLK
SDATA
Figure 13. Typical Connection Diagram
Rev. A | Page 20 of 21
12347-203
27
RESET
DGND
31
PWRDWN
4
SINGLEENDED
CVBS
INPUT
P VDD _1.8V
D VDDIO _3.3V
0.1µF
DGND
SINGLEENDED
CVBS
INPUT
430Ω
1
DIFF2–
430Ω
D VDD
1.3kΩ
PSEUDO
75Ω
DIFFERENTIAL
CVBS INPUT
AIN3
D VDDIO
DIFF2+
Data Sheet
ADV7283
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004570
0.50
0.40
0.30
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-26-2016-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 14. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7283BCPZ
ADV7283BCPZ-RL
ADV7283WBCPZ
ADV7283WBCPZ-RL
EVAL-ADV7283EBZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package
32-Lead Lead Frame Chip Scale Package
32-Lead Lead Frame Chip Scale Package
32-Lead Lead Frame Chip Scale Package
Evaluation Board for the ADV7283
[LFCSP_WQ]
[LFCSP_WQ]
[LFCSP_WQ]
[LFCSP_WQ]
Package Option
CP-32-12
CP-32-12
CP-32-12
CP-32-12
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADV7283W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should
review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive
applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific
Automotive Reliability reports for this model.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors) .
©2014–2016 Analog Devices, Inc. Al l rights reserved. Trademar ks and
registered trademarks are the property of their respective owners.
D12347-0-10/16(A)
Rev. A | Page 21 of 21
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