AND8020

AND8020/D Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure http://onsemi.com Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering APPLICATION NOTE CONTENTS OF APPLICATION NOTE Introduction − DC Termination Analysis Section 1. Unterminated Lines Section 3. Thevenin Equivalent/Parallel Termination R RE VEE R R R Section 2. Parallel Termination − External and Internal External Section 4. Series (Back) Termination R Rt Rt RE VEE Near (Standard Pair) Internal Driver * * RE RE VEE V Rt Rt Vt VTT Rt Rt *All Media D1 VBB D2 Far (Standard Pair) RE VTT Rt RE R RE Section 5. Diode Termination VBB D1 D2 Receiver to (Open) Section 6. Capacitive Coupling R RE VEE RE Vt1 Vt2 Rt Rt Vt1 Vt2 VTT Rt Rt R VBB R R R (Shorted) Near (Standard Pair) Far (Standard Pair) VCC © Semiconductor Components Industries, LLC, 2004 1 July, 2004 − Rev. 5 Publication Order Number: AND8020/D AND8020/D INTRODUCTION Static DC Termination Analysis A standard Emitter Coupled Logic (ECL) output driver typically uses a current switching differential with an emitter follower for level shifting the output and the internal CML levels to familiar ECL levels. This output driver architecture presents about 6−8 W internal impedance in both LOW and VCC 8 W Internal Output Impedance HIGH states when properly current biased. This results in a typical VPP signal of 800 mVPP (measured single−endedly on each line) swinging around a DC voltage point of VCC − 1.3 V when properly terminated and operating correctly as shown in Figure 1. VCC Q D Q RE VEE VEE Driver RE D VEE Receiver Figure 1. Typical ECL Output with Emitter Follower Output Structure, Typical Termination, and Typical ECL Input Interconnect For proper static and dynamic operation, the output emitter follower transistor must remain in the active region of operation which requires an external resistive path be provided from the output pin to a voltage more negative than worst case VOL, such as VEE. The resistor, RE, is considered a current bias for the Emitter Follower output structure. When properly terminated and current biased (loaded), the outputs will generate both: (1) static state voltage levels VOL (LOW) or VOH (HIGH) and (2) a dynamic transition edge (tr or tf) between state levels. Static State Voltage Levels Figure 2 illustrates the typical relationship of static signal levels and dynamic transition edges between an Output Driver Signal and a Receiver Input Signal. Both outputs of a differential driver should always be terminated and loaded as identically as possible to preserve minimum skew and jitter operation of the device. Output Driver Signal VCC VOH VIH Input Receiver Signal VCC −1.3 V VOL VEE tr VCC VOH VIH VCC −1.3 V VOL VEE tf tr VIL tf VIL Figure 2. State Levels VOH, VOL, and Dynamic Transitions at Q or Q and D or D http://onsemi.com 2 AND8020/D Output Open, Short, and Safe DC Current Left open, an output will only swing a few millivolts due to parasitic “minimum current” leakage paths. Shorted to VEE, a maximum current will develop, limited only by the output transistor 8 W impedance, and may cause damage to the output. Worst case short circuit current risks destruction of the devices. ISC + VOH + 4 V 8W RINT (eq. 1) = 500 mA! Where: VOH = 4.0 V VCC = 5.0 V VEE = 0.0 V Rint = 8 W The continuous safe output current, Iout (continuous), maximum limit is 50 mA under all spec operating conditions. The continuous safe repetitive surge, Iout (surge), maximum current limit is 100 mA for 10 milliseconds per second duty cycle, provided the device’s total thermal limits are observed. Output current polarity will always be sinking into the termination scheme during proper operation. Static Analysis of Termination Resistor RE The output continuous safe current limit, Iout (cont), determines RE minimum DC termination scheme resistance to VEE although this will not provide a practical AC signal termination as shown in Table A: Minimum RE Values. RE + VOH I max (eq. 2) Dynamic Analysis of Termination Resistor RE The dynamic function of the termination resistor, RE is to develop the voltage change, DV, during a high−to−low or low−to−high transition and present this to the transmission medium such as coax, twisted pair, microstrip or stripline. The DV signal propagates to the receiver and is either reflected, dissipated, or a combination. Since the reflection coefficient at the load is of opposite polarity to that of the source, a reflection will travel back and forth over the transmission changing polarity after each reflection until critically damped by line impedance. Thus, steps may appear in the signal DV at the receiving gate input due to impedance mismatch and consequent partial reflections. When RE is too large, steps appear in the trailing edge of the propagating signal, DV, at the input to the receiving gate, slowing the edge speed and increasing the net propagation delay. A reasonable negative−going signal swing at the input of the receiving gate results when the value of RE is selected to produce an initial step of 75% of the expected DV, or a 600 mV step for an 800 mV signal at the driving gate. For a RSECL expected DV swing of 400, a 300 mV initial step is desired. Hence for a 600 mV initial step: I(init) * Z0 u 0.6 ( VOH * VEE ) * Z0 y 0.6 ( Rt ) Z0 ) (eq. 3) Table A. Minimum RE Values Line PECL LVPECL LVEP PECL VOH 4.0 V 2.4 V 1.6 V RE(min) 80 W 48 W 32 W The value for RE is found in Table B: Recommended Values of RE in Dynamic Functional Application. This table lists recommended RE values for the various ECL devices by Family Series according to the equation above. The table assumes operation with various data sheet VOH values and various VCC values driving a Z0 = 50 W line. Lowering the value of RE will increase the voltage change, DV, launched into the transmission media. Raising the value of RE will decrease the voltage change, DV, launched into the transmission media. Table B. Recommended Nominal Values of RE in Dynamic Functional Application Series NB NB 10/100LVEP 10/100EP, 100LVEL 10/100EL, 10/100E |VCC−VEE| 2.5 3.3 2.5 3.3 5.0 RE (W) 140 250 50 120 235 A DC terminating resistor minimum, RE (min), of 80 W, while sufficiently limiting the output load current to VEE, may generate insufficient PECL output LOW and HIGH state transitions. The RE maximum is effectively determined by the application load capacitance, CL, since an RC network is formed by RE and CL which limits the signal fall time, discharging the line to the LOW state voltage level. A sufficiently high value RE or CL can cause the signal fall time to the VOL level to violate specification limits. Designed RE or CL values may selectively eliminate undesirable noise. http://onsemi.com 3 AND8020/D SECTION 1. UNTERMINATED LINES Interconnect Line Lengths The output signal Waveform rise (tr) and fall (tf) time are measured from the 20% and 80% levels of the static signal levels. This edge rate represents the waveforms highest harmonic and determines the maximum unterminated open line trace length, Lmax, permissible without sustaining signal reflections. The impetus in restricting interconnect lengths, L, is to mitigate the effects of overshoot and undershoot. A handy rule of thumb is that the undershoot can be limited to less than 15% of the logic swing if the two way line delay is less than the rise time of the pulse. With an undershoot of