ASDP-21365BBCZ-1AA

a SUMMARY SHARC® Processor ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 The ADSP-2136x processors are available with a 333 MHz core instruction rate and unique peripherals such as the digital audio interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 52. High performance, 32-bit/40-bit, floating-point processor optimized for high performance processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bit of on-chip SRAM Code compatible with all other members of the SHARC family CORE PROCESSOR TIMER INSTRUCTION CACHE 32-BIT 48-BIT 4 BLOCKS OF ON-CHIP MEMORY BLOCK 0 SRAM 1M BIT BLOCK 1 SRAM 1M BIT BLOCK 2 SRAM 0.5M BIT BLOCK 3 SRAM 0.5M BIT ROM 2M BIT ROM 2M BIT DAG1 8 4 32 DAG2 8 4 32 PROGRAM SEQUENCER ADDR DATA ADDR DATA ADDR DATA ADDR DATA PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS 32 32 64 DM DATA BUS 64 IOA IOD IOA IOD IOA IOD IOA IOD PX REGISTER PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY) IOP REGISTERS (MEMORY MAPPED) 6 JTAG TEST AND EMULATION SPI SPORTS IDP PCG TIMERS SRC SPDIF DTCP SIGNAL ROUTING UNIT S Figure 1. Functional Block Diagram—Processor Core I/O PROCESSOR AND PERIPHERALS SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel : 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 KEY FEATURES—PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x performs 2 GFLOPS/666 MMACs 3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit in blocks 2 and 3) for simultaneous access by the core processor and DMA 4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1) Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single-instruction multiple-data (SIMD) architecture provides: Two computational processing elements Concurrent execution Code compatibility with other SHARC family members at the assembly level Parallelism in buses and computational units allows single cycle execution (with or without SIMD) of a multiply operation, an ALU operation, a dual memory read or write, and an instruction fetch Transfers between memory and core at a sustained 5.4G bytes/s bandwidth at 333 MHz core instruction rate Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the processor core, configurable as eight channels of serial data or seven channels of serial data, and up to a 20-bit wide parallel data channel Signal routing unit provides configurable and flexible connections between all DAI components–six serial ports, one SPI port, eight channels of asynchronous sample rate converters, an S/PDIF receiver/transmitter, three timers, an SPI port,10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px) Two serial peripheral interfaces (SPI): primary on dedicated pins, secondary on DAI pins provide: Master or slave serial boot through primary SPI Full-duplex operation Master slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 muxed flag/IRQ lines 1 muxed flag/timer expired line DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter supports: EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards Left-justified, I2S, or right-justified serial data input with 16-, 18-, 20- or 24-bit word widths (transmitter) Two channel mode and single channel double frequency (SCDF) mode Sample rate converter (SRC) contains a serial input port, de-emphasis filter, sample rate converter (SRC) and serial output port providing up to –140 dB SNR performance (see Table 2 on Page 4) Supports left-justified, I2S, TDM, and right-justified 24-, 20-, 18-, and 16-bit serial formats (input) Pulse-width modulation provides: 16 PWM outputs configured as four groups of four outputs Supports center-aligned or edge-aligned PWM waveforms Can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA package (see Ordering Guide on Page 52) INPUT/OUTPUT FEATURES DMA controller supports: 25 DMA channels for transfers between ADSP-2136x internal memory and a variety of peripherals 32-bit DMA transfers at peripheral clock speed, in parallel with full-speed processor execution Asynchronous parallel port provides access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 55M byte per sec transfer rate External memory access in a dedicated DMA channel 8-bit to 32-bit and 16-bit to 32-bit packing options Programmable data cycle duration: 2 CCLK to 31 CCLK Digital audio interface (DAI) includes six serial ports, two precision clock generators, an input data port, three timers, an S/PDIF transceiver, a DTCP cipher, an 8-channel asynchronous sample rate converter, an SPI port, and a signal routing unit Six dual data line serial ports that operate at up to 41.67M bits/s on each data line—each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S-compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Rev. A | Page 2 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ................................................................1 Key Features—Processor Core ..................................2 Input/Output Features ............................................2 Dedicated Audio Components ..................................2 General Description ..................................................4 SHARC Family Core Architecture .............................5 Memory and I/O Interface Features ............................6 Development Tools .............................................. 10 Additional Information ......................................... 11 Pin Function Descriptions ........................................ 12 Address Data Pins as FLAGs .................................. 15 Address/Data Modes ............................................ 15 Boot Modes ........................................................ 15 Core Instruction Rate to CLKIN Ratio Modes ............. 15 ADSP-2136x Specifications ....................................... 16 Operating Conditions ........................................... 16 Electrical Characteristics ........................................ 16 Package Information ............................................ 17 Maximum Power Dissipation ................................. 17 Absolute Maximum Ratings ................................... 17 ESD Sensitivity .................................................... 17 Timing Specifications ........................................... 18 Output Drive Currents .......................................... 46 Test Conditions ................................................... 46 Capacitive Loading ............................................... 46 Thermal Characteristics ........................................ 47 136-Ball BGA Pin Configurations ............................... 48 Outline Dimensions ................................................ 51 Surface Mount Design .......................................... 51 Ordering Guide ...................................................... 52 REVISION HISTORY 12/06—Rev 0 to Rev A This version of the data sheet combines the ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366 data sheets. Throughout this document, these products are referred to as “ADSP-2136x” except where features or specifications apply to a specific processor. For a comparison of each processor, see Table 2 on Page 4. Added Package Information ......................................17 Fixed Figure 6, Core Clock and System Clock Relationship to CLKIN .................................................................18 Fixed Figure 24, IDP Master Timing ............................34 This version of the data sheet is for BGA parts only. An alternate LQFP package (exposed pad) will be available in the future. Information on that option is available on the ADSP-21365 product page. See Ordering Guide ...............................52 Rev. A | Page 3 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 GENERAL DESCRIPTION The ADSP-2136x SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x is a 32-bit/40-bit floating-point processor optimized for high performance automotive audio applications with a large onchip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. Fabricated in a stateof-the-art, high speed, CMOS process, the ADSP-2136x processor achieves an instruction cycle time of 3.0 ns at 333 MHz. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. Table 2 shows the features of the individual product offerings and Table 1 shows performance benchmarks for the processors running at 333 MHz. Table 1. Benchmarks (at 333 MHz) Speed Benchmark Algorithm (at 333 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs FIR Filter (per tap)1 1.5 ns 6.0 ns IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3×3] × [3×1] 13.5 ns [4×4] × [4×1] 23.9 ns Divide (y/x) 10.5 ns Inverse Square Root 16.3 ns 1 • On-chip ROM (4M bit) • 8-bit or 16-bit parallel port that supports interfaces to offchip memory peripherals • JTAG test access port Table 2. ADSP-2136x SHARC Processor Family Features ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 3M bit 4M bit Yes Yes Yes No 128 dB Feature RAM ROM Audio Decoders in ROM1 Pulse Width Modulation S/PDIF DTCP2 SRC Performance 1 3M bit 4M bit No 3M bit 4M bit No 3M bit 4M bit No 3M bit 4M bit Yes Yes Yes Yes 128 dB Yes No No No SRC Yes Yes No 140 dB Yes Yes Yes 128 dB Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like Bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. Assumes two files in multichannel SIMD mode The block diagram on Page 7 illustrates the following architectural features: • DMA controller • Six full duplex serial ports • Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins • Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, eight channels asynchronous sample rate converter, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Figure 2 shows a sample SPORT configuration using the precision clock generators to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible. The ADSP-2136x continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram on Page 1, illustrates the following architectural features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • Three programmable interval timers with PWM generation, PWM capture/pulse width measurement, and external event counter capabilities • On-chip SRAM (3M bit) Rev. A | Page 4 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADSP-2136x CLK OU T C LOC K 2 2 3 C LK IN X TA L C LK _C FG1-0 B OOTC FG1 -0 FLA G3-1 RD WR FLA G0 A DC (OPTI ONA L) C LK FS S D AT A LE AD 1 5-0 LA TCH A DD R D ATA OE WE CS PA R A LLEL POR T RAM I /O D EVI CE CONTROL D A I_P1 DA I_ P2 DA I_ P3 SR U D A I_P 18 D AI _P 19 DA I_ P2 0 S C LK 0 S FS0 S D 0A S D 0B SP OR T0-5 TIME R S SPD IF SR C ID P S PI D AC (OPTI ONA L) C LK FS S D AT C LK FS DAI R ES ET PC GA P CG B JTA G 6 Figure 2. ADSP-2136x System Sample Configuration SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as detailed in the following sections. bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. SIMD Computational Engine The ADSP-2136x contains two computational processing elements that operate as a single-instruction multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the Rev. A | Page 5 of 52 | Data Register File A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2136x enhanced December 2006 ADDRESS DATA ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Single-Cycle Fetch of Instruction and Four Operands The ADSP-2136x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With the processor’s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-2136x can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Instruction Cache The ADSP-2136x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. MEMORY AND I/O INTERFACE FEATURES The ADSP-2136x adds the following architectural features to the SIMD SHARC family core. On-Chip Memory The ADSP-2136x contains three megabits of internal SRAM and four megabits of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-2136x’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital Table 3. ADSP-2136x Internal Memory Space IOP Registers 0x0000 0000–0003 FFFF Long Word (64 Bits) BLOCK 0 ROM 0x0004 0000–0x0004 7FFF Reserved 0x0004 8000–0x0004 BFFF BLOCK 0 SRAM 0x0004 C000–0x0004 FFFF BLOCK 1 ROM 0x0005 0000–0x0005 7FFF Reserved 0x0005 8000–0x0005 BFFF BLOCK 1 SRAM 0x0005 C000–0x0005 FFFF BLOCK 2 SRAM 0x0006 0000–0x0006 1FFF Reserved 0x0006 2000–0x0006 FFFF BLOCK 3 SRAM 0x0007 0000–0x0007 1FFF BLOCK 3 SRAM 0x000E 0000–0x000E 2AA9 BLOCK 1 SRAM 0x000B 0000–0x000B 5554 BLOCK 2 SRAM 0x000C 0000–0x000C 2AA9 BLOCK 0 SRAM 0x0009 0000–0x0009 5554 BLOCK 1 ROM 0x000A 0000–0x000A AAA9 Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) BLOCK 0 ROM 0x0008 0000–0x0008 AAA9 BLOCK 0 ROM 0x0008 0000–0x0008 FFFF Reserved 0x0009 0000–0x0009 7FFF BLOCK 0 SRAM 0x0009 8000–0x0009 FFFF BLOCK 1 ROM 0x000A 0000–0x000A FFFF Reserved 0x000B 0000–0x000B 7FFF BLOCK 1 SRAM 0x000B 8000–0x000B FFFF BLOCK 2 SRAM 0x000C 0000–0x000C 3FFF Reserved 0x000C 4000–0x000D FFFF BLOCK 3 SRAM 0x000E 0000–0x000E 3FFF Short Word (16 Bits) BLOCK 0 ROM 0x0010 0000–0x0011 FFFF Reserved 0x0012 0000–0x0012 FFFF BLOCK 0 SRAM 0x0013 0000–0x0013 FFFF BLOCK 1 ROM 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 FFFF BLOCK 1 SRAM 0x0017 0000–0x0017 FFFF BLOCK 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x0018 8000–0x001B FFFF BLOCK 3 SRAM 0x001C 0000–0x001C 7FFF Rev. A | Page 6 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 3. ADSP-2136x Internal Memory Space (Continued) IOP Registers 0x0000 0000–0003 FFFF Long Word (64 Bits) Reserved 0x0007 2000–0x0007 FFFF Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Reserved 0x000E 4000–0x000F FFFF Short Word (16 Bits) Reserved 0x001C 8000–0x001F FFFF Reserved 0x0020 0000–0xFFFF FFFF The SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. DAI- associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. TO PROCESSOR BUSES AND SYSTEM MEMORY IO DATA BUS (32) IO ADDRESS BUS (18) GPIO FLAGS/IRQ/TIMEXP 4 DMA CONTROLLER 25 CHANNELS CONTROL/GPIO ADDRESS/DATA BUS/ GPIO 3 16 PARALLEL PORT PWM (16) 4 SPI PORT (1) CONTROL, STATUS, AND DATA BUFFERS DMA Controller The ADSP-2136x’s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port. Twenty-five channels of DMA are available on the processors—two for the SPI interface, 12 via the serial ports, eight via the input data port, two for DTCP (or memoryto-memory data transfer when DTCP is not used), and one via the processor’s parallel port. Programs can be downloaded to the processors using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. 4 SPI PORT (1) IOP REGISTERS (MEMORY MAPPED) SERIAL PORTS (6) INPUT DATA PORTS (8) DTCP CIPHER SIGNAL ROUTING UNIT 20 SPDIF (Rx/Tx) SRC (8 CHANNELS) PRECISION CLOCK GENERATORS (2) 3 TIMERS (3) Digital Audio Interface (DAI) The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU, shown in Figure 3). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DIGITAL AUDIO INTERFACE I/O PROCESSOR Figure 3. ADSP-2136x I/O Processor and Peripherals Block Diagram The DAI also includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and December 2006 Rev. A | Page 7 of 52 | ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 three timers. The IDP provides an additional input path to the ADSP-2136x core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. For complete information on using the DAI, see the ADSP-2136x SHARC Processor Hardware Reference. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8-bit or 16-bit, the maximum data transfer rate is 55M bytes/sec. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. Serial Ports The ADSP-2136x features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and a frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTS are enabled, or six full duplex TDM streams of 128 channels per frame. The serial ports operate at a maximum data rate of 41.67 M bits/s. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface commonly used by audio codecs, ADCs, and DACs, such as the Analog Devices AD183x family), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional μ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the ADSP-2136x SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPIcompatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 140 dB SNR (see Table 2 on Page 4 for details). The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The S/PDIF and SRC are not available on the ADSP-21363 models. Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance Rev. A | Page 8 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) will be protected by this copy protection system. This feature is available on the ADSP-21362 and ADSP-21365 processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or test access port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. Program Booting The internal memory of the ADSP-2136x boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOTCFG1–0) pins (see Table 7 on Page 15). Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Pulse-Width Modulation The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Phase-Locked Loop The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power up, the CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1 (see Table 8 on Page 15). After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. Power Supplies The ADSP-2136x has a separate power supply connection for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement for K, B, and Y grade models, and the 1.0 V requirement for Y and W Grade models. (For information on the temperature ranges offered for this product, see Operating Conditions on Page 16, Package Information on Page 17, and Ordering Guide on Page 52. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 4. (A recommended ferrite chip is the muRata BLM18AG102SN1D). To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 4 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Timers The ADSP-2136x has a total of four timers: a core timer that can generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. ROM-Based Security The ADSP-2136x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the processor does not boot-load any external code, executing exclusively from internal SRAM/ROM. Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices’ DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection Rev. A | Page 9 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 100nF VDDINT 10nF 1nF ADSP-213xx AVDD Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C/C++ and assembly code (interleaved source and object information) • Insert breakpoints • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. VisualDSP++ component software engineering (VCSE) is Analog Devices’ technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. It allows downloading components from the Web, dropping them into the application, and publishing component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a HI Z FERRITE BEAD CHIP AVSS LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS Figure 4. Analog Power (AVDD) Filter Circuit and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User’s Guide.” DEVELOPMENT TOOLS The ADSP-2136x is supported with a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and VisualDSP++®‡ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2136x. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. † ‡ CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. A | Page 10 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 drag of the mouse and examine runtime stack and heap usage. The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices’ JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2136x architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)— use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. Evaluation Kit Analog Devices offers a range of EZ-KIT Lite®† evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite platform includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. † EZ-KIT Lite is a registered trademark of Analog Devices, Inc. Rev. A | Page 11 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PIN FUNCTION DESCRIPTIONS The ADSP-2136x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: • DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and AD15–0 (NOTE: These pins have pull-up resistors.) The following symbols appear in the Type column of Table 4: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Table 4. Pin Descriptions Pin AD15–0 Type I/O/T (pu) State During and After Reset Three-state with pull-up enabled Description Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address/Data Modes on Page 15 for details of the AD pin operation. For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23–8; ALE is used in conjunction with an external latch to retain the values of the A23–8. For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x SHARC Processor Hardware Reference. Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16-bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. RD has a 22.5 kΩ internal pull-up resistor. Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted. WR has a 22.5 kΩ internal pull-up resistor. Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor. Flag Pins. Each flag pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x SHARC Processor Hardware Reference. Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. RD O (pu) O (pu) O (pd) Three-state, driven high1 Three-state, driven high1 Three-state, driven low1 WR ALE FLAG3–0 I/O/A Three-state DAI_P20–1 I/O/T (pu) Three-state with programmable pull-up Rev. A | Page 12 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 4. Pin Descriptions (Continued) Pin SPICLK Type I/O (pu) State During and After Reset Three-state with pull-up enabled Description Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. Serial Peripheral Interface Slave Device Select. An active low signal used to select the processor as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the processor’s SPIDS signal can be driven by a slave device to signal to the processor (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For processor to processor SPI interaction, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device. SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pull-up resistor. SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by setting (=1) Bit 5 (DMISO) of the SPICTL register. Boot Configuration Select. This pin is used to select the boot mode for the processor. The BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the boot modes. Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It configures the ADSP-2136x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. SPIDS I Input only MOSI I/O (O/D) (pu) Three-state with pull-up enabled MISO I/O (O/D) (pu) Three-state with pull-up enabled BOOTCFG1–0 I Input only CLKIN I Input only XTAL CLKCFG1–0 O I Output only2 Input only Rev. A | Page 13 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 4. Pin Descriptions (Continued) Pin Type RSTOUT/CLKOUT O State During and After Reset Output only Description Local Clock Out/Reset Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin. The functionality can be switched between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register. The default is reset out. Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the processors. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 kΩ internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU has a 22.5 kΩ internal pull-up resistor. Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the Y and W grade models, and supplies the processor’s core (13 pins). I/O Power Supply. Nominally +3.3 V dc (6 pins). Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the Y and W Grade models, and supplies the processor’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page 9. Analog Power Supply Return. Power Supply Return. (54 pins) RESET I/A Input only TCK TMS TDI TDO TRST I I/S (pu) I/S (pu) O I/A (pu) O (O/D) (pu) P P P Input only3 Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled Three-state with pull-up enabled EMU VDDINT VDDEXT AVDD AVSS GND 1 2 G G RD, WR, and ALE are three-stated (and not driven) only when RESET is active. Output only is a three-state driver with its output path always enabled. 3 Input only is a three-state driver with both output path and pull-up disabled. 4 Three-state is a three-state driver with pull-up disabled. Rev. A | Page 14 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the SYSCTL register to disable the parallel port. Then set (=1) Bits 22 to 25 in the SYSCTL register accordingly. Table 5. AD15–0 to Flag Pin Mapping AD Pin AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Flag Pin FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 AD Pin AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Flag Pin FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 BOOT MODES Table 7. Boot Mode Selection BOOTCFG1–0 00 01 10 Booting Mode SPI Slave Boot SPI Master Boot Parallel Port Boot via EPROM CORE INSTRUCTION RATE TO CLKIN RATIO MODES For details on processor timing, see Timing Specifications and Figure 6 on Page 18. Table 8. Core Instruction Rate/CLKIN Ratio Selection CLKCFG1–0 00 01 10 Core to CLKIN Ratio 6:1 32:1 16:1 ADDRESS/DATA MODES The following table shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches Address Bits A23–A8 when asserted, followed by Address Bits A7–A0 and Data Bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches Address Bits A15–A0 when asserted, followed by Data Bits D15–D0 when deasserted. Table 6. Address/Data Mode Selection PP Data Mode 8-bit 8-bit 16-bit 16-bit ALE Asserted Deasserted Asserted Deasserted AD7–AD0 Function A15–A8 D7–D0 A7–A0 D7–D0 AD15–AD8 Function A23–A16 A7–A0 A15–A8 D15–D8 Rev. A | Page 15 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADSP-2136x SPECIFICATIONS OPERATING CONDITIONS K Grade Parameter1 VDDINT AVDD VDDEXT VIH 2 B Grade Min 1.14 1.14 3.13 2.0 –0.5 1.74 –0.5 –40 Max 1.26 1.26 3.47 VDDEXT + 0.5 +0.8 VDDEXT + 0.5 +1.19 +85 Unit V V V V V V V °C Description Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min High Level Input Voltage @ VDDEXT = max Low Level Input Voltage @ VDDEXT = min Ambient Operating Temperature Min 1.14 1.14 3.13 2.0 –0.5 1.74 –0.5 0 Max 1.26 1.26 3.47 VDDEXT + 0.5 +0.8 VDDEXT + 0.5 +1.19 +70 VIL2 VIH_CLKIN3 VIL_CLKIN TAMB 1 2 4, 5 Specifications subject to change without notice. Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST. 3 Applies to input pin CLKIN. 4 See Thermal Characteristics on Page 47 for information on thermal specifications. 5 See Engineer-to-Engineer Note (No. EE-277) for further information. ELECTRICAL CHARACTERISTICS Parameter1 VOH2 VOL IIH 2 Description High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Test Conditions @ VDDEXT = min, IOH = –1.0 mA3 @ VDDEXT = min, IOL = 1.0 mA 3 Min 2.4 Max Unit V 0.4 10 10 200 10 10 200 800 10 4.7 V μA μA μA μA μA μA mA mA pF 4, 5 @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT= max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V tCCLK = min, VDDINT = nom AVDD = max fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V IIL4 IILPU IOZH IOZL 5 6, 7 Low Level Input Current Pull-Up Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Pull-Up 8, 9 6 IOZLPU7 IDD-INTYP AIDD CIN 1 2 Supply Current (Internal) Supply Current (Analog) Input Capacitance 10 11, 12 Specifications subject to change without notice. Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. 3 See Output Drive Currents on Page 46 for typical drive current capabilities. 4 Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. 5 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI. 6 Applies to three-stateable pins: FLAG3–0. 7 Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI. 8 Typical internal current data reflects nominal operating conditions. 9 See Engineer-to-Engineer Note (No. EE-277) for further information. 10 Characterized, but not tested. 11 Applies to all signal pins. 12 Guaranteed, but not tested. Rev. A | Page 16 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION The information presented in Figure 5 provides details about the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Ordering Guide on Page 52. MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note (EE-277) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 47. ABSOLUTE MAXIMUM RATINGS a ADSP-2136x tppZ-cc vvvvvv.x n.n yyww country_of_origin Stresses greater than those listed below may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (AVDD) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature Under Bias Rating –0.3 V to +1.5 V –0.3 V to +1.5 V –0.3 V to +4.6 V –0.5 V to +3.8 V –0.5 V to VDDEXT + 0.5 V 200 pF –65°C to +150°C 125°C S Figure 5. Typical Package Brand Table 9. Package Brand Information Brand Key t pp Z cc vvvvvv.x n.n yyww Field Description Temperature Range Package Type Lead Free Option See Ordering Guide Assembly Lot Code Silicon Revision Date Code ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2136x features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 17 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TIMING SPECIFICATIONS The ADSP-2136x’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1–0 pins (see Table 8 on Page 15). To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The ADSP-2136x’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock (the clock source for the parallel port logic and I/O pads). Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 10 and Table 11. Table 10. ADSP-2136x Clock Generation Operation Timing Requirements CLKIN CCLK Description Input Clock Core Clock Calculation 1/tCK 1/tCCLK Table 11. Clock Periods Timing Requirements tCK tCCLK tPCLK tSCLK tSPICLK 1 Description1 CLKIN Clock Period (Processor) Core Clock Period (Peripheral) Clock Period = 2 × tCCLK Serial Port Clock Period = (tPCLK) × SR SPI Clock Period = (tPCLK) × SPIR where: SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT CLKDIV) SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD register) DAI_Px = serial port clock SPICLK = SPI clock Figure 6 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP-2136x SHARC Processor Programming Reference. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 39 on Page 46 under Test Conditions for voltage reference levels. CLKIN XTAL XTAL OSC INDIV ÷1, 2 PLLM PLLICLK DIVEN ÷2, 4, 8, 16 CCLK (CORE CLOCK) ÷2 PCLK (PERIPHERAL CLOCK) CLK_CFG [1:0] (6:1, 16:1, 32:1) RESET DELAY CLKOUT OR RESETOUT Figure 6. Core Clock and System Clock Relationship to CLKIN Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Rev. A | Page 18 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing The timing requirements for processor startup are given in Table 12. Table 12. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD1 tCLKRST tPLLRST Min RESET Low Before VDDINT/VDDEXT On VDDINT On Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid CLKIN Valid Before RESET Deasserted PLL Control Setup Before RESET Deasserted 0 –50 0 102 20 Max Unit ns ms ms μs μs +200 +200 Switching Characteristic Core Reset Deasserted After RESET Deasserted tCORERST 1 4096tCK + 2 tCCLK 3, 4 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 4 The 4096 cycle count depends on tSRST specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum. RESET tRSTVDD VDDINT tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1-0 tPLLRST RSTOUT tCORERST Figure 7. Power-Up Sequencing Rev. A | Page 19 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Clock Input Table 13. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK2 CCLK Period CLKIN Jitter Tolerance tCKJ3,4 1 2 Min 181 7.51 7.51 3.01 –250 333 MHz Max 100 Unit ns ns ns ns ns ps 3 10 +250 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL. Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 3 Actual input jitter should be combined with ac specifications for accurate timing analysis. 4 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. tC K C LK IN tC K H tC K L tC K J Figure 8. Clock Input Clock Signals The ADSP-2136x can use an external clock or a crystal. See the CLKIN pin description in Table 4 on Page 12. The user application program can configure theADSP-2136x to use its internal clock generator by connecting the necessary components to the CLKIN and XTAL pins. Figure 9 shows the component connections used for a fundamental frequency crystal operating in parallel mode. Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266.72 MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. ADSP-2136X CLKIN R1 1M * XTAL R2 47 * C1 22pF Y1 24.576MHz C2 22pF R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS *TYPICAL VALUES Figure 9. 333 MHz Operation (Fundamental Mode Crystal) Rev. A | Page 20 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 14. Reset Parameter Timing Requirements tWRST1 RESET Pulse Width Low tSRST RESET Setup Before CLKIN Low 1 Min 4tCK 8 Max Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST RESET tSRST Figure 10. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 15. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width Min 2 × tPCLK + 2 Max Unit ns DAI20-1 FLAG2-0 (IRQ2-0) tIPW Figure 11. Interrupts Rev. A | Page 21 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 16. Core Timer Parameter Switching Characteristic tWCTIM CTIMER Pulse Width Min 2 × tPCLK – 1 Max Unit ns FLAG3 (CTIMER) tWCTIM Figure 12. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 17. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min 2 tPCLK – 1 Max 2(231 – 1) tPCLK Unit ns tPWM O DAI_P20 -1 (TIMER2-0) Figure 13. Timer PWM_OUT Timing Rev. A | Page 22 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. Table 18. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min 2 tPCLK Max 2(231– 1) tPCLK Unit ns tPWI DAI_P20-1 (TIMER2-0) Figure 14. Timer Width Capture Timing DAI Pin to Pin Direct Routing For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 19. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min 1.5 Max 10 Unit ns DAI_Pn DAI_Pm tDPIO Figure 15. DAI Pin to Pin Direct Routing Rev. A | Page 23 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 20. Precision Clock Generator (Direct Pin Routing) Parameter Min Max Unit Timing Requirements tPCGIP Input Clock Period 20 ns tSTRIG PCG Trigger Setup Before Falling 4.5 ns Edge of PCG Input Clock tHTRIG PCG Trigger Hold After Falling 3 ns Edge of PCG Input Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2.5 10 ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) × tPCGIP) 10 + ((2.5 + D) × tPCGIP) ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) ns tPCGOP Output Clock Period 2 × tPCGIP1 ns D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). In normal mode, tPCGOP (min) = 2 × tPCGIP. tSTRIG DAI_Pn PCG_TRIGx_I tHTRIG tPCGIP DAI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO tPCGOP DAI_Pz PCG_FSx_O tDTRIGFS Figure 16. Precision Clock Generator (Direct Pin Routing) Rev. A | Page 24 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 4, “Pin Descriptions,” on Page 12 for more information on flag use. Table 21. Flags Parameter Timing Requirement tFIPW FLAG3–0 IN Pulse Width Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width Min 2 × tPCLK + 3 Max Unit ns 2 × tPCLK – 1 ns DAI_P20-1 (FLAG3-0IN) (DATA31-0) tFIPW DAI_P20-1 (FLAG3-0OUT) (DATA31-0) tFOPW Figure 17. Flags Rev. A | Page 25 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2136x is accessing external memory space. Table 22. 8-Bit Memory Read Cycle Parameter Timing Requirements AD7–0 Data Setup Before RD High tDRS1 tDRH AD7–0 Data Hold After RD High tDAD1 AD15–8 Address to AD7–0 Data Valid Min 3.3 0 D + tPCLK – 5.0 Max Unit ns ns ns Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS2 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tRRH Delay Between RD Rising Edge to Next H + tPCLK – 1.4 Falling Edge tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 tRWALE Read Deasserted to ALE Asserted F + H + 0.5 tADAH2 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 ALE Deasserted to AD7–0 Address in High Z tPCLK tALEHZ2 tRW RD Pulse Width D – 2.0 tRDDRV AD7–0 ALE Address Drive After Read High F + H + tPCLK – 2.3 tADRH AD15–8 Address Hold After RD High H tDAWH AD15–8 Address to RD High D + tPCLK – 4.0 D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) tPCLK = (peripheral) clock period = 2 × tCCLK 1 2 ns ns ns ns ns ns ns ns ns ns ns tPCLK + 3.0 The timing specified here is sufficient to satisfy either tDAD or tDRS as they are independent. On reset, ALE is an active high cycle. However, it can be configured by software to be active low. Rev. A | Page 26 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 tRWALE ALE tALEW tALERW tRRH RD tRW tRDDRV WR tDAWH tADAS tADAH VALID ADDRESS tADRH VALID ADDRESS VALID ADDRESS AD15-8 VALID ADDRESS tDAD VALID ADDRESS VALID DATA tDRS tDRH VALID ADDRESS AD7-0 VALID DATA tALEHZ NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION. Figure 18. Read Cycle for 8-Bit Memory Timing Rev. A | Page 27 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 23. 16-Bit Memory Read Cycle Parameter Timing Requirements tDRS AD15–0 Data Setup Before RD High AD15–0 Data Hold After RD High tDRH Min 3.3 0 Max Unit ns ns Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tADAS1 tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 tRRH2 Delay Between RD Rising Edge to Next Falling Edge H + tPCLK – 1.4 tRWALE Read Deasserted to ALE Asserted F + H + 0.5 tRDDRV ALE Address Drive After Read High F + H + tPCLK – 2.3 tADAH1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 ALE Deasserted to Address/Data15–0 in High Z tPCLK tALEHZ1 tRW RD Pulse Width D – 2.0 D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) tPCLK = (peripheral) clock period = 2 × tCCLK 1 2 tPCLK + 3.0 ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. This parameter is only available when in EMPP = 0 mode. tRWALE tALERW ALE tALEW tRRH RD tRW WR tALEHZ tADAS tADAH tRDDRV tDRS tDRH VALID DATA VALID ADDRESS AD15-0 VALID ADDRESS VALID DATA NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE. Figure 19. Read Cycle for 16-Bit Memory Timing Rev. A | Page 28 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2136x is accessing external memory space. Table 24. 8-Bit Memory Write Cycle Parameter Switching Characteristics ALE Pulse Width tALEW tADAS1 AD15–0 Address Setup Before ALE Deasserted tALERW ALE Deasserted to Write Asserted tRWALE Write Deasserted to ALE Asserted tWRH Delay Between WR Rising Edge to Next WR Falling Edge tADAH1 AD15–0 Address Hold After ALE Deasserted WR Pulse Width tWW tADWL AD15–8 Address to WR Low tADWH AD15–8 Address Hold After WR High tDWS AD7–0 Data Setup Before WR High tDWH AD7–0 Data Hold After WR High tDAWH AD15–8 Address to WR High D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK. tPCLK = (peripheral) clock period = 2 × tCCLK 1 Min 2 × tPCLK – 2.0 tPCLK – 2.8 2 × tPCLK – 3.8 H + 0.5 F + H + tPCLK – 2.3 tPCLK – 0.5 D – F – 2.0 tPCLK – 2.8 H D – F + tPCLK – 4.0 H D – F + tPCLK – 4.0 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. ALE tALEW tALERW tRWALE tWW WR tADWL tDAWH RD tWRH tADAS AD15-8 tADAH tADWH VALID ADDRESS VALID ADDRESS VALID ADDRESS tDWH tDWS AD7-0 VALID ADDRESS VALID DATA VALID DATA NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE ONLY SHOWS TWO MEMORY WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION. Figure 20. Write Cycle for 8-Bit Memory Timing Rev. A | Page 29 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 25. 16-Bit Memory Write Cycle Parameter Min Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tADAS1 tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 tRWALE Write Deasserted to ALE Asserted H + 0.5 tWRH2 Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 tADAH1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tWW WR Pulse Width D – F – 2.0 tDWS AD15–0 Data Setup Before WR High D – F + tPCLK – 4.0 AD15–0 Data Hold After WR High H tDWH D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK. tPCLK = (peripheral) clock period = 2 × tCCLK 1 2 Max Unit ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. This parameter is only available when in EMPP = 0 mode. tALEW ALE tALERW tRWALE tWW WR tWRH RD tADAS AD15-0 tADAH tDWH VALID ADDRESS VALID DATA VALID DATA VALID ADDRESS tDWS NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE. Figure 21. Write Cycle for 16-Bit Memory Timing Rev. A | Page 30 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 26. Serial Ports—External Clock Parameter Timing Requirements tSFSE1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) tHFSE1 FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode) 1 tSDRE Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 FS Delay After SCLK (Internally Generated FS in Either Transmit or Receive Mode) tHOFSE2 FS Hold After SCLK (Internally Generated FS in Either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK tHDTE2 Transmit Data Hold After Transmit SCLK 1 2 Serial port signals (SCLK, FS, data channel A, data channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Min Max Unit 2.5 2.5 2.5 2.5 12 24 ns ns ns ns ns ns 9.5 2 9.5 2 ns ns ns ns Referenced to sample edge. Referenced to drive edge. Table 27. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode) FS Hold After SCLK tHFSI1 (Externally Generated FS in Either Transmit or Receive Mode) 1 tSDRI Receive Data Setup Before SCLK tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 FS Delay After SCLK (Internally Generated FS in Transmit Mode) FS Hold After SCLK (Internally Generated FS in Transmit Mode) tHOFSI2 2 tDFSIR FS Delay After SCLK (Internally Generated FS in Receive Mode) tHOFSIR2 FS Hold After SCLK (Internally Generated FS in Receive Mode) tDDTI2 Transmit Data Delay After SCLK 2 tHDTI Transmit Data Hold After SCLK tSCLKIW Transmit or Receive SCLK Width 1 2 Min Max Unit 7 2.5 7 2.5 ns ns ns ns 3 –1.0 8 –1.0 3 –1.0 0.5tSCLK – 2 0.5tSCLK + 2 ns ns ns ns ns ns ns Referenced to the sample edge. Referenced to drive edge. Rev. A | Page 31 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 28. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK Data Disable from External Transmit SCLK tDDTTE1 tDDTIN1 Data Enable from Internal Transmit SCLK 1 Min 2 Max Unit ns ns ns 7 –1 Referenced to drive edge. Table 29. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 1 Max Unit 9 ns ns The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DAI_P20-1 (SCLK) DRIVE SAMPLE DRIVE tSFSE/I DAI_P20-1 (FS) tHFSE/I tDDTENFS DAI_P20-1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20-1 (SCLK) tSFSE/I DAI_P20-1 (FS) tHFSE/I tDDTENFS DAI_P20-1 (DATA CHANNEL A/B) tDDTE/I tHDTE/I 1ST BIT 2ND BIT tDDTLFSE NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS. Figure 22. External Late Frame Sync1 1 This figure reflects changes made to support left-justified sample pair mode. Rev. A | Page 32 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20-1 (SCLK) DAI_P20-1 (SCLK) tSCLKW tDFSIR tHOFSR DAI_P20-1 (FS) tSFSI tHFSI DAI_P20-1 (FS) tDFSE tHOFSE tSFSE tHFSE tSDRI DAI_P20-1 (DATA CHANNEL A/B) tHDRI DAI_P20-1 (DATA CHANNEL A/B) tSDRE tHDRE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE tSCLKIW DAI_P20-1 (SCLK) DAI_P20-1 (SCLK) tSCLKW tDFSI tHOFSI DAI_P20-1 (FS) tSFSI tHFSI DAI_P20-1 (FS) tDFSE tHOFSE tSFSE tHFSE tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI DAI_P20-1 (DATA CHANNEL A/B) tHDTE tDDTE NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P20-1 SCLK (EXT) SCLK DRIVE EDGE tDDTEN DAI_P20-1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20-1 SCLK (INT) tDDTTE tDDTIN DAI_P20-1 (DATA CHANNEL A/B) Figure 23. Serial Ports Rev. A | Page 33 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in Table 30. IDP signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 30. IDP Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge 1 tSIHFS FS Hold After SCLK Rising Edge SDATA Setup Before SCLK Rising Edge tSISD1 tSIHD1 SDATA Hold After SCLK Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min 3 3 3 3 9 24 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tIDPCLK DAI_P20-1 (SCLK) tIDPCLKW tSISFS DAI_P20-1 (FS) tSIHFS tSISD DAI_P20-1 (SDATA) tSIHD Figure 24. IDP Master Timing Rev. A | Page 34 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 31. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Table 31. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDSD1 tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 1 Hardware Reference. Note that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining 4 bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Min 2.5 2.5 3.0 2.5 7.0 24 Max Unit ns ns ns ns ns ns 2 × tPCLK – 1 2 × tPCLK – 1.5 ns ns Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG. SAMPLE EDGE t PDCLK t PDCLKW DAI_P20 -1 (PDAP_CLK) t SPCLKEN DAI_P20 -1 (PDAP_CLKEN) t HPCLKEN t PDSD DATA t PDHD DAI_P20-1 (PDAP_STROBE) tPDSTRB t PDHLDD Figure 25. PDAP Timing Rev. A | Page 35 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Pulse-Width Modulation Generators Table 32. PWM Timing Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period Min tPCLK – 2 2 × tPCLK – 1.5 Max (216 – 2) × tPCLK – 2 (216 – 1) × tPCLK Unit ns ns tPWMW PWM OUTPUTS tPWMP Figure 26. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 33 are valid at the DAI_P20–1 pins. This feature is not available on the ADSP-21363 models. Table 33. SRC, Serial Input Port Parameter Timing Requirements tSRCSFS1 FS Setup Before SCLK Rising Edge FS Hold After SCLK Rising Edge tSRCHFS1 1 tSRCSD SDATA Setup Before SCLK Rising Edge tSRCHD1 SDATA Hold After SCLK Rising Edge tSRCCLKW Clock Width tSRCCLK Clock Period 1 Min 3 3 3 3 36 80 Max Unit ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK DAI_P20-1 (SCLK) tSRCCLKW tSRCSFS DAI_P20-1 (FS) tSRCHFS tSRCSD DAI_P20-1 (SDATA) tSRCHD Figure 27. SRC Serial Input Port Timing Rev. A | Page 36 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time and delay specification with regard to SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Table 34. SRC, Serial Output Port Parameter Timing Requirements tSRCSFS1 FS Setup Before SCLK Rising Edge tSRCHFS1 FS Hold After SCLK Rising Edge Switching Characteristics tSRCTDD1 Transmit Data Delay After SCLK Falling Edge tSRCTDH1 Transmit Data Hold After SCLK Falling Edge 1 Min 3 3 Max Unit ns ns 10.5 2 ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK DAI_P20-1 (SCLK) tSRCCLKW tSRCSFS DAI_P20-1 (FS) tSRCHFS tSRCTDD DAI_P20-1 (SDATA) tSRCTDH Figure 28. SRC Serial Output Port Timing Rev. A | Page 37 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPDIF Transmitter Serial data input to the SPDIF transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The following sections provide timing for the transmitter. This feature is not available on the ADSP-21363 models. SPDIF Transmitter—Serial Input Waveforms Figure 29 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. LRCLK SCLK SDATA LEFT CHANNEL RIGHT CHANNEL LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB Figure 29. Right -Justified Mode Figure 30 shows the default I2S-justified mode. LRCLK is LO for the left channel and HI for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition but with a single SCLK period delay. RIGHT CHANNEL LRCLK LEFT CHANNEL SCLK SDATA MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB Figure 30. I2S-Justified Mode Figure 31 shows the left-justified mode. LRCLK is HI for the left channel and LO for the right channel. Data is valid on the rising edge of SCLK. The MSB is left-justified to an LRCLK transition with no MSB delay. LRCLK SCLK SDATA LEFT CHANNEL RIGHT CHANNEL MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB+1 Figure 31. Left-Justified Mode Rev. A | Page 38 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPDIF Transmitter Input Data Timing The timing requirements for the input port are given in Table 35. Input signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 35. SPDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 FS Setup Before SCLK Rising Edge tSIHFS1 FS Hold After SCLK Rising Edge tSISD1 SDATA Setup Before SCLK Rising Edge tSIHD1 SDATA Hold After SCLK Rising Edge Clock Width tSISCLKW tSISCLK Clock Period tSITXCLKW Transmit Clock Width tSITXCLK Transmit Clock Period 1 Min 3 3 3 3 36 80 9 20 Max Unit ns ns ns ns ns ns ns ns DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. tSITXCLKW SAMPLE EDGE DAI_P20-1 (TXCLK) tSITXCLK DAI_P20-1 (SCLK) tSISCLKW tSISFS DAI_P20-1 (FS) tSIHFS tSISD DAI_P20-1 (SDATA) tSIHD Figure 32. SPDIF Transmitter Input Timing Oversampling Clock (TXCLK) Switching Characteristics SPDIF Transmitter has an over sampling clock. This TXCLK input is divided down to generate the biphase clock. Table 36. Oversampling Clock (TXCLK) Switching Characteristics Parameter TXCLK Frequency for TXCLK = 768 × FS TXCLK Frequency for TXCLK = 512 × FS TXCLK Frequency for TXCLK = 384 × FS TXCLK Frequency for TXCLK = 256 × FS Frame Rate Min Max 147.5 98.4 73.8 49.2 192.0 Unit MHz MHz MHz MHz kHz Rev. A | Page 39 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPDIF Receiver The following section describes timing as it relates to the SPDIF receiver. This feature is not available on the ADSP-21363 models. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode) Parameter Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW1 tCCLK 1 Min LRCLK Delay After SCLK LRCLK Hold After SCLK Transmit Data Delay After SCLK Transmit Data Hold After SCLK Transmit SCLK Width Core Clock Period Max 5 Unit ns ns ns ns ns ns –2 5 –2 38 5 SCLK frequency is 64 × FS where FS = the frequency of LRCLK. DRIVE EDGE tSCLKIW DAI_P20-1 (SCLK) SAMPLE EDGE tDFSI tHOFSI DAI_P20-1 (FS) tHDTI DAI_P20-1 (DATA CHANNEL A/B) tDDTI Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing Rev. A | Page 40 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The ADSP-2136x contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 38 and Table 39 applies to both. Table 38. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements Data Input Valid to SPICLK Edge (Data Input Setup Time) tSSPIDM tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics Serial Clock Cycle tSPICLKM tSPICHM Serial Clock High Period tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) tHDSM Last SPICLK Edge to FLAG3–0IN High tSPITDM Sequential Transfer Delay Min 5.2 8.2 2 Max Unit ns ns ns 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 3.0 8.0 2 4 × tPCLK – 2.5 4 × tPCLK – 2.5 4 × tPCLK – 2 4 × tPCLK – 1 ns ns ns ns ns ns ns ns ns ns Rev. A | Page 41 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 FLAG3-0 (OUTPUT) tSDSCIM SPICLK (CP = 0) (OUTPUT) tSPICHM tSPICLM tSPICLKM tHDSM tSPIT DM tSPICLM SPICLK (CP = 1) (OUTPUT) tSPICHM tD D S P I D M MOSI (OUTPUT) MSB t HDSPIDM LSB tS S P I D M CPHASE = 1 MISO (INPUT) MSB VALID tSSPIDM tHSPIDM LSB VALID tH S P I D M tDDSPIDM MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB tHDSPIDM LSB tSSPIDM MSB VALID tHSPIDM LSB VALID Figure 34. SPI Master Timing Rev. A | Page 42 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Slave Table 39. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSDSCO SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tHDS tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active 1 tDSOE SPIDS Assertion to Data Out Active (SPI2) tDSDHI SPIDS Deassertion to Data High Impedance SPIDS Deassertion to Data High Impedance (SPI2) tDSDHI1 tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 1 Min 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK Max Unit ns ns ns ns ns ns ns ns ns 0 0 0 0 2 × tPCLK 5 8 5 8.6 9.5 5 × tPCLK ns ns ns ns ns ns ns The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. Rev. A | Page 43 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT) t S P IC H S SPICLK (CP = 0) (INPUT) tSPICLS tSPICL KS tHDS tSDPPW tSDSCO SPICLK (CP = 1) (INPUT) tSPICLS tSPICHS tDSOE tDDSPIDS tDDSPIDS MSB LSB tDSDHI tHDSPIDS MISO (OUTPUT) CPHASE = 1 MOSI (INPUT) tHSPIDS tSSPIDS MSB VALID tSSPIDS LSB VALID tDSOV tD S O E MISO (OUTPUT) CPHASE = 0 MOSI (INPUT) MSB tDDSPIDS tHDSPIDS tDSDHI LSB tSSPIDS MSB VALID LSB VALID tHSPIDS Figure 35. SPI Slave Timing Rev. A | Page 44 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 40. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 System Outputs Delay After TCK Low tDSYS 1 2 Min tCK 5 6 7 18 4tCK Max Unit ns ns ns ns ns ns 7 tCK ÷ 2 + 7 ns ns System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE. tTCK TCK tSTAP TMS TDI tHTAP tDTDO TDO tSSYS SYSTEM INPUTS tHSYS tDSYS SYSTEM OUTPUTS Figure 36. IEEE 1149.1 JTAG Test Access Port Rev. A | Page 45 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS Figure 37 shows typical I-V characteristics for the output drivers of the ADSP-2136x. The curves represent the current drive capability of the output drivers as a function of output voltage. CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 40, Figure 41, and Figure 42 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) vs. Load Capacitance. 40 30 SOURCE (VDDEXT) CURRENT (mA) VOH 3.3V, +25°C 3.47V, -45°C 20 10 0 12 3.11V, +125°C 10 RISE AND FALL TIMES (ns) y = 0.0467x + 1.6323 8 RISE FALL -10 3.11V, +125°C -20 3.3V, +25°C -30 -40 6 VOL 3.47V, -45°C 0 0.5 1.5 2.5 1.0 2.0 SWEEP (VDDEXT) VOLTAGE (V) 3.0 3.5 4 y = 0.045x + 1.524 2 Figure 37. ADSP-2136x Typical Drive 0 0 50 100 150 200 250 TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 14 on Page 21 through Table 40 on Page 45. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 38. Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. 12 LOAD CAPACITANCE (pF) Figure 40. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) RISE 10 RISE AND FALL TIMES (ns) y = 0.049x + 1.5105 8 FALL TO OUTPUT PIN 50 1.5V 6 y = 0.0482x + 1.4604 4 30pF 2 Figure 38. Equivalent Device Loading for AC Measurements (Includes All Fixtures) 0 0 50 100 150 200 250 LOAD CAPACITANCE (pF) INPUT 1.5V OR OUTPUT 1.5V Figure 41. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) Figure 39. Voltage Reference Levels for AC Measurements Rev. A | Page 46 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 10 8 OUTPUT DELAY OR HOLD (ns) Table 41. Thermal Characteristics for BGA (No thermal vias in PCB) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 25.40 21.90 20.90 5.07 0.140 0.330 0.410 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W 6 4 Y = 0.0488x - 1.5923 2 0 -2 -4 0 50 100 150 200 Table 42. Thermal Characteristics for BGA (Thermal vias in PCB) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 23.40 20.00 19.20 5.00 0.130 0.300 0.360 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W LOAD CAPACITANCE (pF) Figure 42. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-2136x processor is rated for performance over the temperature range specified in Operating Conditions on Page 16. Table 41 and Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board and thermal via design comply with JEDEC standards JESD51-9 (BGA). The junction-to-case measurement complies with MILSTD-883. All measurements use a 2S2P JEDEC test board. Industrial applications using the BGA package require thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-9 for printed circuit board thermal ball land and thermal via design information. To determine the junction temperature of the device while on the application PCB, use: T J = T T + ( Ψ JT × P D ) where: TJ = junction temperature (°C) TT = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 41. PD = power dissipation (see EE Note No. EE-277 for more information). Values of θJA are provided for package comparison and PCB design considerations. Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. Note that the thermal characteristics values provided in Table 41 and Table 42 are modeled values. Rev. A | Page 47 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-2136x’s pin names and their default function after reset (in parentheses). Table 43. BGA Pin Assignments Ball Name CLKCFG0 XTAL TMS TCK TDI CLKOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 Ball Name CLKCFG1 GND VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT GND GND GND FLAG1 FLAG0 GND GND GND GND GND GND FLAG2 DAI_P20 (SFS45) Ball No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 F01 F02 F04 F05 F06 F09 F10 F11 F13 F14 Ball Name BOOTCFG1 BOOTCFG0 GND GND GND VDDINT Ball No. C01 C02 C03 C12 C13 C14 Ball Name VDDINT GND GND GND GND GND GND GND GND VDDINT Ball No. D01 D02 D04 D05 D06 D09 D10 D11 D13 D14 AD7 VDDINT VDDEXT DAI_P19 (SCLK45) G01 G02 G13 G14 AD6 VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A) H01 H02 H13 H14 Rev. A | Page 48 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 43. BGA Pin Assignments (Continued) Ball Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) Ball No. J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 Ball Name AD3 VDDINT GND GND GND GND GND GND GND DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 AD9 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Ball No. K01 K02 K04 K05 K06 K09 K10 K11 K13 K14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Ball Name AD2 AD1 GND GND GND GND GND GND GND DAI_P14 (SFS23) Ball No. L01 L02 L04 L05 L06 L09 L10 L11 L13 L14 Ball Name AD0 WR GND GND DAI_P12 (SD3B) DAI_P13 (SCLK23) Ball No. M01 M02 M03 M12 M13 M14 Rev. A | Page 49 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P KEY VDDINT VDDEXT GND* AVSS AVDD I/O SIGNALS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 43. BGA Pin Assignments (Bottom View, Summary) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P KEY VDDINT VDDEXT GND* AVSS AVDD I/O SIGNALS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 44. BGA Pin Assignments (Top View, Summary) Rev. A | Page 50 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTLINE DIMENSIONS The ADSP-2136x is available in a 136-ball BGA package. 12.00 BSC SQ 10.40 BSC SQ 0.80 BSC TYP PIN A1 INDICATOR A B C D E F G H J K L M N P 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.80 BSC TYP TOP VIEW 1.70 MAX DETAIL A BOTTOM VIEW 0.25 1. DIMENSIONS ARE IN MILIMETERS (MM). MIN 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER. 4. CENTER DIMENSIONS ARE NOMINAL. 0.50 0.45 0.40 (BALL DIAMETER) SEATING PLANE 0.12 MAX (BALL COPLANARITY) DETAIL A Figure 45. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA](BC-136-2) SURFACE MOUNT DESIGN Table 44 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 44. BGA Data for Use with Surface Mount Design Package 136-Ball Grid Array (BC-136-2) Ball Attach Type Solder Mask Defined Solder Mask Opening 0.40 mm diameter Ball Pad Size 0.53 mm diameter Rev. A | Page 51 of 52 | December 2006 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE Operating Voltage Internal/External 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V 1.2 V/3.3 V Model ADSP-21362KBC-1AA ADSP-21362KBCZ-1AA2 ADSP-21362BBC-1AA ADSP-21362BBCZ-1AA2 ADSP-21362WBBCZ-1A2 ADSP-21363KBC-1AA ADSP-21363KBCZ-1AA2 ADSP-21363BBC-1AA ADSP-21363BBCZ-1AA2 ADSP-21363WBBCZ-1A2 ADSP-21364KBC-1AA ADSP-21364KBCZ-1AA2 ADSP-21364BBC-1AA ADSP-21364BBCZ-1AA2 ADSP-21364WBBCZ-1A2 ASDP-21365KBC-1AA3 ASDP-21365KBCZ-1AA2, 3 ASDP-21365BBC-1AA3 ASDP-21365BBCZ-1AA2, 3 ASDP-21365WBBCZ-1A2, 3 ADSP-21366KBC-1AA3 ADSP-21366KBCZ-1AA2, 3 ADSP-21366BBC-1AA3 ADSP-21366BBCZ-1AA2, 3 ADSP-21366WBBCZ-1A2, 3 1 2 Temperature Range 1 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Instruction Rate 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz On-Chip SRAM 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit ROM 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit Package Description 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA 136-Ball CSP-BGA Package Option BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 BC-136-2 Referenced temperature is ambient temperature. Z = Pb-free part. 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-12/06(A) Rev. A | Page 52 of 52 | December 2006