DAC8426BR/883C

a Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference DAC8426 FEATURES No Adjustments Required, Total Error 61 LSB Max Over Temperature Four Voltage-Output DACs on a Single Chip Internal 10 V Bandgap Reference Operates from Single 115 V Supply Fast 50 ns Data Load Time, All Temperatures Pin-for-Pin Replacement for PM-7226 and AD7226, Eliminates External Reference APPLICATIONS Process Controls Multichannel Microprocessor Controlled: System Calibration Op Amp Offset and Gain Adjust Level and Threshold Setting GENERAL DESCRIPTION The DAC8426 is a complete quad voltage output D/A converter with internal reference. This product fits directly into any existing 7226 socket where the user currently has a 10 V external reference. The external reference is no longer necessary. The internal reference of the DAC8426 is laser-trimmed to ± 0.4% offering a 25 ppm/°C temperature coefficient and 5 mA of external load driving capability. The DAC8426 contains four 8-bit voltage-output CMOS D/A converters on a single chip. A 10 V output bandgap reference sets the output full-scale voltage. The circuit also includes four input latches and interface control logic. One of the four latches, selected by the address inputs, is loaded from the 8-bit data bus input when the write strobe is active low. All digital inputs are TTL/CMOS (5 V) compatible. The on-board amplifiers can drive up to 10 mA from either a single or dual supply. The on-board reference that is always connected to the internal DACs has 5 mA available to drive external devices. Its compact size, low power, and economical cost-per-channel, make the DAC8426 attractive for applications requiring multiple D/A converters without sacrificing circuit-board space. System reliability is also increased due to reduced parts count. PMI’s advanced oxide-based, silicon-gate, CMOS process allows the DAC8426’s analog and digital circuitry to be manufactured on the same chip. This, coupled with PMI’s highly stable thin-film R-2R resistor ladder, aids in matching and temperature tracking between DACs. FUNCTIONAL BLOCK DIAGRAM REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 DAC8426–SPECIFICATIONS (VDD = +15 V 6 10%, AGND = DGND = 0 V, VSS = 0 V, TA = –558C to +1258C applies for DAC8426AR/BR, TA = –408C to +858C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted.) Parameter Symbol Conditions STATIC PERFORMANCE Resolution Total Unadjusted Error1 N TUE Includes Reference Min 8 INL Differential Nonlinearity2 Full-Scale Temperature Coefficient Zero Scale Error Zero Scale Error Temperature Coefficient DNL TCGFS VZSE Includes Reference TCVZS Dual Supply VSS = –5 V VREFOUT No Load A, E B, F TCVREFOUT LDREG LNREG en rms IREFOUT ∆IL = 5 mA ∆VDD ± 10% f = 0.1 Hz to 10 Hz ∆VREFOUT < 40 mV Temperature Coefficient Load Regulation Line Regulation Output Noise3 Output Current DIGITAL INPUTS Logic Input “0” Logic Input “1” Input Current Input Capacitance3 VINL VINH IIN CIN POWER SUPPLIES Positive Supply Current4 Negative Supply Current 4 Power Dissipation5 Power Supply Sensitivity IDD ISS PDISS PSS Max ±1 ±2 ± 1/2 ±1 ±1 A, E B, F A, E B, F Relative Accuracy REFERENCE OUTPUT Output Voltage Typ 25 20 5 10.04 10.08 20 0.02 0.008 3 7 0.1 0.04 10 0.8 Dual Supply VSS = –5 V ∆VDD = ± 5% V V ppm/°C %/mA %/V µV p-p mA 0.1 4 10 8 V V µA pF 6 4 90 0.0002 14 10 210 0.01 mA mA mW %/% 2.4 VIN = 0 V or VDD Bits LSB LSB LSB LSB LSB ppm/°C mV µV/°C 10 9.96 9.92 Units ELECTRICAL CHARACTERISTICS VDD = +15 V 6 10%, AGND = DGND = 0 V, VSS = 0 V, TA = –558C to +1258C applies for DAC8426AR/BR, TA = –408C to +858C applies for DAC8426ER/EP/FR/FP/FS, unless otherwise noted. Parameter Symbol DAC OUTPUT Output Current (Source)3 Output Current (Sink) 3 Minimum Load Resistance DYNAMIC PERFORMANCE 3 VOUT Slew Rate VOUT Settling Time (Positive or Negative) Digital Crosstalk SWITCHING CHARACTERISTICS Address To Write Setup Time Address To Write Hold Time Data Valid To Write Setup Time Data Valid To Write Hold Time Write Pulse Width Conditions IOUTSOURCE IOUTSINK RL(MIN) Digital In = All Ones Digital In = All Zeroes V SS = –5 V Digital In = All Ones SR tS To ± 1/2 LSB, RL = 2 kΩ Min 10 350 2 Q Typ6 Max Units 450 mA µA kΩ 4 3 V/µs µs 10 nVs 3 tAS tAH tDS tDH tWR 0 0 70 10 50 ns ns ns ns ns NOTES 1 Includes Full-Scale Error, Relative Accuracy, and Zero Code Error. Note ± 1 LSB = ± 0.39% error. 2 All devices guaranteed monotonic over the full operating temperature range. 3 Guaranteed and not subject to production test. 4 Digital inputs V IN = VINL or VINH; VOUT and VREFOUT unloaded. 5 PDISS calculated by IDD × VDD. 6 Typicals represent measured characteristics at T A = +25°C. Specifications subject to change without notice. –2– REV. C DAC8426 ABSOLUTE MAXIMUM RATINGS CAUTION VDD to AGND or DGND . . . . . . . . . . . . . . . . . –0.3 V, +17 V VSS to AGND or DGND . . . . . . . . . . . . . . . . . . . . . –7 V, VDD VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +5 V Digital Input Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD VREFOUT to AGND1 . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD VOUT to AGND1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Operating Temperature Military AR/BR . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Extended Industrial ER/EP/FR/FP/FS . . . . –40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C 1. Do not apply voltages higher than VDD or less than VSS potential on any terminal. 2. The digital control inputs are zener-protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Do not insert this device into powered sockets. Remove power before insertion or removal. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to device. PIN CONNECTIONS THERMAL RESISTANCE Package Type 20-Pin Cerdip (R) 20-Pin Plastic DIP (P) 20-Pin SOL(S) uJA 70 61 80 2 uJC 7 24 22 20-Pin Cerdip (R Suffix) Units °C/W °C/W °C/W 20-Pin Epoxy DIP (P Suffix) 20-Pin SOL (S Suffix) NOTES 1 Outputs may be shorted to any terminal provided the package power dissipation is not exceeded. Typical output short-circuit current to AGND is 50 mA. 2 θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for cerdip and P-DIP packages; θJA is specified for device soldered to printed circuit board for SOL package. ORDERING GUIDE1 Model Total Unadjusted Error Temperature Range Package Description DAC8426AR2 DAC8426ER DAC8426EP DAC8426BR2 DAC8426FR DAC8426FP DAC8426FS3 ± 1 LSB ± 1 LSB ± 1 LSB ± 2 LSB ± 2 LSB ± 2 LSB ± 2 LSB –55°C to +125°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 20-Pin Cerdip (Q-20) 20-Pin Cerdip (Q-20) 20-Pin Plastic DIP (N-20) 20-Pin Cerdip (Q-20) 20-Pin Cerdip (Q-20) 20-Pin Plastic DIP (N-20) 20-Lead SOL (R-20) NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office. Burn-In Circuit REV. C –3– DAC8426 DICE CHARACTERISTICS 1. VOUT B 2. VOUT A 3. VSS 4. VREF OUT 5. AGND 6. DGND 7. DB7 (MSB) 8. DB6 9. DB5 10. DB4 11. DB3 12. DB2 13. DB1 14. DB0 (LSB) 15. WR 16. A1 17. A0 18. VDD 19. VOUT D 20. VOUT C DIE SIZE 0.129 × 0.152 inch, 19,608 sq. mils (3.28 × 3.86 mm, 12.65 sq. mm) WAFER TEST LIMITS at VDD = +15 V 6 5%; VSS = AGND = DGND = 0 V; unless otherwise specified. TA = +258C. All specifications apply for DACs A, B, C, and D. Parameter Symbol Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Zero Code Error DAC Output Current Reference Output Voltage Load Regulation Line Regulation Reference Output Current Logic Inputs High Logic Inputs Low Logic Input Current Positive Supply Current Negative Supply Current TUE INL DNL GFSE VZSE IOUTSOURCE VREFOUT LDREG LNREG IREFOUT VINH VINL IIN IDD ISS Conditions Digital In = All Ones No Load ∆IL = 5 mA ∆VDD = ± 10 V ∆VREFOUT < 40 mV VIN = 0 V or VDD VIN = VINL or VINH VIN = VINL or VINH’ VSS = –5 V DAC8426GBC Limits Units ±2 ±1 ±1 ±1 ± 20 10 10.04 0.1 0.04 5 2.4 0.8 ±1 14 10 LSB max LSB max LSB max LSB max mV max mA min V max %/mA max %/V max mA min V min V max µA max mA max mA max NOTE Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8426 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. C Typical Performance Characteristics–DAC8426 Channel-to-Channel Matching (DACs A, B, C, D, Superimposed) Long Term Drift Accelerated by Burn-In Relative Accuracy vs. Code at TA = –55°C, +25°C, +125°C (All Superimposed) Zero Code Error vs. Temperature VOUT Noise Density vs. Frequency Broadband Noise (DC to 200 kHz) V OUT (0)  , PSRR(+) = –20 LOG  D V  DD  VDD = +15 V 61 VP, VSS = 0 V V OUT (0)  , PSRR(–) = –20 LOG  D V  SS  VDD = +15 V, VSS = –4 V 61 VP Power Supply Current vs. Temperature REV. C PSRR vs. Frequency –5– DAC8426–Typical Performance Characteristics VREFOUT Error from 10.000 V vs. Temperature Output Impedance (VREFOUT) vs. Frequency VREFOUT Load Regulation vs. Temperature VREFOUT Start Up VREFOUT Line Regulation vs. Temperature –6– REV. C DAC8426 PARAMETER DEFINITIONS Table I. DAC Control Logic Truth Table TOTAL UNADJUSTED ERROR (TUE) This specification includes the Full-Scale-Error, Relative Accuracy Zero-Code-Error and the internal reference voltage. The ideal Full-Scale output voltage is 10 V minus 1 LSB which equals 9.961 volts. Each LSB equals 10 V × (1/256) = 0.039 volts. DIGITAL CROSSTALK Digital crosstalk is the signal coupled to the output of a DAC due to a changing digital input from adjacent DACs being updated. It is specified in nano-Volt-seconds (nVs). CIRCUIT DESCRIPTION The DAC8426 is a complete quad 8-bit D/A converter. It contains an internal bandgap reference, four voltage switched R-2R ladder DACs, four DAC latches, four output buffer amplifiers, and an address decoder. All four DACs share the internal ten volt reference and analog ground(AGND). Figure 1 provides an equivalent DAC plus buffer schematic. WR Logic Control A1 A0 H X X L g L g L g L g L L L L H H H H L L H H L L H H DAC8426 Operation No Operation Device Not Selected DAC A Transparent DAC A Latched DAC B Transparent DAC B Latched DAC C Transparent DAC C Latched DAC D Transparent DAC D Latched L = Low State, H = High State, X = Don’t Care Figure 1. Simplified Circuit Configuration for One DAC. (Switches Are Shown for All “1s” on the Digital Inputs.) The eleven digital inputs are compatible with both TTL and 5 V (or higher) CMOS logic. Table I shows the DAC control logic truth table for WR, A1, and A0 operation. When WR is active low the input latch of the selected DAC is transparent, and the DAC’s output responds to the data present on the eight digital data inputs (DBx). The data (DBx) is latched into the addressed DAC’s latch on the positive edge of the WR control signal. The important timing requirements are shown in the Write Cycle Timing Diagram, Figure 2. INTERNAL 10 VOLT REFERENCE The internal 10 V bandgap reference of the DAC8426 is trimmed to the output voltage and temperature drift specifications. This internal reference is connected to the reference inputs of the four internal 8-bit D/A converters. The output terminal of the internal 10 V reference is available on pin 4. The 10 V output of the reference is produced with respect to the AGND pin. This reference output can be used to supply as much as 5 mA of additional current to external devices. Care has been taken in REV. C Figure 2. Write Cycle Timing Diagram the design of the internal DAC switching to minimize transients on the reference voltage terminal (VREFOUT). Other devices connected to this reference terminal should have well behaved input loading characteristics. D/A converters such as the PMI PM7226A have been designed to minimize reference input transient currents and can be directly connected to the DAC8426 10 V reference. Devices exhibiting large current transients due to internal switching should be buffered with an op amp to maintain good overall system noise performance. A 10 µF reference output bypass capacitor is required. BUFFER AMPLIFIER SECTION The four internal unity-gain voltage buffers provide low output impedance capable of sourcing 5 mA or sinking 350 µA. Typical output slew rates of ±4 V/µs are achieved with 10 V full-scale output changes and RL = 2 kΩ. Figure 3 photographs show large signal and settling time response. Capacitive loads to 3300 pF maximum, and resistive loads to 2 kΩ minimum can be applied. –7– DAC8426 a) Large Signal b) Settling Time Response (Negative Transition) Test Conditions, All Photos: VDD = +15 V CREFOUT = 10 mF RL = 2 kV Digital Input Sequence 0, 255, 0 c) Settling Time Response (Positive Transition) Figure 3. Dynamic Response four output buffer amplifiers are connected to VSS. Operating the DAC8426 from dual supplies (VDD = +15 V and VSS = –5 V) improves negative going output settling time near zero volts. The outputs can withstand an indefinite short-circuit to AGND to typically 50 mA. The output may also be shorted to any voltage between VDD and VSS; however, care must be taken to not exceed the device maximum power dissipation. When operating single supply (VDD = +15 V and VSS = 0 V) the output sink current decreases as the output approaches zero voltage. Within 200 mV of AGND (single-supply operation) the internal sinking capability appears resistive at a value of approximately 1200 Ω. The buffer amplifier output current and voltage characteristics are plotted in Figure 5. The amplifier’s emitter follower output stage consists of an intrinsic NPN bipolar transistor with a 400 µA NMOS pull-down current-source load connected to VSS. This circuit configuration shown in Figure 4 enables the output amplifier to develop output voltages very close to AGND. Only the negative supply of the –8– REV. C DAC8426 APPLICATIONS SETUP UNIPOLAR OUTPUT OPERATION The output voltage appearing at any output VOUT is equal to the internal 10 V reference multiplied by the decimal value of the latched digital input divided by 28 (= 256). In equation form: VOUT(D) = D/256 × 10 V where D = 010 to 25510 One additional characteristic guaranteed is a DNL of ± 1 LSB on all grades. The DAC8426 is therefore guaranteed to be monotonic. In the situation where a continuously positive 1 LSB digital increment is applied, the output voltage will always increase in value, never decrease. This is very important is servo applications and other closed-loop feedback systems. Finally, in the typical characteristic curves, long term output voltage drift (stability) is provided. BIPOLAR OUTPUT OPERATION An external op amp plus two resistors can easily convert any DAC output to bipolar output voltage swings. Figure 6 shows all four DACs output operating in bipolar mode. This is the general expression describing the bipolar output transfer equation: VOUT(D) = [(1 +R2/R1) × D/256 × 10 V] –R2/R1 × 10 V, where D = 010 to 25510 If R1 = R2, then VOUT becomes: VOUT (D) = (D/128–1) × 10 V Figure 4. Amplifier Output Stage Note that the maximum possible output is 1 LSB less than the internal 10 V reference, that is, 255/256 × 10 V = 9.961 V. Table II lists output voltages for a given digital input. The total unadjusted error (TUE) specification of the product grade used determines the output tolerances of the values listed in Table II. For example, a ± 2 LSB grade DAC8426FP loaded with decimal 12810 (half-scale) would have a guaranteed output voltage occurring in the range of 5 V ± 2 LSB, which is 5 V ± (2 × 10 V/256) = 5 V ± 0.078 V. Therefore VOUT is guaranteed to occur in the following range: 4.922 V ≤ VOUT(128) ≤ 5.078 V Table III lists various output voltages with R1 = R2 versus digital input code. This coding is considered offset binary. Note that the LSB step size is now 20 V/256 = 0.078 V, twice as large as the unipolar output case previously discussed. In order to minimize gain and offset errors, choose R1 and R2 to match and track within 0.1% over the selected operating temperature range of interest. Table II. Unipolar Output Voltage as a Function of Digital Input Code Digital Input Code Analog Output Voltage (= D/256 × 10 V) 255 254 129 128 127 1 0 9.961 V 9.922 V 5.039 V 5.000 V 4.961 V 0.039 V 0.000 V Full-Scale (FS) FS-1 LSB Half-Scale 1 LSB Zero-Scale OFFSETTING AGND Figure 5. DAC Output Current Sink For the top grade DAC8426EP ± 1 LSB total unadjusted error (TUE), the guaranteed range is 4.961 V ≤ VOUT (12810) ≤ 5.039 V. These tolerances provide the worst case analysis including temperature changes. REV. C Since the DAC ladder and bandgap reference are terminated at AGND, it is possible to offset AGND positive with respect to DGND. The 10 V output span remains if a positive offset is applied to AGND. The offset voltage source connected to AGND must be capable of sinking 14 mA. AGND cannot be taken negative with respect to DGND; this would forward bias an internal diode. Allowance must be made at VDD to maintain 3.5 V of headroom above VREFOUT. This connection setup is useful in single supply applications where virtual ground needs to be slightly positive with respect to ground. In this application connect VSS to DGND to take advantage of the extra buffer output current sinking capability when the DAC output is programmed to all zeros code, see Figure 7. –9– DAC8426 Table III. Bipolar Output Voltage as a Function of Digital Input Code Digital Input Code Analog Output Voltage (= D/256 × 10 V) 255 254 129 128 127 1 0 9.922 V 9.844 V 0.078 V 0.000 V –0.078 V –9.922 V –10.000 V Full-Scale (FS) FS-1 LSB Zero-Scale Neg Full-Scale Figure 7. AGND Biasing Scheme Providing Offset Output Range Figure 6. Bipolar Operation CONNECTION AND LAYOUT GUIDELINES Layout and design techniques used in the interface between digital and analog circuitry require special attention to detail. The following considerations should be evaluated prior to PCB layout. 1. Return signal paths through the ground system should be carefully considered. High-speed digital logic current pulses traveling on return ground traces generate glitches that can be radiated to the analog circuits if the ground path layout produces loop antennas. Ground planes can minimize this situation. Separate digital and analog grounding areas to minimize crosstalk. Ideally a single common-point ground should be on the same PCB board as the DAC8426. The analog ground returns should take advantage of the appropriate placement of power supply bypass capacitors. 2. For optimum performance, bypass VDD and VSS (if using negative supply voltage) with 0.1 µF ceramic disk capacitors to shunt high-frequency spikes. Also use in parallel 6.8 µF to 10 µF capacitors to provide a charge reservoir for lower frequency load change requirements. The reference output (VREFOUT) should be bypassed with a 10 µF tantalum capacitor to optimize reference output stability during data input changes. This helps to minimize digital crosstalk. 3. Power Supply Sequencing—No special requirements exist with the DAC8426. However, users should be aware that often the 5 V logic supply may be powered up momentarily prior to the +15 V analog supply. In this situation, the DAC8426 ESD input protection diodes will forward bias if the applied input logic is at logic “1”. No damage will result to the input since the DAC8426 is designed to withstand momentary currents of up to 130 mA. This situation will likely exist for any DAC or ADC operating from a separate analog supply. 4. ESD input protection—Attention has been given in the design of the DAC8426 to ESD sensitivity. Using the human body model test technique (MIL-STD 3015.4) the DAC8426 generally will withstand 1500 V ESD transients on all pins. Handling and testing prior to PCB insertion generally exposes ICs to the toughest environment they will experience. Once the IC is soldered in the PCB, it is still important to consider any traces that connect to PCB edge connectors. These traces should be protected with appropriate devices especially if the boards will experience field replacement or adjustment. Handling the exposed edge connectors by field maintenance people in a low humidity environment can produce 20 kV ESD transients which will be detrimental to almost any integrated IC connected to the edge connector. –10– REV. C DAC8426 MICROPROCESSOR INTERFACING The DAC8426 easily interfaces to most 8- and 16-bit wide databus systems. Serial and 4-bit busses can also be accommodated with additional latches and control circuitry. Interfacing can be accomplished with databus transfers running with 50 ns write pulse widths. Examples of various microprocessor interface circuits are provided in Figures 8 through 12. These figures have omitted circuitry not essential to the bus interface. The design process should include review of the DAC8426 timing diagram with the µP system timing diagram. Figure 10. DAC8426 to 6809 Interface (Simplified circuit, only lines of interest are shown.) Figure 8. DAC8426 to 8085A Interface (Simplified circuit, only lines of interest are shown.) Figure 9. DAC8426 to Z-80 Interface (Simplified circuit, only lines of interest are shown.) REV. C Figure 11. DAC8426 to 6502 Interface (Simplified circuit, only lines of interest are shown.) Figure 12. DAC8426 to 68000 Interface (Simplified circuit, only lines of interest are shown.) –11– DAC8426 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.005 (0.13) MIN 000000000 20-Pin Cerdip (Q-20) 0.098 (2.49) MAX 20 11 0.310 (7.87) 0.220 (5.59) 1 10 PIN 1 1.060 (26.92) MAX 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 (2.54) BSC 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) 20-Pin Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50) 20 11 1 10 PIN 1 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.015 (0.381) 0.008 (0.204) 0.070 (1.77) SEATING 0.045 (1.15) PLANE 20-Lead SOL (R-20) 1 10 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0.0500 0.0192 (0.49) 0° (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) –12– PRINTED IN U.S.A. 11 0.2992 (7.60) 0.2914 (7.40) 20 0.4193 (10.65) 0.3937 (10.00) 0.5118 (13.00) 0.4961 (12.60) 0.0500 (1.27) 0.0157 (0.40) REV. C