EVAL-AD7738EBZ

a FEATURES High Resolution ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Optimized for Fast Channel Switching 18-Bits p-p Resolution (21 Bits Effective) at 500 Hz 16-Bits p-p Resolution (19 Bits Effective) at 8.5 kHz 15-Bits p-p Resolution (18 Bits Effective) at 15 kHz On-Chip Per Channel System Calibration Configurable Inputs 8 Single-Ended or 4 Fully Differential Input Ranges +625 mV, +1.25 V, +2.5 V, 625 mV, 1.25 V, 2.5 V 3-Wire Serial Interface SPI™, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger on Logic Inputs Single-Supply Operation 5 V Analog Supply 3 V or 5 V Digital Supply Package: 28-Lead TSSOP APPLICATIONS PLCs/DCS Multiplexing Applications Process Control Industrial Instrumentation GENERAL DESCRIPTION The AD7738 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 117 µs (8.5 kHz channel switching), making it ideally suitable for high resolution multiplexing applications. The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to a 15.4 kHz. The analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mV, 1.25 V, and 2.5 V input ranges and accepts a common-mode input voltage from 200 mV above AGND to AVDD – 300 mV. The multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before applying the input to the ADC. 8-Channel, High Throughput, 24-Bit
- ADC AD7738 FUNCTIONAL BLOCK DIAGRAM MUXOUT ADCIN REFIN– REFIN+ REFERENCE DETECT AIN0 AIN1 AIN2 BUFFER AIN3 24-BIT
- ADC MUX AIN4 AIN5 AIN6 AD7738 AIN7 SCLK CALIBRATION CIRCUITRY AINCOM/P0 SERIAL INTERFACE DOUT DIN CS I/O PORT SYNC/P1 AGND AVDD CLOCK GENERATOR MCLKOUT MCLKIN RDY CONTROL LOGIC DGND RESET DVDD The differential reference input features “No-Reference” detect capability. The ADC also supports per channel system calibration options. The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The part is specified for operation over the extended industrial temperature range of –40C to +105C. Other parts in the AD7738 family are the AD7734 and the AD7732. The AD7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to ± 10 V while operating from a single 5 V analog supply. The AD7734 accepts an analog input overvoltage to ± 16.5 V while not degrading the performance of the adjacent channels. The AD7732 is similar to AD7734, but its analog front end features two fully differential input channels. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 (–40ⴗC to +105ⴗC, AV = 5 V ⴞ 5%, DV = 2.7 V to 3.6 V or 5 V ⴞ 5%, AD7738–SPECIFICATIONS REFIN(+) = 2.5 V, REFIN(–) = 0 V, AINCOM = 2.5 V, MUXOUT(+) = ADCIN(+), MUXOUT(–) = ADCIN(–), Internal Buffer ON, AIN Range = ⴞ1.25 V, DD DD fMCLK = 6.144 MHz; unless otherwise noted.) Parameter Min Typ Max Unit Test Conditions/Comment 12190 Hz Bits Configure via Conversion Time Register FW ≥ 6 (Conversion Time ≥ 165 µs) See Typical Performance Characteristics % of FSR % of FSR µV nV/°C % ppm of FS/ⴗC % of FSR ppm of FS/ⴗC % of FSR dB dB AIN Range = ± 2.5 V AIN Range = ± 1.25 V Before Calibration Hz Bits Configure via Conversion Time Register FW ≥ 8 (Conversion Time ≥ 117 µs) See Typical Perfomance Charateristics ADC PERFORMANCE— CHOPPING ENABLED Conversion Time Rate No Missing Codes1 372 24 Output Noise Resolution Integral Nonlinearity (INL) Offset Error (Unipolar, Bipolar) 2 Offset Drift vs. Temperature 1 Gain Error2 Gain Drift vs. Temperature1 Positive Full-Scale Error 2 Positive Full-Scale Drift vs. Temperature 1 Bipolar Negative Full-Scale Error 3 Common-Mode Rejection 80 Power Supply Rejection 70 ADC PERFORMANCE— CHOPPING DISABLED Conversion Time Rate No Missing Codes1 737 24 Output Noise Resolution Integral Nonlinearity (INL) Offset Error (Unipolar, Bipolar) 4 Offset Drift vs. Temperature Gain Error2 Gain Drift vs. Temperature Positive Full-Scale Error 2 Positive Full-Scale Drift vs. Temperature Bipolar Negative Full-Scale Error 3 Common-Mode Rejection Power Supply Rejection ANALOG INPUTS Analog Input Voltage Ranges 1, 5 ± 2.5 V Range +2.5 V Range ± 1.25 V Range +1.25 V Range ± 0.625 V Range +0.625 V Range AIN, AINCOM Common-Mode Voltage 1 AIN, AINCOM Input Current 6 AIN to MUXOUT On Resistance 1 REFERENCE INPUT REFIN(+) to REFIN(–) Voltage 1, 7 NOREF Trigger Voltage REFIN(+), REFIN(–) Common-Mode Voltage1 Reference Input Current8 SYSTEM CALIBRATION1, 9 Full Scale Calibration Limit Zero Scale Calibration Limit Input Span See Table I See Tables II and III ± 0.0015 ± 0.0015 ± 10 ± 280 ± 0.2 ± 2.5 ± 0.2 ± 2.5 ± 0.0030 100 80 15437 See Table IV See Tables V and VI ± 0.0015 ±1 ± 1.5 ± 0.2 ± 2.5 ± 0.2 ± 2.5 ± 0.0030 75 65 –2.9 0 –1.45 0 –725 0 0.2 ± 2.5 0 to 2.5 ± 1.25 0 to 1.25 ± 625 0 to 625 +2.9 2.9 +1.45 1.45 +725 725 AVDD – 0.3 200 V V V V mV mV V nA Ω 2.525 V V 200 2.475 2.5 0.5 0 –1.05 ⫻ FS 0.8 ⫻ FS % of FSR mV µV/ⴗC % ppm of FS/ⴗC % of FSR ppm of FS/ⴗC % of FSR dB dB AVDD 400 Before Calibration Before Calibration After Calibration3 At DC, AIN = 1 V At DC, AIN = 1 V Before Calibration Before Calibration Before Calibration After Calibration3 At DC, AIN = 1 V At DC, AIN = 1 V Only One Channel, Chop Disabled NOREF Bit in Channel Status Register V µA +1.05 ⫻ FS V V 2.1 ⫻ FS V –2– REV. 0 AD7738 Parameter Min Typ LOGIC INPUTS SCLK, DIN, CS, and RESET Inputs Input Current Input Current CS Input Capacitance VT+1 VT–1 VT+ – VT–1 VT+1 VT–1 VT+ – VT–1 MCLK IN Only Input Current Input Capacitance VINL Input Low Voltage VINH Input High Voltage VINL Input Low Voltage VINH Input High Voltage LOGIC OUTPUTS MCLKOUT10, DOUT, RDY VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current Floating State Leakage Capacitance P1 INPUT Input Current VINL Input Low Voltage VINH Input High Voltage VOH Output High Voltage AVDD Current (Normal Mode) AVDD Current (Internal Buffer Off ) DVDD Current (Normal Mode)11 DVDD Current (Normal Mode)11 AVDD + DVDD Current (Standby Mode) 12 Power Dissipation (Normal Mode) 11 Power Dissipation (Standby Mode) 12 Unit ±1 ± 10 –40 µA µA µA pF V V V V V V DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V µA pF V V V V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V 4 1.4 0.8 0.3 0.95 0.4 0.3 2 1.4 0.85 2 1.1 0.85 ± 10 4 0.8 3.5 0.4 2.5 0.4 4.0 0.4 DVDD – 0.6 ±1 3 V V V V µA pF Test Conditions/Comment CS = AVDD Internal Pull-Up Resistor ISINK = 800 µA, DVDD = 5 V ISOURCE = 200 µA, DVDD = 5 V ISINK = 100 µA, DVDD = 3 V ISOURCE = 100 µA, DVDD = 3 V Levels Referenced to Analog Supplies ± 10 0.8 µA V V AVDD = 5 V AVDD = 5 V 0.4 0.4 0.4 V V V V ISINK = 8 mA, TMAX = 70°C, AVDD = 5 V ISINK = 5 mA, TMAX = 85°C, AVDD = 5 V ISINK = 2.5 mA, TMAX = 105°C, AVDD = 5 V ISOURCE = 200 µA, AVDD = 5 V 5.25 5.25 3.60 16 V V V mA mA mA mA µA mW µW 3.5 P0, P1 OUTPUT VOL Output Low Voltage POWER REQUIREMENTS AVDD – AGND Voltage DVDD – DGND Voltage Max 4.0 4.75 4.75 2.70 13.6 8.5 2.7 1.0 80 85 500 3 1.5 100 AVDD = 5 V AVDD = 5 V DVDD = 5 V DVDD = 3 V AVDD = DVDD = 5 V AVDD = DVDD = 5 V NOTES 1 Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release. 2 Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise. 3 Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error. 4 Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise. 5 The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max. Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the Mode register. See the register description and circuit description for more details. 6 If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. See the circuit description for more details. 7 For specified performance. Part is functional with Lower VREF 8 Dynamic current charging the sigma-delta modulator input switching capacitor. 9 Outside the specified calibration range, calibration is possible but the performance may degrade. 10 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 11 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register). 12 External MCLKIN = 0 V or DVDD, Digital Inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD. Specifications are subject to change without notice. REV. 0 –3– AD7738 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 5 V  5%; DVDD = 2.7 V to 3.6 V or 5 V  5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.) Parameter Min MASTER CLOCK RANGE t1 t2 1 50 500 READ OPERATION t4 t5 4 0 Typ Max Unit Test Conditions/Comment 6.144 MHz ns ns SYNC Pulsewidth RESET Pulsewidth 0 0 60 80 ns ns 0 0 50 50 0 10 60 80 ns ns ns ns ns ns CS Falling Edge to SCLK Falling Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V CS Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time Bus Relinquish Time after SCLK Rising Edge ns ns ns ns ns ns CS Falling Edge to SCLK Falling Edge Setup Data Valid to SCLK Rising Edge Setup Time Data Valid after SCLK Rising Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time ns t5A4, 5 t6 t7 t8 t9 6 WRITE OPERATION t11 t12 t13 t14 t15 t16 0 30 25 50 50 0 80 NOTES 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. 3 See Figures 1 and 2. 4 These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the VOL or VOH limits. 5 This specification is relevant only if CS goes low while SCLK is low. 6 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications are subject to change without notice. –4– REV. 0 AD7738 CS t4 t8 t6 SCLK t7 t5 t9 t5A DOUT MSB LSB Figure 1. Read Cycle Timing Diagram CS t11 t16 t14 SCLK t15 t12 t13 DIN MSB LSB Figure 2. Write Cycle Timing Diagram ISINK (800A AT DVDD = 5V 100A AT DVDD = 3V) TO OUTPUT PIN 1.6V 50pF ISOURCE ( 200A AT DVDD = 5V 100A AT DVDD = 3V) Figure 3. Load Circuit for Access Time and Bus Relinquish Time REV. 0 –5– AD7738 Operating Temperature Range . . . . . . . . . . –40C to +105C Storage Temperature Range . . . . . . . . . . . . –65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C TSSOP Package, Power Dissipation . . . . . . . . . . . . . 660 mW ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C ABSOLUTE MAXIMUM RATINGS* (TA = 25C unless otherwise noted.) AVDD to AGND, DVDD to DGND . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +5 V AIN, AINCOM to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V REFIN(+), REFIN(–) to AGND . . . . . –0.3 V to AVDD + 0.3 V MUXOUT(+) to AGND . . . . . . . . . . . –0.3 V to AVDD + 0.3 V MUXOUT(–) to AGND . . . . . . . . . . . –0.3 V to AVDD + 0.3 V ADCIN(+), ADCIN(–) to AGND . . . . –0.3 V to AVDD + 0.3 V P1 Voltage to AGND . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . . –0.3 V to AVDD + 0.3 V Digital Output Voltage to DGND . . . . –0.3 V to AVDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Options AD7738BRU –40C to +105C TSSOP 28 RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7738 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. MUXOUT ADCIN REFIN– REFIN+ REFERENCE DETECT AIN0 AIN1 BUFFER AIN2 AIN3 24-BIT
- ADC MUX AIN4 AIN5 DVDD AIN6 AD7738 AIN7 CS CALIBRATION CIRCUITRY AINCOM/P0 SCLK SERIAL INTERFACE DOUT DIN AVDD I/O PORT SYNC/P1 AGND AVDD CLOCK GENERATOR MCLKOUT MCLKIN RDY CONTROL LOGIC DGND RESET DVDD Figure 4. Block Diagram –6– REV. 0 AD7738 PIN CONFIGURATION SCLK 1 28 DGND MCLKIN 2 27 DVDD MCLKOUT 3 26 DIN 25 DOUT CS 4 RESET 5 AVDD 6 24 RDY AD7738 23 AGND AINCOM/P0 7 TOP VIEW 22 REFIN(–) (Not to Scale) 21 REFIN(+) SYNC/P1 8 AIN7 9 20 AIN0 AIN6 10 19 AIN1 AIN5 11 18 AIN2 AIN4 12 17 AIN3 MUXOUT(+) 13 16 ADCIN(+) MUXOUT(–) 14 15 ADCIN(–) PIN FUNCTION DESCRIPTION Pin No. Mnemonic Description 1 SCLK Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7738. 2 MCLKIN Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and MCLKOUT left unconnected. 3 MCLKOUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to lower the device power consumption. MCLKOUT is capable of driving one CMOS load. 4 CS Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7738 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. 5 RESET Schmitt-Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. 6 AVDD Analog Positive Supply Voltage. 5 V to AGND nominal. 7 AINCOM/P0 Analog Inputs Common Terminal/Digital Output. The pin is determined by the P0 Dir bit; the digital value can be written as the P0 bit in the I/O Port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 Dir bit set to 1), the single-ended Analog Inputs 0 to 7 can be referenced to this pin’s voltage level. 8 SYNC/P1 SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 Dir bit; the digital value can be read/written as the P1 bit in the I/O Port register. When the SYNC Enable bit in the I/O Port register is set to 1, the SYNC/P1 pin can be used to synchronize the AD7738 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low. 9–12, 17–20 AIN0–AIN7 Analog Inputs 13 MUXOUT(+) Analog Multiplexer Positive Output 14 MUXOUT(–) REV. 0 Analog Multiplexer Negative Output –7– AD7738 PIN FUNCTION DESCRIPTION (continued) Pin No. Mnemonic Pin Description 15 ADCIN(–) ADC Negative Input. In normal circuit configuration, this pin should be connected to the MUXOUT– pin. 16 ADCIN(+) ADC Positive Input. In normal circuit configuration, this pin should be connected to the MUXOUT+ pin. 21 REFIN(+) Positive Terminal of the Differential Reference Input. REFIN+ voltage potential can lie any where between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. 22 REFIN(–) Negative Terminal of the Differential Reference Input. REFIN– voltage potential can lie any where between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. 23 AGND Ground Reference Point for Analog Circuitry 24 RDY Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available—according to the RDY function bit in the I/O Port register. In calibration mode, a falling edge on this output indicates that calibration is complete. See more details in Digital Interface Description section later in this data sheet. 25 DOUT Serial Data Output with serial data being read from the output shift register on the part. This output shift register can contain information from any AD7738 register depending on the address bits of the Communications register. 26 DIN Serial Data Input (Schmitt triggered) with serial data being written to the input shift register on the part. Data from this input shift register is transferred to any AD7738 register depending on the address bits of the Communications register. 27 DVDD Digital Supply Voltage, 3 V or 5 V Nominal 28 DGND Ground Reference Point for Digital Circuitry –8– REV. 0 AD7738 OUTPUT NOISE AND RESOLUTION SPECIFICATION The AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. CHOPPING ENABLED The first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register. Table I. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V, +2.5 V 1.25 V, +1.25 V, 625 mV, +625 mV 127 46 17 8 4 2 FFh AEh 91h 88h 84h 82h 2686 999 395 207 124 82 194 521 1317 2510 4198 6326 1.8 3.0 5.1 8.1 9.3 17.0 1.1 1.8 3.0 4.5 5.3 10.6 372 1001 2534 4826 8074 12166 Input Range Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV 127 46 17 8 4 2 FFh AEh 91h 88h 84h 82h 2686 999 395 207 124 82 194 521 1317 2510 4198 6326 21.4 20.6 19.9 19.2 19.0 18.1 20.4 19.6 18.9 18.2 18.0 17.1 21.1 20.4 19.6 19.0 18.8 17.8 20.1 19.4 18.6 18.0 17.8 16.8 20.1 19.4 18.6 18.0 17.8 16.8 19.1 18.4 17.6 17.0 16.8 15.8 372 1001 2534 4826 8074 12166 Input Range Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV 127 46 17 8 4 2 FFh AEh 91h 88h 84h 82h 2686 999 395 207 124 82 194 521 1317 2510 4198 6326 18.4 17.8 16.8 16.5 16.0 15.0 17.4 16.8 15.8 15.5 15.0 14.0 18.2 17.5 16.7 16.2 16.0 15.0 17.2 16.5 15.7 15.2 15.0 14.0 17.2 16.5 15.7 15.2 15.0 14.0 16.2 15.5 14.7 14.2 14.0 13.0 REV. 0 372 1001 2534 4826 8074 12166 Input Range –9– AD7738 CHOPPING DISABLED The second mode, in which the AD7738 is configured with chopping disabled (CHOP = 0), provides faster conversion time while still maintaining high resolution. Tables IV to VI show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table IV shows the typical output rms noise. Table V shows the typical effective resolution based on the rms noise. Table VI shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register. Table IV. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V, +2.5 V 1.25 V, +1.25 V, 625 mV, +625 mV 127 92 35 16 9 8 3 7Fh 5Ch 23h 10h 9h 8h 3h 1357 992 398 200 127 117 65 671 917 2285 2510 7141 7776 14013 2.7 3.0 5.1 7.5 10.2 11.4 15.5 1.5 1.8 3.0 4.5 5.9 6.5 10.3 737 1008 2511 4991 7847 8545 15398 Input Range Table V. Typical RMS Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV 127 92 35 16 9 8 3 7Fh 5Ch 23h 10h 9h 8h 3h 1357 992 398 200 127 117 65 671 917 2285 2510 7141 7776 14013 20.8 20.6 19.9 19.3 18.9 18.7 18.0 19.8 19.6 18.9 18.3 17.9 17.7 16.7 20.6 20.4 19.6 19.0 18.7 18.5 17.8 19.6 19.4 18.6 18.0 17.7 17.5 17.1 19.6 19.4 18.6 18.0 17.7 17.5 17.1 18.6 18.4 17.6 17.0 16.7 16.5 16.1 737 1008 2511 4991 7847 8545 15398 Input Range Table VI. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled FW Conversion Time Register Conversion Output Time Data Rate (s) (Hz) –3 dB Frequency (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV 127 92 35 16 9 8 3 7Fh 5Ch 23h 10h 9h 8h 3h 1357 992 398 200 127 117 65 671 917 2285 2510 7141 7776 14013 17.9 17.8 17.0 16.3 16.1 16.0 15.0 16.9 16.8 16.0 15.3 15.1 15.0 14.0 17.8 17.4 16.8 16.2 15.9 15.7 14.8 16.8 16.4 15.8 15.2 14.9 14.7 13.8 16.8 16.4 15.8 15.2 14.9 14.7 13.8 15.8 15.4 14.8 14.2 13.9 13.7 12.8 737 1008 2511 4991 7847 8545 15398 Input Range –10– REV. 0 Typical Performance Characteristics–AD7738 25 0 24 THD = 115dB –20 23 –40 22 –60 21 –80 GAIN – dB NO MISSING CODES CHOP = 1 20 –100 19 –120 18 –140 17 –160 16 1 2 3 4 5 6 FILTER WORD 7 8 9 –180 10 0 200 400 600 800 1000 INPUT FREQUENCY 1200 1400 TPC 3. Typical FFT Plot; Input Sinewave 183 Hz, 1.2 V Peak, Range ± 1.25 V, Conversion Time 394 µ s, Chopping Enabled TPC 1. No Missing Codes Performance, Chopping Enabled 140 25 24 120 CHOP = 0 EFFECTIVE RES. 19.9 BITS P-P RES. 17.0 BITS 23 NUMBER OF CODES NO MISSING CODES 100 22 21 20 19 80 60 40 18 20 17 16 1 2 3 4 5 6 FILTER WORD 7 8 9 0 –80 10 TPC 2. No Missing Codes Performance, Chopping Disabled REV. 0 –11– –60 –40 –20 0 VALUE 20 40 60 80 TPC 4. Typical Histogram; Analog Inputs Shorted; Range ± 2.5 V, Conversion Time 394 µ s; Chopping Enabled AD7738 Table VII. Register Summary Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDY FN 0 0 0 0 0 SYNC 0 0 Chip Generic Code 0 0 Register hex Default Value Communications 00 W 0 R/W 6-Bit Register Address I/O Port 01 R/W P0 P0 Pin P1 P1 Pin P0 DIR P1 DIR 1 1 Revision 02 R x Chip Revision Code x x x Test 03 R/W ADC Status 04 R RDY7 0 Checksum 05 R/W 16-Bit Checksum Register ADC ZS Calibration 06 R/W 24-Bit ADC Zero-Scale Calibration Register 800000h ADC FS 07 R/W 24-Bit ADC Full-Scale Register 800000h Channel Data1 08-0F R 16-/24-Bit Data Registers 8000h Channel ZS Calibration1 10–17 R/W 24-Bit Channel Zero-Scale Calibration Registers 800000h Channel FS Calibration1 18–1F R/W 24-Bits Channel Full-Scale Calibration Registers 200000h Channel Status1 20–27 CH2 CH1 Channel Number Channel Setup1 28–2F R/W BUF OFF COM1 COM0 Stat. Opt. ENABLE RNG2 0 0 0 0 0 0 Channel Conv. Time1 30–37 CHOP 1 FW (7-Bit Filter Word) 11h Mode2 38–3F R/W MD2 0 MD1 0 R R/W 1 24 Bits Manufacturing Test Register RDY6 0 RDY5 0 CH0 MD0 0 RDY4 0 RDY3 0 0/P0 0 RDY/P1 0 CLKDIS 0 DUMP 0 RDY2 0 RDY1 0 RDY0 0 NOREF 0 SIGN 0 OVR 0 RNG1 0 RNG0 0 Cont. RD 0 24/16 Bits CLAMP 0 0 NOTES 1 The three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the Communication register, specify the channel number of the register being accessed. 2 There is only one Mode register, although the Mode register can be accessed in one of eight address locations The address used to write the Mode register specifies the ADC channel on which the mode will be applied. Address 38h only must be used for reading from the Mode register. Table VIII. Operational Mode Summary Table IX. Input Range Summary MD2 MD1 MD0 Mode RNG2 RNG1 RNG0 Nominal Input Voltage Range 0 0 0 0 1 1 1 1 Idle Mode Continuous Conversion Mode Single Conversion Mode Power-Down (Standby) Mode ADC Zero-Scale Self Calibration For Future Use Channel Zero-Scale System Calibration Channel Full-Scale System Calibration 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 ± 2.5 V 0 V to +2.5 V ± 1.25 V 0 V to +1.25 V ± 0.625 V 0 V to +0.625 V 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 –12– REV. 0 AD7738 REGISTER DESCRIPTION The AD7738 is configurable through a series of registers. Some of them configure and control general AD7738 features, others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the Communication register, i.e., any communication to the AD7738 must start with a write to the Communication register, specifying which register will be subsequently read or written. Communications Register 8 Bits, Write-Only Register, Address 00h All communications to the part must start with a write operation to the Communications register. The data written to the Communications register determines whether the subsequent operation will be a read or write and to which register this operation will be directly placed. The digital interface defaults to expect write operation to the Communication register after power on, after reset, or after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low (Note that all of the parts including modulator, filter, interface and all registers are reset in this case). Remember to keep DIN low while reading 32 or more bits either in Continuous Read mode or with the DUMP bit and “24/16” bit in the Mode register set. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Mnemonic 0 R/W Bit Mnemonic Description 7 0 This bit must be zero for proper operation. 6 R/W A zero in this bit indicates that the next operation will be a write to a specified register. A one in this bit indicates that the next operation will be a read from a specified register. 5–0 Address Address specifying to which register the read or write operation will be directed. For channel specific registers the three LSBs, i.e., Bit 2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes to the Mode register, then the three LSBs specify the channel selected for operation determined by the Mode register value. See Table X. (The analog input’s configuration depends on the COM1, COM0 bits in the Channel Setup register.) Bit 0 6-Bit Register Address Table X. REV. 0 Bit 1 Bit 2 Bit 1 Bit 0 Channel Single Input Differential Input 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0–AIN1 AIN2–AIN3 AIN4–AIN5 AIN6–AIN7 AIN0–AIN1 AIN2–AIN3 AIN4–AIN5 AIN6–AIN7 –13– AD7738 I/O Port Register 8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value  40h The bits in this register are used to configure and access the digital I/O pin on the AD7738. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic P0 P1 P0 DIR P1 DIR RDY FN 0 0 SYNC Default P0 Pin P1 Pin 1 1 0 0 0 0 Bit Mnemonic Description 7 6 P0 P1 5 P0 DIR 4 P1 DIR 3 RDY FN When the AINCOM/P0 pin is configured as a digital output, the P0 bit determines the pin’s output level. When the P1 pin is configured as an output, the P1 bit determines the pin’s output level. When the P1 pin is configured as an input, the P1 bit reflects the current input level on the pin. When set to 1, the AINCOM/P0 pin is configured as an analog input. When set to 0, the AINCOM/P0 pin is configured as a digital output. This bit determines whether P1 pin is configured as an input or an output. When set to 1, the P1 pin will be a digital input; when reset to 0, the pin will be a digital output. This bit is used to control the function of the RDY pin on the AD7738. When this bit is reset to 0 the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will only go low if all enabled channels have unread data. 2, 1 0 These bits must be zero for proper operation. 0 SYNC This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC EN bit is set to 1, the SYNC pin can be used to synchronize the AD7738 modulator and digital filter with other devices in the system. Revision Register 8 Bits, Read-Only Register, Address 02h, Default Value 01h + Chip Revision  10h Bit Bit 7 Mnemonic Default Bit 6 Bit 5 Bit 4 Bit 3 Chip Revision Code x x x Bit 2 Bit 1 Bit 0 Chip Generic Code x 0 Bit Mnemonic Description 7–4 3–0 Chip Revision Code Chip Generic Code 4-Bit Factory Chip Revision Code On the AD7738, these bits will read back as 01h. 0 0 1 Test Register 24 Bits, Read/Write Register, Address 03h This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register. ADC Status Register 8 Bits, Read-Only Register, Address 04h, Default Value 00h In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding Channel Data register is updated and the corresponding RDY bit is set to 1. When the Channel Data register is read, the corresponding bit is reset to 0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the Channel Data register. Writing to the Mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress and all the bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of ADC Status register as defined by the RDY Function bit in the I/O Port register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 Default 0 0 0 0 0 0 0 0 The RDY0 bit corresponds to Channel 0, RDY1 bit to Channel 1, and so on. –14– REV. 0 AD7738 Checksum Register 16 Bits, Read/Write Register, Address 05h This register is described in the “AD7732/34/38 Checksum Register” Technical Note. ADC Zero Scale Calibration Register 24 Bits, Read/Write Register, Address 06h, Default Value 800000h The register holds the ADC Zero-Scale Calibration coefficient. The value in this register is used in conjunction with the value in the ADC Full-Scale Calibration register and corresponding Channel Zero-Scale and Channel Full-Scale Calibration registers to scale digitally all channels’ conversion results. The value in this register is updated automatically following the execution of an ADC ZeroScale ADC Self-Calibration. Writing to this register is possible in the Idle Mode only. See the calibration description for more details. ADC Full-Scale Register 24 Bits, Read/Write Register, Address 07h, Default Value 800000h The register holds the ADC Full-Scale coefficient. The user is advised not to change the default configuration of this register. Channel Data Registers 16/24 Bits, Read-Only Registers, Address 08h–0Fh, Default Width 16 Bits, Default Value 8000h These registers contain the most up-to-date conversion results corresponding to each analog input channel. The 16- or 24-bit data width can be configured by setting the “16/24” bit in the Mode register. The relevant RDY bit in the Channel Status register goes high when the result is updated. The RDY bit will return low once the Data register reading has begun. The RDY pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any Channel Data Register read operation is in progress when the new result is updated, then no update of the Data register occurs. This is to avoid getting corrupted data. Reading the Status registers can be associated with reading the Data registers in the Dump mode. Reading the Status registers is always associated with reading the Data registers in the Continuous Read mode. See the digital interface description for more details. Channel Zero-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 10h–17h, Default Value 800000h These registers hold the particular channel Zero-Scale Calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding Channel Full-Scale Calibration register, the ADC Zero-Scale Calibration register, and ADC Full-Scale Calibration register to scale digitally the particular channel conversion results. The value in this register is updated automatically following the execution of a Channel Zero-Scale System Calibration. The format of the Channel Zero-Scale Calibration register is a sign bit and 22 bits unsigned value. Writing this register is possible in the Idle Mode only. See the calibration description for more details. Channel Full-Scale Calibration Registers 24 Bits, Read/Write Registers, Address 18h–1Fh, Default Value 200000h These registers hold the particular channel Full-Scale Calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding Channel Zero-Scale Calibration register, the ADC Zero-Scale Calibration register, and ADC Full Scale Calibration register to scale digitally the particular channel conversion results. The value in this register is updated automatically following the execution of a Channel Full-Scale System Calibration. Writing this register is possible in the Idle mode only. See the calibration description for more details. REV. 0 –15– AD7738 Channel Status Registers 8 Bits, Read-Only Register, Address 20h–27h, Default Value 20h  Channel Number These registers contain individual channel status information and some general AD7738 status information. Reading the Status registers can be associated with reading the Data registers in the Dump mode. Reading the Status registers is always associated with reading the Data registers in the Continuous Read mode. See the Digital Interface Description section for more details. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN OVR Default Channel Number 0 0 0 0 0 Bit Mnemonic Description 7–5 CH2–CH0 These bits reflect the channel number. This can be used for current channel identification and easier operation in the Dump mode and Continuous Read mode. 4 0/P0 When the Status Option bit in the corresponding Channel Setup register is reset to 0, this bit is read as a zero. When the Status Option bit in set to 1, this bit reflects the state of the P0 output pin. 3 RDY/P1 When the Status Option bit in the corresponding Channel Setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC Status register. When the Status Option bit is set to 1, this bit reflects the state of the P1 pin whether it is configured as an input or output. 2 NOREF This bit indicates the reference input status. If the voltage between the REFIN+ and REFIN– pins is less than the NOREF trigger voltage, then the NOREF bit goes to a 1. 1 SIGN The voltage polarity at the analog input. Will be 0 for a positive voltage; will be 1 for a negative voltage. 0 OVR This bit reflects either overrange or underrange on an analog input. The bit is set to 1 when the analog input voltage goes over or under the Nominal Voltage Range. See the Analog Inputs Extended Voltage Range section. –16– REV. 0 AD7738 Channel Setup Registers 8 Bits, Read/Write Register, Address 28h–2Fh, Default Value 00h These registers are used to configure the selected channel, its input voltage range, and set up the corresponding Channel Status register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic BUF OFF COM1 COM0 Stat. Opt. ENABLE RNG2 RNG1 RNG0 Default 0 0 0 0 0 0 0 0 Bit Mnemonic 7 BUF OFF Description 6, 5 Buffer Off. If reset to 0, then internal buffer is enabled. Only operation with internal buffer enabled is recommended. COM1, COM0 Analog Input Configuration. See Table XI. 4 Stat. Opt. Status Option. When this bit is set to 1, the P1 bit in the Status Channel register will reflect the state of the P1 pin. When this bit is reset to 0, the P1 bit in the Status Channel register bit will reflect the channel corresponding RDY bit in the ADC Status register. 3 ENABLE Channel Enable. Set this bit to 1 to enable the channel in the Continuous Conversion mode. A single conversion will take place regardless of this bit value. 2–0 RNG2–0 The Channel Input Voltage Range. See Table XII. Table XI. Channel COM1 0 COM0 0 0 1 2 3 4 5 6 7 AIN0–AINCOM AIN1–AINCOM AIN2–AINCOM AIN3–AINCOM AIN4–AINCOM AIN5–AINCOM AIN6–AINCOM AIN7–AINCOM Table XII. COM1 1 COM0 1 AIN0–AIN1 AIN2–AIN3 AIN4–AIN5 AIN6–AIN7 AIN0–AIN1 AIN2–AIN3 AIN4–AIN5 AIN6–AIN7 RNG2 RNG1 RNG0 Nominal Input Voltage Range 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 ± 2.5 V 0 V to +2.5 V ± 1.25 V 0 V to +1.25 V ± 0.625 V 0 V to +0.625 V Channel Conversion Time Registers 8 Bits, Read/Write Register, Address 30h–37h, Default Value 91h The Conversion Time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC. Bit Bit 7 Mnemonic CHOP Default 1 Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FW (7-Bit Filter Word) 11h Mnemonic Description 7 CHOP Chop Enable Bit. Set to 1 to apply chopping mode for a particular channel. 6–0 FW CHOP = 1, Single Conversion or Continuous Conversion with one channel enabled. Conversion Time (µs) = (FW  128 + 248)/MCLK Frequency (MHz), the FW in range of 2 to 127. CHOP = 1, Continuous Conversion with two or more channels enabled. Conversion Time (µs) = (FW  128 + 249)/MCLK Frequency (MHz), the FW in range of 2 to 127. CHOP = 0, Single Conversion or Continuous Conversion with one channel enabled. Conversion Time (µs) = (FW  64 + 206)/MCLK Frequency (MHz), the FW in range of 3 to 127. CHOP = 0, Single Conversion or Continuous Conversion with two or more channels enabled. Conversion Time (µs) = (FW  64 + 207)/MCLK Frequency (MHz), the FW in range of 3 to 127. REV. 0 –17– AD7738 Mode Register 8 Bits Read/Write Register, Address 38h–3Fh, Default Value 00h The Mode register configures the part and determines the part’s operating mode. Writing to the Mode register will clear the ADC Status register, set the RDY pin to logic high level, exit all current operations, and start the mode specified by the Mode bits. The AD7738 contains only one Mode register. The three LSBs of the address used for writing to the Mode register specify the channel selected for operation determined by the MD2 to MD0 bits. The address 38h only must be used for reading from the Mode register. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic MD2 MD1 MD0 CLKDIS DUMP CONT RD 24/16 BIT CLAMP Default 0 0 0 0 0 0 0 0 Bit Mnemonic Description 7–5 MD2–MD0 Mode Bits. These three bits determine the AD7738 operation mode. Writing a new value to the Mode bits will exit the part from the mode in which it has been operating and place it in the new requested mode immediately. The function of the Mode bits is described in more detail below. 4 CLKDIS Master Clock Output Disable. When this bit is set to 1 the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7738 continues to have internal clocks and will convert normally regardless of CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7738 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7738 digital interface can still be accessed using the SCLK pin. 3 DUMP DUMP Mode. When this bit is reset to 0, the Channel Status register and Channel Data register will be addressed and read separately. When the DUMP bit is set to 1, the Channel Status register will be followed immediately by a read of the Channel Data register regardless of whether the Status or Data register has been addressed through the Communication register. The Continuous Read mode will always be a “Dump Mode” reading of the Channel Status and Data register regardless of the Dump Bit value. See the Digital Interface Description section for more details. 2 CONT RD When this bit is set to 1, the AD7738 will operate in the Continuous Read mode. See the Digital Interface Description section for more details. 1 24/16 BIT The Channel Data Register Data Width Selection Bit. When set to 1, the Channel Data registers will be 24 bits wide. When set to 0, then the Channel Data registers will be 16 bits wide. 0 CLAMP This bit determines the Channel Data register’s value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the Channel Data register will be digitally clamped either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the Data registers reflect the analog input voltage even outside the nominal voltage range. See the Analog Inputs Extended Voltage Range section. MD2 MD1 MD0 Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Idle Mode Continuous Conversion Mode Single Conversion Mode Power Down (Standby) Mode ADC Zero-Scale Self Calibration For Future Use Channel Zero-Scale System Calibration Channel Full-Scale System Calibration Address Used for Mode Register Write Specify The First Channel to Start Converting Channel to Convert Channel Conversion Time Used for the ADC Self-Calibration Channel to Calibrate Channel to Calibrate –18– REV. 0 AD7738 MD2 MD1 MD0 Operating Mode 0 0 0 Idle Mode The default mode after Power-On or Reset. The AD7738 returns to this mode automatically after any calibration or after a single conversion. 0 0 1 Continuous Conversion Mode The AD7738 performs a conversion on the specified channel. After the conversion is complete, the relevant Channel Data register and Channel Status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7738 continues converting on the next enabled channel. The AD7738 will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by corresponding Channel Conversion Time registers. 0 1 0 Single Conversion Mode The AD7738 performs a conversion on the specified channel. After the conversion is complete, the relevant Channel Data register and Channel Status register are updated, the relevant RDY bit in the ADC status register is set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. Requesting a single conversion ignores the Channel Setup registers’ Enable bits and a conversion will be performed even if that channel is disabled. 0 1 1 Power-Down (Standby) Mode The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7738 digital interface can still be accessed. The CLKDIS bit works separately, the MCLKOUT mode is not affected by Power-Down (Standby) mode. 1 0 0 ADC Zero-Scale Self-Calibration Mode A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is complete, the contents of the ADC Zero-Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and the AD7738 returns to the Idle mode. 1 0 1 For Future Use 1 1 0 Channel Zero-Scale System Calibration Mode A zero-scale system calibration is performed on the selected channel. An external system zero-scale voltage should be provided at the AD7738 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding Channel Zero Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. 1 1 1 Channel Full-Scale System Calibration Mode A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7738 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding Channel Full-Scale Calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2, MD1, and MD0 bits are reset, and AD7738 returns to the Idle mode. REV. 0 –19– AD7738 DIGITAL INTERFACE DESCRIPTION Hardware Relinquish Time in the Timing Characteristics). The AD7738 cannot operate in the Continuous Read mode in 2-wire serial interface configuration. The AD7738 serial interface can be connected to the host device via the serial interface in several different ways. All the digital interface inputs are Schmitt-Triggered. Therefore, the AD7738 interface features higher noise immunity and the AD7738 can be easily isolated from the host system via optocouplers. The CS pin can be used to select the AD7738 as one of several circuits connected to the host serial interface. When the CS is high, the AD7738 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state. When the CS signal is not used, connect the CS pin to DGND. Figure 5 outlines some of the possible host device interfaces: (a) SPI without using the CS signal, (b) DSP interface, and (c) 2-wire configuration. The RDY pin can be either polled for high to low transition or can drive the host device interrupt input to indicate that the AD7738 has finished the selected operation and/or new data from the AD7738 are available. The host system can also wait a designated time after a given command is written to the device before reading. Alternatively, the AD7738 status can be polled. When the RDY pin is not used in the system, it should be left as an open circuit. (Note that the RDY pin is always an active digital output, i.e., never goes into a high impedance state). Reset The AD7738 can be reset by the RESET pin or by writing a reset sequence to the AD7738 serial interface. The reset sequence is N ⫻ “0” + 32 ⫻ “1”, which could be the data sequence 00h + FFh + FFh + FFh + FFh in a byte oriented interface. The AD7738 also features a power-on reset with a trip point of 2 V and goes to the defined default state after power on. The RESET pin can be used to reset the AD7738. When not used, connect this pin to DVDD. It is the system designer’s responsibility to prevent an unwanted write operation to the AD7738. The unwanted write operation could happen when a spurious clock appears on the SCLK while the CS pin is low. It should be noted that on system power-on, if the AD7738 interface signals are floating or undefined, the part can be inadvertently configured into an unknown state. This could be easily overcome by initiating either a HW reset event or a 32 ones reset sequence as the first step in the system configuration. The AD7738 interface can be reduced to just two wires connecting DIN and DOUT pins to a single bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction with reference to the AD7738 timing specification (see the Bus DVDD AD7738 DVDD DVDD 68HC11 RESET SS AD7738 DVDD AD7738 ADSP-2105 RESET 8xC51 RESET SCLK SCK SCLK SCLK SCLK P3.1/TXD DOUT MISO DOUT DR DOUT P3.0/RXD DIN MOSI DIN RDY INT CS DIN DT RDY INT CS TFS CS RFS DGND DGND a. b. c. Figure 5. AD7738 to Host Device Possible Interface Access the AD7738 Registers CS All communications to the part start with a write operation to the Communications register followed by either reading or writing the addressed register. SCLK DIN In a simultaneous read-write interface (such as SPI), write “0” to the AD7738 while reading data. DOUT WRITE COMMUNICATIONS REGISTER Figure 6 shows the AD7738 interface read sequence for the ADC Status register. READ ADC STATUS REGISTER Figure 6. The Serial Interface Signals—Register Access –20– REV. 0 AD7738 Single Conversion and Reading Data Dump Mode When the Mode register is being written, the ADC Status Byte is cleared and the RDY pin goes high regardless of its previous state. When the single conversion command is written to the Mode register, the ADC starts the conversion on the channel selected by the address of the Mode register. After the conversion is completed, the Data register is updated, the Mode register is changed to Idle mode, the relevant RDY bit is set, and the RDY pin goes low. The RDY bit is reset and the RDY pin returns high when the relevant Channel Data register is being read. When the DUMP bit in the Mode register is set to 1, the Channel Status register will be read immediately by a read of the Channel Data register regardless of whether the Status or the Data register has been addressed through the Communication register. The DIN pin should not be high while reading 24-bit data in Dump mode. Otherwise the AD7738 will be reset. Figure 7 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin low, and reading the Channel 0 Data register. Figure 8 shows the digital interface signals executing a single conversion on Channel 0, waiting for for the RDY pin low, and reading the Channel 0 Status register and Data register in the Dump mode. CS SCLK 40h 38h DIN 48h DOUT (00h) (00h) DATA DATA RDY WRITE COMMUNICATIONS REGISTER WRITE MODE REGISTER CONVERSION TIME WRITE COMMUNICATIONS REGISTER READ DATA REGISTER Figure 7. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading CS SCLK DIN 38h 48h 48h DOUT (00h) (00h) (00h) CH. STAT DATA DATA RDY WRITE COMMUNICATIONS REGISTER WRITE MODE REGISTER CONVERSION TIME WRITE COMMUNICATIONS REGISTER READ CHANNEL STATUS READ DATA REGISTER Figure 8. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode REV. 0 –21– AD7738 If an ADC conversion result has not been read before a new ADC conversion is completed, then the new result will overwrite the previous one. The relevant RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles (~26.5 µs), indicating when the Data register is updated and the previous conversion data is lost. Continuous Conversion Mode When the Mode register is being written, the ADC Status Byte is cleared and the RDY pin goes high regardless of its previous state. When the continuous conversion command is written to the Mode register, the ADC starts conversion on the channel selected by the address of the Mode register. After the conversion is complete, the relevant Channel Data register and Channel Status register are updated, the relevant RDY bit in the ADC Status register is set, and the AD7738 continues converting on the next enabled channel. The AD7738 will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels’ conversion times, set by corresponding Channel Conversion Time registers. If the Data register is being read as an ADC conversion completes, then the Data Register will not be updated with the new result (to avoid data corruption) and the new conversion data is lost. The RDY bit is reset when the relevant Channel Data register is being read. The behavior of the RDY pin depends on the RDYFN bit in the I/O Port register. When RDYFN bit is 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1 the RDY pin will only go low if all enabled channels have unread data. START CONTINUOUS CONVERSION READ DATA CH0 Figure 9 shows the digital interface signals sequence for the Continuous Conversion mode with Channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the Data Register is read after each conversion. Figure 10 shows a similar sequence, but with the RDYFN bit set to 1. The RDY pin goes low and the Data register is read after all conversions are completed. Figure 11 shows the RDY pin when no data are read from the AD7738. READ DATA CH1 READ DATA CH0 READ DATA CH1 SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 9. Continuous Conversion, CH0 and CH1, RDYFN = 0 START CONTINUOUS CONVERSION SERIAL INTERFACE READ READ DATA DATA CH0 CH1 READ READ DATA DATA CH0 CH1 RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 10. Continuous Conversion, CH0 and CH1, RDYFN = 1 START CONTINUOUS CONVERSION SERIAL INTERFACE RDY CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION CH1 CONVERSION CH0 CONVERSION Figure 11. Continuous Conversion, CH0 and CH1, No Data Read –22– REV. 0 AD7738 CS SCLK DIN 38h 48h 48h DOUT 00h 00h 00h 00h 00h 00h CH.STAT. DATA DATA CH.STAT. DATA DATA RDY WRITE COMM. REGISTER WRITE CONVERSION WRITE MODE ON CH0 COMM. REGISTER COMPLETE REGISTER READ CH0 STATUS READ CH0 DATA REGISTER CONVERSION ON CH1 COMPLETE READ CH1 STATUS READ CH1 DATA REGISTER Figure 12. Continuous Conversion CH0 and CH1, Continuous Read Note that the Continuous Read mode is “Dump Mode” reading of the Channel Status and Data register regardless of the Dump bit value. Use the Channel bits in the Channel Status register to check/recognize which channel data is actually being shifted out. The AD7738 contains a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma-delta modulator. With the internal buffer enabled, the analog inputs feature relatively high input impedance. However, if chopping is enabled and/or when switching between channels, there is a dynamic current charging the capacitance of the multiplexer, capacitance of the pins, and any additional capacitance connected to the MUXOUT. In typical configurations with MUXOUT connected directly to the ADCIN, this capacitance could be approximately 20 pF. The AD7738 has been designed to provide adequate settling time after a multiplexer switch and before the actual sampling starts only if the analog inputs resistive source impedance does not exceed 10 kΩ. Note that the last completed conversion result is being read. Therefore, the RDYFN bit in the I/O Port register should be 0, and reading the result should always start before the next conversion is completed. An RC connected to the analog inputs may convert the dynamic charging currents to a dc voltage and cause additional gain or offset errors. The recommended low-pass RC filter on the AD7738 analog inputs is 20 Ω and 100 nF. The AD7738 will stay in Continuous Read mode as long as the DIN pin is low while the CS pin is low. Therefore, write 0 to the AD7738 while reading in Continuous Read mode. To exit Continuous Read mode, take the DIN pin high for at least 100 ns after a read is complete. (Write “80h” to the AD7738 to exit continuous reading.) The multiplexer output and the ADC input are pinned out externally. This facilitates shared signal conditioning between the multiplexer and the ADC. Please note that if chop is enabled and/or when switching between channels, any circuit connected between MUXOUT and ADCIN should be fully settled within the settling time provided by the AD7738. See the Multiplexer, Conversion, and Data Output Timing section. Continuous Read (Continuous Conversion) Mode When the Continuous RD bit in the Mode register is set, the first write “48h” to the communication register starts the Continuous Read mode. As shown in Figure 12, subsequent accesses to the part sequentially reads the Channel Status and Data registers of the last completed conversion without any further configuration of the Communication register being required. Note that the Continuous Conversion bit in the Mode register should be set when entering the Continuous Read mode. The Continuous RD bit in the Mode register is not changed by taking the DIN pin high. Therefore, the next write “48h” starts the Continuous Read mode again. To completely stop the continuous read mode, write to the Mode register to clear the Continuous RD bit. CIRCUIT DESCRIPTION The AD7738 is a sigma-delta A/D converter, intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, PLC, and DSC. It contains a multiplexer, an input buffer, a sigma-delta (or charge-balancing) ADC, digital filter, clock oscillator, digital I/O port, and a serial communications interface. Analog Front End The AD7738 has nine analog input pins connected to the ADC through the internal multiplexer. The analog front end can be configured as eight single-ended inputs four differential inputs, or any combination of these. Selection of ADC inputs is determined via the COM0 and COM1 bits in the Channel Setup registers. REV. 0
- ADC The AD7738 core consists of a charge balancing sigma-delta modulator and a digital filter. The architecture is optimized for fast fully settled conversion. This allows for fast channel-to-channel switching while maintaining inherently excellent linearity, high resolution, and low noise. Chopping With chopping enabled, the multiplexer repeatedly reverses the ADC inputs. Every output data result is then calculated as an average of two conversions, the first with positive and the second with negative offset term included. This effectively removes any offset error of the input buffer and sigma-delta modulator, resulting in excellent dc offset and offset drift specifications. Figure 13 shows the channel signal chain with chopping enabled. –23– AD7738 MULTIPLEXER MUXOUT ADCIN BUFFER
- AIN(+) AIN(– ) CHOP fMCLK/2 + SCALING ARITHMETIC - (CALIBRATIONS) DIGITAL FILTER MODULATOR DIGITAL INTERFACE OUTPUT DATA AT THE SELECTED DATA RATE CHOP fMCLK/2 Figure 13. Channel Signal Chain Diagram with Chopping Enabled channel conversion cycle is finished. If in Continuous Conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel. Multiplexer, Conversion, and Data Output Timing The specified “Conversion Time” includes one or two “Settling” and “Sampling” periods and a “Scaling” time. With chopping enabled (Figure 14), a conversion cycle starts with a “Settling” time of 43 or 44 MCLK cycles (~7 µs with 6.144 MHz MCLK) to allow the circuits following the multiplexer to settle. Then the sigma-delta modulator samples the analog signals, and the digital filter processes the digital data stream. The “Sampling” time depends on FW, i.e., on the Channel Conversion Time register contents. After another “Settling” of 42 MCLK cycles (~6.8 µs), the “Sampling” time is repeated with a reversed (chopped) analog input signal. Then, during the “Scaling” time of 163 MCLK cycles (~26.5 µs), the two results from the digital filter are averaged, scaled using the Calibration registers, and written into the Channel Data register. With chopping disabled (Figure 15), there is only one “Sampling” time preceded by a “Settling” time of 43 or 44 MCLK cycles and followed by a “Scaling” time of 163 MCLK cycles. The RDY pin goes high during the “Scaling time” regardless of its previous state. The relevant RDY bit is set in the ADC Status register, and in the Channel Status register the RDY pin goes low when the Channel Data register is updated and the MULTIPLEXER -CHANNEL 0 Note, that every channel can be configured independently for conversion time and chopping mode. The overall cycle and effective per channel data rate depends on all enabled channel settings. Frequency Response The sigma-delta modulator runs at 1/2 of MCLK frequency, which is effectively the sampling frequency. Therefore, the Nyquist frequency is 1/4 of the MCLK frequency. The digital filter, in association with the modulator, features frequency response of a first order low-pass filter. The –3 dB point is close to the frequency of 1/Channel Conversion Time. The roll-off is –20 dB/dec up to the Nyquist frequency. If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response features notches close to the frequency of 1/Channel Conversion Time. The top envelope is again the ADC response of –20 dB/dec. The typical frequency response plots are in Figure 16. The plots are normalized to 1/Channel Conversion Time. +CHANNEL 1 +CHANNEL 2 -CHANNEL 1 RDY SETTLING TIME SAMPLING TIME SETTLING TIME SAMPLING TIME SCALING TIME CONVERSION TIME Figure 14. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled MULTIPLEXER +CHANNEL 0 +CHANNEL 1 +CHANNEL 2 RDY SETTLING TIME SAMPLING TIME SCALING TIME CONVERSION TIME Figure 15. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled –24– REV. 0 AD7738 0 0 –10 –10 CHOP = 0 CHOP = 1 –20 GAIN – dB GAIN – dB –20 –30 –30 –40 –40 –50 –50 –60 0.1 1 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY  CONVERSION TIME) –60 0.1 10 1 10 100 NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY  CONVERSION TIME) 1000 b. Chopping Disabled a. Chopping Enabled Figure 16. Typical ADC Frequency Response Analog Inputs Voltage Range Table XIII. Input Voltage Range 1.25 V, 16 Bits, CLAMP = 0 The absolute input voltage range with input the buffer enabled is restricted from AGND + 200 mV to AVDD – 300 mV, which also places restrictions on the common-mode range. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded, otherwise there will be degradation in linearity performance. The analog inputs on the AD7738 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages with respect to system ground on its analog inputs. Unipolar and bipolar signals on the AIN(+) input are referenced to the voltage on the respective AIN(–) input. For example, if AINCOM is 2.5 V and CH0 is configured to measure AIN0 – AINCOM, 0 V to 1.25 V, the input voltage range on the AIN0 input is 2.5 V to 3.75 V. If CH0 is configured to measure AIN0 – AINCOM, ± 1.25 V, the input voltage range on the AIN0 input is 1.25 V to 3.75 V. The AD7738 output data code span corresponds to the nominal input voltage range. However, the correct operation of the ADC is guaranteed within the min/max input voltage range. As shown in Tables XIII and XIV, when CLAMP = 0, the data reflect the analog input voltage outside the nominal voltage range. In this case, the SIGN and OVR bits in the Channel Status register should be considered along with the Data register value to decode the actual conversion result. REV. 0 Data (Hex) SIGN OVR +1.45000 +1.25008 +1.25004 +1.25000 +0.00004 0.00000 –0.00004 –1.25000 –1.25004 –1.25008 –1.45000 147B 0001 0000 FFFF 8001 8000 7FFF 0000 FFFF FFFE EB85 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 Table XIV. Input Voltage Range 0 V to 1.25 V, 16 Bits, CLAMP = 0 Analog Inputs Extended Voltage Range When the CLAMP bit of the Mode register is set to 1, the Channel Data register will be digitally clamped either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range. Input (V) Input (V) Data (Hex) SIGN OVR 1.45000 1.25004 1.25002 1.25000 0.00002 0.00000 –0.00002 28F5 0001 0000 FFFF 0001 0000 0000 0 0 0 0 0 0 1 1 1 1 0 0 0 1 –25– AD7738 Voltage Reference Inputs Reference Detect The AD7738’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage for specified operation is 2.5 V. Both reference inputs feature a high impedance, dynamic load. Because the input impedance on each reference input is dynamic, external resistance/capacitance combinations may result in gain errors on the part. The AD7738 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the REFIN(+) and REFIN(–) pins goes below the NOREF Trigger Voltage (0.5 V typ) and the AD7738 is performing conversion, the NOREF bit in the Channel Status register is set. I/O Port The AD7738 Pin SYNC/P1 can be used as a general-purpose digital I/O pin or to synchronize the AD7738 with other devices in the system. When the SYNC bit in the I/O Port register is set and the SYNC pin is low, the AD7738 doesn’t process any conversion. If it is put into single conversion mode, Continuous Conversion mode, or any Calibration mode, the AD7738 waits until the SYNC pin goes high and then starts operation. This allows the user to start conversion from a known point in time, i.e., the rising edge of the SYNC pin. The output noise performance outlined in Tables I to VI is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7738. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7738. Recommended reference voltage sources for the AD7738 include the ADR421, AD780, REF43, and REF192. It is generally recommended to decouple the output of these references to further reduce the noise level. AVDD DVDD MUXOUT - ADCIN 10F + 0.1F AVDD DVDD MCLKIN 20 AIN0 CLOCK GENERATOR 0.1F + 0.1F 6.144MHz MCLKOUT 33pF ANALOG INPUTS DVDD BUFFER AIN7 RESET 0.1F 20 AINCOM AD7738 0.1F AVDD VIN ADR421 VOUT REFIN(+) SERIAL INTERFACE AND CONTROL LOGIC 10F 0.1F GND 0.1F SCLK DIN DOUT HOST SYSTEM RDY CS REFIN(–) + 33pF 24-BIT
- ADC MUX 20 10F AGND DGND Figure 17. Typical Connection for the AD7738 Application –26– REV. 0 AD7738 CALIBRATION ADC Zero-Scale Self-Calibration The AD7738 provides zero-scale self-calibration, and zero and full system calibration capability, which can effectively reduce the offset error and gain error to the order of the noise. After each conversion, the ADC conversion result is scaled using the ADC Calibration Registers and the relevant Channel Calibration registers before being written to the Data register. See the equations shown below. The ADC Zero-Scale Self-Calibration can effectively remove the offset error in Chopping Disabled mode. If repeated after a temperature change, it can also remove the offset drift error in Chopping Disabled mode. The zero-scale self-calibration is performed on internally shorted ADC inputs. The negative Analog Input terminal on the selected channel is used to set the ADC ZS Calibration common mode. Therefore, either the negative terminal on selected differential pair or AINCOM on single-ended channel configuration should be driven to a proper commwon-mode voltage. For unipolar ranges: Data = ((ADC result – ADC ZS Cal. reg.)  ADC FS reg./ 200000h – Ch. ZS Cal. reg.)  Ch. FS Cal. reg./200000h It is strongly recommended that the ADC ZS Calibration register should only be updated as part of a zero-scale self-calibration. For bipolar ranges: Data = ((ADC result – ADC ZS Cal. reg.)  ADC FS reg./ 400000h + 800000h – Ch. ZS Cal. reg.)  Ch. FS Cal. reg./ 200000h Per Channel System Calibration If the per channel system calibrations are used, these should be initiated in the following order: first a Channel ZS System Calibration followed by a Channel FS System Calibration. Where the ADC result is in the range of 0 to FFFFFFh. Note that the Channel ZS Calibration register has the format of a sign bit + 22 bits Channel offset value. The System Calibration is affected by the ADC ZS and FS Calibration registers; therefore, if both Self-Calibration and System Calibration are used in a system, an ADC Self-Calibration cycle should be performed first followed by a System Calibration cycle. It is strongly recommended that the user does not change the ADC FS register. To start any calibration, write the relevant mode bits to the AD7738 Mode register. After the calibration is complete, the contents of the corresponding Calibration registers are updated, all RDY bits in the ADC Status register are set, the RDY pin goes low, and the AD7738 reverts to Idle mode. The calibration duration is the same as conversion time configured on the selected channel. The longer conversion time gives less noise and yields a more exact calibration. Therefore, use at least the default conversion time to initiate any calibration. REV. 0 While executing a system calibration, the fully settled system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs. The per channel Calibration registers can be read, stored, or modified and written back to the AD7738. Note, when writing the Calibration registers the AD7738 must be in the idle mode. Note that outside the specified calibration range, the calibration is possible but the performance may degrade. (See the System Calibration section in the specification pages of this data sheet.) –27– AD7738 OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) C03072–0–11/02(0) Dimensions shown in millimeters 9.80 9.70 9.60 28 15 4.50 4.40 4.30 1 6.40 BSC 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 PRINTED IN U.S.A. COMPLIANT TO JEDEC STANDARDS MO-153AE –28– REV. 0