8-Channel, 24-Bit,
Simultaneous Sampling ADC
AD7770
Data Sheet
FEATURES
8-channel, 24-bit simultaneous sampling analog-to-digital
converter (ADC)
Single-ended or true differential inputs
Programmable gain amplifier (PGA) per channel (gains of
1, 2, 4, and 8)
Low dc input current
±4 nA (differential) and ±8 nA (single-ended)
Up to 32 kSPS output data rate (ODR) per channel
Programmable ODRs and bandwidth
Sample rate converter (SRC) for coherent sampling
Sampling rate resolution up to 15.2 × 10−6 SPS
Low latency sinc3 filter path
Adjustable phase synchronization
Internal 2.5 V reference
Two power modes optimizing power dissipation and
performance: high resolution mode and low power mode
Low resolution successive approximation register (SAR) ADC
for system and chip diagnostics
Power supply
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
Digital input/output (I/O) supply: 1.8 V to 3.6 V
Performance temperature range: −40°C to +105°C
Functional temperature range: −40°C to +125°C
Performance
Combined ac and dc performance
103 dB dynamic range at 32 kSPS in high resolution mode
−109 dB total harmonic distortion (THD)
±9 ppm of FSR integral nonlinearity (INL)
±15 µV offset error
±0.1% FS gain error
±10 ppm/°C typical temperature coefficient
APPLICATIONS
Protection relays
General-purpose data acquisition
Industrial process control
GENERAL DESCRIPTION
The AD7770 is an 8-channel, simultaneous sampling ADC. Eight
full sigma-delta (Σ-Δ) ADCs are on chip. The AD7770 provides
a low input current to allow direct sensor connection. Each input
channel has a programmable gain stage allowing gains of 1, 2, 4,
and 8 to map lower amplitude sensor outputs into the full-scale
ADC input range, maximizing the dynamic range of the signal
chain. The AD7770 accepts a VREF voltage from 1 V up to 3.6 V.
Rev. E
The analog inputs accept unipolar (0 V to VREF) or true bipolar
(±VREF/2) analog input signals with 3.3 V or ±1.65 V analog
supply voltages, respectively for PGAGAIN = 1. The analog inputs
can be configured to accept true differential, pseudo differential,
or single-ended signals to match different sensor output
configurations.
Each channel contains a PGA, an ADC modulator and a
sinc3, low latency digital filter. An SRC is provided to allow fine
resolution control over the AD7770 ODR. This control can be
used in applications where the ODR resolution is required to
maintain coherency with 0.01 Hz changes in the line frequency.
The SRC is programmable through the serial port interface (SPI).
The AD7770 implements two different interfaces: a data output
interface and SPI control interface. The ADC data output interface
is dedicated to transmitting the ADC conversion results from
the AD7770 to the processor. The SPI writes to and reads from
the AD7770 configuration registers and for the control and
reading of data from the SAR ADC. The SPI can also be
configured to output the Σ-Δ conversion data.
The AD7770 includes a 12-bit SAR ADC. This ADC can be
used for AD7770 diagnostics without having to decommission
one of the Σ-Δ ADC channels dedicated to system measurement
functions. With the use of an external multiplexer, which can be
controlled through the three general-purpose input/output pins
(GPIOs), and signal conditioning, the SAR ADC can validate
the Σ-Δ ADC measurements in applications where functional
safety is required. In addition, the AD7770 SAR ADC includes
an internal multiplexer to sense internal nodes.
The AD7770 contains a 2.5 V reference and reference buffer. The
reference has a typical temperature coefficient of 10 ppm/°C.
The AD7770 offers two modes of operation: high resolution mode
and low power mode. High resolution mode provides a higher
dynamic range while consuming 10.75 mW per channel; low
power mode consumes just 3.37 mW per channel at a reduced
dynamic range specification.
The specified operating temperature range is −40°C to +105°C,
although the device is operational up to +125°C.
Note that throughout this data sheet, certain terms are used to
refer to either the multifunction pins or a range of pins. The multifunction pins, such as DCLK0/SDO, are referred to either by the
entire pin name or by a single function of the pin, for example,
DCLK0, when only that function is relevant. In the case of ranges
of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B,
AVSS2A, AVSS2B, AVSS3, and AVSS4.
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AD7770
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Σ-∆ Output Data............................................................................. 51
Applications ....................................................................................... 1
ADC Conversion Output—Header and Data ........................ 51
General Description ......................................................................... 1
Sample Rate Converter (SRC) (SPI Control Mode) .............. 52
Revision History ............................................................................... 4
Data Output Interface ................................................................ 53
Functional Block Diagram .............................................................. 5
Calculating the CRC Checksum .............................................. 58
Specifications..................................................................................... 6
Register Summary .......................................................................... 60
DOUTx Timing Characterististics ........................................... 10
Register Details ............................................................................... 64
SPI Timing Characterististics ................................................... 11
Channel 0 Configuration Register ........................................... 64
Synchronization Pins and Reset Timing Characteristics ...... 12
Channel 1 Configuration Register ........................................... 64
SAR ADC Timing Characterististics ....................................... 13
Channel 2 Configuration Register ........................................... 65
GPIO SRC Update Timing Characterististics......................... 13
Channel 3 Configuration Register ........................................... 65
Absolute Maximum Ratings.......................................................... 14
Channel 4 Configuration Register ........................................... 66
Thermal Resistance .................................................................... 14
Channel 5 Configuration Register ........................................... 66
ESD Caution ................................................................................ 14
Channel 6 Configuration Register ........................................... 67
Pin Configuration and Function Descriptions ........................... 15
Channel 7 Configuration Register ........................................... 67
Typical Performance Characteristics ........................................... 18
Disable Clocks to ADC Channel Register .............................. 68
Terminology .................................................................................... 31
Channel 0 Sync Offset Register ................................................ 68
Theory of Operation ...................................................................... 33
Channel 1 Sync Offset Register ................................................ 68
Analog Inputs .............................................................................. 33
Channel 2 Sync Offset Register ................................................ 68
Transfer Function ....................................................................... 34
Channel 3 Sync Offset Register ................................................ 69
Core Signal Chain....................................................................... 35
Channel 4 Sync Offset Register ................................................ 69
Capacitive PGA........................................................................... 35
Channel 5 Sync Offset Register ................................................ 69
Internal Reference and Reference Buffers ............................... 35
Channel 6 Sync Offset Register ................................................ 69
Integrated LDOs ......................................................................... 36
Channel 7 Sync Offset Register ................................................ 69
Clocking and Sampling.............................................................. 36
General User Configuration 1 Register ................................... 70
Digital Reset and Synchronization Pins .................................. 36
General User Configuration 2 Register ................................... 70
Digital Filtering........................................................................... 37
General User Configuration 3 Register ................................... 71
Shutdown Mode.......................................................................... 37
Data Output Format Register ................................................... 72
Controlling the AD7770 ............................................................ 38
Main ADC Meter and Reference Mux Control Register ...... 73
Pin Control Mode ....................................................................... 38
Global Diagnostics Mux Register............................................. 74
SPI Control .................................................................................. 40
GPIO Configuration Register ................................................... 74
Digital SPI .................................................................................... 43
GPIO Data Register.................................................................... 75
RMS Noise and Resolution............................................................ 46
Buffer Configuration 1 Register ............................................... 75
High Resolution Mode............................................................... 46
Buffer Configuration 2 Register ............................................... 75
Low Power Mode ........................................................................ 46
Channel 0 Offset Upper Byte Register..................................... 76
Diagnostics and Monitoring ......................................................... 47
Channel 0 Offset Middle Byte Register ................................... 76
Self Diagnostics Error ................................................................ 47
Channel 0 Offset Lower Byte Register ..................................... 76
Monitoring Using the AD7770 SAR ADC (SPI Control
Mode) ........................................................................................... 48
Channel 0 Gain Upper Byte Register ....................................... 76
Σ-Δ ADC Diagnostics (SPI Control Mode) ............................ 50
Channel 0 Gain Middle Byte Register ..................................... 76
Channel 0 Gain Lower Byte Register ....................................... 77
Rev. E | Page 2 of 97
Data Sheet
AD7770
Channel 1 Offset Upper Byte Register .....................................77
Channel 6 Gain Lower Byte Register ....................................... 84
Channel 1 Offset Middle Byte Register ....................................77
Channel 7 Offset Upper Byte Register ..................................... 84
Channel 1 Offset Lower Byte Register .....................................77
Channel 7 Offset Middle Byte Register .................................... 84
Channel 1 Gain Upper Byte Register........................................78
Channel 7 Offset Lower Byte Register ..................................... 85
Channel 1 Gain Middle Byte Register ......................................78
Channel 7 Gain Upper Byte Register ....................................... 85
Channel 1 Gain Lower Byte Register........................................78
Channel 7 Gain Middle Byte Register ...................................... 85
Channel 2 Offset Upper Byte Register .....................................78
Channel 7 Gain Lower Byte Register ....................................... 85
Channel 2 Offset Middle Byte Register ....................................78
Channel 0 Status Register .......................................................... 86
Channel 2 Offset Lower Byte Register .....................................79
Channel 1 Status Register .......................................................... 86
Channel 2 Gain Upper Byte Register........................................79
Channel 2 Status Register .......................................................... 87
Channel 2 Gain Middle Byte Register ......................................79
Channel 3 Status Register .......................................................... 87
Channel 2 Gain Lower Byte Register........................................79
Channel 4 Status Register .......................................................... 88
Channel 3 Offset Upper Byte Register .....................................79
Channel 5 Status Register .......................................................... 88
Channel 3 Offset Middle Byte Register ....................................80
Channel 6 Status Register .......................................................... 89
Channel 3 Offset Lower Byte Register .....................................80
Channel 7 Status Register .......................................................... 89
Channel 3 Gain Upper Byte Register........................................80
Channel 0/Channel 1 DSP Errors Register.............................. 90
Channel 3 Gain Middle Byte Register ......................................80
Channel 2/Channel 3 DSP Errors Register.............................. 90
Channel 3 Gain Lower Byte Register........................................80
Channel 4/Channel 5 DSP Errors Register.............................. 91
Channel 4 Offset Upper Byte Register .....................................81
Channel 6/Channel 7 DSP Errors Register.............................. 91
Channel 4 Offset Middle Byte Register ....................................81
Channel 0 to Channel 7 Error Register Enable Register........ 92
Channel 4 Offset Lower Byte Register .....................................81
General Errors Register 1 ........................................................... 92
Channel 4 Gain Upper Byte Register........................................81
General Errors Register 1 Enable .............................................. 93
Channel 4 Gain Middle Byte Register ......................................81
General Errors Register 2 ........................................................... 93
Channel 4 Gain Lower Byte Register........................................82
General Errors Register 2 Enable .............................................. 94
Channel 5 Offset Upper Byte Register .....................................82
Error Status Register 1 ................................................................ 94
Channel 5 Offset Middle Byte Register ....................................82
Error Status Register 2 ................................................................ 95
Channel 5 Offset Lower Byte Register .....................................82
Error Status Register 3 ................................................................ 95
Channel 5 Gain Upper Byte Register........................................82
Decimation Rate (N) MSB Register ......................................... 95
Channel 5 Gain Middle Byte Register ......................................83
Decimation Rate (N) LSB Register ........................................... 96
Channel 5 Gain Lower Byte Register........................................83
Decimation Rate (IF) MSB Register ......................................... 96
Channel 6 Offset Upper Byte Register .....................................83
Decimation Rate (IF) LSB Register .......................................... 96
Channel 6 Offset Middle Byte Register ....................................83
SRC Load Source and Load Update Register .......................... 96
Channel 6 Offset Lower Byte Register .....................................83
Outline Dimensions ........................................................................ 97
Channel 6 Gain Upper Byte Register........................................84
Ordering Guide ........................................................................... 97
Channel 6 Gain Middle Byte Register ......................................84
Rev. E | Page 3 of 97
AD7770
Data Sheet
REVISION HISTORY
5/2020—Rev. D to Rev. E
Changes to Table 1 ............................................................................ 6
Changes to Table 6 and Figure 6 ................................................... 13
Changes to Terminology Section.................................................. 31
Changes to Figure 99 ...................................................................... 40
Changes to Sample Rate Converter (SRC) (SPI Control Mode)
Section and Figure 110................................................................... 52
Changes to Figure 119.................................................................... 56
5/2018—Rev. C to Rev. D
Change to t22B Parameter, Table 3 ................................................. 11
Changes to AUXAIN± Parameter, Table 7 .................................. 14
Changes to Table 13 ........................................................................ 38
Changes to Σ-Δ Data, ADC Mode Section ................................. 45
Added Figure 105; Renumbered Sequentially ............................ 45
Changes to SRC Group Delay and Latency Section................... 53
Changed SPI Section to SPI Interface Section ............................ 57
Updated Outline Dimensions ....................................................... 97
Changes to Ordering Guide .......................................................... 97
8/2017—Rev. B to Rev. C
Changes to Features Section and General Description Section....... 1
Change to START Pin Description, Table 9 ................................ 15
Changes to Figure 48 ...................................................................... 24
Change to Digital Reset and Synchronization Pins Section and
Internal Reference and Reference Buffers Section ..................... 36
Change to Figure 95 ....................................................................... 37
Changes to Phase Adjustment Section and Table 16 ................. 41
Added Table 17; Renumbered Sequentially ................................ 41
Change to Digital SPI Section....................................................... 43
Change to Table 25 ......................................................................... 46
10/2016—Rev. A to Rev. B
Changes to Figure 45...................................................................... 24
Changes to Figure 56, Figure 59, and Figure 61 ......................... 26
Changes to Figure 72 and Figure 73 ............................................ 28
Changes to Figure 76...................................................................... 29
Added Figure 82; Renumbered Sequentially .............................. 30
Changes to Figure 86 to Figure 89 ............................................... 34
Changes to SPI Transmission Errors (SPI Control Mode)
Section.............................................................................................. 48
Changes to Table 33 and Table 34 ................................................ 51
Changes to SRC Group Delay and Latency Section and Settling
Time Section ................................................................................... 53
Changes to Table 39 and Table 40 ................................................ 57
Changes to Calculating the CRC Checksum Section and
Table 42 ............................................................................................ 58
Changes to Ordering Guide .......................................................... 97
5/2016—Rev. 0 to Rev. A
Change to Features ............................................................................1
Changes to Table 1.............................................................................6
Changes to Figure 33 and Figure 36 ............................................ 21
Change to Figure 78 ....................................................................... 28
4/2016—Revision 0: Initial Version
Rev. E | Page 4 of 97
Data Sheet
AD7770
FUNCTIONAL BLOCK DIAGRAM
AVDD1x
VCM
REF_OUT
REFx+ REFx–
AVDD2
COMMONMODE
VOLTAGE
AREGxCAP
ANALOG
LDO
IOVDD
DREGCAP
DIGITAL
LDO
2.5V REF
AIN0+
AIN0–
CLOCK
MANAGER
XTAL1
XTAL2/MCLK
SYNC_IN
SYNC_OUT
START
280mV p-p
EXT_REF
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
GAIN
OFFSET
GAIN
OFFSET
DCLK
DRDY
INT_REF
AIN1+
AIN1–
PGA
DATA OUTPUT
INTERFACE
DOUT3
DOUT2
DOUT1
REFERENCES
DOUT0
AIN2+
AIN2–
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
GAIN
OFFSET
GAIN
OFFSET
GAIN
OFFSET
REGISTER MAP
AND
LOGIC CONTROL
RESET
REFERENCES
AIN3+
AIN3–
REFERENCES
AIN4+
AIN4–
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
REFERENCES
AIN5+
AIN5–
REFERENCES
AIN6+
AIN6–
FORMAT0
HARDWARE
MODE
CONFIGURATION
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
PGA
Σ-Δ ADC
SINC3/
SRC
FILTER
REFERENCES
GAIN
OFFSET
GAIN
OFFSET
AUXAIN+
AUXAIN–
MODE3/ALERT
MODE2/GPIO2
MODE1/GPIO1
MODE0/GPIO0
ALERT/CS
SPI INTERFACE
REFERENCES
AIN7+
AIN7–
FORMAT1
DCLK2/SCLK
DCLK1/SDI
DCLK0/SDO
AD7770
SAR ADC
AVSSx
AVDD4
CONVST_SAR
Figure 1.
Rev. E | Page 5 of 97
12538-001
DIAGNOSTIC
INPUTS
AD7770
Data Sheet
SPECIFICATIONS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = analog ground (AGND) (single-supply operation),
AVDD2x − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), master clock
(MCLK) = 8192 kHz for high resolution mode and 4096 kHz for low power mode, ODR = 32 kSPS for high resolution mode and 8 kSPS for
low power mode; all specifications at TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Σ-Δ ADC CHANNELS
Speed and Performance
Resolution
ODR
No Missing Codes
Gain Settings, PGAGAIN
Bandwidth
AC Accuracy
Dynamic Range
32 kSPS
8 kSPS
2 kSPS
THD
Signal-to-Noise-and-Distortion
Ratio (SINAD)
SFDR
Intermodulation Distortion
(IMD)
DC Power Supply Rejection
DC Common-Mode Rejection
Ratio
Crosstalk
DC ACCURACY
INL
High Resolution Mode
Low Power Mode
Test Conditions/Comments
Min
Typ
Max
Unit
32
8
Bits
kSPS
kSPS
Bits
2
512
5
1.5
MHz
kHz
kHz
kHz
24
High resolution mode
Low power mode
Up to 24 kSPS
24
1, 2, 4, or 8
Small signal, high resolution mode
Small signal, low power mode
Large signal, high resolution mode
Large signal, low power mode
Shorted inputs, PGAGAIN = 1
High resolution mode
High resolution mode
Low power mode
Low power mode
−0.5 dBFS, high resolution mode
−0.5 dBFS, low power mode
fIN = 60 Hz
High resolution mode, 16 kSPS,
PGAGAIN = 1
fA = 50 Hz, fB = 51 Hz, high
resolution mode
fA = 50 Hz, fB = 51 Hz, low power
mode
AVDD1x = 3.3 V
103
113
103
113
−109
−105
106
dB
dB
dB
dB
dB
dB
dB
132
dB
−125
dB
−105
dB
−90
dB
dB
−120
dB
±8
±4
±9
±6
±15
±0.25
−2
ppm of FSR
ppm of FSR
ppm of FSR
ppm of FSR
µV
µV/°C
µV/
1000 hours
µV
% FS
ppm/°C
%
80
Endpoint method, PGAGAIN = 1
Other PGA gains
Endpoint method, PGAGAIN = 1
Other PGA gains
Offset Error
Offset Error Drift
Over time
Offset Matching
Gain Error
Gain Drift vs. Temperature
Gain Matching
25
±0.1
±0.75
±0.1
Rev. E | Page 6 of 97
±90
Data Sheet
Parameter
ANALOG INPUTS
Differential Input Voltage Range
Single-Ended Input Voltage Range
AINx± Common-Mode Input
Range
Absolute AINx± Voltage Limits
DC Input Current
Differential
Single-Ended
Input Current Drift
AC Input Capacitance
REFERENCE
Internal
Initial Accuracy
Temperature Coefficient
Reference Load Current, IL
DC Power Supply Rejection
Load Regulation, ∆VOUT/∆IL
Voltage Noise, eN p-p
Voltage Noise Density, eN
Turn On Settling Time
External
Input Voltage
Buffer Headroom
REFx− Input Voltage
Average REFx± Input Current
TEMPERATURE RANGE
Specified Performance
Functional2
TEMPERATURE SENSOR
Accuracy
DIGITAL FILTER RESPONSE (SINC3)
Group Delay
Settling Time
Pass Band
Decimation Rate
AD7770
Test Conditions/Comments
Min
Typ
VREF = (REFx+ − REFx−)
AVSSx + 0.10
(AVDD1x +
AVSSx)/2
AVSSx + 0.10
High resolution, MCLK = 8192 kHz
Low power mode, MCLK = 4096 kHz
High resolution, MCLK = 8192 kHz
Low power mode, MCLK = 4096 kHz
REF_OUT, TA = 25°C
Unit
±VREF/PGAGAIN
0 to VREF/PGAGAIN
AVDD1x − 0.10
V
V
V
AVDD1x − 0.10
V
4
1
8
2
50
8
2.495
2.5
±10
−10
Line regulation
nA
nA
nA
nA
pA/°C
pF
2.505
±38
+10
V
ppm/°C
mA
dB
µV/mA
µV rms
nV/√Hz
ms
AVDD1x
AVDD1x − 0.1
AVDD1x − REFx+
V
V
V
95
100
6.8
273.5
1.5
0.1 Hz to 10 Hz
1 kHz, 2.5 V reference
100 nF
VREF = (REFx+ − REFx−)
1
AVSSx + 0.1
2.5
AVSSx
Current per channel
Reference buffer disabled, high
resolution mode
Reference buffer precharge mode
(pre-Q), high resolution mode
Reference buffer disabled, low
power mode
Reference buffer pre-Q, low power
mode
Reference buffer enabled, high
resolution mode
Reference buffer enabled, low
power mode
TMIN to TMAX
TMIN to TMAX
Max
18
µA/V
600
nA/V
4.5
µA/V
100
nA/V
12
nA/V
5
nA/V
−40
−40
+105
+125
±2
−0.1 dB
−3 dB
64
Rev. E | Page 7 of 97
See the SRC Group Delay section
See the Settling Time section
See the SRC Bandwidth section
See the SRC Bandwidth section
4095.99
°C
°C
°C
AD7770
Parameter
CLOCK SOURCE
Frequency
Duty Cycle
SAR ADC
Speed and Performance
Resolution
Analog Input Range
Analog Input Common-Mode
Range
Analog Input Dynamic Current
Throughput
DC Accuracy
INL
DNL
Offset
Gain
AC Performance
SNR
THD
VCM PIN
Output
Load Current, IL
Load Regulation, ∆VOUT/∆IL
Short-Circuit Current
LOGIC INPUTS
Input Voltage
High, VIH
Low, VIL
Hysteresis
Input Currents
LOGIC OUTPUTS3
Output Voltage
High, VOH
Low, VOL
Leakage Current
Output Capacitance
Σ-Δ ADC Data Output Coding
SAR ADC Data Output Coding
Data Sheet
Test Conditions/Comments
Min
High resolution mode
Low power mode
0.655
1.3
45:55
Typ
Max
Unit
50:50
8.192
4.096
55:45
MHz
MHz
%
AVDD4 − 0.1
AVDD4 − 0.1
Bits
V
V
256
nA
kSPS
12
AVSS4 + 0.1
AVSS4 + 0.1
256 kSPS, 0 dBFS
(AVDD4 +
AVSS4)/2
±100
Differential mode
1.5
No missing codes (12-bit)
±1
12
LSB
LSB
LSB
LSB
66
−81
dB
dB
(AVDD1x +
AVSSx)/2
1
12
5
V
−0.99
1 kHz
1 kHz
+1
mA
mV/mA
mA
0.7 × IOVDD
0.4
0.1
−10
IOVDD ≥ 3 V, ISOURCE = 1 mA
2.3 V ≤ IOVDD < 3 V, ISOURCE =
500 μA
IOVDD < 2.3 V, ISOURCE = 200 μA
IOVDD ≥ 3 V, ISINK = 2 mA
2.3 V ≤ IOVDD < 3 V, ISINK = 1 mA
IOVDD < 2.3 V, ISINK = 100 μA
Floating state
Floating state
+10
V
V
V
µA
0.8 × IOVDD
0.8 × IOVDD
V
V
0.8 × IOVDD
V
V
V
V
µA
pF
0.4
0.4
0.4
+10
−10
Rev. E | Page 8 of 97
10
Twos complement
Binary
Data Sheet
Parameter
POWER SUPPLIES
AVDD1x − AVSSx
IAVDD1x4, 5
AVDD2x − AVSSx
IAVDD2x
AD7770
Test Conditions/Comments
All Σ-Δ channels enabled
AVSSxv − DGND
IOVDD − DGND
IIOVDD
Power Dissipation6
High Resolution Mode
Low Power Mode
Power-Down
Typ
Max
Unit
3.6
V
18.5
5
23.7
6.4
mA
mA
20.5
5.5
26.7
7.1
mA
mA
14.3
3.9
18.8
5.1
3.6
9.45
3.7
AVDD1x
mA
mA
V
mA
mA
V
2
10
0
3.6
11.3
4.4
mA
µA
V
V
mA
mA
136
44
mW
mW
μW
3.0
Reference buffer pre-Q, VCM
enabled, internal reference
enabled
High resolution mode
Low power mode
Reference buffer enabled, VCM
enabled, internal reference
enabled
High resolution mode
Low power mode
Reference buffer disabled, VCM
disabled, internal reference
disabled
High resolution mode
Low power mode
2.2
High resolution mode
Low power mode
9
3.5
AVDD1x −
0.3
AVDD4 − AVSSx
IAVDD4
Min
SAR enabled
SAR disabled
1.7
1
−1.8
1.8
High resolution mode
Low power mode
Internal buffers bypassed, internal
reference disabled, internal
oscillator disabled, SAR disabled
32 kSPS
8 kSPS
All ADCs disabled
8
3
117
38
530
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
At temperatures higher than 105°C, the device can be operated normally, though slight degradation on the maximum/minimum specifications is expected because
these specifications are only guaranteed up to 105°C. See the Typical Performance Characteristics section for plots showing the typical performance of the device at
high temperatures.
3
The SDO pin and the DOUTx pin are configured in the default mode of strength.
4
AVDD1x = 3.3 V, AVSSx = GND = ground, IOVDD = 1.8 V, CMOS clock.
5
Disabling either the VCM pin or the internal reference results in a 40 µA typical current consumption reduction.
6
Power dissipation is calculated using the maximum supply voltage, 3.6 V.
1
2
Rev. E | Page 9 of 97
AD7770
Data Sheet
DOUTx TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND (single-supply operation), AVDD2 −
AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V internal/external, MCLK = 8192 kHz; all
specifications at TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
2
Test Conditions/Comments
50:50
MCLK/2
MCLK/2
Min
0.655
60
60
121
121
Typ
Max
8.192
45
45
2
1
20
20
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
t1
t2
t3
MCLK
DCLK
t4
t6
t5
t8
t7
t9
DRDY
DOUTx
LSB
MSB
MSB – 1
t10
t11
Figure 2. Data Interface Timing Diagram
Rev. E | Page 10 of 97
LSB + 1
LSB
12538-002
1
Description2
MCLK frequency
MCLK low time
MCLK high time
DCLK high time
DCLK low time
MCLK falling edge to DCLK rising edge
MCLK falling edge to DCLK falling edge
DCLK rising edge to DRDY rising edge
DCLK rising edge to DRDY falling edge
DOUTx setup time
DOUTx hold time
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
AD7770
SPI TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,
unless otherwise noted.
Table 3.
Parameter
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22A
t22B
t23
t24
t25
2
Test Conditions/Comments
50:50
Min
7
7
10
10
10
10
10
5
5
30
49
10
10
30
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
t19
CS
t15
t16
t17
t13
t14
t18
SCLK
t20
SDI
MSB
t22A
SDO
MSB – 1
t12
LSB + 1
LSB
t21
MSB
t22B
MSB – 1
LSB + 1
t24
t23
Figure 3. SPI Control Interface Timing Diagram
Rev. E | Page 11 of 97
LSB
t25
12538-003
1
Description2
SCLK period
SCLK low time
SCLK high time
SCLK rising edge to CS falling edge
CS falling edge to SCLK rising edge
SCLK rising edge to CS rising edge
CS rising edge to SCLK rising edge
Minimum CS high time
SDI setup time
SDI hold time
CS falling edge to SDO enable (SPI = Mode 0)
SCLK falling edge to SDO enable (SPI = Mode 3)
SDO setup time
SDO hold time
CS rising edge to SDO disable
Typ
Max
30
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD7770
Data Sheet
SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter
t26
t27
t28
t29
t30
tINIT_SYNC_IN
tINIT_RESET
t31
tPOWER_UP
2
Test Conditions/Comments
16 kSPS, high resolution mode
16 kSPS, high resolution mode
Min
10
MCLK
MCLK
10
MCLK
145
225
2 × MCLK
Typ
tPOWER_UP is not shown in Figure 4
2
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
START
t26
t27
SYNC_OUT
t28
SYNC_IN
t29
t30
DRDY
tINIT_SYNC_IN
RESET
t31
tINIT_RESET
Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram
Rev. E | Page 12 of 97
12538-004
1
Description2
START setup time
START hold time
MCLK falling edge to SYNC_OUT falling edge
SYNC_IN setup time
SYNC_IN hold time
SYNC_IN rising edge to first DRDY
RESET rising edge to first DRDY
RESET hold time
Start time
Max
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ms
Data Sheet
AD7770
SAR ADC TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,
unless otherwise noted.
Table 5.
Parameter
t32
t33
t34
t35
1
2
3
Description2
Conversion time
Acquisition time3
Delay time
Throughput data rate
Min
1
500
50
Typ
Max
3.4
Unit
µs
ns
ns
kSPS
256
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
Direct mode enabled. If deglitch mode is enabled, add 1.5/MCLK as described in Table 30.
CS
t33
t32
t34
12538-005
CONVST_SAR
t35
Figure 5. SAR ADC Timing Diagram
GPIO SRC UPDATE TIMING CHARACTERISTISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications TMIN to TMAX,
unless otherwise noted.
Table 6.
Parameter
t36
t37
t37
t38
t39
t40
2
Min
10
Typ
MCLK
2 × MCLK
20
MCLK
5
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3 and AVSS4. This term is used throughout the data sheet.
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
GPIO2
t36
t37
GPIO1
t38
GPIO0
t39
t40
Figure 6. GPIOs for SRC Update Timing Diagram
Rev. E | Page 13 of 97
12538-006
1
Description2
GPIO2 setup time
GPIO2 hold time
High resolution mode
Low power mode
MCLK rising edge to GPIO1 rising edge time
GPIO0 hold time
GPIO0 setup time
Max
Unit
ns
ns
ns
ns
ns
AD7770
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Any Supply Pin to AVSSx
AVSSx to DGND
AREGxCAP to AVSSx
DREGCAP to DGND
IOVDD to DGND
IOVDD to AVSSx
AVDD4 to AVSSx
Analog Input Voltage
REFx± Input Voltage
AUXAIN±
Digital Input Voltage to
DGND
Digital Output Voltage to
DGND
XTAL1 to DGND
AINx±, AUXAIN±, and
Digital Input Current
Operating Temperature
Range
Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
ESD
Field Induced Charged
Device Model (FICDM)
Rating
−0.3 V to +3.96 V
−1.98 V to +0.3 V
−0.3 V to +1.98 V
−0.3 V to +1.98 V
−0.3 V to +3.96 V
−0.3 V to +5.94 V
AVDD1x − 0.3 V to 3.96 V
AVSSx − 0.3 V to AVDD1x + 0.3 V or
3.96 V (whichever is less)
AVSSx − 0.3 V to AVDD1x + 0.3 V or
3.96 V (whichever is less)
AVSSx − 0.3 V to AVDD4 + 0.3 V or
3.96 V (whichever is less)
DGND − 0.3 V to IOVDD + 0.3 V or
3.96 V (whichever is less)
DGND − 0.3 V to IOVDD + 0.3 V or
3.96 V (whichever is less)
DGND − 0.3 V to DREGCAP + 0.3 V
or 1.98 V (whichever is less)
±10 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 8. Thermal Resistance
Package Type1
64-Lead LFCSP
No Thermal Vias
49 Thermal Vias
1
θJA
θJB
ΨJT
ΨJB
Unit
30.43
22.62
N/A2
3.17
0.13
0.09
6.59
3.19
°C/W
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51.
2
N/A means not applicable.
ESD CAUTION
−40°C to +125°C
150°C
−65°C to +150°C
260°C
2 kV
500 V
Rev. E | Page 14 of 97
Data Sheet
AD7770
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AUXAIN–
AUXAIN+
AVDD4
AVSS4
AVSS2A
AREG1CAP
AVDD2A
VCM
CLK_SEL
FORMAT0
FORMAT1
AVSS3
AVDD2B
AREG2CAP
AVSS2B
REF_OUT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD7770
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AIN4–
AIN4+
AIN5–
AIN5+
AVSS1B
AVDD1B
REF2–
REF2+
AIN6–
AIN6+
AIN7–
AIN7+
RESET
SYNC_IN
SYNC_OUT
START
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AVSSx.
12538-007
CONVST_SAR
ALERT/CS
DCLK2/SCLK
DCLK1/SDI
DCLK0/SDO
DGND
DREGCAP
IOVDD
DOUT3
DOUT2
DOUT1
DOUT0
DCLK
DRDY
XTAL1
XTAL2/MCLK
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AIN0–
AIN0+
AIN1–
AIN1+
AVSS1A
AVDD1A
REF1–
REF1+
AIN2–
AIN2+
AIN3–
AIN3+
MODE0/GPIO0
MODE1/GPIO1
MODE2/GPIO2
MODE3/ALERT
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
AIN0−
AIN0+
AIN1−
AIN1+
AVSS1A
Type
Analog input
Analog input
Analog input
Analog input
Supply
Direction
Input
Input
Input
Input
Supply
6
AVDD1A
Supply
Supply
7
REF1−
Reference
Input
8
9
10
11
12
13
REF1+
AIN2−
AIN2+
AIN3−
AIN3+
MODE0/GPIO0
Reference
Analog input
Analog input
Analog input
Analog input
Digital I/O
Input
Input
Input
Input
Input
I/O
14
MODE1/GPIO1
Digital I/O
I/O
Description
Analog Input Channel 0, Negative.
Analog Input Channel 0, Positive.
Analog Input Channel 1, Negative.
Analog Input Channel 1, Positive.
Negative Front-End Analog Supply for Channel 0 to Channel 3, Typical at −1.65 V
(Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the
same potential.
Positive Front-End Analog Supply for Channel 0 to Channel 3, Typical at AVSSx +
3.3 V. Connect this pin to AVDD1B.
Negative Reference Input 1 for Channel 0 to Channel 3, Typical at AVSSx.
Connect all the REFx− pins to the same potential.
Positive Reference Input 1 for Channel 0 to Channel 3, Typical at REF1− + 2.5 V.
Analog Input Channel 2, Negative.
Analog Input Channel 2, Positive.
Analog Input Channel 3, Negative.
Analog Input Channel 3, Positive.
Mode 0 Input in Pin Control Mode (MODE0). See Table 14 for more details.
Configurable General-Purpose Input/Output 0 in SPI Control Mode (GPIO0). If
not in use, connect this pin to DGND or IOVDD.
Mode 1 Input in Pin Control Mode (MODE1). See Table 14 for more details.
Configurable General-Purpose Input/Output 1 in SPI Control Mode (GPIO1). If
not in use, connect this pin to DGND or IOVDD.
Rev. E | Page 15 of 97
AD7770
Data Sheet
Pin No.
15
Mnemonic
MODE2/GPIO2
Type
Digital I/O
Direction
I/O
16
MODE3/ALERT
Digital I/O
I/O
17
CONVST_SAR
Digital input
Input
18
ALERT/CS
Digital input
Input
19
DCLK2/SCLK
Digital input
Input
20
DCLK1/SDI
Digital input
Input
21
DCLK0/SDO
Digital output
Output
22
23
DGND
DREGCAP
Supply
Supply
Supply
Output
24
IOVDD
Supply
Supply
25
DOUT3
Digital output
I/O
26
DOUT2
Digital output
I/O
27
28
29
30
31
DOUT1
DOUT0
DCLK
DRDY
XTAL1
Digital output
Digital output
Digital output
Digital output
Clock
Output
Output
Output
Output
Input
32
XTAL2/MCLK
Clock
Input
33
START
Digital input
Input
34
SYNC_OUT
Digital output
Input
35
SYNC_IN
Digital input
Input
36
RESET
Digital input
Input
37
38
39
40
41
AIN7+
AIN7−
AIN6+
AIN6−
REF2+
Analog input
Analog input
Analog input
Analog input
Reference
Input
Input
Input
Input
Input
Description
Mode 2 Input in Pin Control Mode (MODE2). See Table 14 for more details.
Configurable General-Purpose Input/Output 2 in SPI Control Mode (GPIO2). If
not in use, connect this pin to DGND or IOVDD.
Mode 3 Input in Pin Control Mode (MODE3). See Table 14 for more details.
Alert Output in SPI Control Mode (ALERT).
Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table 13 for more
details. This pin also functions as the start for the SAR conversion in SPI control
mode.
Alert Output in Pin Control Mode (ALERT).
Chip Select in SPI Control Mode (CS).
DCLK Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15 for
more details.
SPI Clock in SPI Control Mode (SCLK).
DCLK Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 15 for
more details.
SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the
device is configured in pin control mode with the SPI as the data output interface.
DCLK Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 15 for
more details.
SPI Data Output in SPI Control Mode (SDO).
Digital Ground.
Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a 1 μF
capacitor.
Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V.
IOVDD must not be lower than DREGCAP.
Data Output Pin 3. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details.
Data Output Pin 2. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details.
Data Output Pin 1.
Data Output Pin 0.
Data Output Clock.
Data Output Ready Pin.
Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to
DGND. See Table 12 for more details.
Crystal 2 Input Connection (XTAL2). See Table 12 for more details.
CMOS Clock (MCLK). See Table 12 for more details.
Synchronization Pulse. This pin internally synchronizes an external START
asynchronous pulse with MCLK. The synchronize signal is shifted out by the
SYNC_OUT pin. If not in use, tie this pin to IOVDD. See the Phase Adjustment
section and the Digital Reset and Synchronization Pins section for more details.
Synchronization Signal. This pin generates a synchronous pulse generated and
driven by hardware (via the START pin) or by software (GENERAL_USER_
CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin. See
the Phase Adjustment section and the Digital Reset and Synchronization Pins
section for more details.
Reset for the Internal Digital Block and Synchronize for Multiple Devices. See
the Digital Reset and Synchronization Pins section for more details.
Asynchronous Reset Pin. This pin resets all registers to their default value. It is
recommended to generate a pulse on this pin after the device is powered up
because a slow slew rate in the supplies may generate an incorrect
initialization in the digital block.
Analog Input Channel 7, Positive.
Analog Input Channel 7, Negative.
Analog Input Channel 6, Positive.
Analog Input Channel 6, Negative.
Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2− + 2.5 V.
Rev. E | Page 16 of 97
Data Sheet
AD7770
Pin No.
42
Mnemonic
REF2−
Type
Reference
Direction
Input
43
AVDD1B
Supply
Supply
44
AVSS1B
Supply
Supply
45
46
47
48
49
AIN5+
AIN5−
AIN4+
AIN4−
REF_OUT
Analog input
Analog input
Analog input
Analog input
Reference
Input
Input
Input
Input
Output
50
51
52
53
54
55
56
57
58
AVSS2B
AREG2CAP
AVDD2B
AVSS3
FORMAT1
FORMAT0
CLK_SEL
VCM
AVDD2A
Supply
Supply
Supply
Supply
Digital input
Digital input
Digital input
Analog output
Supply
Supply
Output
Supply
Supply
Input
Input
Input
Output
Input
59
60
61
AREG1CAP
AVSS2A
AVSS4
Supply
Supply
Supply
Output
Input
Supply
62
63
64
AVDD4
AUXAIN+
AUXAIN−
EPAD
Supply
Analog input
Analog input
Supply
Supply
Input
Input
Input
Description
Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx.
Connect all the REFx− pins to the same potential.
Positive Front-End Analog Supply for Channel 4 to Channel 7. Connect this pin
to AVDD1A.
Negative Front-End Analog Supply for Channel 4 to Channel 7, typical at −1.65 V
(Dual Supply) or AGND (Single Supply). Connect all the AVSSx pins to the
same potential.
Analog Input Channel 5, Positive.
Analog Input Channel 5, Negative.
Analog Input Channel 4, Positive.
Analog Input Channel 4, Negative.
2.5 V Reference Output. Connect a 100 nF capacitor on this pin if using the
internal reference.
Negative Analog Supply. Connect all the AVSSx pins to the same potential.
Analog LDO Output 2. Decouple this pin to AVSS2B with a 1 μF capacitor.
Positive Analog Supply. Connect this pin to AVDD2A.
Negative Analog Ground. Connect all the AVSSx pins to the same potential.
Output Data Frame 1. See Table 13 for more details.
Output Data Frame 0. See Table 13 for more details.
Select Clock Source. See Table 12 for more details.
Common-Mode Voltage Output, Typical at (AVDD1 + AVSSx)/2.
Analog Supply from 2.2 V to 3.6 V. AVSS2x must not be lower than AREGxCAP.
Connect this pin to AVDD2B.
Analog LDO Output 1. Decouple this pin to AVSSx with a 1 μF capacitor.
Negative Analog supply. Connect all the AVSSx pins to the same potential.
Negative SAR Analog Supply and Reference. Connect all AVSSx pins to the same
potential.
Positive SAR Analog Supply and Reference Source.
Positive SAR Analog Input Channel.
Negative SAR Analog Input Channel.
Exposed Pad. Connect the exposed pad to AVSSx.
Rev. E | Page 17 of 97
AD7770
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
5
INL (ppm)
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
INPUT VOLTAGE (V)
Figure 8. INL vs. Input Voltage and Channel at 16 kSPS, High Resolution Mode
10
8
6
1.77
1.41
1.06
0.70
0
0.35
–0.35
–0.70
–15
–1.06
1.77
1.41
1.06
0.70
0
0.35
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–2.48
–10
–10
–2.48
–8
12538-208
–6
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–5
2.48
–4
2.48
–2
0
INPUT VOLTAGE (V)
12538-211
0
2.12
2
2.12
INL (ppm)
4
–1.41
6
TEMPERATURE = 25°C
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
–1.77
8
15
TEMPERATURE = 25°C
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
–2.12
10
Figure 11. INL vs. Input Voltage and Channel at 4 kSPS, Low Power Mode
10
TEMPERATURE = 25°C
VREF = 2.5V
DIFFERENTIAL VIN × GAIN
VCM = (AVDD1x + AVSSx) ÷ 2
TEMPERATURE = 25°C
VREF = 2.5V
DIFFERENTIAL VIN × GAIN
VCM = (AVDD1x + AVSSx) ÷ 2
5
2
INL (ppm)
INL (ppm)
4
0
–2
0
–5
–4
Figure 9. INL vs. Input Voltage and PGA Gain at 16 kSPS, High Resolution Mode
10
8
6
2.48
2.12
1.77
1.41
1.06
0.70
0.35
0
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–2.48
–15
INPUT VOLTAGE (V)
12538-212
INPUT VOLTAGE (V)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–10
12538-209
2.48
1.41
1.06
0.70
0.35
0
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–2.48
–10
2.12
–8
1.77
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–6
Figure 12. INL vs. Input Voltage and PGA Gain at 4 kSPS, Low Power Mode
15
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
10
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
4
5
INL (ppm)
0
–2
–4
0
–5
–6
INPUT VOLTAGE (V)
Figure 13. INL vs. Input Voltage and Temperature at 4 kSPS,
Low Power Mode
Figure 10. INL vs. Input Voltage and Temperature at 16 kSPS,
High Resolution Mode
Rev. E | Page 18 of 97
2.48
2.12
1.77
1.41
1.06
0.70
0.35
0
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–2.48
–15
12538-213
INPUT VOLTAGE (V)
TA = –40°C
TA = +25C
TA = +105°C
TA = +125°C
–10
12538-210
2.48
2.12
1.06
0.70
0.35
0
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–12
1.77
–10
1.41
TA = –40°C
TA = +25C
TA = +105°C
TA = +125°C
–8
–2.48
INL (ppm)
2
Data Sheet
20
20
TEMPERATURE = 25°C
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VCM = (AVDD1x + AVSSx) ÷ 2
15
10
10
5
5
0
–5
–15
–20
–4
–3
–2
–1
0
1
2
= 1V
= 1.5V
= 2V
= 2.5V
= 3V
= 3.3V
3
–15
4
INPUT VOLTAGE (V)
–20
–4
6
–2
–1
0
1
2
3
4
Figure 17. INL vs. Input Voltage and VREF at 4 kSPS, Low Power Mode
15
TEMPERATURE = 25°C
VREF = 2.5V
DIFFERENTIAL INPUT SIGNAL
GAIN = 1
8
–3
= 1V
= 1.5V
= 2V
= 2.5V
= 3V
= 3.3V
INPUT VOLTAGE (V)
Figure 14. INL vs. Input Voltage and Reference Voltage (VREF)
at 16 kSPS, High Resolution Mode
10
VREF
VREF
VREF
VREF
VREF
VREF
–10
12538-214
VREF
VREF
VREF
VREF
VREF
VREF
–10
TEMPERATURE = 25°C
VREF = 2.5V
DIFFERENTIAL INPUT SIGNAL
GAIN =1
10
4
5
2
INL (ppm)
0
–2
0
–5
–10
1000
2.48
12538-218
2.12
1.77
1.06
0.70
0.35
–0.35
–0.70
–1.06
0
Rev. E | Page 19 of 97
12538-219
ADC CODE
Figure 19. Noise Histogram at 4 kSPS, Low Power Mode
Figure 16. Noise Histogram at 16 kSPS, High Resolution Mode
8388644
8388604
8388564
8388524
8388484
8388444
8388404
8388364
12538-216
8388652
8388608
8388564
8388520
8388476
8388432
0
8388388
0
8388344
200
8388300
200
8388256
400
8388212
400
ADC CODE
–1.41
600
8388324
600
800
8388284
800
8388244
1000
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
TEMPERATURE = 25°C
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
1200
SAMPLE COUNT
1200
Figure 18. INL vs. Input Voltage and VCM at 4 kSPS, Low Power Mode
1400
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
TEMPERATURE = 25°C
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–1.77
INPUT VOLTAGE (V)
Figure 15. INL vs. Input Voltage and VCM at 16 kSPS, High Resolution Mode
1400
–2.12
–2.48
2.48
INPUT VOLTAGE (V)
VCM = 1.35V
VCM = 1.65V
VCM = 1.95V
–15
12538-215
2.12
1.41
1.06
0.70
0
0.35
–0.35
–0.70
–1.06
–1.41
–1.77
–2.12
–2.48
–10
1.77
VCM = 1.35V
VCM = 1.65V
VCM = 1.95V
–8
8388204
–6
1.41
–4
8388164
INL (ppm)
0
12538-217
–5
SAMPLE COUNT
TEMPERATURE = 25°C
GAIN = 1
DIFFERENTIAL INPUT SIGNAL
VCM = (AVDD1x + AVSSx) ÷ 2
15
INL (ppm)
INL (ppm)
AD7770
AD7770
8
Data Sheet
8
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
7
6
NOISE (µV rms)
5
4
3
4
3
2
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
0
–40
25
105
TEMPERATURE (°C)
125
0
–40
Figure 20. Noise vs. Temperature at 16 kSPS, High Resolution Mode
25
105
TEMPERATURE (°C)
125
Figure 23. Noise vs. Temperature at 4 kSPS, Low Power Mode
7
7
6
6
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
TEMPERATURE = 25°C
DECIMATION = 256
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
TEMPERATURE = 25°C
DECIMATION = 256
5
NOISE (µV rms)
5
4
3
4
3
2
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
CLOCK FREQUENCY (Hz)
0
CLOCK FREQUENCY (Hz)
Figure 21. Noise vs. Clock Frequency, High Resolution Mode
140
120
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
1
12538-221
335360
652800
970240
1287680
1605120
1922560
2240000
2557440
2874880
3192320
3509760
3827200
4144640
4462080
4779520
5096960
5414400
5731840
6049280
6366720
6684160
7001600
7319040
7636480
7953920
1
12538-224
2
0
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
1
12538-220
1
12538-223
2
5
294400
448000
601600
755200
908800
1062400
1216000
1369600
1523200
1676800
1830400
1984000
2137600
2291200
2444800
2598400
2752000
2905600
3059200
3212800
3366400
3520000
3673600
3827200
3980800
NOISE (µV rms)
6
NOISE (µV rms)
VREF = 2.5V
VCM = (AVDD1x + AVSSx) ÷ 2
7
Figure 24. Noise vs. Clock Frequency, Low Power Mode
300
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
250
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
NOISE (nV/√Hz)
80
60
200
150
100
40
0
2000
4000
8000
16000
32000
ODR (SPS)
Figure 22. Noise vs. ODR, High Resolution Mode
0
500
1000
2000
4000
ODR (SPS)
Figure 25. Noise vs. ODR, Low Power Mode
Rev. E | Page 20 of 97
8000
12538-225
50
20
12538-222
NOISE (nV/√Hz)
100
FREQUENCY (Hz)
3925.78125
12538-229
3664.06250
3402.34375
3140.62500
2878.90625
2617.18750
2355.46875
2093.75000
1832.03125
1570.31250
1308.59375
12538-230
3828.1250
3554.6875
3281.2500
3007.8125
2734.3750
2460.9375
2187.5000
1914.0625
1640.6250
1367.1875
1093.7500
–100
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–105
–110
THD (dB)
–115
–120
–115
–120
–125
Figure 28. THD vs. Input Frequency at 16 kSPS, High Resolution Mode
Rev. E | Page 21 of 97
INPUT FREQUENCY (Hz)
Figure 31. THD vs. Input Frequency at 4 kSPS, Low Power Mode
12538-231
1870.0
1660.0
1440.0
1220.0
1010.0
811.9
604.0
VIN = –0.5dBFS
VREF = 2.5V
TEMPERATURE = 25°C
406.0
7860
7160
6320
5620
4710
–130
12538-228
INPUT FREQUENCY (Hz)
3870
3170
2400
1700
1000
901
802
703
604
505
406
307
208
10
109
VIN = –0.5dBFS
VREF = 2.5V
TEMPERATURE = 25°C
208.0
–125
10.0
THD (dB)
820.3125
Figure 30. FFT at 8 kSPS, Low Power Mode,
Input Frequency (fIN) = 1 kHz
–110
–130
546.8750
FREQUENCY (Hz)
Figure 27. FFT at 32 kSPS, High Resolution Mode,
Input Frequency (fIN) = 1 kHz
–105
VREF = 2.5V
TEMPERATURE = 25°C
DIFFERENTIAL INPUT = –0.5dBFS
VCM = (AVDD1x + AVSSx) ÷ 2
INPUT FREQUENCY = 1kHz
8192 SAMPLES
8kSPS
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
12538-227
0
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
273.4375
AMPLITUDE (dB)
14984.375000
13914.062500
12843.750000
FREQUENCY (Hz)
–100
785.15625
Figure 29. FFT at 8 kSPS, Low Power Mode,
Input Frequency (fIN) = 50 Hz
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
11773.437500
9632.812500
10703.125000
8562.500000
7648.437500
6533.203125
5462.890625
4388.671875
3304.687500
2234.375000
0
1103.515625
AMPLITUDE (dB)
VREF = 2.5V
TEMPERATURE = 25°C
DIFFERENTIAL INPUT = –0.5dBFS
VCM = (AVDD1x + AVSSx) ÷ 2
INPUT FREQUENCY = 1kHz
16384 SAMPLES
32kSPS
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
FREQUENCY (Hz)
Figure 26. FFT at 32 kSPS, High Resolution Mode,
Input Frequency (fIN) = 50 Hz
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
1046.87500
VREF = 2.5V
TEMPERATURE = 25°C
DIFFERENTIAL INPUT = –0.5dBFS
VCM = (AVDD1x + AVSSx) ÷ 2
INPUT FREQUENCY = 50Hz
8192 SAMPLES
8kSPS
523.43750
0
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
261.71875
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
AMPLITUDE (dB)
VREF = 2.5V
TEMPERATURE = 25°C
DIFFERENTIAL INPUT = –0.5dBFS
VCM = (AVDD1x + AVSSx) ÷ 2
INPUT FREQUENCY = 50Hz
16384 SAMPLES
32kSPS
12538-226
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
AD7770
0
656.250000
1296.875000
1986.328125
2617.187500
3250.000000
3884.765625
4156.250000
4789.062500
5427.734375
6066.406250
6703.125000
7312.500000
7921.875000
8531.250000
9140.625000
9750.000000
10359.375000
10968.750000
11578.125000
12187.500000
12796.875000
13406.250000
14015.625000
14625.000000
15234.375000
15843.750000
AMPLITUDE (dB)
Data Sheet
AD7770
Data Sheet
–105
–110
–115
–115
THD (dB)
–110
–120
–125
–130
–130
INPUT FREQUENCY = 50Hz
VREF = 2.5V
TEMPERATURE = 25°C
INPUT VOLTAGE (V)
0.172
0.344
0.516
0.688
0.860
1.032
1.204
1.376
1.548
1.720
1.892
2.064
2.236
2.408
2.580
2.752
2.924
3.096
3.268
3.440
3.612
3.784
3.956
4.128
4.300
4.472
4.644
–140
INPUT VOLTAGE (V)
Figure 32. THD vs. Input Voltage at 16 kSPS, High Resolution Mode
–90
Figure 35. THD vs. Input Voltage at 4 kSPS, Low Power Mode
–90
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–95
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–95
–100
–105
–105
THD (dB)
–100
–110
–115
–110
–115
–120
INPUT FREQUENCY = 50Hz
INPUT VOLTAGE = –0.5dBFS
TEMPERATURE = 25°C
REFERENCE VOLTAGE (V)
–125
12538-233
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
–105
Figure 36. THD vs. Reference Voltage at 4 kSPS, Low Power Mode
–100
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
INPUT FREQUENCY = 50Hz
VREF = 2.5V
INPUT VOLTAGE = –0.5dBFS
TEMPERATURE = 25°C
DECIMATION = 256
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
REFERENCE VOLTAGE (V)
Figure 33. THD vs. Reference Voltage at 16 kSPS, High Resolution Mode
–100
INPUT FREQUENCY = 50Hz
INPUT VOLTAGE = –0.5dBFS
TEMPERATURE = 25°C
12538-236
–120
–125
INPUT FREQUENCY = 50Hz
VREF = 2.5V
TEMPERATURE = 25°C
–135
0.172
0.344
0.516
0.688
0.860
1.032
1.204
1.376
1.548
1.720
1.892
2.064
2.236
2.408
2.580
2.752
2.924
3.096
3.268
3.440
3.612
3.784
3.956
4.128
4.300
4.472
4.644
–140
THD (dB)
–120
–125
–135
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–105
12538-232
THD (dB)
–100
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
12538-235
–100
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
INPUT FREQUENCY = 50Hz
VREF = 2.5V
INPUT VOLTAGE = –0.5dBFS
TEMPERATURE = 25°C
DECIMATION = 256
–105
THD (dB)
–115
–115
–120
–120
Figure 34. THD vs. MCLK Frequency, High Resolution Mode
Rev. E | Page 22 of 97
3976960
3659520
3342080
3024640
2707200
2389760
2072320
1754880
1437440
802560
1120000
485120
167680
MCLK FREQUENCY (Hz)
Figure 37. THD vs. MCLK Frequency, Low Power Mode
12538-237
MCLK FREQUENCY (Hz)
–130
12538-234
7953920
7319040
6684160
6049280
5414400
4779520
4144640
3509760
2874880
2240000
1605120
970240
–125
–125
335360
THD (dB)
–110
–110
Data Sheet
AD7770
GAIN =
GAIN =
GAIN =
GAIN =
115
110
110
SNR (dB)
115
105
100
95
95
VIN = 0dBFS
VREF = 2.5V
TEMPERATURE = 25°C
1
2
VIN = 0dBFS
VREF = 2.5V
TEMPERATURE = 25°C
90
4
8
16
32
ODR (kHz)
85
0.5
120
TEMPERATURE = 25°C
ODR = 16kSPS
DYNAMIC RANGE (dB)
TEMPERATURE = 25°C
ODR = 4kSPS
110
105
110
105
100
1
2
4
95
12538-239
95
8
PGA GAIN
1
8
Figure 42. Dynamic Range vs. PGA Gain, Low Power Mode
5
TEMPERATURE = 25°C
VIN = 0V
VREF = 2.5V
AVDD1x = 3.3V
–5
4
PGA GAIN
Figure 39. Dynamic Range vs. PGA Gain, High Resolution Mode
0
2
12538-242
DYNAMIC RANGE (dB)
8
115
100
TEMPERATURE = 25°C
VIN = 0V
VREF = 2.5V
AVDD1x = 3.3V
0
–5
OFFSET ERROR (µV)
–10
–15
–20
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–25
–30
1
2
4
PGA GAIN
–10
–15
–20
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–25
–30
8
12538-240
OFFSET ERROR (µV)
4
Figure 41. SNR vs. ODR at 4 kSPS, Low Power Mode
115
–35
2
ODR (kHz)
Figure 38. SNR vs. ODR at 16 kSPS, High Resolution Mode
120
1
Figure 40. Offset Error vs. PGA Gain, High Resolution Mode
–35
1
2
4
PGA GAIN
Figure 43. Offset Error vs. PGA Gain, Low Power Mode
Rev. E | Page 23 of 97
8
12538-243
85
1
2
4
8
105
100
90
GAIN =
GAIN =
GAIN =
GAIN =
120
12538-238
SNR (dB)
120
125
1
2
4
8
12538-241
125
AD7770
0
Data Sheet
–2
4
TEMPERATURE = 25°C
VIN = 0V
VREF = 2.5V
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
2
0
–2
OFFSET ERROR (µV)
–6
–8
–10
–12
–4
–6
–8
–14
–12
–16
–16
3.0
Figure 44. Offset Error vs. Power Supply Setting, High Resolution Mode
40
3.3
3.6
POWER SUPPLY SETTING
12538-247
3.6
12538-244
3.3
POWER SUPPLY SETTING
Figure 47. Offset Error vs. Power Supply Setting, Low Power Mode
45
AVDD1x = 3.3V
40
30
35
GAIN ERROR DRIFT (ppm)
20
10
0
–10
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–50
–40
–20
0
20
40
60
80
100
30
25
20
15
10
5
0
–5
–10
–15
120
–20
TEMPERATURE (°C)
0
0
0.017
TEMPERATURE = 25°C
GAIN = 1
VREF = 2.5V
VIN = 0dBFS
0.008
0
–0.008
–0.017
–0.035
3.6
AVDD1x SUPPLY (V)
12538-246
–0.035
3.3
Figure 46. Gain Error vs. AVDD1x Supply, High Resolution Mode
TEMPERATURE = 25°C
GAIN = 1
VREF = 2.5V
VIN = 0dBFS
–0.017
–0.026
3.0
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–0.008
–0.026
–0.043
1000
Figure 48. Gain Error Drift vs. Time
GAIN ERROR (%)
0.008
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
500
TIME (Hours)
Figure 45. Offset Drift vs. Temperature
0.017
168
12538-248
–40
12538-245
–20
–30
GAIN ERROR (%)
TEMPERATURE = 25°C
VIN = 0V
VREF = 2.5V
–14
–18
3.0
OFFSET DRIFT (µV)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–10
–0.043
3.0
3.3
AVDD1x SUPPLY (V)
Figure 49. Gain Error vs. AVDD1x Supply, Low Power Mode
Rev. E | Page 24 of 97
3.6
12538-249
OFFSET ERROR (µV)
–4
Data Sheet
0.005
0
–0.005
–0.011
–0.017
–0.011
–0.017
–0.023
–0.029
–0.029
–0.035
–0.035
25
105
125
TEMPERATURE (°C)
–0.400
–40
0.09
3
0.06
HIGH RESOLUTION
LOW POWER
0.05
0.04
0.03
0.02
0.01
2
1
0
–1
–2
–3
–4
1
2
4
8
PGA GAIN
–6
–40
25
105
125
TEMPERATURE (°C)
Figure 51. Channel Gain Mismatch, High Resolution Mode
12538-254
–5
12538-251
0
125
4
REFERENCE VOLTAGE DRIFT (mV)
0.07
105
Figure 53. Gain Error vs. Temperature, Low Power Mode
TEMPERATURE = 25°C
AVDD1x = 3.3V
VREF = 2.5V
VIN = 0dBFS
0.08
25
TEMPERATURE (°C)
Figure 50. Gain Error vs. Temperature, High Resolution Mode
GAIN ERROR (%)
–0.005
–0.023
–0.400
–40
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
AVDD1x = 3.3V
VREF = 2.5V
VIN = 0dBFS
0.005
12538-250
GAIN ERROR (%)
0
0.011
12538-253
0.011
0.017
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
AVDD1x = 3.3V
VREF = 2.5V
VIN = 0dBFS
GAIN ERROR (%)
0.017
AD7770
Figure 54. Internal Reference Voltage Drift
0.005
0.010
0
0.005
TEMPERATURE = 25°C
VIN = –0.5dBFS
VREF = 2.5V
AVDD1x = 3.3V
GAIN = 1
–0.015
–0.020
TEMPERATURE = 25°C
VIN = –0.5dBFS
VREF = 2.5V
AVDD1x = 3.3V
GAIN = 1
–0.025
–0.030
–40
25
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
105
TEMPERATURE (°C)
Figure 52. Total Unadjusted Error (TUE) vs. Temperature,
High Resolution Mode
125
0
–0.005
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
–0.010
–0.015
–40
25
105
TEMPERATURE (°C)
125
12538-255
TUE (% OF INPUT)
–0.010
12538-252
TUE (% OF INPUT)
–0.005
Figure 55. Total Unadjusted Error (TUE) vs. Temperature, Low Power Mode
Rev. E | Page 25 of 97
AD7770
Data Sheet
1.0
4
AINx+; VCM = 1.95V
AINx–; VCM = 1.95V
AINx+; VCM = 1.35V
AINx–; VCM = 1.35V
3
AINx+; VCM = 1.95V
AINx–; VCM = 1.95V
AINx+; VCM = 1.35V
AINx–; VCM = 1.35V
0.8
0.6
INPUT CURRENT (nA)
INPUT CURRENT (nA)
2
1
0
–1
0.4
0.2
0
–0.2
–0.4
–2
–0.6
–0.8
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
Figure 56. Input Current vs. Differential Input Voltage, High Resolution Mode
ABSOLUTE INPUT CURRENT (nA)
–4
–6
–8
–10
–12
–40
AIN0+
AIN0–
AIN2+
AIN2–
105
125
TEMPERATURE (°C)
Figure 57. Absolute Input Current vs. Temperature, High Resolution Mode
VREF = 2.5V
AVDD1x = 3.3V
2
1
0
–1
–2
–3
–4
–5
–2.5
2.0
2.5
–3
–4
–6
–40
AIN0+
AIN0–
AIN2+
AIN2–
25
105
125
TEMPERATURE (°C)
Figure 60. Absolute Input Current vs. Temperature, Low Power Mode
1.0
3
1.5
–2
1.2
AINx+ – AINx–; V CM = 1.95V
AINx+ – AINx–; V CM = 1.35V
1.0
–1
DIFFERENTIAL INPUT CURRENT (nA)
4
0.5
0
VREF = 2.5V
AVDD1x = 3.3V
AINx+ – AINx–; V CM = 1.95V
AINx+ – AINx–; V CM = 1.35V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
2.5
12538-258
DIFFERENTIAL INPUT CURRENT (nA)
5
0
1
–5
25
–0.5
2
12538-257
ABSOLUTE INPUT CURRENT (nA)
–2
–1.0
VREF = 2.5V
VIN = 2.5V
AVDD1x = 3.3V
3
0
–1.5
Figure 59. Input Current vs. Differential Input Voltage, Low Power Mode
4
2
–2.0
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
VREF = 2.5V
VIN = 2.5V
AVDD1x = 3.3V
4
VREF = 2.5V
AVDD1x = 3.3V
Figure 58. Differential Input Current vs. Differential Input Voltage,
High Resolution Mode
–1
–2.5
–2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
DIFFERENTIAL INPUT VOLTAGE ((AINx+) – (AINx–))
2.5
Figure 61. Differential Input Current vs. Differential Input Voltage,
Low Power Mode
Rev. E | Page 26 of 97
12538-261
6
–1.0
–2.5
12538-259
VREF = 2.5V
AVDD1x = 3.3V
12538-256
–4
–2.5
12538-260
–3
Data Sheet
AD7770
8
105
125
TEMPERATURE (°C)
Figure 62. Differential Input Current vs. Temperature, High Resolution Mode
0
–20
6
5
4
3
2
1
0
–40
125
0
–20
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
AVDD1x = 3.3V
VCM = 1.65V + 100mV p-p
Figure 64. AC Power Supply Rejection Ratio (PSRR) vs. Input Frequency at
16 kSPS, High Resolution Mode
Rev. E | Page 27 of 97
188933.526
12538-266
175653.757
162215.895
148461.848
121586.125
107990.171
81114.447
135023.987
INPUT FREQUENCY (Hz)
Figure 67. AC PSRR vs. Input Frequency at 4 kSPS, Low Power Mode
12538-267
9460001.00
8900002.00
8360002.00
7780003.00
7240004.00
6680005.00
6140006.00
5580007.00
5040007.00
4500008.00
3880009.00
12538-264
9460001.00
8900002.00
8360002.00
7780003.00
7240004.00
6680005.00
6140006.00
5580007.00
5040007.00
4500008.00
3880009.00
3320010.00
2780011.00
–150
–160
2220012.00
–150
–160
1680012.00
–130
–140
1140013.00
–120
–130
–140
20014.97
–120
3320010.00
–100
–110
2780011.00
–100
–110
–80
–90
2220012.00
–80
–90
1680012.00
AC PSRR (dB)
–60
–70
1140013.00
198023.844000
–50
–60
–70
580014.13
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–30
–40
–50
INPUT FREQUENCY (Hz)
94552.309
0
AVDD1x = 3.3V + 100mV p-p
–10
TEMPERATURE = 25°C
–20
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–30
–40
67360.401
Figure 66. CMRR vs. Input Frequency at 4 kSPS, Low Power Mode
20014.97
0
AVDD1x = 3.3V + 100mV p-p
–10
TEMPERATURE = 25°C
–20
40642.77
INPUT FREQUENCY (Hz)
Figure 63. Common-Mode Rejection Ratio (CMRR) vs. Input Frequency at
16 kSPS, High Resolution Mode
580014.13
INPUT FREQUENCY (Hz)
12538-263
184506.936000
171543.352000
158105.490000
145141.906000
132178.322000
118661.414000
92101.875000
105697.830000
79138.291000
–140
66174.707000
–140
52578.753000
–120
39615.169000
–120
26177.307000
–100
250.138735
–100
53922.539
–80
26888.723
–80
–60
13450.862
–60
171.09249
CMRR (dB)
–40
13213.723000
CMRR (dB)
105
Figure 65. Differential Input Current vs. Temperature, Low Power Mode
–40
AC PSRR (dB)
25
TEMPERATURE (°C)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
AVDD1x = 3.3V
VCM = 1.65V + 100mV p-p
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
12538-265
25
VREF = 2.5V
VIN = 2.5V
AVDD1x = 3.3V
7
DIFFERENTIAL INPUT CURRENT (nA)
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
12538-262
DIFFERENTIAL INPUT CURRENT (nA)
VREF = 2.5V
VIN = 2.5V
AVDD1x = 3.3V
AD7770
Data Sheet
0
0
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–10
–20
–20
–30
–70
Figure 68. Filter Profiles at 16 kSPS, High Resolution Mode
20
18
7681.0
7202.5
6724.0
6245.5
5767.0
5288.5
4810.0
4331.5
3853.0
Figure 71. Filter Profiles at 4 kSPS, Low Power Mode
6
AVDD1x
AVDD2x
AVDD4
IOVDD
5
ALL CHANNELS ENABLED
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
16
3374.5
FREQUENCY (Hz)
12538-271
FREQUENCY (Hz)
12538-268
30721.0
28802.5
26884.0
24965.5
23047.0
21128.5
19210.0
17291.5
15373.0
13454.5
9617.5
11536.0
7699.0
–120
5780.5
–110
–120
3862.0
–110
25.0
–100
1943.5
–90
–100
2896.0
–80
–90
2417.5
–80
–60
1939.0
–70
–50
982.0
–60
–40
1460.5
–50
25.0
–40
503.5
ATTENUATION (dB)
–30
ATTENUATION (dB)
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
–10
14
12
10
8
6
4
AVDD1x
AVDD2x
AVDD4
IOVDD
ALL CHANNELS ENABLED
4
3
2
1
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
0
2.0
12538-269
0
2.0
2.6
2.8
3.0
3.2
3.4
3.6
Figure 72. Supply Current vs. Supply Voltage, Low Power Mode
25
7
AVDD1x
AVDD2x
AVDD4
IOVDD
ALL CHANNELS ENABLED
SUPPLY CURRENT (mA)
6
15
10
5
AVDD1x
AVDD2x
AVDD4
IOVDD
ALL CHANNELS ENABLED
5
4
3
2
0
–40
25
105
125
TEMPERATURE (°C)
Figure 70. Supply Current vs. Temperature, High Resolution Mode
0
–40
25
105
125
TEMPERATURE (°C)
Figure 73. Supply Current vs. Temperature, Low Power Mode
Rev. E | Page 28 of 97
12538-273
1
12538-270
SUPPLY CURRENT (mA)
2.4
SUPPLY VOLTAGE (V)
Figure 69. Supply Current vs. Supply Voltage, High Resolution Mode
20
2.2
12538-272
2
Data Sheet
300
REF1–
REF1+
REF2–
REF2+
200
REFERENCE INPUT CURRENT (nA)
200
0
–200
–400
100
0
–100
–200
–300
–400
–500
–800
–600
12538-274
TEMPERATURE (°C)
Figure 74. Reference Input Current vs. Temperature, High Resolution Mode
TEMPERATURE (°C)
Figure 77. Reference Input Current vs. Temperature, Low Power Mode
60
80
SHUTDOWN SUPPLY CURRENT (µA)
70
60
50
40
30
20
AVDD1x
AVDD2x
AVDD4
IOVDD
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
40
30
20
10
0
–40
POWER CONSUMPTION (mW)
12
25
20
15
10
60
80
100
120
ONLY ONE CHANNEL ENABLED
AVDD1x
AVDD2x
AVDD4
IOVDD
10
8
6
4
2
5
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
12538-276
POWER CONSUMPTION (mW)
40
14
ONLY ONE CHANNEL ENABLED
AVDD1x
AVDD2x
AVDD4
IOVDD
0
1.8
20
Figure 78. Shutdown Supply Current vs. Temperature
40
30
0
TEMPERATURE (°C)
Figure 75. Shutdown Supply Current vs. Supply Voltage
35
–20
Figure 76. Power Consumption per Channel vs. Supply Voltage,
High Resolution Mode
0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
Figure 79. Power Consumption per Channel vs. Supply Voltage,
Low Power Mode
Rev. E | Page 29 of 97
12538-279
10
AVDD1x
AVDD2x
AVDD4
IOVDD
50
12538-275
SHUTDOWN SUPPLY CURRENT (µA)
REF1–
REF1+
REF2–
REF2+
–35.263
–29.594
–22.185
–15.223
–7.366
–0.405
7.006
14.429
22.067
29.170
36.646
44.122
52.009
58.557
66.064
74.427
81.446
89.252
96.238
105.348
112.092
119.542
123.075
–600
12538-277
400
12538-278
600
–35.263
–29.594
–22.185
–15.223
–7.366
–0.405
7.006
14.429
22.067
29.170
36.646
44.122
52.009
58.557
66.064
74.427
81.446
89.252
96.238
105.348
112.092
119.542
123.075
REFERENCE INPUT CURRENT (nA)
800
AD7770
AD7770
Data Sheet
90
80
70
300
Figure 80. Power Dissipation vs. Temperature, High Resolution Mode
25
15
10
5
125.9
12538-281
114.5
104.1
77.9
48.1
27.9
6.6
–15.2
–20.2
–28.8
–35.9
–37.1
0
TEMPERATURE (°C)
1475.0
12538-300
1372.2
1268.4
1165.5
950.6
1061.8
847.6
744.8
ELAPSED TIME (Hours)
Figure 82. Internal Reference Long Term Drift from 0 Hours to 1500 Hours
AVDD1x
AVDD2x
AVDD4
IOVDD
20
639.9
0
125.9
12538-280
114.5
104.1
77.9
48.1
27.9
6.6
–15.2
–100
–20.2
0
–28.8
–50
–35.9
0
10
535.6
50
20
TEMPERATURE (°C)
POWER DISSIPATION (mW)
100
432.3
30
150
327.6
40
200
224.1
50
120.3
60
44.5
VOLTAGE DRIFT (ppm)
250
–37.1
POWER DISSIPATION (mW)
350
AVDD1x
AVDD2x
AVDD4
IOVDD
Figure 81. Power Dissipation vs. Temperature, Low Power Mode
Rev. E | Page 30 of 97
Data Sheet
AD7770
TERMINOLOGY
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output of a
100 mV p-p differential input (AINx+ − AINx−), at a fixed
frequency, f = 1 kHz, to the power of a 100 mV p-p sine wave
applied to the common-mode voltage of AINx+ and AINx− at
frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Differential Nonlinearity (DNL) Error
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value.
DNL error is often specified in terms of resolution for which no
missing codes are guaranteed.
Integral Nonlinearity (INL) Error
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is a level 1½ LSB beyond
the last code transition. The deviation is measured from the middle
of each code to the true straight line.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale
input signal to the rms noise measured for an input. The value
for dynamic range is expressed in decibels.
Channel to Channel Isolation
Channel to channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale frequency
sweep sine wave signal to all seven unselected input channels and
determining how much that signal is attenuated in the selected
channel. The value is given for worst case scenarios across all
eight channels of the AD7770.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fA
and fB, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfA and nfB,
where m, n = 0,1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n is equal to 0. For
example, the second-order terms include (fA + fB) and (fA – fb)
and the third-order terms include (2fA + fB), (2fA − fb), (fA + 2fB),
and (fA − 2fB). The AD7770 is tested using the CCIF standard,
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second-order and third-order terms
are specified separately.
The calculation of the intermodulation distortion is per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum of
the fundamentals, expressed in decibels.
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale (−2.49999 V for the
±2.5 V range). The last transition (from 011 … 110 to 011 …
111) occurs for an analog voltage 1½ LSB below the nominal
full scale (2.49999 V for the ±2.5 V range). The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Gain Error Drift
Gain error drift is the ratio of the gain error change due to a
temperature change of 1°C and the full-scale range (2N). It is
expressed in parts per million.
Least Significant Bit (LSB)
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is
LSB (V) =
2VREF
2N
The LSB referred to the input is
LSB (VIN) =
2 VREF
PGAGAIN
2N
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but not
the linearity of the converter. PSRR is the maximum change in the
full-scale transition point due to a change in the power supply
voltage from the nominal value.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude of
the input signal and the peak spurious signal (including
harmonics).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Rev. E | Page 31 of 97
AD7770
Data Sheet
Offset Error
Offset error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.
Offset Error Drift
Offset error drift is the ratio of the offset error change due to a
temperature change of 1°C and the full-scale code range (2N). It
is expressed in μV/°C.
Rev. E | Page 32 of 97
Data Sheet
AD7770
THEORY OF OPERATION
The AD7770 is an 8-channel, simultaneously sampling, low
noise, 24-bit Σ-Δ ADC with integrated digital filtering per
channel and SRC.
Due to the high oversampling rate, this technique spreads the
quantization noise from 0 Hz to fCLKIN/2 (in the case of the AD7770,
fCLKIN relates to the external clock); therefore, the noise energy
contained in the band of interest is reduced (see Figure 83). To
further reduce the quantization noise, a high order modulator is
employed to shape the noise spectrum so that most of the noise
energy is shifted out of the band of interest (see Figure 84). The
digital filter that follows the modulator removes the large out of
band quantization noise (see Figure 85).
For more information on basic and advanced concepts of Σ-Δ
ADCs, see the MT-022 Tutorial and MT-023 Tutorial.
Digital filtering has certain advantages over analog filtering.
Because digital filtering occurs after the analog-to-digital
conversion process, it can remove noise injected during the
conversion. Analog filtering cannot remove noise injected
during conversion.
fCLKIN/2
Figure 83. Σ-Δ ADC Operation, Reduction of Noise Energy Contained in the
Band of Interest (Linear Scale X-Axis)
NOISE SHAPING
BAND OF INTEREST
fCLKIN/2
Figure 84. Σ-Δ ADC Operation, Majority of Noise Energy Shifted Out of the
Band of Interest (Linear Scale X-Axis)
DIGITAL FILTER CUTOFF FREQUENCY
BAND OF INTEREST
fCLKIN/2
Figure 85. Σ-Δ ADC Operation, Removal of Noise Energy from the Band of
Interest (Linear Scale X-Axis)
The Σ-Δ ADC starts the conversions of the input signal after the
supplies generated by the internal LDOs become stable. An
external signal is not required to generate the conversions.
ANALOG INPUTS
The AD7770 can be operated in bipolar or unipolar modes and
accepts true differential, pseudo differential, and single-ended
input signals, as shown in Figure 86 through Figure 89.
Table 10 summarizes the maximum differential input signal and
dynamic range for the different input modes.
Table 10. Input Signal Modes
Input Signal Mode
True differential
Pseudo differential
Single-ended
PGA Gain
All gains
All gains
All gains
12538-101
The AD7770 employs a Σ-Δ conversion technique to convert the
analog input signal into an equivalent digital word. The
overview of the Σ-Δ technique is that the modulator samples
the input waveform and outputs an equivalent digital word at
the input clock frequency, fCLKIN.
BAND OF INTEREST
12538-102
The AD7770 offers two operation modes: high resolution mode,
which offers up to 32 kSPS, and low power mode, which offers
up to 8 kSPS.
12538-100
QUANTIZATION NOISE
Maximum Differential Signal
±(VREF/PGAGAIN)
±(VREF/PGAGAIN)
VREF/PGAGAIN
Rev. E | Page 33 of 97
Maximum Peak-to-Peak Signal
2 × VREF/PGAGAIN
2 × VREF/PGAGAIN
VREF/PGAGAIN
AD7770
Data Sheet
BIPOLAR OR UNIPOLAR
TRUE DIFFERENTIAL
AVDD1x – 0.1V
AVSSx + 0.1V
Figure 86. Σ-Δ ADC Input Signal Configuration, True Differential
–0.4125
–0.8250
VREF = 2.5V
AVDD1x = 1.65V
AVSSx = –1.65V
–1.6500
1
2
4
PGA GAIN
–1.2375
8
The AD7770 provides a common-mode voltage pin (AVDD1x +
AVSSx)/2), VCM, for the single-supply, pseudo differential, or true
differential input configurations.
AVDD1x – 0.1V
VREF/PGAGAIN
TRANSFER FUNCTION
AINx+
AINx–
The AD7770 can operate with up to a 3.6 V reference, typical at
2.5 V, and converts the differential voltage between the analog
inputs (AINx+ and AINx−) into a digital output. The ADC
converts the voltage difference between the analog input pins
(AINx+ − AINx−) into a digital code on the output. The 24-bit
conversion result is in MSB first, twos complement format, as
shown in Table 11 and Figure 91.
12538-104
PSEUDO DIFFERENTIAL
0.4125
(AVDD1x + AVSSx)/2
Figure 90. Maximum Common-Mode Voltage Range for a Maximum
Differential Input Signal
BIPOLAR OR UNIPOLAR
VCM
TRUE DIFFERENTIAL
PSEUDO DIFFERENTIAL
0.8250
12538-103
AINx+
VCM
AINx–
VREF /PGAGAIN
1.2375
12538-107
COMMON-MODE VOLTAGE (V)
1.6500
AVSSx + 0.1V
Figure 87. Σ-Δ ADC Input Signal Configuration, Pseudo Differential
BIPOLAR
SINGLE-ENDED
Table 11. Output Codes and Ideal Input Voltages for PGA = 1×
VREF /PGAGAIN
AINx+
AINx–
12538-105
AVSSx + 0.1V
Figure 88. Σ-Δ ADC Input Signal Configuration, Single-Ended Bipolar
Condition
FS − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FS + 1 LSB
−FS
Analog Input
((AINx+) − (AINx−)),
VREF = 2.5 V
+2.499999702 V
+298 nV
0V
−298 nV
−2.499999702 V
−2.5 V
Digital Output Code,
Twos Complement
(Hex)
0x7FFFFF
0x000001
0x000000
0xFFFFFF
0x800001
0x800000
+ 0.1V
Figure 89. Σ-Δ ADC Input Signal Configuration, Single-Ended Unipolar
The common-mode input signal is not limited, but keep the
absolute input signal voltage on any AINx± pin between AVSSx +
100 mV and AVDD1x − 100 mV; otherwise, the input signal
linearity degrades and, if the signal voltage exceeds the absolute
maximum signal rating, damages the device.
Figure 90 shows the maximum and minimum voltage commonmode range at different PGA gains for a maximum differential
input voltage.
Rev. E | Page 34 of 97
011 ... 111
011 ... 110
011 ... 101
100 ... 010
100 ... 001
100 ... 000
–FSR
–FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
ANALOG INPUT
Figure 91. Transfer Function
12538-108
AINx+
AINx–
ADC CODE (TWOS COMPLEMENT)
VREF /PGAGAIN
12538-106
SINGLE-ENDED
UNIPOLAR
Data Sheet
AD7770
MCLK
START
SYNC_OUT
SYNC_IN
RESET
PGA
GAIN 1, 2, 4, 8
AINx+
Σ-Δ
MODULATOR
AINx–
DIGITAL
FILTER
SINC3
SRC
ESD
PROTECTION
GAIN
SCALING
AND
OFFSET
CORRECTION
DRDY
CONVERSION
DATA INTERFACE
DOUTx
SCLK
SIGNAL CHAIN FOR CHANNEL x
CONTROL BLOCK
FORMAT0
AND
FORMAT1
CONTROL
OPTION
PIN OR SPI
MODE0 TO MODE3
SPI CONTROL
12538-109
PIN CONTROL
CS SCLK SDO SDI
Figure 92. Top Level Core Signal Chain
CORE SIGNAL CHAIN
Each Σ-Δ ADC channel on the AD7770 has an identical signal path
from the analog input pins to the digital output pins. Figure 92
shows a top level implementation of this signal chain. Prior to
each Σ-Δ ADC, a PGA maps sensor outputs into the ADC inputs,
providing low input current in dc (±8 nA in high resolution
mode) single-ended input current, and ±4 nA differential input
current in high resolution mode), an 8 pF input capacitance in
ac, and configurable gains of 1, 2, 4, and 8. See the AN-1392
Application Note for more information. Each ADC channel has its
own Σ-Δ modulator, which oversamples the analog input and
passes the digital representation to the digital filter block. The
data is filtered, scaled for gain and offset, and is then output on
the data interface.
To minimize power consumption, the channels can be
individually disabled.
for the maximum common-mode voltage at maximum
differential input signals.
INTERNAL REFERENCE AND REFERENCE BUFFERS
The AD7770 integrates a 2.5 V, ±10 ppm/°C typical, voltage
reference that is disabled at power-up. The buffered reference is
available at Pin 49 and offers up to 10 mA of continuous current. A
100 nF capacitor is required if the reference is enabled.
In applications where a low noise reference is required, it is
recommended to add a low-pass filter (LPF) with a cutoff
frequency (fCUTOFF) below 10 Hz to the REF_OUT pin. Connect
the output of this filter to REFx+, and connect AVSSx to REFx−.
In this scenario, configure the Σ-Δ reference to be external by
configuring the reference buffers in enable or precharge mode. An
example of performance with and without the output filter is
shown in Figure 93.
115
CAPACITIVE PGA
VREF = INTERNAL REFERENCE
fCUTOFF < 10Hz
105
SNR (dB)
The AD7770 uses chopping of the PGA to minimize offset and
offset drift in the input amplifier, reducing the 1/f noise as well.
For the AD7770, the chopping frequency is set to 128 kHz for
high resolution mode, and 32 kHz for low power mode (see the
AN-1392 Application Note for more information). The chopping
tone is rejected by the sinc3 filter.
To minimize intermodulation effects that may cause image in
the band of interest, it is recommended to limit the input signal
bandwidth to 2/3 of the chop frequency.
The capacitive PGA common-mode voltage does not depend on
the gain, and can be any value as long as the input signal voltage
is within AVSSx + 100 mV to AVDD1x − 100 mV. See Figure 90
95
85
75
0.05
0.50
1.00
2.00
DIFFERENTIAL INPUT VOLTAGE (V)
2.50
12538-110
Each Σ-Δ ADC has a dedicated PGA, offering gain ranges of 1,
2, 4, and 8. This PGA reduces the need for an external input buffer
and allows the user to amplify small sensor signals to use the
full dynamic range of the AD7770. The PGA maximize the
signal chain dynamic range for small sensor output signals.
Figure 93. SNR Adding External LPF with VREF = Internal Reference and
fCUTOFF < 10 Hz
The AD7770 can be used with an external reference connected
between the REFx+ and REFx− pins. Recommended reference
voltage sources for the AD7770 include the ADR441 and ADR4525
family of low noise, high accuracy voltage references.
Rev. E | Page 35 of 97
AD7770
Data Sheet
DCLK DIVIDER
1, 2, 4, 8, 16, 32, 64, 128
MCLK
MCLK DIVIDER
HIGH RESOLUTION MODE: MCLK/4
LOW POWER MODE: MCLK/8
MOD_MCLK
DCLKx
PGA
ADC
MODULATOR
DATA
INTERFACE
CONTROL
SINC
FILTER
AINx–
DRDY
DOUT3
TO
DOUT0
DEC RATES = FROM ×64 TO ×4095.99
12538-111
AINx+
Figure 94. Clock Generation on the AD7770
The reference buffers can be operated in three different modes:
buffer enabled mode, buffer bypassed mode, and buffer pre-Q
mode.
In buffer enabled mode, the buffer is fully enabled, minimizing
the current requirements from the external references. Note that
the buffer output voltage headroom is ±100 mV from the rails.
In buffer bypassed mode, the external reference is directly
connected to the ADC reference capacitors; the reference must
provide enough current to correctly charge the internal ADC
reference capacitors. In this mode of operation, a slight
degradation in crosstalk is expected because the ADC channels
are not isolated from each other.
Buffer pre-charged (pre-Q) mode is the default operation
mode. It is a hybrid mode where the internal reference buffers are
connected during the initial acquisition time to precharge the
internal ADC reference capacitors. During the final phase of the
acquisition, the reference is connected directly to the ADC
capacitors. This mode has some benefits compared to the buffer
enabled and buffer bypassed modes. In buffer pre-Q mode, the
reference current requirements are minimized compared to
buffer bypassed mode and the noise contribution from the
internal reference buffers is removed (compared to buffer
enabled mode).
In buffer pre-Q mode, the headroom/footroom of the buffer
reference is not applicable because the reference sets the final
voltage in the ADC reference capacitors.
INTEGRATED LDOs
The AD7770 has three internal LDOs to regulate the internal
supplies: two LDOs for the analog block and one LDO for the
digital core. The internal LDOs requires an external 1 μF
decoupling capacitor on the DREGCAP, AREG1CAP, and
the AREG2CAP pins. The LDO slew rate may be low because
it depends on the main supply slew rate; therefore, a hardware
reset generated by pulsing the RESET pin at power-up is required
to guarantee that the digital block initializes correctly.
CLOCKING AND SAMPLING
The AD7770 includes eight Σ-Δ ADC cores. Each ADC receives
the same master clock signal. The AD7770 requires a maximum
external MCLK frequency of 8192 kHz for high resolution mode
and 4096 kHz for low power mode. The MCLK is internally
divided by 4 in high performance mode and by 8 in low power
mode to produce the modulator MCLK (MOD_MCLK) signal
used as the modulator sampling clock for the ADCs. The MCLK
can be decreased to accommodate lower ODRs if the minimum
ODR selected by the sinc3 filter is not low enough. If the external
clock is lower than 256 kHz, set the CLK_QUAL_DIS bit (in
SPI control mode only).
The AD7770 integrates an internal oscillator clock that initializes
the internal registers at power-up. The CLK_SEL pin defines the
external clock used after initialization (see Table 12).
Table 12. Clock Sources
CLK_SEL State
0
Clock Source
CMOS
1
Crystal
Connection
Input to XTAL2/MCLK, IOVDD
logic level. XTAL1 must be
tied to DGND.
Connected between XTAL1
and XTAL2/MCLK.
The MCLK signal generates the DCLK output signal, which in
turn clocks the Σ-Δ conversion data from the AD7770, as shown
in Figure 94.
DIGITAL RESET AND SYNCHRONIZATION PINS
An external pulse in the SYNC_IN pin generates the internal
reset of the digital block; this pulse does not affect the data
programmed in the internal registers. A pulse in this pin is
required in two cases as follows:
After updating one or more registers directly related to the
sinc3 filter. These are power mode, offset, gain, and phase
compensation.
To synchronize multiple devices.
The pulse in the SYNC_IN pin must be synchronous with MCLK.
Rev. E | Page 36 of 97
Data Sheet
AD7770
There are two different ways to achieve a synchronous pulse if
the controller/processor cannot generate it, as follows:
The SYNC_IN and SYNC_OUT pins must be externally
connected if internal synchronization is used.
The digital filter implements three main notches, one at the
maximum ODR (32 kHz or 8 kHz, depending on the power
mode) and another two at the ODR frequency selected to stop
noise aliasing into the pass band.
Figure 96 shows the typical filter transfer function for the high
resolution and low power modes using a decimation rate of 128.
0
–20
–30
If the START pin is not used, tie it to IOVDD.
ASYNCHRONOUS
PULSE
–40
–50
–60
–70
AD7770
START
MCLK
LOW POWER MODE DECIMATION = 128
HIGH RESOLUTION MODE DECIMATION = 128
–10
GAIN (dB)
If multiple AD7770 devices must be synchronized, the
SYNC_OUT pin of one device can be connected to multiple
devices. This synchronization method requires the use of a
common MCLK signal for all the AD7770 devices connected,
as shown in Figure 95.
The AD7770 offers a low latency sinc3 filter. Most precision
Σ-Δ ADCs use sinc3 filters because the sinc3 filter offers a low
latency path for applications requiring low bandwidth signals,
for example, in control loops or where application specific
postprocessing is required. The digital filter adds notches at
multiples of the sampling frequency.
–80
SYNCHRONIZATION SYNC_OUT
LOGIC
–90
–100
DIGITAL FILTER
0
10
20
30
40
50
60
FREQUENCY (kHz)
SYNC_IN
12538-113
Applying an asynchronous pulse on the START pin, which
is then internally synchronized with the external MCLK
clock, and the resulting synchronous signal is output on
the SYNC_OUT pin.
Triggering the SYNC_OUT internally. When the AD7770
is configured in SPI control mode, toggling Bit 0 in the
GENERAL_USER_CONFIG_2 register generates a
synchronous pulse that is output on the SYNC_OUT pin.
Figure 96. Sinc3 Frequency Response
The sample rate converter featured allows fine tuning of the
decimation rate, even for noninteger multiples of the decimation
rate. See the Sample Rate Converter (SRC section for more
information on filter profiles for noninteger decimation rates.
IOVDD
AD7770
MCLK
MCLK
START
SYNCHRONIZATION SYNC_OUT
LOGIC
NC
SHUTDOWN MODE
DIGITAL FILTER
The AD7770 can be placed in shutdown mode by pulling AVDD2
to ground and connecting 1 MΩ resistance, pulled low, to
XTAL2. In this mode, the average current consumption is
reduced below 1 mA, as shown in Figure 97.
SYNC_IN
IOVDD
AD7770
1.0
IAVDD1x
IAVDD2x
IAVDD4x
IIOVDD
START
SYNCHRONIZATION SYNC_OUT
LOGIC
NC
SYNC_IN
NOTES
1. NC = NO CONNECT.
Figure 95. Multiple AD7770 Devices Synchronization
12538-112
DIGITAL FILTER
SUPPLY CURRENT (mA)
MCLK
AVDDx = 3.3V
IOVDD = 3.3V
0.5
0
–0.5
–40
10
60
TEMPERATURE (°C)
Figure 97. Shutdown Current
Rev. E | Page 37 of 97
125
12538-114
DIGITAL FILTERING
AD7770
Data Sheet
CONTROLLING THE AD7770
The AD7770 can be controlled using either pin control mode or
SPI control mode.
Pin control mode allows the AD7770 to be hardwired to predefined
settings that offer a subset of the overall functionality of the
AD7770. In this mode, the SRC and diagnostic features or
extended errors source are not available.
Controlling the AD7770 over the SPI allows the user access to
the full monitoring, diagnostic, and Σ-Δ control functionality.
SPI control offers additional functionality such
as offset, gain, and phase correction per channel, in addition to
access to the flexible SRC to achieve a coherent sampling.
See Table 13 for more details about these different configurations.
PIN CONTROL MODE
In pin control mode, the AD7770 is configured at power-up
based on the level of the mode pins, MODE0, MODE1, MODE2,
and MODE3. These four pins set the following functions on the
AD7770: the mode of operation, the decimation rate/ODR, the
PGA gain, and the reference source, as shown in Table 14.
Due to the limited number of mode pins and the number of
options available, the PGA gain control is grouped into blocks
of 4, and the ODR is selected for the maximum value defined by
the decimation rate; ODR (kHz) = 2048/decimation for high
resolution mode, and ODR (kHz) = 512/decimation for low
power mode.
Depending on the mode selected, the device is configured to
use an external or an internal reference.
The conversion data can be read back using the SPI or the data
output interface, as shown in Table 13. If the data output interface
is used to read back the data from the conversions, the number of
DOUTx lines enabled and the number of clocks required for
the Σ-Δ data transfer are determined by the logic level of the
CONVST_SAR, FORMAT0, and FORMAT1 pins. In this case,
the DCLK2, DCLK1, and DCLK0 pins select the Σ-Δ output
interface and control the DCLKx divide function, which is a
submultiple of MCLK, as shown in Table 15. The DCLKx divide
function sets the frequency of the data output interface DCLKx
signal. The DCLK minimum frequency depends on the decimation rate and operation mode. See the Data Output Interface
section for more details about the minimum DCLKx frequency.
All the pins that define the AD7770 configuration mode are
reevaluated each time the SYNC_IN pin is pulsed. The typical
connection diagram for pin control mode is shown in Figure 98.
Table 13. Format of the Data Interface
CONVST_SAR State
1
0
FORMAT1
0
0
1
1
0
FORMAT0
0
1
0
1
0
Control Mode
Pin
Pin
Pin
SPI
Pin
0
1
Pin
1
1
0
1
Pin
SPI
Data Output Mode
SPI output
SPI output
SPI output
Defined in Register 0x013 and Register 0x014
DOUT0, Channel 0 and Channel 1
DOUT1, Channel 2 and Channel 3
DOUT2, Channel 4 and Channel 5
DOUT3, Channel 6 to Channel 7
DOUT0, Channel 0 to Channel 3
DOUT1, Channel 4 to Channel 7
DOUT0, Channel 0 to Channel 7
Defined in Register 0x013 and Register 0x014
Table 14. Pin Mode Options
Pin State
MODE3
0
0
0
0
0
0
0
0
1
MODE2
0
0
0
0
1
1
1
1
0
MODE1
0
0
1
1
0
0
1
1
0
MODE0
0
1
0
1
0
1
0
1
0
Decimation
Rate
1024
512
256
128
64
512
256
128
64
Power Mode
High resolution
High resolution
High resolution
High resolution
High resolution
High resolution
High resolution
High resolution
High resolution
Rev. E | Page 38 of 97
PGA Gain Channel
Channel 0 to
Channel 4 to
Channel 3
Channel 7
1
1
1
1
1
1
1
1
1
1
1
4
1
4
1
4
1
4
Reference
Source
External
External
External
External
External
External
External
External
External
Data Sheet
AD7770
Pin State
MODE3
1
1
1
1
1
1
1
MODE2
0
0
0
1
1
1
1
MODE1
0
1
1
0
0
1
1
Decimation
Rate
512
256
128
512
256
128
64
MODE0
1
0
1
0
1
0
1
Power Mode
High resolution
High resolution
High resolution
Low power
Low power
Low power
Low power
PGA Gain Channel
Channel 0 to
Channel 4 to
Channel 3
Channel 7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reference
Source
Internal
Internal
Internal
External
External
External
External
Table 15. DCLKx Selection for Pin Control Mode State
DCLK2/SCLK
0
0
0
0
1
1
1
1
DCLK1/SDI
0
0
1
1
0
0
1
1
DCLK0/SDO
0
1
0
1
0
1
0
1
MCLK Divider
1
2
4
8
16
32
64
128
EXTERNAL
REFERENCE
AVDD 3.3V
AVDD 3.3V
AVSSx
AVDD1x
VCM
REFx+
VCM
AVDD 3.3V
AVSSx
AVSSx
AVSSx
REFx–
AVDD4
REF_OUT AVDD2x AREGxCAP
BUFFER
AVSSx
IOVDD 1.8V TO 3.6V
AVSSx
IOVDD
AD7770
BUFFER
DREGCAP SYNC_IN
SYNC_OUT
START
RESET
DRDY
AIN0+
PGA
AIN7+
24-BIT
Σ-Δ
ADC
PGA
AIN7–
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
ADC
DATA
SERIAL
INTERFACE
AIN0–
SINC3/SRC
CS
SCLK
SDO
SPI
CONTROL
INTERFACE
SDI
SPI/SPORT
SLAVE
INTERFACE
FPGA
OR
DSP
SPI
MASTER
INTERFACE
CLK_SEL
XTAL1
XTAL2
MODE3
TO
MODE0
CONVST_SAR
DCLK2
TO
DCLK0
FORMAT1
AND
FORMAT0
12538-115
AVSSx
CLOCK
SOURCE
Figure 98. Pin Mode Connection Diagram with External Reference
Rev. E | Page 39 of 97
AD7770
Data Sheet
AVDD 3.3V
AVDD3.3V
AVSSx
AVSSx
AVDD1x
VCM
REFx+
VCM
REFx–
AVSSx
REF_OUT
BUFFER
AVDD4
IOVDD 2V TO 3.6V
AVSSx
AVSSx
AVDD2x AREGxCAP
AD7770
BUFFER
IOVDD
DREGCAP SYNC_IN
SYNC_OUT
START
RESET
DRDY
AIN0+
PGA
ADC
DATA
SERIAL
INTERFACE
AIN0–
24-BIT
Σ-Δ
ADC
PGA
AIN7–
SINC3/SRC
SPI
CONTROL
INTERFACE
DIAGNOSTIC
INPUTS
CS
SCLK
SDO
SDI
FULL BUFFER
AUXAIN+
12-BIT
SAR ADC
MUX
AUXAIN–
AVSSx
GPIO2
TO
GPIO0
CLK_SEL
XTAL1
SPI/SPORT
SLAVE
INTERFACE
FPGA
OR
DSP
SPI
MASTER
INTERFACE
CONVST_SAR
XTAL2
FORMAT1
IOVDD
FORMAT0
IOVDD
CLOCK
SOURCE
12538-116
AIN7+
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
Figure 99. SPI Control Mode Connection Diagram with Internal Reference
SPI CONTROL
The second option for control and monitoring the AD7770 is via
the SPI. This option allows access to the full functionality on the
AD7770, including access to the SAR converter, phase
synchronization, offset and gain adjustment, diagnostics and
the SRC. To use the SPI control, set the FORMAT0 and
FORMAT1 pins to logic high.
In this mode, the SPI can also read the Σ-Δ conversation data by
setting the SPI_SLAVE_MODE_EN bit.
The typical connection diagram for SPI control mode is shown
in Figure 99.
Functionality Available in SPI Mode
SPI control of the AD7770 offers the super set of the functions
and diagnostics. The SPI Control Functionality section describes
the functionality and diagnostics offered when in SPI control mode.
Offset and Gain Correction
Offset and gain registers are available for system calibration.
The gain register is preprogrammed during final production for
a PGA gain of 1, but can be overwritten with a new value if
required.
The gain register is 24 bits long and is split across three registers,
CHx_GAIN_UPPER_BYTE, CHx_GAIN_MID_BYTE, and
CHx_GAIN_LOWER_BYTE, which set the gain on a per
channel basis. The gain value is relative to 0x555555, which
represents a gain of 1.
The offset register is 24 bits long and is spread across three byte
registers, CHx_OFFSET_UPPER_BYTE, CHx_OFFSET_MID_
BYTE, and CHx_OFFSET_LOWER_BYTE. The default value is
0x000000 at power-up. Program the offset as a twos complement,
signed 24-bit number. If the channel gain is set to its nominal
value of 0x555555, an LSB of offset register adjustment changes
the digital output by −4/3 LSBs.
As an example of calibration, the offset measured is −200 LSB
(with both AINx± pins connected to the same potential).
An offset adjustment of −150 LSB changes the digital output by
−150 × (−4/3) = 200 LSBs (gain value = 0x555555), representing
this number as two complement, 0xFFFFFF − 0x96 + 1 =
0xFFFF70. Program the offset register as follows:
CHx_OFFSET_UPPER_BYTE = 0xFF
CHx_OFFSET_MID_BYTE = 0xFF
CHx_OFFSET_LOWER_BYTE = 0x70
Note that the offset compensation is performed before the gain
compensation. The gain is programmed during final testing for
PGAGAIN = 1. The gain register values can be overwritten; however,
after a reset or power cycle, the gain register values revert to the
hard coded programmed factory setting.
If the gain required is 0.75 of the nominal value (0x555555), the
value that must be programmed is
0x555555 × 0.75 = 0x400000
Then, an LSB of the offset register adjustment changes the
digital output by −4/3 × 0.75 = 1 LSB. Program the gain register
as follows:
Rev. E | Page 40 of 97
CHx_GAIN_UPPER_BYTE = 0x40
CHx_GAIN_MID_BYTE = 0x00
CHx_GAIN_LOWER_BYTE = 0x00
Data Sheet
AD7770
SPI Control Functionality
Global Control Functions
Table 16. Phase Adjustment vs. Decimation Rate
The following list details the global control functions of the
AD7770:
High resolution and low power modes of operation
ODR: SRC
VCM buffer power-down
Internal/external reference selection
Enable, precharged, or bypassed reference buffer modes
Internal reference power-down
SAR diagnostic mux
SAR power-down
GPIO write/read
SPI SAR conversion readback
SPI slave mode—read Σ-Δ results
SDO and DOUTx drive strength
DOUTx mode
DCLK division
Internal LDO bypassed
CRC protection: enabled or disabled
Per Channel Functions
The following list details the per channel functions of the
AD7770:
Phase Adjustment Compensation (n)
×1
×2
×4
×8
×16
Decimation Rate
≤255
≤511
≤1023
≤2047
≤4095
The maximum phase delay cannot be equal to or greater than
the decimation rate. If this is the case, the value changes
internally to the decimation rate value minus 1.
When the CHx_SYNC_OFFSET register is written it automatically
overwrites itself multiplied by the corresponding factor (n), as
defined in Table 16. As CHx_SYNC_OFFSET is only 8 bits
long, the resulting value is scaled down to fit 8 bits. To know
whether the phase adjustment has clipped or not, see Table 17.
Table 17.
CHx_SYNC_OFFSET × n
≤255
≤511
≤1023
≤2047
≤4095
CHx_SYNC_OFFSET Overwrite
CHx_SYNC_OFFSET × n
CHx_SYNC_OFFSET × n/2
CHx_SYNC_OFFSET × n/4
CHx_SYNC_OFFSET × n/8
CHx_SYNC_OFFSET × n/16
As an example, the phase mismatch between Channel 0 and
Channel 1 is 5°, and the ODR is 5 kSPS in high resolution mode. In
this case, the decimation rate is 2048 kHz/5 kHz = 409.6, which
means that the offset register value is multiplied internally by 2.
PGA gain
Σ-Δ channel power-down
Phase delay: synchronization phase offset per channel
Calibration of offset
Calibration of gain
Σ-Δ input signal mux
Channel error register
PGA gain
Assuming an input signal of 50 Hz, the number of MOD_
MCLK pulses required to sample a full period is 2048 kHz/
50 Hz = 40960 > 360°/40960 = 0.00878°.
Phase Adjustment
The AD7770 phase delay can be adjusted to compensate for phase
mismatches between channels due to sensors or signal channel
phase errors connected to the AD7770. Achieve phase adjustment
by programming the CHx_SYNC_OFFSET register. This
programming delays the synchronization signal by a certain
number of modulator clocks (MOD_CLK) to individually initiate
the digital filter for each Σ-Δ ADC. In other words, program the
channel with a higher phase with Phase 0, whereas for the
channel with lower phase, delay to compensate the phase
mismatch.
The phase adjustment register is read after a pulse on the
SYNC_IN pin; consequently, any further changes on the register
have no effect unless a pulse is generated (see the Digital Reset
and Synchronization Pins section for more information on how
to generate a pulse in the pin).
The phase offset register is multiplied internally by a factor (n)
that depends on the decimation rate, as shown in Table 16.
If a 5° delay is required, the number of MOD_MCLK delays
must be 569 (5°/0.00878°) because the offset register is multiplied
by 2; the final offset register value is 409.6/2 − 569/2, which
gives a negative value. In this case, if the offset value programmed
to the register is higher than 204 (for example, 210 × 2 = 420),
the value is internally changed to 408, resulting in a phase
compensation of 408 × 0.00878° = 3.58°.
PGA Gain
The PGA gain can be selected individually by appropriately
selecting Bits[7:6] in the CHx_CONFIG register, as shown in
Table 18.
Table 18. PGA Gain Settings via CHx_CONFIG
CHx_CONFIG, Bits[7:6] Setting
00
01
10
11
PGA Gain Setting
1
2
4
8
If the Σ-Δ reference is updated, it is recommended to apply a
pulse on the SYNC_IN pin to remove invalid samples during
the transition of the reference
Rev. E | Page 41 of 97
AD7770
Data Sheet
Decimation
Σ-Δ Reference Configuration
The decimation defines the sampling frequency as follows:
The AD7770 can operate with internal or external references. In
addition, for diagnostic purposes, the analog supply can be used
as a reference, as shown in Table 19. REFx−/REFx+ allows the
selection of a voltage reference where the REFx+ is lower
voltage than REFx− pin.
In high resolution mode, the sampling frequency =
MCLK/(4 × decimation)
In low power mode, the sampling frequency = MCLK/
(8 × decimation)
Table 19. Σ-Δ References
Refer to the Sample Rate Converter (SRC section for more
information.
GPIOx Pins
If the AD7770 operates in SPI control mode, the mode pins
operate as GPIOx pins, as shown in Figure 100. The GPIOx pins
can be configured as inputs or outputs in any order.
GPIO0
Setting for
ADC_MUX_CONFIG,
Bits[7:6]
00
01
10
11
Channel 0 to
Channel 3
REF1+/REF1−
Internal reference
AVDD1A/AVSS1A
REF1−/REF1+
Channel 4 to
Channel 7
REF2+/REF2−
Internal reference
AVDD1B/AVSS1B
REF2−/REF2+
Reference buffer operation is described in Table 20. The
selected reference and buffer operation mode affect all
channels.
GPIO1
REGISTER
MAP
If the Σ-Δ reference is updated, it is recommended to apply a
pulse on the SYNC_IN pin to remove invalid samples during
the transition of the reference.
12538-117
GPIO2
Power Modes
Figure 100. GPIOx Pin Functionality
Configuration control and readback of the GPIOx pins are set
via Bits[2:0] in the GPIO_CONFIG register (0 = input, 1 = output)
and the GPIO_DATA register. Among other uses, the GPIOs
can control an external mux connected to the auxiliary inputs of
the SAR ADC. Use this mux to verify the results on the Σ-Δ ADCs.
In addition, the GPIOx pins can be used to externally trigger a
new decimation rate. Refer to the Sample Rate Converter (SRC
section for more information about this functionality.
The AD7770 offers different power modes to improve the power
efficiency, high resolution and low power mode, which can be
controlled via GENERAL_USER_CONFIG_1, Bit 6. To further
reduce the power, additional blocks can be disabled independently,
as described in Table 21.
If the power mode changes, a pulse on the SYNC_IN pin is
required.
Table 20. Reference Buffer Operation Modes
Reference Buffer
Operation Mode
Enabled
Precharged
Disabled
REFx+
BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 0
BUFFER_CONFIG_1, Bit 4 = 1; BUFFER_CONFIG_2, Bit 7 = 1
BUFFER_CONFIG_1, Bit 4 = 0
REFx−
BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 0
BUFFER_CONFIG_1, Bit 3 = 1; BUFFER_CONFIG_2, Bit 6 = 1
BUFFER_CONFIG_1, Bit 3 = 0
Table 21. Additional Disable Power-Down Blocks
Block
VCM
Reference Buffer
Internal Reference Buffer
Σ-Δ Channel
SAR
Internal Oscillator
Register
GENERAL_USER_CONFIG_1, Bit 5
BUFFER_CONFIG_1, Bits[4:3]
GENERAL_USER_CONFIG_1, Bit 4
CH_DISABLE, Bits[7:0]
GENERAL_USER_CONFIG_1, Bit 3
GENERAL_USER_CONFIG_1, Bit 2
Rev. E | Page 42 of 97
Notes
Enable by default
Precharged mode by default
Disable by default
All channels enable
Disable by default
Enable by default
Data Sheet
AD7770
LDO Bypassing
The internal LDOs can be individually bypassed and an external
supply can be applied directly to the AREG1CAP, AREG2CAP,
or DREGCAP pin. Table 22 shows the absolute minimum and
maximum supplies for these pins, as well as the associated
register used to bypass the regulator.
Table 22. LDO Bypassing
LDO
AREG1CAP
AREG2CAP
DREGCAP
1
BUFFER_CONFIG_2,
Bits[2:0]1
1XX
X1X
XX1
Max (V)
1.9
1.9
1.98
Supply
Min (V)
1.85
1.85
1.65
Table 24. SDO Strength
GENERAL_USER_CONFIG_2, Bits[4:3] Setting
00
01
10
11
Mode
Nominal
Strong
Weak
Extra strong
SCLK is the serial clock input for the device. All data transfers
(on either SDO or SDI) occur with respect to this SCLK signal.
X means don’t care.
DIGITAL SPI
The SPI serial interface on the AD7770 consists of four signals:
CS, SDI, SCLK, and SDO. A typical connection diagram of the
SPI is shown in Figure 101.
DSP/FPGA
AD7770
In SPI control mode, there are four different levels of I/O strength
on the SDO pin that can be selected in GENERAL_USER_
CONFIG_2, Bits[4:3], as described in Table 24.
CS
SCLK
SDI
The SPI can operate in multiples of eight bits. For example, in
SPI control mode, if the SDO pin is used to read back the data
from the internal register or the SAR ADC, the data frame is 16 bits
wide (CRC disabled), as shown in Figure 102, or 24 bits wide (CRC
enabled), as shown in Figure 103. In this case, the controller can
generate one frame of 16 bits or 24 bits (with and without the
CRC enabled), or 2 or 3 frames of 8 bits (with and without the
CRC enabled). When the SDO pin reads back the data from the
Σ-Δ channels, 64 bits must be read back from the controller (in
this case, the controller can generate a frame of 64 bits—either
2 × 32 bits, 4 × 16 bits, or 8 × 8 bits).
SPI CRC—Checksum Protection (SPI Control Mode)
12538-118
SDO
Figure 101. SPI Control Interface—AD7770 is the SPI Slave, Digital Signal
Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master
The SPI operates in Mode 0 and Mode 3: CPOL = 0, CPHA = 0
(Mode 0) or CPOL = 1, CPHA = 1 (Mode 3).
In pin control mode, the SDO can read back the Σ-Δ results,
depending on the level of the CONVST_SAR pin, as described in
Table 13.
In SPI control mode, the SPI transfers data into the on-chip
registers while the SDO pin reads back data from the on-chip
registers or reads the SAR or the Σ-Δ conversions results,
depending on the selected operation mode.
The AD7770 has a checksum mode that improves SPI
robustness in SPI control mode. Using the checksum ensures
that only valid data is written to a register and allows data read
from the device to be validated. The SPI CRC can be enabled by
setting the SPI_CRC_TEST_EN bit. If an error occurs during a
register write, the SPI_CRC_ERR is set in the error register.
Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum
being performed on all the R/W operations. When SPI_
CRC_TEST_EN is enabled, an 8-bit CRC word is appended
to every SPI transaction for SAR and register map operations.
For more information on Σ-Δ readback operations, see the
CRC Header section.
To ensure that the register write is successful, it is recommended to
read back the register and verify the checksum.
The SDO data source in SPI control mode is defined by the
GENERAL_USER_CONFIG_2 and GENERAL_USER_
CONFIG_3 registers, as described in Table 23.
For CRC checksum calculations, the following polynomial is
always used: x8 + x2 + x + 1. See the SPI Control Mode
Checksum section for more information.
Table 23. SPI Operation Mode in SPI Control Mode
SPI Read/Write Register Mode (SPI Control Mode)
GENERAL_USER_
CONFIG_2, Bit 5
Setting
0
0
1
The AD7770 has on-board registers to configure and control the
device.
1
X means don’t care.
GENERAL_USER_
CONFIG_3, Bit 4
Setting1
0
1
X
Mode
Internal register
Σ-Δ data conversion
SAR conversion
The registers have 7-bit addresses—the 7-bit register address on
the SDI line selects the register for the read/write function. The
7-bit register address follows the R/W bit in the SDI data. The
8 bits on the SDI line following the 7-bit register address are the
data to be written to the selected register if the SPI is a write
transfer. Data on the SDI line is clocked into the AD7770 on
the rising edge of SCLK, as shown in Figure 3.
Rev. E | Page 43 of 97
AD7770
Data Sheet
register address, the 8-bit data, and an 8-bit CRC (if enabled).
To avoid unwanted writes to the internal register while the SAR
conversions are read back through the SDO line, it is recommended to send a readback command, for example, 0x8000,
to the device, which is ignored because the SDO pin shifts out
the content of the SAR ADC.
The data on the SDO line during the SPI transfer contains the
8-bit 0010 0000 header: 8 bits of register data in the case of a read
(R) operation, or 8 zeros in the case of a write (W) operation.
With the CRC disabled, the basic data frame on the SDI line
during the transfer is 16 bits long, as shown in Figure 102.
When the CRC is enabled, a minimum frame length of 24 SCLK
periods are required on SPI transfers. The 24 bits of data on the
SDO line consist of an 8-bit header (0010 0000), 8 bits of data, and
an 8-bit CRC (see Figure 103).
If consecutive conversions are performed in the SAR ADC, read
back the result from the previous conversion before a new
conversion is generated. Otherwise, the results are corrupted.
SPI SAR Diagnostic Mode (SPI Control Mode)
Σ-Δ Data, ADC Mode
Setting Bit 5 in the GENERAL_USER_CONFIG_2 register
configures the SDO line to shift out data from the SAR ADC
conversions, as described in Table 23.
In pin control mode, the SPI can be used to read back the Σ-Δ
conversions as described in Table 13. In SPI control mode, the SPI
reads back the Σ-Δ conversions by setting GENERAL_USER_
CONFIG_3, Bit 4, as described in Table 23; in this mode, the
AD7770 internal register can be written to, but any readback
command is ignored because the SDO data frame is dedicated to
shifting out the conversion results from the Σ-Δ ADCs. To
avoid unwanted writes to the internal register, it is recommended
to send a readback command, for example, 0x8000, to the device,
which is ignored because the SDO pin shifts out the content of
the Σ-Δ ADC.
In SAR mode, the AD7770 internal registers can be written to,
but any readback command is ignored because the SDO data
frame is dedicated to shift out the conversion results from the
SAR ADC.
To exit this mode of operation, reset Bit 5 in the GENERAL_
USER_CONFIG_2 register.
The data on the SDO line during the SPI transfer contains a
4-bit 0010 header and the 12-bit SAR conversion result if the
CRC is disabled.
The SDO pin data can be read back in any multiple of 8 bits, for
example, as 64 bits, 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits. See the
24-bit example in Figure 105.
When the CRC is enabled, a minimum frame length of 24 SCLK
periods are required on SPI transfers. The 24 bits of data on the
SDO line consist of a 4-bit header (0010), the 12-bit data, and
an 8-bit CRC, as shown in Figure 104.
SPI Software Reset
Keeping the SDI pin high during 64 consecutives clocks
generates a software reset.
Per the SPI read/write register mode (see the SPI Read/Write
Register Mode section), the SDI line contains the R/W bit, a 7-bit
CS
SDI
SDO
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
12538-119
SCLK
Figure 102. 16-Bit SPI Transfer—CRC Disabled
CS
SDI
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
SDO
0
0
1
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
Figure 103. 24-Bit SPI Transfer—CRC Enabled
Rev. E | Page 44 of 97
12538-120
SCLK
Data Sheet
AD7770
CS
SCLK
R/W
A6
A5
A4
SDO
0
0
1
0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR SAR I
CRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0
11
10
9
8
7
6
5
4
3
2
1
0
12538-121
SDI
Figure 104. SAR ADC/Diagnostic Mode—CRC Enabled
DRDY
CS
SCLK
SDO
0x800000
0x800000
HEADER CH0
D23 TO D8CH0
D7 TO D0CH0
HEADER CH1
Figure 105. SPI Used to Read Back the Σ-Δ ADC Data, in 24-Bit Frames
Rev. E | Page 45 of 97
D23 TO D16CH1
12538-301
SDI
AD7770
Data Sheet
RMS NOISE AND RESOLUTION
Table 25 through Table 27 show the dynamic range (DR), rms
noise referred to input (RTI), effective number of bits (ENOB),
and effective resolution (ER) of the AD7770 for various output
data rates and gain settings. The numbers given are for the bipolar
input range with an external 2.5 V reference. These numbers are
typical and are generated with a differential input voltage of 0 V
when the ADC is continuously converting on a single channel.
It is important to note that the effective resolution is calculated
using the rms noise; 16,384 consecutives samples were used to
calculate the rms noise.
Effective Resolution = log2(Input Range/RMS Noise)
ENOB = (DR − 1.78)/6
HIGH RESOLUTION MODE
Table 25. DR and RTI for High Resolution Mode
Decimation
Rate
64
128
256
512
1024
2048
Output Data
Rate (SPS)
32,000
16,000
8000
4000
2000
1000
f−3 dB (Hz)
8369
4818.8
2511
1269
636.3
318.5
Gain = 1
DR (dB) RTI (μV rms)
103.20
12.10
109.43
6.00
112.97
4.00
116.00
2.80
119.00
1.98
123.00
1.38
Gain = 2
DR (dB) RTI (μV rms)
101.96
6.97
108.30
3.39
112.38
2.13
115.86
1.45
119.19
1.01
121.98
0.72
Gain = 4
DR (dB) RTI (μV rms)
99.20
4.71
105.07
2.38
110.23
1.39
113.68
0.92
116.75
0.65
119.79
0.46
Gain = 8
DR (dB) RTI (μV rms)
95.30
3.82
100.71
1.94
105.98
1.13
109.81
0.7
113.12
0.51
115.88
0.35
Gain = 2
ENOB (Bits) ER (Bits)
16.94
18.45
17.99
19.49
18.67
20.16
19.24
20.72
19.8
21.24
20.26
21.73
Gain = 4
ENOB (Bits) ER (Bits)
16.48
18.02
17.45
19.00
18.31
19.78
18.88
20.38
19.39
20.89
19.9
21.39
Gain = 8
ENOB (Bits) ER (Bits)
15.83
17.32
16.73
18.30
17.6
19.08
18.24
16.39
18.79
20.23
19.25
20.76
Gain = 2
DR (dB) RTI (μV rms)
101.63
7.19
108.38
3.51
112.01
2.24
115
1.51
118.72
1.05
Gain = 4
DR (dB) RTI (μV rms)
99.35
4.84
104.7
2.47
109.4
1.49
112.95
0.99
116.43
0.67
Gain = 8
DR (dB) RTI (μV rms)
93.96
4.15
100.25
2.12
105.18
1.18
109.14
0.77
112.47
0.54
Gain = 2
ENOB (Bits) ER (Bits)
16.88
18.41
18.00
19.44
18.60
20.09
19.10
20.66
19.72
21.18
Gain = 4
ENOB (Bits) ER (Bits)
16.5
17.98
17.39
18.95
18.17
19.68
18.76
20.27
19.34
20.84
Gain = 8
ENOB (Bits) ER (Bits)
15.61
17.2
16.65
18.17
17.47
19.01
18.13
19.62
18.68
20.15
Table 26. ENOB and ER for High Resolution Mode
Decimation
Rate
64
128
256
512
1024
2048
Output Data
Rate (SPS)
32,000
16,000
8000
4000
2000
1000
f−3 dB (Hz)
8369
4818.8
2511
1269
636.3
318.5
Gain = 1
ENOB (Bits) ER (Bits)
17.14
18.66
18.18
19.67
18.76
20.25
19.27
20.77
19.77
21.27
20.43
21.79
LOW POWER MODE
Table 27. DR and RTI for Low Power Mode
Decimation
Rate
64
128
256
512
1024
Output Data
Rate (SPS)
8000
4000
2000
1000
500
f−3 dB (Hz)
2092.2
1204.8
627.75
317.25
159.25
Gain = 1
DR (dB) RTI (μV rms)
102.8
12.5
108.94
6.45
112.7
4.23
115.83
2.94
118.97
2.04
Table 28. ENOB and ER for Low Power Mode
Decimation
Rate
64
128
256
512
1024
Output Data
Rate (SPS)
8000
4000
2000
1000
500
f−3 dB (Hz)
2092.2
1204.8
627.75
317.25
159.25
Gain = 1
ENOB (Bits) ER (Bits)
17.07
18.61
18.09
19.56
18.72
20.17
19.24
20.70
19.76
21.22
Rev. E | Page 46 of 97
Data Sheet
AD7770
DIAGNOSTICS AND MONITORING
SELF DIAGNOSTICS ERROR
The AD7770 includes self diagnostic features to guarantee the
correct operation. If an error is detected, the ALERT pin is
pulled high to generate an external interruption to the controller.
In addition, the header of the Σ-Δ output data contains an alert
bit that informs the controller of a chip error (see the ADC
Conversion Output—Header and Data section).
the EXT_MCLK_SWITCH_ERR bit is set in the general error
register, GEN_ERR_REG_2.
If EXT_MCLK_SWITCH_ERR is set, the device is operating off
the internal oscillator, and is waiting for an appropriate external
clock.
To use a slow external clock (
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