HMC241ALP3E

GaAs, Nonreflective, SP4T Switch 100 MHz to 4 GHz HMC241ALP3E Data Sheet 13 NIC 14 GND 12 RF1 NIC 2 11 NIC HMC241ALP3E NIC 3 10 NIC RF3 4 9 A 8 B 7 VDD 6 2:4 TTL DECODER RF2 PACKAGE BASE 16215-001 Cellular/4 G infrastructure Wireless infrastructure Automotive telematics Mobile radios Test equipment RF4 1 GND 5 APPLICATIONS 15 RFC FUNCTIONAL BLOCK DIAGRAM Broadband frequency range: 100 MHz to 4 GHz Nonreflective 50 Ω design Low insertion loss: 0.7 dB at 2 GHz High isolation: 43 dB at 2 GHz High input linearity at 250 MHz to 4 GHz 1 dB compression (P1dB): 29 dBm typical Third order intercept (IP3): 47 dBm typical High power handling 28.5 dBm through path 25 dBm terminated path Single positive supply: 3 V to 5 V Integrated 2 to 4 line decoder 16-lead, 3 mm × 3 mm LFCSP package ESD rating: 250 V (Class 1A) Pin compatible with the HMC7992 16 GND FEATURES Figure 1. GENERAL DESCRIPTION The HMC241ALP3E is a general-purpose, nonreflective, 100 MHz to 4 GHz single-pole, four-throw (SP4T) switch manufactured using a gallium arsenide (GaAs) process. This switch offers high isolation of 43 dB typical at 2 GHz, low insertion loss of 0.7 dB at 2 GHz, and on-chip termination of the isolated ports. The on-chip circuitry allows the HMC241ALP3E to operate at a single, positive supply voltage range of 3 V to 5 V. This switch requires two positive logic control voltages. The HMC241ALP3E Rev. C includes an on-chip, binary two to four line decoder that provides logic control from two logic input lines to select one of the four radio frequency (RF) lines. The HMC241ALP3E is available in a 3 mm × 3 mm, 16-lead LFCSP package. The HMC7992 is the silicon version of this switch and features better performance up to higher frequencies. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC241ALP3E Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Charcteristics ................................................6 Applications ....................................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................6 Functional Block Diagram .............................................................. 1 Input Power Compression and Third-Order Intercept (IP3) ..7 General Description ......................................................................... 1 Theory of Operations........................................................................8 Revision History ............................................................................... 2 Applications Information .................................................................9 Specifications..................................................................................... 3 Evaluation Board ...........................................................................9 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 11 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 11 Pin Configuration and Function Descriptions ............................. 5 Interface Schematics..................................................................... 5 REVISION HISTORY 8/2018—Rev. B to Rev. C Changed Reflow Temperature (MSL1 Rating) to Reflow Temperature, Table 2 ........................................................................ 4 Deleted Note 1, Table 2; Renumbered Sequentially ..................... 4 Changes to Theory of Operation Section ...................................... 8 Changes to Ordering Guide .......................................................... 11 11/2017—Rev. A to Rev. B This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Changed N/C to NIC .................................................... Throughout Changes to Features, Applications, and General Description .... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Figure 2 and Table 3 ..................................................... 5 Changes to Figure 10 through Figure 13 ....................................... 7 Added Theory of Operation Section ............................................. 8 Added Applications Information Section ..................................... 9 Changes to Table 5 ............................................................................ 9 Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 Rev. C | Page 2 of 11 Data Sheet HMC241ALP3E SPECIFICATIONS VDD = 3 V or 5 V, VCTRL = 0 V or VDD, TCASE = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1 to RF4 (On) Symbol f 100 MHz to 1 GHz 1 GHz to 2 GHz 2 GHz to 2.5 GHz 2.5 GHz to 4 GHz RETURN LOSS RFC and RF1 to RF4 (On) Third-Order Intercept SUPPLY Voltage Current DIGITAL CONTROL INPUTS Voltage Low High Current Low High 1 Min 0.1 100 MHz to 1 GHz 1 GHz to 2 GHz 2 GHz to 2.5 GHz 2.5 GHz to 4 GHz ISOLATION Between RFC and RF1 to RF4 (Off ) RF1 to RF4 (Off ) SWITCHING Rise and Fall Time On and Off Time INPUT LINEARITY1 1 dB Power Compression Test Conditions/Comments tRISE, tFALL tON, tOFF P1dB IP3 100 MHz to 2.5 GHz 2.5 GHz to 4 GHz 100 MHz to 4 GHz 250 MHz to 4 GHz 10 % to 90 % of RF output 50 % VCTL to 90 % of RF output 250 MHz to 4 GHz VDD = 3 V VDD = 5 V 10 dBm per tone, 1 MHz spacing VDD = 3 V VDD = 5 V VDD pin VDD IDD 40 38 35 25 23 Typ Max 4 Unit GHz 0.6 0.7 0.9 1.2 0.9 1.0 1.2 1.5 dB dB dB dB 45 43 41 32 dB dB dB dB 18 12 12 dB dB dB 30 100 ns ns 24 29 dBm dBm 50 47 dBm dBm 3 2.5 5 5 V mA 0.8 0.8 3 5 V V V V CTRLA and CTRLB pins VCTL VINL VINH VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V 0 0 2 2 IINL IINH 0.2 40 Input linearity performance degrades at frequencies less than 250 MHz. Rev. C | Page 3 of 11 µA µA HMC241ALP3E Data Sheet ABSOLUTE MAXIMUM RATINGS For recommended operating conditions, see Table 1. Table 2. Parameter Positive Supply Voltage (VDD) Digital Control Input Voltage RF Input Power (f = 100 MHz to 4 GHz, TCASE = 85°C) VDD = 3 V Through Path Terminated Path Hot Switching VDD = 5 V Through Path Terminated Path Hot Switching Junction Temperature, TJ Storage Temperature Range Reflow Temperature Junction to Case Thermal Resistance, θJC Through Path Terminated Path Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Rating 7V −0.5 V to VDD +1 V 23.5 dBm 20 dBm 17.5 dBm Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 28.5 dBm 25 dBm 22.5 dBm 150°C −65°C to +150°C 260°C 144°C/W 300°C/W 250 V (Class 1A) Rev. C | Page 4 of 11 Data Sheet HMC241ALP3E 13 NIC RF4 1 12 RF1 NIC 2 11 NIC NIC 3 HMC241ALP3E TOP VIEW (Not to Scale) 10 NIC 9 RF2 A 8 B 7 VDD 6 GND 5 RF3 4 NOTES 1. NOT INTERNALLY CONNECTED. THESE PINS MUST BE CONNECTED TO PCB RF GROUND TO MAXIMIZE ISOLATION. 2. THE EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 16215-003 14 GND 16 GND 15 RFC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2, 3, 10, 11, 13 4 5, 14, 16 6 7 Mnemonic RF4 NIC 8 A 9 12 15 RF2 RF1 RFC EPAD RF3 GND VDD B Description RF Port 4. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Not Internally Connected. These pins must be connected to the printed circuit board (PCB) RF ground to maximize isolation. RF Port 3. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Ground. The package bottom has an exposed metal pad that must connect to the PCB RF/dc ground. Supply Voltage. Logic Control Input B. See Figure 4 for the control input interface schematic. See Table 4 and the recommended input control voltages range in Table 1 Logic Control Input A. See Figure 4 for the control input interface schematic. See Table 4 and the recommended input control voltages range in Table 1 RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Exposed Pad. The exposed pad must be connected to RF/dc ground. INTERFACE SCHEMATICS Figure 3. RFC to RF4 Interface Schematic Figure 5. Supply Voltage Schematic VDD 80kΩ 16215-005 600Ω 3Ω 16215-006 2pF VDD 16215-004 RFC, RF1, RF2, RF3, RF4 Figure 4. CTRLA and CTRLB Interface Schematic Rev. C | Page 5 of 11 HMC241ALP3E Data Sheet TYPICAL PERFORMANCE CHARCTERISTICS 0 –1 –1 –3 +85°C +25°C –40°C –4 1 2 3 4 5 6 FREQUENCY (GHz) 0 –10 –10 –20 RETURN LOSS (dB) –5 –20 –25 RFC RF1 TO RF4 OFF RF1 TO RF4 ON 2 3 4 5 6 FREQUENCY (GHz) 16215-008 1 3 4 5 6 –30 –40 –50 RF1 RF2 RF3 RF4 –60 –35 0 2 Figure 8. Insertion Loss Between RFC to RFx vs. Frequency 0 –15 1 FREQUENCY (GHz) 0 –30 RF1 RF2 RF3 RF4 –5 Figure 6. Insertion Loss Between RFC and RF1 vs. Frequency at Various Temperatures RETURN LOSS (dB) –3 –4 –5 0 –2 Figure 7. Return Loss for RFC, RF1 to RF4 On, and RF1 to RF4 Off vs. Frequency –70 0 1 2 3 4 5 FREQUENCY (GHz) Figure 9. Isolation Between RFC and RFx vs. Frequency Rev. C | Page 6 of 11 6 16215-010 –2 16215-009 INSERTION LOSS (dB) 0 16215-007 INSERTION LOSS (dB) INSERTION LOSS, RETURN LOSS, AND ISOLATION Data Sheet HMC241ALP3E INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT (IP3) 35 INPUT COMPRESSION (dB) 30 25 20 30 25 20 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 10. Input Compression vs. Frequency at Room Temperature, VDD = 3 V 0 2 3 4 5 6 Figure 12. Input Compression vs. Frequency at Room Temperature, VDD = 5 V 55 55 50 50 45 1 FREQUENCY (GHz) INPUT IP3 (dB) INPUT IP3 (dB) 15 16215-011 15 16215-013 P1dB P0.1dB P1dB P0.1dB 40 45 35 0 1 2 3 4 5 6 FREQUENCY (GHz) 16215-012 40 Figure 11. Input IP3 vs. Frequency at Room Temperature, VDD = 3 V 35 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 13. Input IP3 vs. Frequency at Room Temperature, VDD = 5 V Rev. C | Page 7 of 11 16215-014 INPUT COMPRESSION (dB) 35 HMC241ALP3E Data Sheet THEORY OF OPERATIONS The ideal power-up sequence is as follows: The HMC241ALP3E requires a positive supply voltage at the VDD pin and two logic control inputs at the A and B pins to control the state of the RF paths. Depending on the logic level applied to the A and B pins, one RF path is in the insertion loss state while the other three paths are in an isolation state (See Table 4). The insertion loss path conducts the RF signal between the RF throw pad and RF common pad while the isolation paths provide high loss between RF throw pads terminated to internal 50 Ω resistors and the insertion loss path. 1. 2. 3. 4. Power up GND. Power up VDD. Power up the digital control inputs. The relative order of the logic control inputs is not important. However, powering the digital control inputs before the VDD supply can inadvertently become forward biased and damage the internal ESD protection structures. Apply an RF input signal. The design is bidirectional; the RF input signal can be applied to the RFC pad while the RF throw pads are the outputs, or the RF input signal can be applied to the RF throw pads while the RFC pad is the output. All of the RF ports are dc-coupled to VDD through internal resistors. Therefore, dc blocking the capacitors are required at the RF ports. The power-down sequence is the reverse of the power-up sequence. Table 4. Control Voltage Truth Table Digital Control Input CTRLA CTRLB Low Low High Low Low High High High RFC to RF1 Insertion loss (on) Isolation (off ) Isolation (off ) Isolation (off ) RFC to RF2 Isolation (off ) Insertion loss (on) Isolation (off ) Isolation (off ) Rev. C | Page 8 of 11 RF Paths RFC to RF3 Isolation (off ) Isolation (off ) Insertion loss (on) Isolation (off ) RFC to RF4 Isolation (off ) Isolation (off ) Isolation (off ) Insertion loss (on) Data Sheet HMC241ALP3E APPLICATIONS INFORMATION of 50 Ω. For optimal RF and thermal grounding, as many plated through vias as possible are arranged around transmission lines and under the exposed pad of the package. EVALUATION BOARD The 108333-HMC241ALP3 is a 4-layer evaluation board. Each copper layer is 0.7 mil (0.5 oz) and separated by dielectric materials. Figure 14 shows the stack up for this evaluation board. Figure 15 shows the layout of the 108333-HMC241ALP3 evaluation board with component placement. The power supply port is connected to the VDD test point, J6. The control voltages are connected to the A and B test points, J8 and J7. The ground reference is connected to the GND test point, J9. The NIC pins are connected to the PCB ground to maximize isolation. On the supply trace, VDD, a 10 nF bypass capacitor, is used to filter high frequency noise. G = 13mil W = 16mil 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) 0.5oz Cu (0.7mil) T = 0.7mil H = 10mil TOTAL THICKNESS ~62mil R04350 0.5oz Cu (0.7mil) FR4 0.5oz Cu (0.7mil) 16215-015 R04350 0.5oz Cu (0.7mil) Figure 14. The 108333-HMC241ALP3 Evaluation Board (Cross Sectional View) All RF and dc traces are routed on the top copper layer whereas the inner and bottom layers are grounded planes that provide a solid ground for the RF transmission lines. Top dielectric material is a 10 mil Rogers RO4350. The middle and bottom dielectric materials provide mechanical strength. The overall board thickness is 62 mil, allowing the SMA launchers to be connected at the board edges. The RF transmission lines were designed using a coplanar waveguide (CPWG) model, with trace width of 16 mil and ground clearance of 13 mil to have a characteristic impedance The RF input and output ports (RFC, RF1, RF2, RF3, and RF4) are connected through 50 Ω transmission lines to the soldered down SMA launchers, J1 to J5. For dc blocking to the RF pins, C1 to C5 are populated with 100 pF capacitors. A thru calibration line connects the unpopulated J10 and J11 launchers; this transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. Table 5 and Figure 16 are the bill of materials and schematic, respectively. Table 5. Evaluation Board Components Component J1 to J5 J6 to J9 J10, J11 C1 to C5 C6 U1 PCB Rev. C | Page 9 of 11 Default Value Not Applicable Not Applicable Do not insert 100 pF 10 nF Not Applicable 104708 Description PCB mount SMA connector DC pin PCB mount SMA connector Capacitor, C0402 package Capacitor, C0402 package HMC241ALP3E SP4T switch Evaluation PCB Data Sheet 16215-016 HMC241ALP3E Figure 15. 108333-HMC241ALP3 Evaluation Board Component Placement J1 C5 EPAD C1 J2 1 2 3 4 RF4 RF3 HMC241ALP3E RF4 NIC NIC RF3 RF1 NIC NIC RF2 J4 C3 12 11 10 9 RF1 RF2 C2 J5 C4 THRU CAL J10 J11 C6 Figure 16. Evaluation Board Schematic Rev. C | Page 10 of 11 A J8 B J7 VDD J6 16215-017 5 6 7 8 GND VDD B A J3 GND RFC GND NIC 16 15 14 13 RFC Data Sheet HMC241ALP3E OUTLINE DIMENSIONS 0.30 0.25 0.20 0.50 BSC 13 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 16 1 12 1.70 1.60 SQ 1.50 EXPOSED PAD 9 TOP VIEW 0.90 0.85 0.80 4 5 8 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PKG-004831 0.45 0.40 0.35 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VEED-4 11-22-2016-A PIN 1 INDICATOR DETAIL A (JEDEC 95) 3.10 3.00 SQ 2.90 Figure 17. 16-Terminal Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.85 mm Package Height (CP-16-50) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC241ALP3E HMC241ALP3ETR 108333-HMC241ALP3 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Terminal Lead Frame Chip Scale Package [LFCSP] 16-Terminal Lead Frame Chip Scale Package [LFCSP] Evaluation Board All models are RoHS compliant. ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16215-0-8/18(C) Rev. C | Page 11 of 11 Package Option CP-16-50 CP-16-50