LT3967
1.3A Eight-Switch Matrix
LED Dimmer with CRC-8
FEATURES
DESCRIPTION
Eight Independent 15V/110mΩ NMOS Switches
n Controls LED Dimming of Strings Up to 54V
n I2C Serial Interface with Programmable Address
n I2C Packet Error Checking with CRC-8
n Programmable 256:1 (8-Bit) PWM Dimming
n 11-Bit Precision Exponential Fade with
Programmable Time
n Independent On/Off Control for Each Switch
n Programmable Shorted/Open LED Threshold with
Fault Reporting
n Internal PWM Signal Generator
n Programmable Watchdog Timer
n Accurate V Referred Enable Pin
IN
n User Defined Power-Up/Reset State of Switches
n Thermally Enhanced TSSOP Package
n
The LT®3967 is an LED bypass switching device for dimming individual LEDs in a string using a common current
source. It features eight individually controlled floating
source 15V/110mΩ NMOS switches. The eight switches
can be connected in parallel and/or in series to bypass
current around LEDs in a string. The LT3967 uses the I2C
serial interface to communicate with a microcontroller.
Each of the eight channels can be independently programmed to bypass the LED string in constant on or off,
or PWM dimming with or without fade transition. Using
the programmable fade option provides 11-bit resolution
exponential transition between PWM dimming states. The
LT3967 provides an internal clock generator and also supports an external clock source for PWM dimming. The
LT3967 reports fault conditions for each channel such as
open LED and shorted LED. The four address pins allow
16 LT3967 devices to share the I2C bus and define the
power-up state of the switches.
n
All registered trademarks and trademarks are the property of their respective owners.
n
APPLICATIONS
Automotive LED Headlight Clusters
Large LED Displays
n RGBW Color Mixing Lighting
TYPICAL APPLICATION
1A Matrix LED Dimmer Powered by a Buck LED Driver
VIN
32V TO 36V
10µF
50V
VIN
1µF ×2
50V
LED+
BST
DRN8
22nF
255k
EN/UVLO
L1
33µH
1A
100mΩ
SW
VOUT
10.2k
267k
22nF
50V
FB
LT3932
2.2µF
GND
D1: NEXPERIA BAT46WJ
D2: NXP PMEG4010CEJ
L1: WURTH 74437349330
PWMTG, FAULT, AND
ISMON NOT USED
CTRL
INTVCC
1M
ISN
SYNC/SPRD
INTVCC
SS
RT
RP
287k
350kHz
2.2µF
49.9k
LED+
VDD
SRC7
DRN6
SRC6
DRN5
CLKIN
1A
UP TO 26V LED
VC
10k
ENH
SRC8
DRN7
VDD
2.2µF
LT3967
10k
ALERT
SCL
SDA
SRC4
DRN3
ISP
PWM
VIN
SRC5
DRN4
10k
VREF
1µF
50V
D2
D1
INTVCC
RTSYNC
SRC3
DRN2
WDI
SRC2
DRN1
ADDR1
10k
10k
CLKIN
350kHz
3.3V
0V
10nF
ADDR2
ADDR3
330pF
10nF
SRC1
GND
ADDR4
3967 TA01
Rev 0
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1
LT3967
TABLE OF CONTENTS
Features............................................................................................................................. 1
Applications........................................................................................................................ 1
Typical Application................................................................................................................ 1
Description......................................................................................................................... 1
Absolute Maximum Ratings...................................................................................................... 3
Pin Configuration.................................................................................................................. 3
Order Information.................................................................................................................. 3
Electrical Characteristics......................................................................................................... 4
Typical Performance Characteristics........................................................................................... 7
Pin Functions....................................................................................................................... 9
Block Diagram.....................................................................................................................11
Applications Information........................................................................................................12
Overview................................................................................................................................................................ 12
Power-On Reset and Dimming Cycle Initialization................................................................................................. 12
Operation in Shutdown Condition.......................................................................................................................... 12
Dimming without Fade Transition vs Dimming with Fade Transition...................................................................... 13
LT3967 I2C Registers............................................................................................................................................ 14
LT3967 Command Registers and Channel Control................................................................................................ 14
I2C Serial Interface................................................................................................................................................. 14
The Start and Stop Conditions............................................................................................................................... 17
I2C Serial Port Data Transfer.................................................................................................................................. 17
LT3967 I2C Commands and Write/Read Protocols................................................................................................ 19
LT3967 Alert Response Protocol Using Alert Response Address (ARA)................................................................ 23
Watchdog Timeout Reset....................................................................................................................................... 24
RTSYNC Input Clock Fault Detection and Alert Assertion....................................................................................... 24
LED/Overheat Fault Detection And Reporting......................................................................................................... 24
Open LED Fault Detection and Alert Assertion....................................................................................................... 25
Shorted LED Fault Detection and Alert Assertion................................................................................................... 25
LED Fault Status Bit Clearance............................................................................................................................... 25
Overheat Fault Detection and Alert Assertion......................................................................................................... 25
Overheat Status Bits Clearance.............................................................................................................................. 25
Alert Deassertion................................................................................................................................................... 25
Printed Circuit Board Layout.................................................................................................................................. 25
Typical Applications..............................................................................................................27
Package Description.............................................................................................................28
Typical Application...............................................................................................................30
Related Parts......................................................................................................................30
2
Rev 0
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LT3967
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
VIN.............................................................................60V
VIN - SRC[8:1].........................................................–0.3V
ENH............................................................................60V
DRN[8:1]....................................................................60V
SRC[8:1].....................................................................60V
DRN[8:1] - SRC[8:1] (Each Channel)...............–0.3V, 17V
VDD..............................................................................6V
WDI..............................................................................6V
SDA, SCL, ALERT............................. –0.3V to VDD + 0.3V
RTSYNC.......................................................................6V
ADDR[4:1]....................................................................6V
Operating Junction Temperature Range (Note 2)
LT3967E.............................................. –40°C to 125°C
LT3967J.............................................. –40°C to 150°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
DRN8
1
28 SRC8
VIN
2
27 DRN7
ENH
3
26 SRC7
ALERT
4
25 DRN6
SCL
5
24 SRC6
SDA
6
23 DRN5
VDD
7
RTSYNC
8
ADDR1
9
20 SRC4
ADDR2 10
19 DRN3
ADDR3 11
18 SRC3
ADDR4 12
17 DRN2
WDI 13
16 SRC2
SRC1 14
15 DRN1
29
GND
22 SRC5
21 DRN4
FE PACKAGE
28-LEAD PLASTIC TSSOP
θJA = 30°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3967EFE#PBF
LT3967EFE#TRPBF
LT3967FE
28-Lead Plastic TSSOP
–40°C to 125°C
LT3967JFE#PBF
LT3967JFE#TRPBF
LT3967FE
28-Lead Plastic TSSOP
–40°C to 150°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev 0
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3
LT3967
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied
to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise
noted.
PARAMETER
CONDITIONS
VDD Input Supply Voltage
MIN
l
TYP
2.7
VDD Operating IQ
I2C Bus Idle, RTSYNC = 28k
1.5
VDD Shutdown IQ
VIN - ENH < 1.15V, All Channels LED ON
VIN - ENH < 1.15V, All Channels LED OFF
0.5
0.6
VIN Operating Voltage
All Channels VOTH = VSTH = 0 (Note 3)
VIN Operating IQ (Channel Not Switching)
All Channels VOTH = VSTH = 0, LED ON
VIN Shutdown IQ
5.5
V
2.2
mA
mA
mA
V
1.3
1.8
mA
All Channels VOTH = VSTH = 1, LED OFF
2.5
3.5
mA
All Channels VOTH = 1, VSTH = 0, LED ON
1.8
2.5
mA
VIN - ENH < 1.15V, All Channels LED ON
VIN - ENH < 1.15V, All Channels LED OFF
0.9
1.4
DRN[8:1] Operating Voltage
l
Channel LED Is On (Channel Switch Is Off)
Channel LED Is Off (Channel Switch Is On)
mA
mA
VIN – 1V
l
SRC[8:1] Operating Voltage
Current Out of SRC[8:1] Pins (Each Channel)
UNITS
60
l
8
MAX
11
45
l
l
Switch On-Resistance
VIN – 6V
V
20
75
µA
µA
110
Switch Leakage Current
DRN = 8V, SRC = 0V, VOTH = 1
Switch Transition Time (tr/tf)
DRN to 5V Through a 50Ω Resistor, VOTH = 1
1.0
V
mΩ
1
µA
1.6
2.2
µs
DRN[8:1] to SRC[8:1] Overvoltage Protection LED or Switch Bypass Current is 1.3A
Clamp Voltage
l
15
17
V
Response Time from Switch Overvoltage
Protection to Switch Turn On
LED or Switch Bypass Current is 1.3A
l
5.2
6.6
µs
Programmable Open LED Threshold (VOTH)
SRC = 0V, VOTH = 0 (Note 3)
SRC = 0V,VOTH = 1
SRC = 2V, VOTH = 0
SRC = 2V,VOTH = 1
l
l
l
l
5.2
10.4
5.0
10.1
6.1
11.4
5.5
10.8
7.0
12.4
6.0
11.5
V
V
V
V
Programmable Shorted LED Threshold (VSTH) VSTH = 0 (Note 3)
VSTH = 1
l
l
0.85
3.6
1
4
1.15
4.4
V
V
ENH Threshold Voltage Falling
ENH(VTH) (VIN - ENH)
l
1.1
1.22
1.34
V
ENH Threshold Voltage Rising Hysteresis
ENH Pin Input Bias Current
50
VIN – ENH = 1.5V, Current Out of ENH Pin
mV
40
100
nA
170
450
880
198
500
1010
220
550
1130
Hz
Hz
Hz
0.83
0.88
0.93
V
1000
Hz
58
Hz
RTSYNC Programmable Internal Oscillator or External Clock Source
LED PWM Dimming Frequency
(= RTSYNC Programmed Oscillator
Frequency/2048 or External Clock
Frequency/2048)
RTSYNC = 80.6kΩ
RTSYNC = 28kΩ
RTSYNC = 10kΩ
RTSYNC Output Voltage (Using Internal
Oscillator)
RTSYNC = 28kΩ
l
l
l
Programmable LED PWM Dimming
Frequency Range (Using Internal Oscillator)
100
Standby Fixed LED PWM Dimming Frequency RTSYNC = Float
32
4
45
Rev 0
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LT3967
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied
to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise
noted.
PARAMETER
CONDITIONS
MIN
RTSYNC Input Clock Frequency Range
TYP
200
RTSYNC Input Low Threshold (RTVIL)
l
RTSYNC Input High Threshold (RTVIH)
l
MAX
UNITS
2000
kHz
0.4
V
1.5
V
RTSYNC Input Clock Pulse Width High (TRTH)
100
ns
RTSYNC Input Clock Pulse Width Low (TRTL)
100
ns
RTSYNC Input Clock Ramp Time Between
RTVIL and RTVIH (TRTR)
TRTH + TRTL > TRTR
2.5
µs
Watchdog Timer
Watchdog Upper Boundary (Timeout)
A 10nF Capacitor Between WDI and GND
l
15
17.5
20
ms
WDI Pin Pull-Up Current
WDI = 0.8V
l
9
10
11
µA
WDI Pin Pull-Down Current
WDI = 2.2V
200
µA
WDI Low Threshold Voltage
1
V
WDI High Threshold Voltage
2
V
Address Select and ACMREG Register Power-On Reset
ADDR[4:1] Input Low Resistance to GND,
ACMREG[M:N] = "00" at VDD Power-Up
M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3],
M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1]
l
ADDR[4:1] Input Low Resistance to GND,
ACMREG[M:N] = "11" at VDD Power-Up
M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3],
M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1]
l
ADDR[4:1] Input High Resistance to VDD,
ACMREG[M:N] = "11" at VDD Power-Up
M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3],
M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1]
l
ADDR[4:1] Input High Resistance to VDD,
ACMREG[M:N] = "00" at VDD Power-Up
M:N=7:6 for ADDR[4], M:N=5:4 for ADDR[3],
M:N=3:2 for ADDR[2], M:N=1:0 for ADDR[1]
l
5
kΩ
50
150
kΩ
50
150
kΩ
5
kΩ
Alert Status Output
ALERT Output Low Voltage
IALERT = 3mA
ALERT Output High Leakage Current
ALERT = 5.5V
0.3
0.4
V
0.1
µA
I2C Port (See Note 5 for I2C Timing Diagram)
SDA and SCL Input Threshold Rising
l
SDA and SCL Input Threshold Falling
l
SDA and SCL Input Hysteresis
l
SDA and SCL Input Current
SDA = SCL = 0V to 5.5V
SDA Output Low Voltage
ISDA = 3mA
SCL Clock Operating Frequency
0.7VDD
V
0.25VDD
0.05VDD
–250
V
V
250
nA
l
0.4
V
l
400
kHz
Rev 0
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5
LT3967
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 40V, ENH = 38.5V, VDD = 5V, SRC[8:1] = 0V, ADDR[4:1] are tied
to GND through a 100kΩ resistor respectively, SDA and SCL are pulled up to VDD by a 4.99kΩ resistor respectively, unless otherwise
noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
(Repeated) Start Condition Hold Time
(tHD_STA)
l
0.6
µs
Repeated Start Condition Set-Up Time
(tSU_STA)
l
0.6
µs
Stop Condition Setup Time (tSU_STO)
l
0.6
Data Hold Time Output (tHD_DAT(O))
l
0
Data Hold Time Input (tHD_DAT(I))
l
0
Data Set-Up Time (tSU_DAT)
l
100
ns
SCL Clock Low Period (tLOW)
l
1.3
µs
SCL Clock High Period (tHIGH)
l
0.6
µs
µs
900
ns
ns
Data Rise Time (tr)
CB = Capacitance of One BUS Line (pF) (Note 4)
20+0.1CB
300
ns
Data Fall Time (tf)
CB = Capacitance of One BUS Line (pF) (Note 4)
20+0.1CB
300
ns
Input Spike Suppression Pulse Width (tSP)
Bus Free Time (tBUF)
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3967E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3967I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The LT3967H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
degrade operating lifetimes. Operating lifetime is derated at junction
temperatures greater than 125°C.
50
ns
1.3
µs
Note 3: VOTH and VSTH register bits are set by a LT3967 I2C command.
VOTH/VSTH programmed by VOTH/VSTH register bits refer to the open/
shorted LED threshold between DRN and SRC of a channel. For a channel,
VIN > VSRC + VOTH + 1V is required for accurate open LED detection.
Note 4: Rise and fall times are measured at 30% and 70% levels.
Note 5: I2C interface timing diagram (see below).
SDA
tSU,DAT
tHD,DATO
tHD,DATI
tSU,STA
tSP
tHD,STA
tSP
tBUF
tSU,STO
SCL
tHD,STA
REPEATED START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
3967 TD
6
Rev 0
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LT3967
TYPICAL PERFORMANCE CHARACTERISTICS
1.80
3.2
VDD = 5V
1.75
3.0
SWITCHES ARE ON
1.70
2.8
1.60
1.55
2.4
SWITCHES ARE OFF
VOTH = VSTH=1, SWITCHES ARE ON
VOTH = 1, VSTH=0, SWITCHES ARE ON
VOTH = 1, VSTH=0, SWITCHES ARE OFF
VOTH = VSTH=0, SWITCHES ARE OFF
1.4
1.40
–50 –25
0
1.2
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G01
140
530
100
80
60
40
20
1000
FALLING
1.20
1.18
1.16
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G03
Switching Transition Time vs
Temperature
2.0
RTSYNC = 28kΩ
1.9
1.8
520
510
500
490
480
460
–50 –25
RISING
1.7
1.6
1.5
1.4
FALLING
1.3
1.2
470
200
400
600
800
DIMMING FREQUENCY (Hz)
1.22
TRANSITION TIME (µs)
DIMMING FREQUENCY (Hz)
540
120
RISING
1.24
PWM Dimming Frequency vs
Temperature
160
0
1.26
3967 G02
RTSYNC vs PWM Dimming
Frequency
RTSYNC (kΩ)
1.28
2.0
1.6
1.45
1.30
VDD = 5V, VIN = 40V
2.2
1.8
1.50
0
Enable Threshold ENH(VTH)
vs Temperature
2.6
1.65
VIN IQ (mA)
VDD IQ (mA)
VIN Quiescent Current vs
Temperature
ENH THRESHOLD (V)
VDD Quiescent Current vs
Temperature
1.1
0
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G04
3967 G05
1.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G06
Rev 0
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LT3967
TYPICAL PERFORMANCE CHARACTERISTICS
Standby Dimming Frequency vs
Temperature
48
160
47
150
140
130
120
110
100
90
80
70
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
WDI Pin Pull-Up/Pull-Down
Current vs Temperature
220
VDD = 5V
200
PULL-UP/DOWN CURRENT (µA)
170
STANDBY DIMMING FREQUENCY (Hz)
SWITCH ON–RESISTANCE (mΩ)
Switch On-Resistance vs
Temperature
46
45
44
43
42
180
140
120
100
41
0
40
12
11
VOTH = 1
10.6
9.9
TA = –50°C
TA = 25°C
TA = 150°C
9.2
8.5
7.8
7.1
VOTH = 0
6.4
5.7
5.0
OPEN LED THRESHOLD (V)
OPEN LED THRESHOLD (V)
11.3
3967 G10
25 50 75 100 125 150
TEMPERATURE (°C)
Open LED Threshold vs VIN, for
SRC ≥ 2V
12.0
ALERT
5A/DIV
I(DRN)
500mA/DIV
0
3967 G09
Open LED Threshold vs VIN, for
SRC = 0V
V(DRN-SRC)
5V/DIV
PULL-UP CURRENT AT WDI = 0.8V
3967 G08
Switch Open LED Protection
Response Time Scope Photo
VOTH = 1
10
9
TA = –50°C
TA = 25°C
TA = 150°C
8
7
6
VOTH = 0
5
SRC = 0
5 10 15 20 25 30 35 40 45 50 55 60
VIN (V)
3967 G11
8
60
0
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G07
5µs/DIV
80
20
40
–50 –25
PULL-DOWN CURRENT AT WDI = 2.2V
160
4
SRC ≥ 2V
5 10 15 20 25 30 35 40 45 50 55 60
VIN (V)
3967 G12
Rev 0
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LT3967
TYPICAL PERFORMANCE CHARACTERISTICS
Shorted LED Threshold vs VIN,
Temperature
12.0
5.0
VIN = 40V
4.5
SHORTED LED THRESHOLD (V)
OPEN LED THRESHOLD (V)
11.0
VOTH = 1
10.0
9.0
TA = –50°C
TA = 25°C
TA = 150°C
8.0
7.0
VOTH = 0
6.0
5.0
0.4
0.8
1.2
SRC VOLTAGE (V)
1.6
3.0
2.0
1.5
1.0
100
FADING DOWN
80
FADING UP
60
40
20
0
100
250
400
550
700
FADING TIME (ms)
35
30
25
20
850
1000
SWITCH IS OFF
15
5
5 10 15 20 25 30 35 40 45 50 55 60
VIN (V)
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
3967 G14
RTSYNC INPUT CLOCK FREQUENCY (MHz)
120
40
10
VSTH = 0
2.2
PWM DIMMING END POINTS
0% AND 100%
SWITCH IS ON
45
3967 G15
RTSYNC Input Clock Frequency vs
Fading Time for FTM[2:0] = 001
140
RTSYNC (kΩ)
TA = 150°C
TA = 25°C
TA = –50°C
2.5
RTSYNC vs Fading Time
for FTM[2:0] = 001
160
50
3.5
0
2
55
VSTH = 1
4.0
3967 G13
180
60
SRC = 0V
0.5
0
Current Out of SRC Pin vs
Temperature
CURRENT OUT OF SRC (µA)
Open LED Threshold vs SRC
PWM DIMMING END PONTS
0% AND 100%
2.0
1.8
V(DRN-SRC)
1V/DIV
1.6
1.4
Switch Slew Rate Scope Photo
FADING UP
1.2
LED CURRENT
500mA/DIV
1.0
0.8
0.6
0.4
0.2
0
100
2µs/DIV
FADING DOWN
250
400
550
700
FADING TIME (ms)
850
3967 G16
3967 G18
1000
3967 G17
Rev 0
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9
LT3967
PIN FUNCTIONS
ADDR[4:1]: Programmable Address Select and Initial
Switch State Set Pins. The device address is 010xxxx0
for all channel mode (ACMODE) write, 010xxxx1 for
all channel mode (ACMODE) read, 101xxxx0 for single
channel mode (SCMODE) write, and 101xxxx1 for single
channel mode (SCMODE) read, where xxxx represents the
input logic value from ADDR[4:1] pins. The input logic
value is 0/1 if the pin is connected to GND/VDD through
a 150kΩ resistor or less. A total of 16 LT3967 devices
can be connected to the same I2C bus. Resistor values
at ADDR[4:1] pins are also used to determine the VDD
Power on Reset (POR) default value of ACMREG. A low
value resistor (≤5k) to GND or VDD signals the LED should
be off at start-up. A high value resistor (≥50k) to GND or
VDD signals the LED should be on at start-up.
ALERT: Alert Output for Fault Condition Report. ALERT pin
is asserted (pulled low) to indicate any of the following
fault conditions: an open LED, a shorted LED, overheat
fault condition or a RTSYNC clock fault. The ALERT pin
is deasserted (released to high) after the part sends its
alert response address successfully or the fault condition
is cleared by an I2C write command. The alert function is
disabled when ENH is undervoltage.
DRN[8:1]: Floating N-Channel FET Drain Side Pins. Tie to
VDD with a 100kΩ resistor if not used.
ENH: Shutdown and Undervoltage Detect Pin for VIN.
When ENH pin is 1.22V (nominal) lower than VIN pin, PWM
dimming and fault reporting are enabled. ENH undervoltage is reported through the I2C interface. Typically this pin
is tied to a resistor divider to ensure the part is enabled
only when VIN is at least 6V higher than channel source
voltage.
10
GND: Exposed Pad Pin. Solder the exposed pad directly
to ground plane (GND).
RTSYNC: External PWM Clock Input and Internal Oscillator
Frequency Programming Pin. Set the internal oscillator
frequency using a resistor to GND if the internal oscillator
is used for PWM dimming. An external clock source able
to sink 500µA at 0.4V can be used for PWM dimming by
driving RTSYNC above and below RTVIH and RTVIL respectively to override the internal oscillator. Do not leave the
RTSYNC pin open. Place the resistor close to the IC if a
resistor is used to set the internal oscillator frequency. LED
PWM dimming frequency equals the programmed internal oscillator frequency divided by 2048 or the external
clock frequency divided by 2048. If the programmed internal oscillator frequency or the external clock frequency
becomes slower than 100kHz (nominal), the PWM clock
setting LED dimming will switch to a 100kHz (nominal)
internal standby clock. If the external clock connection is
lost, the PWM clock setting LED dimming will switch to
the RTSYNC programmed internal oscillator frequency if a
programming resistor RTSYNC is connected between the
RTSYNC pin and GND. Otherwise the PWM clock setting
LED dimming will switch to the 100kHz (nominal) internal
standby clock. This selection can be reset by VDD POR,
watchdog timeout or an I2C BCMODE write command.
SCL: Clock Input Pin for the I2C Serial Port. The I2C logic
levels are scaled with respect to VDD.
SDA: Data Input and Output Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to VDD.
Rev 0
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LT3967
PIN FUNCTIONS
SRC[8:1]: Floating N-Channel FET Source Side Pins. The
channel source voltage (SRC[8:1]) must be at least 6V
lower than VIN for proper channel switch bypass operation. Tie to GND if not used.
VIN: Input Supply Pin for LED Bypass Switches and Fault
Detectors. Must be locally bypassed with a 1µF (or larger)
capacitor placed close to this pin. For proper channel
switch bypass operation, VIN must be at least 6V higher
than the channel source voltage.
VDD: Supply Voltage for I2C Serial Port and Input Supply
Pin for Internal Bias and Logic. This pin sets the logic
reference level of I2C SCL and SDA pins. SCL and SDA
logic levels are scaled to VDD. When the VDD supply transitions above 2.5V (nominal), ACMREG and SCMREG
are reset to the default value, and the I2C interface is
active. The LT3967 will acknowledge communications to
its address and data can be written to and read back from
the registers. This is true even if the part is disabled. The
data in ACMREG and SCMREG will not change unless it
is updated by an I2C command, VDD POR or a watchdog
timeout. Connect a 0.1μF (or larger) decoupling capacitor
from this pin to ground.
WDI: Watchdog Timer Input Pin. This pin is used to set
the watchdog upper boundary using a capacitor to GND.
The watchdog starts monitoring I2C communications
when VDD transitions above 2.5V. A timeout occurs when
the time between VDD POR or START and STOP reaches
the programmed watchdog upper boundary. The timeout
resets all LT3967 registers to the default value, resets
channel switches to the default state determined by resistor settings at ADDR[4:1] pins, and resets the PWM clock
to the RTSYNC input clock. Do not leave this pin open. To
disable the watchdog function, tie this pin to GND.
Rev 0
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11
LT3967
BLOCK DIAGRAM
LED+
VIN
VIN
40V
C1
CH8
+
–
1.22V
R1
LED
SW FAULT
8
+
–
ENH
SRC8
CH7
LED
SW FAULT
LED+
BANDGAP
REFERENCE
INTERNAL
BIAS
SRC7
CH6
LED
SW FAULT
VDD
R4
DRN6
FAULT
DETECTOR
DRIVER
SDA
DRN7
FAULT
DETECTOR
DRIVER
C2
SDA
FAULT
DETECTOR
DRIVER
ENABLE
R2
VDD
5V
DRN8
LED FAULT
SRC6
CH5
R5
DRN5
SCL
SCL
ADDR1
ADDR2
ADDR3
ADDR4
I2C
SERIAL
INTERFACE
ADDR1
ADDR2
REGISTERS
AND
CONTROL
LOGIC
ADDR4
100k
+
–
100k
100k
TSD
170°C
ALERT
LED
SW FAULT
0.6V
+
–
SRC4
CH3
LED
SW FAULT
SET RTSYNC
CLOCK FAULT
SRC3
STANDBY
CLK
LED
SW FAULT
1
RTSYNC
CLOCK
RTSYNC
RTSYNC
+
–
FAULT
DETECTOR
DRIVER
PWM
CLOCK
SRC2
CH1
INTERNAL
OSCILLATOR
0.88V
DRN2
0
0
1
CH2
PWM
CLK
SELECT
DRN3
FAULT
DETECTOR
DRIVER
100kHz STANDBY CLK
AND
PWM CLOCK CONTROL
+
–
DRN4
FAULT
DETECTOR
DRIVER
SET OVERHEAT
FAULT
SET LED
FAULT
1.2V
SRC5
CH4
100k
VDD
2
FAULT
DETECTOR
DRIVER
ADDR3
R6
ALERT
LED
SW FAULT
8
LED
SW FAULT
TIMEOUT
CONTROL
DRIVER
DRN1
FAULT
DETECTOR
SRC1
GND
WDI
3967 F01
LED–
C3
Figure 1. Block Diagram
12
Rev 0
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LT3967
APPLICATIONS INFORMATION
OVERVIEW
The LT3967 is an 8-channel LED bypass switching device
with I2C serial interface, designed for dimming LED
strings using a common current source. Each of the eight
channels can be independently programmed to bypass
the LED string in constant on or off, or dimming with or
without fade transition. Operation can be best understood
by referring to the Block Diagram in Figure 1.
The LT3967 operates over the VDD input supply range
of 2.7V to 5.5V. The eight channel switches are powered
by the VIN input supply and can be connected in parallel
and/or in series. Each of the eight channel switches can
bypass one or multiple series LEDs up to 10.1V.
Each channel has an LED fault detector which can be programmed to detect an open LED fault at one of the two
threshold levels: 6.1V/5.5V and 11.4V/10.8V (default setting). When an open LED fault is detected in a channel, the
channel switch will be turned on to bypass the faulty LED
to maintain the continuity of the string and for self protection. The PWM dimming for this channel is interrupted
until reset by the serial interface. Each channel LED fault
detector can also be programmed to detect a shorted LED
fault at one of the two threshold levels: 1V (default setting)
and 4V. The 1V and 4V threshold levels may be used to
differentiate a 2-shorted LED fault from a 1-shorted LED
fault in a multi-LED segment. When a shorted LED fault
is detected in a channel, the channel switch will continue
with the programmed PWM dimming. Besides LED faults,
the LT3967 also detects and reports an overheat fault
condition (≥170°C) and a RTSYNC clock fault condition.
The LT3967 asserts (pulls down) the ALERT pin to interrupt the bus master when an LED fault and/or an overheat
fault and/or a RTSYNC clock fault is detected. The master
can use the alert response address (ARA) to determine
which device is sending the alert.
The LT3967 I2C serial interface contains nine command
registers for configuring channel switches and LED fault
detectors and programming logarithmic fade time. It also
contains two read-only fault status registers for reporting
the LED and overheat faults.
The I2C serial interface supports random addressing of any
register. The LT3967 address select pins ADDR4, ADDR3,
ADDR2 and ADDR1 allow up to 16 LT3967 devices to share
the I2C bus. Resistor values at the address select pins are
also used to determine the VDD POR default state of LEDs.
If a resistor is connected between the RTSYNC pin and the
ground, the internal oscillator is chosen and the LED dimming frequency is set by the resistor. If the RTSYNC pin
is driven by an external clock source, the external clock
source is used to override the internal oscillator and the
dimming frequency equals the external clock frequency
divided by 2048.
Details of the LT3967 operation are found in the following
sections.
POWER-ON RESET AND DIMMING CYCLE
INITIALIZATION
The channels are set in pairs with ADDR4 setting the two
MSBs and ADDR1 setting the two LSBs. See Table 1 for
an overview of the ACMREG register. When VDD transitions above 2.5V, an internal power-on reset (POR) signal
is generated to reset all LT3967 registers to the default
value. Resistor values at ADDR[4:1] pins are used to
determine the POR default state of ACMREG register bits
which set each channel switch state at start-up.
The POR also initializes each channel’s PWM dimming
counter with one-eighth dimming cycle shift, which can
avoid simultaneous channel switching at the beginning
of dimming cycle to reduce switching transients (see
Figure 2). When using PWM dimming (with or without
fade transition), the channel LED string is always turned
on at the beginning of its dimming cycle. The channel LED
string will be turned off if the value of the channel counter,
which is clocked by the PWM clock, equals the dimming
value stored in the channel SCMREG command register.
Once the channel LED string is turned off, it remains off
until its next dimming cycle starts.
OPERATION IN SHUTDOWN CONDITION
The ENH pin is used to enable the IC. When ENH pin is
undervoltage for the VIN supply, the part is in shutdown
condition, in this mode PWM dimming, ALERT pin asserting and fault reporting are disabled, and the IC does not
respond to the broadcast read command. The LT3967
sets all OLFREG and SLFREG register bits high with
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13
LT3967
APPLICATIONS INFORMATION
POR
1 DIMMING CYCLE = 2048 RTCLK CLOCK CYCLES
1/256 DIMMING (8 CLOCK CYCLES)
CH1
PHASE SHIFT OF 1/8 DIMMING CYCLE = 256 CLOCK CYCLES
CH2
CH3
CH4
CH5
CH6
CH7
CH8
3967 F02
Figure 2. POR Dimming Cycle Initialization Diagram
ALERT pin deasserted to indicate that the IC is in shutdown condition. The channel switch state is controlled
only by ACMREG register bits in shutdown condition.
When the IC is in shutdown or with VDD less than 2.5V
(nominal), the open LED detection programmed by VOTH
bit is disabled. However the voltage between the channel DRN pin and the channel SRC pin starts clamping if
it exceeds 13V (nominal). The clamping will trigger the
channel switch to turn on to bypass the faulty LED. The
switch will remain on unless it is reset by the power up
of the digital logic.
Whether the IC is enabled or is in shutdown condition, as
long as VDD is applied, the serial interface is alive and any
data written in the LT3967 command registers does not
change unless updated by another I2C command. When
ENH pin exits undervoltage to enable the IC, the LT3967
resets all OLFREG and SLFREG register bits low, and enables
PWM dimming, ALERT pin asserting and fault reporting.
Because VIN must be at least 6V higher than channel
source voltage for proper channel switch bypass operation, it is recommended to enable the IC when VIN is at
least 6V higher than VLED+. The resistor divider shown in
Figure 1 can be used to generate ENH input signal.
DIMMING WITHOUT FADE TRANSITION VS DIMMING
WITH FADE TRANSITION
Each channel of the LT3967 can be independently programmed to perform dimming without fade transition or
14
dimming with fade transition. For dimming without fade
transition, the dimming changes from the initial value to
the target value in one dimming cycle. For dimming with
fade transition, the dimming changes transitionally from
the initial value to the target value step by step in multiple dimming cycles, following a predetermined exponential curve, which can favor the approximately logarithmic response of the human eye to brightness. The
initial value is an existing 8-bit dimming value stored in
channel SCMREG register. The target value comes from a
SCMODE long format write command and will be stored in
the register to replace the initial value when the STOP condition is received. For dimming with fade transition, each
transitional step value is calculated using 11 bits according to the following formula: DVNEXT = DVPRESENT • CF,
where DV represents a transitional step dimming value,
CF is a constant factor. CF is 1.0625 for up transition and
0.9375 for down transition. The transition process begins
with the initial value served as the first DVPRESENT, and
ends with the target value when the last DVNEXT is no
less than the target value in up transition or no more than
the target value in down transition. The number of the
transitional steps depends on the distance between the
initial value and the target value. The maximum number
of transitional steps from LED constant off to constant on
is 101 (see Figure 3) and the maximum number of transitional steps from LED constant on to constant off is 96
(see Figure 4). Each step can run various PWM dimming
cycles (programmable), and each dimming cycle consists
of 2048 RTSYNC clock cycles. Then TSTEP = TPWM • M =
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LT3967
256
100%
224
87.5%
192
75.0%
160
62.5%
128
50.0%
96
37.5%
64
25.0%
32
12.5%
0
0
20
40
60
NUMBER OF STEPS
80
LT3967 I2C REGISTERS
PWM DIMMING (0% TO 100%)
DIMMING VALUE (0 TO 255)
APPLICATIONS INFORMATION
0%
100
LT3967 COMMAND REGISTERS AND CHANNEL
CONTROL
3967 F03
100%
224
87.5%
192
75.0%
160
62.5%
128
50.0%
96
37.5%
64
25.0%
32
12.5%
0
0
20
40
60
NUMBER OF STEPS
80
PWM DIMMING (100% TO 0%)
DIMMING VALUE (255 TO 0)
Figure 3. LT3967 Up Transition Dimming Curve from LED
Constant Off to Constant On
256
The LT3967 has nine command registers (see Table 1
and Table 2) and two read-only fault status registers (see
Table 3). The command registers are used to store the
configuration bits sent by a master. The fault status registers are used to store the LED/overheat fault status bits.
Both the command registers and the fault status registers
can be read by the master.
0%
100
Upon the VDD POR or an I2C bus timeout, each channel
switch state is initialized according to the ACMREG register default value, which is determined by resistor settings
at the address select pins. After data is received from a
bus master, each channel switch is controlled either by
the ACMODE register or by the channel SCMREG register,
depending on which register has been last updated (see
Figure 5). If SCMODE registers are dominant, the data in
the ACMODE register is retained until it is overwritten or
a POR/timeout occurs. Information about I2C bus timeout
can be found in the Watchdog Timeout Reset section.
I2C SERIAL INTERFACE
3967 F04
Figure 4. LT3967 Down Transition Dimming Curve from
LED Constant On to Constant Off
TRTSYNC • M • 2048, where M is the number of PWM dimming cycles running for each transitional step, which can
be programmed to 1, 2, 4, 8, 16, 24 or 31 for dimming
with fade transition. When M is programmed to 0, the
channel LED dimming functions without fade transition.
The LT3967 communicates through an I2C serial interface. The I2C serial interface is a 2-wire open-drain interface supporting multiple slaves and multiple masters on a
single bus. Each device on the I2C bus is recognized by a
unique address stored in the device and can only operate
either as a transmitter or receiver, depending on the function of the device. A master is the device which initiates a
data transfer on the bus and generates the clock signals to
permit the transfer. Devices addressed by the master are
considered slaves. The LT3967 can only be addressed as
a slave. Once addressed, it can receive configuration data
Table 1. All Channel Mode (ACMODE) Command Register (8 Bits Long. See All Channel Mode (ACMODE) Command section for how to
access this register)
NAME
ACMREG
B[7]
Control Bit
for CH8
B[6]
Control Bit
for CH7
B[5]
Control Bit
for CH6
B[4]
Control Bit
for CH5
B[3]
Control Bit
for CH4
B[2]
Control Bit
for CH3
B[1]
Control Bit
for CH2
B[0]
Control Bit
for CH1
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
1: LED On
0: LED Off
DEFAULT
AABBCCDD
(see Note at
bottom of
next page)
Rev 0
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15
LT3967
APPLICATIONS INFORMATION
Table 2. Single Channel Mode (SCMODE) Command Registers (16 Bits Long. See Single Channel Mode (SCMODE) Command section
for how to access these register bits)
B[15]
OPEN LED
THRESHOLD
PROGRAMMABLE
BITS
B[14
SHORTED LED
THRESHOLD
PROGRAMMABLE
BITS
B[13:11]
FADE TIME
MULTIPLIER
PROGRAMMABLE
BITS
VOTH =
0: 6.1V/5.5V
1: 11.4V/10.8V
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 DDDDDDDD
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
(for CH2,
the channel 1: 11.4V/10.8V
address: 001)
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 DDDDDDDD
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
1: 11.4V/10.8V
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 CCCCCCCC
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
SCMREG4
VOTH =
0: 6.1V/5.5V
(for CH4,
the channel 1: 11.4V/10.8V
address: 011)
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 CCCCCCCC
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
(for CH5,
the channel 1: 11.4V/10.8V
address: 100)
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 BBBBBBBB
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
1: 11.4V/10.8V
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 BBBBBBBB
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
1: 11.4V/10.8V
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 AAAAAAAA
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
VOTH =
0: 6.1V/5.5V
(for CH8,
the channel 1: 11.4V/10.8V
address: 111)
VSTH =
0: 1V
1: 4V
FDI =
FTM[2:0] =
000: No Fade
0: In Fading
001: 1x; 010:2x 1: Fading
011: 4x; 100:8x
Done
101: 16x; 110:24x
111: 31x
AO =
AE =
0: LED Off 0: Async.
1: LED On
Disabled
1: Async.
Enabled
DV[7:0] = 00000000: LED Off 10000100 AAAAAAAA
00000001: 1/256 Dimming
00000001: 2/256 Dimming
(see Note)
…….
11111110: 254/256 Dimming
11111111: LED Constant On
NAME
SCMREG1
(for CH1,
the channel
address: 000)
SCMREG2
SCMREG3
(for CH3,
the channel
address:
010 )
SCMREG5
SCMREG6
(for CH6,
the channel
address: 101)
SCMREG7
(for CH7,
the channel
address: 110)
SCMREG8
B[10]
FADING
DONE
INDICATOR
(READ ONLY)
B[9]
ASYNC.
ON/OFF
BIT
B[8]
ASYNC.
ENABLE
BIT
B[7:0]
DIMMING VALUE
DEFAULT
Note: Default values of A, B, C and D are determined by resistor at ADDR4, ADDR3, ADDR2 and ADDR1 pins respectively. A, B, C or D is set to 0 if the resistor to
GND/VDD is 5kΩ or less, or is set to 1 if the values resistor to GND/VDD is between 50kΩ and 150kΩ.
16
Rev 0
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LT3967
APPLICATIONS INFORMATION
Table 3. Read-Only Fault Status Register (See All Channel Mode (ACMODE) Command section for how to access these register bits)
NAME
OLFREG
B[7]
B[6]
B[4]
B[3]
B[2]
B[1]
B[0]
DEFAULT
Open LED
Open LED
Open LED
Open LED
Open LED
Open LED
Open LED
Open LED
00000000
Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
1: Fault
0: No Fault
SLFREG
B[5]
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
Shorted LED Shorted LED Shorted LED Shorted LED Shorted LED Shorted LED Shorted LED Shorted LED 00000000
Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for Status Bit for
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
1: Fault
0: No Fault
S = 0 IF POR OR IN SHUTDOWN
OR ACMREG IS WRITTEN
S = 1 IF SCMREG1 IS WRITTEN
SCMREG1 (DEFAULT: 10000100 DDDDDDDD)
TO CH2
B[15] B[14] B[13:11]
B[10]
B[9]
B[8]
B[7:0]
VOTH VSTH FTM[2:0]
FDI
AO
AE
DV[7:0]
B[3]
TO CH4
TO CH5
8
POR
TO CH3
B[4]
B[2]
B[1]
B[0]
Note: The LT3967 sets all OLFREG and SLFREG register bits high, with ALERT pin asserted ( pulled low) to indicate the overheat fault condition (≥170°C)
(See LED/Overheat Fault Detection and Reporting section for detail), with ALERT pin deasserted (pulled high) to indicate the IC is in shutdown condition
(See Operation in Shutdown Condition section for detail). If the two conditions are concurrent, the shutdown condition dominates.
PWM
CLOCK
CHANNEL
COUNTER
BOTH DWOFT AND DWFT SIGNALS
ARE SYNCHRONOUS WITH LED
PWM DIMMING CYCLE
DWOFT
11
2
CHANNEL
COMPARATOR
DIMMING
CONTROL
DWFT
7
3
B[5]
TO CH7
SRC1
CHANNEL
LED FAULT
DETECTOR
OPEN LED FAULT TO SET OLFREG B[0]
O
BS
S
A
O
B
S = 0 IF FTM[2:0] = 000
OTHERWISE S = 1
CH1
CH2
↓
CH7
•
•
•
•
•
•
S = 0 IF POR OR IN SHUTDOWN
OR ACMREG IS WRITTEN
S = 1 IF SCMREG8 IS WRITTEN
ACMREG
1: LED ON 0: LED OFF
(POR DEFAULT: AABBCCDD)
SCMREG8 (DEFAULT: 10000100 AAAAAAAA)
B[15] B[14] B[13:11]
B[10]
B[9]
B[8]
B[7:0]
VOTH VSTH FTM[2:0]
FDI
AO
AE
DV[7:0]
8
POR
PWM
CLOCK
CHANNEL
COUNTER
BOTH DWOFT AND DWFT SIGNALS
ARE SYNCHRONOUS WITH LED
PWM DIMMING CYCLE
DWOFT
11
CHANNEL
COMPARATOR
2
DIMMING
CONTROL
DWFT
7
3
DRN8
SRC8
CHANNEL
LED FAULT
DETECTOR
OPEN LED FAULT TO SET OLFREG B[7]
SHORTED LED FAULT TO SET SLFREG B[7]
TO CONTROL
CHANNEL
SWITCH
O = A IF S = 0
O = B IF S = 1
DWOFT: DIMMING WITHOUT FADE TRANSITION
DWFT: DIMMING WITH FADE TRANSITION
SHORTED LED FAULT TO SET SLFREG B[0]
B[7]
TO CH6
B[6]
DRN1
DECODER
A
S
B
O
A
DECODER
A
O
BS
S
B
O
A
S
A
O
B
TO CONTROL
CHANNEL
SWITCH
O = A IF S = 0
O = B IF S = 1
S = 0 IF FTM[2:0] = 000
OTHERWISE S = 1
DWOFT: DIMMING WITHOUT FADE TRANSITION
DWFT: DIMMING WITH FADE TRANSITION
CH8
3967 F05
Figure 5. LT3967 Command Registers and Channel Control Diagram
Rev 0
For more information www.analog.com
17
LT3967
APPLICATIONS INFORMATION
or transmit register contents. The serial clock line (SCL)
is always an input to the LT3967 and the serial data line
(SDA) is bidirectional. The LT3967 can only pull the serial
data line (SDA) LOW and can never drive it HIGH. SCL and
SDA are required to be externally connected to the VDD
supply through a pull-up resistor. When the data line is
not being driven LOW, it is HIGH. Data on the I2C bus can
be transferred at rates up to 100kbits/s in the standard
mode and up to 400kbits/s in the fast mode.
THE START AND STOP CONDITIONS
When the bus is idle, both SCL and SDA must be HIGH. A
bus master signals the beginning of a transmission with
a START condition by transitioning SDA from HIGH to
LOW while SCL is HIGH. When the master has finished
communicating with the slave, it issues a STOP condition by transitioning SDA from LOW to HIGH while SCL
is HIGH. The bus is then free for another transmission.
However, if the master still wishes to communicate on the
bus, it can generate a repeated START condition (Sr) and
address the same or another slave without first generating
a STOP condition. When the bus is in use, it stays busy
if a repeated START (Sr) is generated instead of a STOP
condition. The repeated START (Sr) conditions are functionally identical to the START (S). Various combinations
of read/write commands are then possible within such a
transfer, except that the BCMODE write command for dimming cycle synchronization and the BCMODE read command for alert inquiry and the ACMODE write command
for clearing the overheat fault bits must be self contained
with a terminating STOP condition.
I2C SERIAL PORT DATA TRANSFER
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
LT3967 slave. Data is transferred over the bus in group of
nine bits, one byte followed by one acknowledge (ACK)
bit. The acknowledge signal is used for handshaking
between the master and the slave.
A Packet Error Checking (PEC) mechanism is implemented in the LT3967 to improve I2C communication
reliability. This mechanism requires that a PEC byte (or
CRC-8 checksum), which is calculated over the entire
18
message frame including the address and read/write
bit, is always appended at the end of each ACMODE or
SCMODE command. The polynomial used for the PEC
byte calculation is x8 + x2 + x + 1 (initialized to zero). Both
the transmitter and the receiver need to calculate a PEC
byte. The transmitter sends its PEC byte derived from the
read/write address and subsequent outgoing data bytes.
The receiver calculates its own PEC byte from the read/
write address and subsequent incoming data bytes, and
compares it with the received one. A PEC-byte mismatch
guarantees that an error has occurred during the transaction. A PEC-byte match suggests a reasonable likelihood
of the command being received correctly, as long as the
same polynomial is used. Example Linduino code for calculating CRC-8 PEC is provided (see next page).
When the LT3967 is written to, it acknowledges its device
write address and subsequent data bytes. It acknowledges
the PEC byte if the PEC bytes match. Otherwise it does not
acknowledge it. The received data bytes are validated and
transferred to internal holding latches upon the return of
the acknowledgment of the PEC byte by the LT3967. The
received data bytes are regarded as void by the LT3967 in
case of mismatch. If desired, a repeated START (Sr) condition may be initiated by the master to address another
device on the I2C bus or another register in the same
device for data transfer. The LT3967 remembers the valid
data it has received. Once selected channels of the devices
on the I2C bus have been addressed and sent valid data,
the master issues a STOP condition to finish the communication. The LT3967 will update its command registers
with the data it has validated upon the STOP condition,
except that the VOTH and VSTH bits are updated in the
channel SCMREG command register upon the return of
the acknowledgment of the PEC byte by the LT3967.
When reading from the LT3967, the master initiates
the command by issuing a read address. The LT3967
acknowledges its device read address and responds with
subsequent data bytes plus a PEC byte. The master is not
required to acknowledge the data/PEC bytes.
The master can free the I2C bus by issuing a STOP condition after the data transfer. If desired the master can verify
the data bytes written to the internal holding latches prior
to updating them to the command registers by reading
them back before sending a STOP condition.
Rev 0
For more information www.analog.com
LT3967
APPLICATIONS INFORMATION
// Bytewise CRC-8 for LT3967 using X8 + X2 + X + 1
// Takes a running sum (or 0) as , and current byte to CRC as
// Returns the CRC-8 of and for sending or further CRC’ing
int8_t doCRC(int8_t in, int8_t data){
int8_t crc;
int8_t i;
crc = in ^ data;
// XOR the incoming bytes
for(i = 0; i < 8; i++){
// Step through each bit
if (crc & 0x80) {
// If MSB is set
crc
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