LTC1096/LTC1096L
LTC1098/LTC1098L
Micropower Sampling
8-Bit Serial I/O A/D Converters
FEATURES
DESCRIPTION
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The LTC ® 1096/LTC1096L/LTC1098/LTC1098L are
micropower, 8-bit A/D converters that draw only 80μA of
supply current when converting. They automatically power
down to 1nA typical supply current whenever they are not
performing conversions. They are packaged in 8-pin SO
packages and have both 3V (L) and 5V versions. These
8-bit, switched-capacitor, successive approximation ADCs
include sample-and-hold. The LTC1096/LTC1096L have a
single differential analog input. The LTC1098/LTC1098L
offer a software selectable 2-channel MUX.
n
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80μA Maximum Supply Current
1nA Typical Supply Current in Shutdown
5V Operation (LTC1096/LTC1098)
3V Operation (LTC1096L/LTC1098L)(2.65V Min)
Sample-and-Hold
16μs Conversion Time
33kHz Sample Rate
±0.5LSB Total Unadjusted Error Over Temp
Direct 3-Wire Interface to Most MPU Serial Ports and
All MPU Parallel I/O Ports
8-Pin SO Plastic Package
APPLICATIONS
n
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Battery-Operated Systems
Remote Data Acquisition
Battery Monitoring
Battery Gas Gauges
Temperature Measurement
Isolated Data Acquisition
On-chip serial ports allow efficient data transfer to a wide
range of microprocessors and microcontrollers over three
wires. This, coupled with micropower consumption, makes
remote location possible and facilitates transmitting data
through isolation barriers.
These circuits can be used in ratiometric applications or
with an external reference. The high impedance analog
inputs and the ability to operate with reduced spans (below 1V full scale) allow direct connection to sensors and
transducers in many applications, eliminating the need
for gain stages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
10μW, S8 Package, 8-Bit A/D
Samples at 200Hz and Runs Off a 5V Battery
1000
TA = 25°C
VCC = VREF = 5V
5V
MPU
(e.g., 8051)
ANALOG INPUT
0V TO 5V RANGE
CS/
VCC
SHUTDOWN
CLK
+IN
LTC1096
–IN
DOUT
GND
P1.4
P1.3
P1.2
VREF
SUPPLY CURRENT, ICC (μA)
1μF
Supply Current vs Sample Rate
100
10
10968 TA01
1
0.1
1
10
SAMPLE FREQUENCY, fSMPL (kHz)
100
10968 TA02
10968fc
1
LTC1096/LTC1096L
LTC1098/LTC1098L
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Supply Voltage (VCC) to GND ...................................12V
Voltage
Analog and Reference ................ –0.3V to VCC + 0.3V
Digital Inputs ........................................ –0.3V to 12V
Digital Outputs ........................... –0.3V to VCC + 0.3V
Power Dissipation ...............................................500mW
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATION
Operating Temperature
LTC1096AC/LTC1096C/LTC1096LC/
LTC1098AC/LTC1098C/LTC1098LC .......... 0°C to 70°C
LTC1096AI/LTC1096I/LTC1096LI/
LTC1098AI/LTC1098I/LTC1098LI ......... –40°C to 85°C
Lead Temperature (Soldering, 10 sec.) ................. 300°C
(Note 3)
LTC1096
LTC1098
TOP VIEW
CS/
1
SHUTDOWN
+IN 2
TOP VIEW
8
VCC
7
CLK
–IN 3
6
DOUT
GND 4
5
VREF
CS/
1
SHUTDOWN
CH0 2
N8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC DIP
8-LEAD PLASTIC SOIC
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 175°C/W (S8)
8
VCC(VREF)
7
CLK
CH1 3
6
DOUT
GND 4
5
DIN
N8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC DIP
8-LEAD PLASTIC SOIC
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 150°C, θJA = 175°C/W (S8)
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1096ACN8#PBF
LTC1096ACN8#TRPBF
LTC1096ACN8
8-Lead Plastic DIP
0°C to 70°C
LTC1096ACS8#PBF
LTC1096ACS8#TRPBF
1096A
8-Lead Plastic SOIC
0°C to 70°C
LTC1096AIN8#PBF
LTC1096AIN8#TRPBF
LTC1096AIN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1096AIS8#PBF
LTC1096AIS8#TRPBF
1096AI
8-Lead Plastic SOIC
–40°C to 85°C
LTC1096CN8#PBF
LTC1096CN8#TRPBF
LTC1096CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1096CS8#PBF
LTC1096CS8#TRPBF
1096
8-Lead Plastic SOIC
0°C to 70°C
LTC1096IN8#PBF
LTC1096IN8#TRPBF
LTC1096IN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1096IS8#PBF
LTC1096IS8#TRPBF
1096I
8-Lead Plastic SOIC
–40°C to 85°C
LTC1096LCS8#PBF
LTC1096LCS8#TRPBF
1096L
8-Lead Plastic SOIC
0°C to 70°C
LTC1096LIS8#PBF
LTC1096LIS8#TRPBF
1096LI
8-Lead Plastic SOIC
–40°C to 85°C
LTC1098ACN8#PBF
LTC1098ACN8#TRPBF
LTC1098ACN8
8-Lead Plastic DIP
0°C to 70°C
LTC1098ACS8#PBF
LTC1098ACS8#TRPBF
1098A
8-Lead Plastic SOIC
0°C to 70°C
LTC1098CN8#PBF
LTC1098CN8#TRPBF
LTC1098CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1098CS8#PBF
LTC1098CS8#TRPBF
1098
8-Lead Plastic SOIC
0°C to 70°C
LTC1098IN8#PBF
LTC1098IN8#TRPBF
LTC1098IN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1098IS8#PBF
LTC1098IS8#TRPBF
1098I
8-Lead Plastic SOIC
–40°C to 85°C
LTC1098LCS8#PBF
LTC1098LCS8#TRPBF
1098L
8-Lead Plastic SOIC
0°C to 70°C
LTC1098LIS8#PBF
LTC1098LIS8#TRPBF
1098LI
8-Lead Plastic SOIC
–40°C to 85°C
10968fc
2
LTC1096/LTC1096L
LTC1098/LTC1098L
ORDER INFORMATION
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1096ACN8
LTC1096ACN8#TR
LTC1096ACN8
8-Lead Plastic DIP
0°C to 70°C
LTC1096ACS8
LTC1096ACS8#TR
1096A
8-Lead Plastic SOIC
0°C to 70°C
LTC1096AIN8
LTC1096AIN8#TR
LTC1096AIN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1096AIS8
LTC1096AIS8#TR
1096AI
8-Lead Plastic SOIC
–40°C to 85°C
LTC1096CN8
LTC1096CN8#TR
LTC1096CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1096CS8
LTC1096CS8#TR
1096
8-Lead Plastic SOIC
0°C to 70°C
LTC1096IN8
LTC1096IN8#TR
LTC1096IN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1096IS8
LTC1096IS8#TR
1096I
8-Lead Plastic SOIC
–40°C to 85°C
LTC1096LCS8
LTC1096LCS8#TR
1096L
8-Lead Plastic SOIC
0°C to 70°C
LTC1096LIS8
LTC1096LIS8#TR
1096LI
8-Lead Plastic SOIC
–40°C to 85°C
LTC1098ACN8
LTC1098ACN8#TR
LTC1098ACN8
8-Lead Plastic DIP
0°C to 70°C
LTC1098ACS8
LTC1098ACS8#TR
1098A
8-Lead Plastic SOIC
0°C to 70°C
LTC1098CN8
LTC1098CN8#TR
LTC1098CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1098CS8
LTC1098CS8#TR
1098
8-Lead Plastic SOIC
0°C to 70°C
LTC1098IN8
LTC1098IN8#TR
LTC1098IN8
8-Lead Plastic DIP
–40°C to 85°C
LTC1098IS8
LTC1098IS8#TR
1098I
8-Lead Plastic SOIC
–40°C to 85°C
LTC1098LCS8
LTC1098LCS8#TR
1098L
8-Lead Plastic SOIC
0°C to 70°C
LTC1098LIS8
LTC1098LIS8#TR
1098LI
8-Lead Plastic SOIC
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
RECOMMENDED OPERATING CONDITIONS
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VCC
Supply Voltage
LTC1096
LTC1098
3.0
3.0
9
6
500
UNITS
V
V
VCC = 5V Operation
fCLK
Clock Frequency
VCC = 5V
25
tCYC
Total Cycle Time
LTC1096, fCLK = 500kHz
LTC1098, fCLK = 500kHz
29
29
kHz
μs
μs
thDI
Hold Time, DIN After CLK↑
VCC = 5V
150
ns
tsuCS
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
VCC = 5V, LTC1096
VCC = 5V, LTC1098
500
500
ns
ns
tWAKEUP
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
VCC = 5V, LTC1096
10
μs
Wake-Up Time CS↓ Before MSBF Bit CLK↓
(See Figure 2 LTC1098 Operating Sequence)
VCC = 5V, LTC1098
10
μs
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 5V
400
ns
tWHCLK
CLK High Time
VCC = 5V
0.8
μs
tWLCLK
CLK Low Time
VCC = 5V
0.8
μs
10968fc
3
LTC1096/LTC1096L
LTC1098/LTC1098L
RECOMMENDED OPERATING CONDITIONS
LTC1096/LTC1098
SYMBOL
PARAMETER
CONDITIONS
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 5V
MIN
1
TYP
MAX
UNITS
μs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 500kHz
LTC1098, fCLK = 500kHz
28
28
μs
μs
VCC = 3V Operation
fCLK
Clock Frequency
VCC = 3V
25
tCYC
Total Cycle Time
LTC1096, fCLK = 250kHz
LTC1098, fCLK = 250kHz
58
58
250
kHz
μs
μs
thDI
Hold Time, DIN After CLK↑
VCC = 3V
450
ns
tsuCS
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
VCC = 3V, LTC1096
VCC = 3V, LTC1098
1
1
μs
μs
tWAKEUP
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096 Operating Sequence)
VCC = 3V, LTC1096
10
μs
Wake-Up Time CS↓ Before MSBF Bit CLK↓
(See Figure 2 LTC1098 Operating Sequence)
VCC = 3V, LTC1098
10
μs
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 3V
1
μs
tWHCLK
CLK High Time
VCC = 3V
1.6
μs
tWLCLK
CLK Low Time
VCC = 3V
1.6
μs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 3V
2
μs
tWLCS
CS Low Time During Data Transfer
LTC1096, fCLK = 250kHz
LTC1098, fCLK = 250kHz
56
56
μs
μs
LTC1096L/LTC1098L
SYMBOL
PARAMETER
VCC
Supply Voltage
fCLK
Clock Frequency
tCYC
CONDITIONS
MIN
TYP
MAX
UNITS
2.65
4.0
V
VCC = 2.65V
25
250
kHz
Total Cycle Time
LTC1096L, fCLK = 250kHz
LTC1098L, fCLK = 250kHz
58
58
μs
μs
thDI
Hold Time, DIN After CLK↑
VCC = 2.65V
450
ns
tsuCS
Setup Time CS↓ Before First CLK↑ (See Operating Sequence)
VCC = 2.65V, LTC1096L
VCC = 2.65V, LTC1098L
1
1
μs
μs
tWAKEUP
Wake-Up Time CS↓ Before First CLK↓ After First CLK↑
(See Figure 1 LTC1096L Operating Sequence)
VCC = 2.65V, LTC1096L
10
μs
Wake-Up Time CS↓ Before MSBF Bit CLK↓
(See Figure 2 LTC1098L Operating Sequence)
VCC = 2.65V, LTC1098L
10
μs
tsuDI
Setup Time, DIN Stable Before CLK↑
VCC = 2.65V
1
μs
tWHCLK
CLK High Time
VCC = 2.65V
1.6
μs
tWLCLK
CLK Low Time
VCC = 2.65V
1.6
μs
tWHCS
CS High Time Between Data Transfer Cycles
VCC = 2.65V
2
μs
tWLCS
CS Low Time During Data Transfer
LTC1096L, fCLK = 250kHz
LTC1098L, fCLK = 250kHz
56
56
μs
μs
10968fc
4
LTC1096/LTC1096L
LTC1098/LTC1098L
CONVERTER AND MULTIPLEXER CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
LTC1096A/LTC1098A
PARAMETER
CONDITIONS
MIN
TYP
LTC1096/LTC1098
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Code)
l
Offset Error
l
±0.5
±0.5
LSB
l
±0.5
±0.5
LSB
l
±0.5
±1.0
LSB
l
±0.5
±1.0
LSB
Linearity Error
(Note 4)
Full Scale Error
8
8
Bits
Total Unadjusted Error (Note 5)
VREF = 5.000V
Analog Input Range
(Notes 6, 7)
–0.05V to VCC + 0.05V
V
REF Input Range (Notes 6, 7)
4.5 ≤ VCC ≤ 6V
6V < VCC ≤ 9V, LTC1096
–0.05V to VCC + 0.05V
–0.05V to 6V
V
V
Analog Input Leakage Current
(Note 8)
l
±1.0
±1.0
μA
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096A/LTC1098A
PARAMETER
CONDITIONS
l
Resolution (No Missing Code)
Offset Error
Linearity Error
MIN
(Notes 4, 9)
Full-Scale Error
Total Unadjusted Error (Notes 5, 9)
VREF = 2.500V
Analog Input Range
(Notes 6, 7)
REF Input Range (Notes 6, 7, 9)
3V ≤ VCC ≤ 6V
Analog Input Leakage Current
(Notes 8, 9)
TYP
LTC1096/LTC1098
MAX
MIN
8
TYP
MAX
UNITS
8
Bits
l
±0.75
±1.0
LSB
l
±0.5
±1.0
LSB
l
±1.0
±1.0
LSB
l
±1.0
±1.5
LSB
–0.05V to VCC + 0.05V
V
–0.05V to VCC + 0.05V
l
V
±1.0
±1.0
μA
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
LTC1096A/LTC1098A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Code)
l
Offset Error
l
±1.0
LSB
l
±1.0
LSB
l
±1.0
LSB
l
±1.5
LSB
Linearity Error
(Note 4)
Full-Scale Error
8
Bits
Total Unadjusted Error (Note 5)
VREF = 2.5V
Analog Input Range
(Notes 6, 7)
–0.05V to VCC + 0.05V
V
REF Input Range (Note 6)
2.65V ≤ VCC ≤ 4.0V
–0.05V to VCC + 0.05V
V
Analog Input Leakage Current
(Note 8)
l
±1.0
μA
10968fc
5
LTC1096/LTC1096L
LTC1098/LTC1098L
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VCC = 5.25V
l
VIL
Low Level Input Voltage
VCC = 4.75V
l
IIH
High Level Input Current
VIN = VCC
IIL
Low Level Input Current
VIN = 0V
VOH
High Level Output Voltage
VCC = 4.75V, IO = 10μA
VCC = 4.75V, IO = 360μA
l
l
VOL
Low Level Output Voltage
VCC = 4.75V, IO = 1.6mA
l
l
IOZ
Hi-Z Output Leakage
CS ≥ VIH
ISOURCE
Output Source Current
VOUT = 0V
ISINK
Output Sink Current
VOUT = VCC
IREF
Reference Current
ICC
Supply Current
TYP
MAX
UNITS
2.0
V
0.8
V
l
2.5
μA
l
–2.5
μA
4.5
2.4
4.74
4.72
V
V
0.4
V
±3.0
μA
–25
mA
45
mA
CS = VCC
tCYC ≥ 200μs, fCLK ≤ 50kHz
tCYC = 29μs, fCLK = 500kHz
l
l
l
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
CS = VCC
l
0.001
3.0
μA
LTC1096, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1096, tCYC = 29μs, fCLK = 500kHz
l
l
40
120
80
180
μA
μA
LTC1098, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1098, tCYC = 29μs, fCLK = 500kHz
l
l
44
155
88
230
μA
μA
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VCC = 3.6V
l
MIN
VIL
Low Level Input Voltage
VCC = 3V
l
TYP
MAX
1.9
UNITS
V
0.45
V
IIH
High Level Input Current (Note 9)
VIN = VCC
l
2.5
μA
IIL
Low Level Input Current (Note 9)
VIN = 0V
l
–2.5
μA
VOH
High Level Output Voltage
VCC = 3V, IO = 10μA
VCC = 3V, IO = 360μA
l
l
VOL
Low Level Output Voltage
VCC = 3V, IO = 400μA
l
l
2.3
2.1
2.69
2.64
V
V
0.3
V
IOZ
Hi-Z Output Leakage (Note 9)
CS ≥ VIH
ISOURCE
Output Source Current (Note 9)
VOUT = 0V
ISINK
Output Sink Current (Note 9)
VOUT = VCC
IREF
Reference Current (Note 9)
CS = VCC
tCYC ≥ 200μs, fCLK ≤ 50kHz
tCYC = 58μs, fCLK = 250kHz
l
l
l
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
ICC
Supply Current (Note 9)
CS = VCC
l
0.001
3.0
μA
LTC1096, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1096, tCYC = 58μs, fCLK = 250kHz
l
l
40
120
80
180
μA
μA
LTC1098, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1098, tCYC = 58μs, fCLK = 250kHz
l
l
44
155
88
230
μA
μA
±3.0
–10
μA
mA
15
mA
10968fc
6
LTC1096/LTC1096L
LTC1098/LTC1098L
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VCC = 3.6V
l
VIL
Low Level Input Voltage
VCC = 2.65V
l
TYP
MAX
UNITS
0.45
V
1.9
V
IIH
High Level Input Current
VIN = VCC
l
2.5
μA
IIL
Low Level Input Current
VIN = 0V
l
–2.5
μA
VOH
High Level Output Voltage
VCC = 2.65V, IO = 10μA
VCC = 2.65V, IO = 360μA
l
l
VOL
Low Level Output Voltage
VCC = 2.65V, IO = 400μA
l
l
IOZ
Hi-Z Output Leakage
CS ≥ High
ISOURCE
Output Source Current
VOUT = 0V
ISINK
Output Sink Current
VOUT = VCC
IREF
Reference Current
ICC
Supply Current
2.3
2.1
2.64
2.50
V
V
0.3
V
±3.0
μA
–10
mA
15
mA
CS = VCC
tCYC ≥ 200μs, fCLK ≤ 50kHz
tCYC = 58μs, fCLK = 250kHz
l
l
l
0.001
3.500
35.000
2.5
7.5
50.0
μA
μA
μA
CS = VCC
l
0.001
3.0
μA
LTC1096L, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1096L, tCYC = 58μs, fCLK = 250kHz
l
l
40
120
80
180
μA
μA
LTC1098L, tCYC ≥ 200μs, fCLK ≤ 50kHz
LTC1098L, tCYC = 58μs, fCLK = 250kHz
l
l
44
155
88
230
μA
μA
AC CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
tSMPL
Analog Input Sample Time
See Operating Sequence
MIN
MAX
1.5
l
fSMPL(MAX) Maximum Sampling Frequency
TYP
UNITS
CLK Cycles
33
kHz
tCONV
Conversion Time
See Operating Sequence
tdDO
Delay Time, CLK↓ to DOUT Data Valid
See Test Circuits
l
200
8
450
CLK Cycles
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
l
170
450
ns
ten
Delay Time, CLK↓ to DOUT Enable
See Test Circuits
l
60
250
ns
thDO
Time Output Data Remains Valid After CLK↓
CLOAD = 100pF
tf
DOUT Fall Time
See Test Circuits
l
180
70
250
ns
ns
tr
DOUT Rise Time
See Test Circuits
l
25
100
ns
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
10968fc
7
LTC1096/LTC1096L
LTC1098/LTC1098L
AC CHARACTERISTICS
LTC1096/LTC1098
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
tSMPL
Analog Input Sample Time
See Operating Sequence
MAX
1.5
l
fSMPL(MAX) Maximum Sampling Frequency
TYP
UNITS
CLK Cycles
16.5
kHz
Conversion Time
See Operating Sequence
tdDO
Delay Time, CLK↓ to DOUT Data Valid
See Test Circuits (Note 9)
l
500
1000
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits (Note 9)
l
220
800
ns
ten
Delay Time, CLK↓ to DOUT Enable
See Test Circuits (Note 9)
l
160
480
ns
thDO
Time Output Data Remains Valid After CLK↓
CLOAD = 100pF
tf
DOUT Fall Time
See Test Circuits (Note 9)
l
70
250
ns
tr
DOUT Rise Time
See Test Circuits (Note 9)
l
50
150
ns
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
tCONV
8
CLK Cycles
400
ns
LTC1096L/LTC1098L
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
tSMPL
Analog Input Sample Time
See Operating Sequence
tCONV
Conversion Time
MAX
1.5
l
fSMPL(MAX) Maximum Sampling Frequency
TYP
See Operating Sequence
UNITS
CLK Cycles
16.5
kHz
8
CLK Cycles
tdDO
Delay Time, CLK↓ to DOUT Data Valid
See Test Circuits
l
500
1000
ns
tdis
Delay Time, CS↑ to DOUT Hi-Z
See Test Circuits
l
220
800
ns
ten
Delay Time, CLK↓ to DOUT Enable
See Test Circuits
l
160
480
ns
thDO
Time Output Data Remains Valid After CLK↓
CLOAD = 100pF
400
ns
tf
DOUT Fall Time
See Test Circuits
l
tr
DOUT Rise Time
See Test Circuits
l
CIN
Input Capacitance
Analog Inputs On Channel
Analog Inputs Off Channel
25
5
pF
pF
Digital Input
5
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: For the 8-lead PDIP, consult the factory.
Note 4: Linearity error is specified between the actual and points of the
A/D transfer curve.
Note 5: Total unadjusted error includes offset, full scale, linearity,
multiplexer and hold step errors.
Note 6: Two on-chip diodes are tied to each reference and analog input
which will conduct for reference or analog input voltages one diode
drop below GND or one diode drop above VCC. This spec allows 50mV
forward bias of either diode. This means that as long as the reference or
70
250
ns
50
200
ns
analog input does not exceed the supply voltage by more than 50mV, the
output code will be correct. To achieve an absolute 0V to 5V input voltage
range will therefore require a minimum supply voltage of 4.950V over
initial tolerance, temperature variations and loading. For 5.5V < VCC ≤ 9V,
reference and analog input range cannot exceed 5.55V. If reference and
analog input range are greater than 5.55V, the output code will not be
guaranteed to be correct.
Note 7: The supply voltage range for the LTC1096L/LTC1098L is from
2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,
but the supply voltage range for the LTC1098 is only from 3V to 6V.
Note 8: Channel leakage current is measured after the channel selection.
Note 9: These specifications are either correlated from 5V specifications or
guaranteed by design.
10968fc
8
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Clock Rate
for Active and Shutdown Modes
VCC = 9V
SUPPLY CURRENT, ICC (μA)
150
VCC = 5V
100
50
10
0.002
0
CS = VCC
80
60
“ACTIVE” MODE CS = 0
40
20
0
1
7
3
2
5
6
4
SUPPLY VOLTAGE,VCC (V)
Change in Offset vs
Reference Voltage LTC1096
0.25
0
1
0
0.50
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE, VCC (V)
10968 G04
Change in Linearity vs
Supply Voltage
0.25
0
–0.25
9
10
–O.50
0
–0.1
–0.2
0.2
0.1
0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
0
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE, VCC (V)
9
10
10968 G07
CHANGE IN GAIN (LSB)
0.1
–0.5
5
0.50
0.3
CHANGE IN GAIN (LSB)
0.3
3
4
2
REFERENCE VOLTAGE (V)
Change in Gain vs
Reference Voltage LTC1096
TA = 25°C
VREF = 2.5V
FCLK = 100kHz
0.4
0.2
1
10968 G06
0.5
0.4
0
10968 G05
Change in Gain vs Supply Voltage
TA = 25°C
VREF = 2.5V
FCLK = 100kHz
TA = 25°C
VCC = 5V
FCLK = 500kHz
–0.4
5
0.5
100
Change in Linearity vs
Reference Voltage LTC1096
TA = 25°C
VREF = 2.5V
FCLK = 100kHz
0.4
–0.5
3
4
2
REFERENCE VOLTAGE (V)
1
10
SAMPLE FREQUENCY, fSMPL (kHz)
10968 G03
0.5
TA = 25°C
VCC = 5V
FCLK = 500kHz
–0.25
CHANGE IN LINEARTY (LSB)
0.1
9
Change in Offset vs
Supply Voltage
0.50
–0.5
8
10968 G02
MAGNITUDE OF OFFSET CHANGE (LSB)
MAGNITUDE OF OFFSET CHANGE (LSB = 1/256 s VREF)
10968 G01
–0.50
10
1
0
1000
100
“SHUTDOWN” MODE CS = VCC
0.001
10
100
FREQUENCY (kHz)
1
TA = 25°C
VCC = VREF = 5V
TA = 25°C
VREF = 2.5V
CHANGE IN LINEARITY (LSB)
SUPPLY CURRENT, ICC (μA)
200
1000
100
TA = 25°C
CS = 0V
Supply Current vs Sample
Frequency LTC1096
SUPPLY CURRENT, ICC (μA)
250
Supply Current vs Supply Voltage
Active and Shutdown Modes
TA = 25°C
VCC = 5V
FCLK = 500kHz
0.25
0
–0.25
0
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE, VCC (V)
9
10
10968 G08
–O.50
0
1
3
4
2
VOLTAGE REFERENCE (V)
5
10968 G09
10968fc
9
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Clock Frequency vs
Source Resistance
Maximum Clock Frequency vs
Supply Voltage
1.5
VIN
+ INPUT
– INPUT
0.75
RSOURCE–
0.50
0.25
0
1.25
10
RSOURCE– (kΩ)
0.75
0.5
0
2
Minimum Wake-Up Time
vs Source Resistance
1
7.5
5.0
RSOURCE+
VIN
2.5
100
+
10
ON CHANNEL
1
10
1
0.01
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
100
RSOURCE (kΩ)
10968 G14
10968 G13
Minimum Clock Frequency for
0.1LSB Error† vs Temperature
10968 G15
ENOBs vs Frequency
FFT Plot
0
9
–10
160
8
–20
140
7
120
6
ENOBs
VREF = 5V
VCC = 5V
100
80
AMPLITUDE (dB)
10
200
180
5
4
60
3
40
2
20
TA = 25°C
VCC = VREF = 5V
fSMPL = 31.25kHz
1
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
OFF CHANNEL
0.1
–
10
10968 G12
VREF = 5V
VCC = 5V
0
6
8
4
SUPPLY VOLTAGE, VCC (V)
10
1000
LEAKAGE CURRENT (nA)
MINIMUM WAKE-UP TIME (μs)
2
6
8
4
SUPPLY VOLTAGE, VCC (V)
Input Channel Leakage Current
vs Temperature
TA = 25°C
VREF = 5V
3
2
0
10968 G11
10
2
2
0
10
4
6
8
SUPPLY VOLTAGE (V)
10968 G10
TA = 25°C
VREF = 2.5V
0
3
1
0.25
100
4
WAKE-UP TIME (μs)
4
1.0
Wake-Up Time vs Supply Voltage
MINIMUM CLOCK FREQUENCY (kHz)
TA = 25°C
0
1
0
5
TA = 25°C
VREF = 2.5V
LOGIC THRESH0LD (V)
TA = 25°C
VCC = VREF = 5V
MAXIMUM CLOCK FREQUENCY (MHz)
MAXIMUM CLOCK FREQUENCY* (MHz)
1
Digital Input Logic Threshold
vs Supply Voltage
10
FREQUENCY (kHz)
10968 G16
* Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error at any code
transition from its 0.75MHz value is first detected.
† As the CLK frequency is decreased from 500kHz, minimum CLK frequency (Δerror ≤ 0.1LSB) represents
the frequency at which a 0.1LSB shift in any code transition from its 500kHz value is first detected.
–30
–40
–50
–60
–70
–80
–90
0
1
TA = 25°C
VCC = VREF = 5V
fSMPL = 31.25kHz
fIN = 5.8kHz
100
10968 G17
–100
0
2
4
10 12
6
8
FREQUENCY (kHz)
14
16
10968 G18
10968fc
10
LTC1096/LTC1096L
LTC1098/LTC1098L
PIN FUNCTIONS
LTC1096/LTC1096L
LTC1098/LTC1098L
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1096/LTC1096L. A logic high on this
input disables the LTC1096/LTC1096L and disconnects the
power to the LTC1096/LTC1096L.
CS/SHDN (Pin 1): Chip Select Input. A logic low on this
input enables the LTC1098/LTC1098L. A logic high on this
input disables the LTC1098/LTC1098L and disconnects the
power to the LTC1098/LTC1098L.
IN+ (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
CH0 (Pin 2): Analog Input. This input must be free of noise
with respect to GND.
IN– (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
CH1 (Pin 3): Analog Input. This input must be free of noise
with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
VREF (Pin 5): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
DIN (Pin 5): Digital Data Input. The multiplexer address
is shifted into this pin.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer.
VCC (Pin 8): Power Supply Voltage. This pin provides power
to the A/D converter. It must be free of noise and ripple by
bypassing directly to the analog ground plane.
DOUT (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer.
VCC (VREF)(Pin 8): Power Supply Voltage. This pin provides
power and defines the span of the A/D converter. It must
be free of noise and ripple by bypassing directly to the
analog ground plane.
10968fc
11
LTC1096/LTC1096L
LTC1098/LTC1098L
BLOCK DIAGRAM
LTC1096/LTC1096L
CS (DIN) CLK
VCC (VCC/VREF)
BIAS AND
SHUTDOWN CIRCUIT
IN+ (CH0)
CSAMPLE
IN– (CH1)
SERIAL PORT
DOUT
–
SAR
+
MICROPOWER
COMPARATOR
CAPACITIVE DAC
10968 BD
GND
VREF
PIN NAMES IN PARENTHESES
REFER TO THE LTC1098/LTC1098L
TEST CIRCUITS
On and Off Channel Leakage Current
Load Circuit for tdDO, tr and tf
5V
ION
1.4V
A
ON CHANNEL
IOFF
3kΩ
A
DOUT
•
•
•
•
POLARITY
OFF
CHANNEL
TEST POINT
100pF
10968 TC02
10968 TC01
10968fc
12
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
Voltage Waveforms for DOUT Delay Time, tdDO
CLK
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
VIL
VOH
DOUT
tdDO
VOL
VOH
DOUT
tr
VOL
tf
10968 TC04
10968 TC03
Load Circuit for tdis and ten
Voltage Waveforms for tdis
CS
2.0V
TEST POINT
3k
5V tdis WAVEFORM 2, ten
DOUT
100pF
tdis WAVEFORM 1
10968 TC05
DOUT
WAVEFORM 1
(SEE NOTE 1)
90%
tdis
DOUT
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
10968 TC06
10968fc
13
LTC1096/LTC1096L
LTC1098/LTC1098L
TEST CIRCUITS
Voltage Waveforms for ten
LTC1096/LTC1096L
CS
tWAKEUP
1
CLK
B7
DOUT
VOL
ten
10968 TC07
LTC1098/LTC1098L
CS
START
DIN
CLK
1
2
3
4
5
B7
DOUT
VOL
ten
10968 TC08
10968fc
14
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
OVERVIEW
The LTC1096/LTC1096L/LTC1098/LTC1098L are 8-bit
micropower, switched-capacitor A/D converters. These
sampling ADCs typically draw 120μA of supply current
when sampling up to 33kHz. Supply current drops linearly
as the sample rate is reduced (see Supply Current vs
Sample Rate on the first page of this data sheet). The ADCs
automatically power down when not performing conversion, drawing only leakage current. They are packaged in
8-pin SO packages. The LTC1096L/LTC1098L operate on
a single supply ranging from 2.65V to 4V. The LTC1096
operates on a single supply ranging from 3V to 9V while
the LTC1098 operates from 3V to 6V supplies.
The LTC1096/LTC1096L/LTC1098/LTC1098L comprise an
8-bit, switched-capacitor ADC, a sample-and-hold and a
serial port (see Block Diagram). Although they share the
same basic design, the LTC1096(L) and LTC1098(L) differ
in some respects. The LTC1096(L) has a differential input
and has an external reference input pin. It can measure
signals floating on a DC common mode voltage and can
operate with reduced spans down to 250mV. Reducing the
span allows it to achieve 1mV resolution. The LTC1098(L)
has a 2-channel input multiplexer and can convert either
channel with respect to ground or the difference between
the two.
wake-up time must be provided from CS falling to the
first falling clock (CLK) after the first rising CLK for the
LTC1096(L) and from CS falling to the MSBF bit CLK falling for the LTC1098(L) (see Operating Sequence). If the
LTC1096(L)/LTC1098(L) are running with clock frequency
less than or equal to 100kHz, the wake-up time is inherently provided.
Example
Two cases are shown at right to illustrate the relationship
among wake-up time, setup time and CLK frequency for
the LT1096(L).
In Case 1 the clock frequency is 100kHz. One clock cycle
is 10μs which can be the wake-up time, while half of that
can be the setup time. In Case 2 the clock frequency is
50kHz, half of the clock cycle plus the setup time (=1μs)
can be the wake-up time. If the CLK frequency is higher
than 100kHz, Figure 1 shows the relationship between the
wake-up time and setup time.
tWAKEUP
CS
tsu
CLK
DOUT
NULL BIT
SERIAL INTERFACE
The LTC1098(L) communicates with microprocessors and
other external circuitry via a synchronous, half duplex,
4-wire serial interface while the LTC1096(L) uses a 3-wire
interface (see Operating Sequence in Figures 1 and 2).
Power Down and Wake-Up Time
The LTC1096(L)/LTC1098(L) draw power when the CS
pin is low and shut themselves down when that pin is
high. In order to have a correct conversion result, a 10μs
B7
Case 1. Timing Diagram
CS
tWAKEUP
tsu
CLK
10μs
DOUT
10968 AI Ex
Case 2. Timing Diagram
10968fc
15
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
tCYC
CS
POWER
DOWN
CLK
tsuCS
tWAKEUP
DOUT
HI-Z
NULL
BIT
B7
B6
(MSB)
B5
B4
B3
B2
Hi-Z
B0
B1
tCONV
tCYC
CS
POWER
DOWN
CLK
tsuCS
tWAKEUP
DOUT
Hi-Z
NULL
BIT
B7
(MSB)
B6
B5
B4
B3
B2
B0
B1
B1
B2
B3
B4
B5
B6
B7*
tCONV
Hi-Z
10968 F01
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 1. LTC1096(L) Operating Sequence
The wake-up time is inherently provided for the LTC1098(L)
with setup time = 1μs (see Figure 2).
CS
DIN 1
DOUT 1
Data Transfer
The CLK synchronizes the data transfer with each bit being
transmitted on the falling CLK edge and captured on the
rising CLK edge in both transmitting and receiving systems. The LTC1098(L) first receives input data and then
transmits back the A/D conversion result (half duplex).
Because of the half duplex operation, DIN and DOUT may
be tied together allowing transmission over just three
wires: CS, CLK and DATA (DIN/DOUT).
Data transfer is initiated by a falling chip select (CS) signal.
After CS falls the LTC1098(L) looks for a start bit. After the
start bit is received, the 3-bit input word is shifted into the
DIN input which configures the LTC1098(L) and starts the
conversion. After one null bit, the result of the conversion
DIN 2
DOUT 2
SHIFT MUX
ADDRESS IN
1 NULL BIT
SHIFT A/D CONVERSION
RESULT OUT
10968 AI01
is output on the DOUT line. At the end of the data exchange
CS should be brought high. This resets the LTC1098(L) in
preparation for the next data exchange.
The LTC1096(L) does not require a configuration input
word and has no DIN pin. A falling CS initiates data transferas shown in the LTC1096(L) operating sequence. After
CS falls, the first CLK pulse enables DOUT. After one null
bit, the A/D conversion result is output on the DOUT line.
Bringing CS high resets the LTC1096(L) for the next data
exchange.
10968fc
16
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
MSB-FIRST DATA (MSBF = 1)
tCYC
CS
POWER
DOWN
tWAKEUP
CLK
tsuCS
ODD/
SIGN
START
DIN
DON'T CARE
MSBF
SGL/
DIFF
DOUT
NULL
BIT B7
B6
(MSB)
HI-Z
tSMPL
B5
B4
B3
B2
B1
Hi-Z
B0*
tCONV
MSB-FIRST DATA (MSBF = 0)
tCYC
CS
POWER
DOWN
tWAKEUP
CLK
tsuCS
ODD/
SIGN
START
DIN
DON'T CARE
SGL/
DIFF
DOUT
HI-Z
tSMPL
MSBF
NULL
B6
BIT B7
(MSB)
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7*
tCONV
Hi-Z
10968 F02
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.
Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH+, CH–)
Input Data Word
Start Bit
The LTC1096(L) requires no DIN word. It is permanently
configured to have a single differential input. The conversion result, in which output on the DOUT line is MSB-first
sequence, followed by LSB sequence providing easy
interface to MSB- or LSB-first serial ports.
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1098(L) will ignore all leading zeros which
precede this logical one. After the start bit is received,
the remaining bits of the input word will be clocked in.
Further inputs on the DIN pin are then ignored until the
next CS cycle.
The LTC1098(L) clocks data into the DIN input on the rising edge of the clock. The input data words are defined
as follows:
START
SGL/
DIFF
ODD/
MSBF
SIGN
MUX MSB-FIRST/
ADDRESS LSB-FIRST
10968 AI02
10968fc
17
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Multiplexer (MUX) Address
Unipolar Transfer Curve
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the followintg tables.
In single-ended mode, all input channels are measured
with respect to GND.
The LTC1096(L)/LTC1098(L) are permanently configured
for unipolar only. The input span and code assignment for
this conversion type are shown in the following figures
for a 5V reference.
11111111
LTC1098(L) Channel Selection
SINGLE-ENDED MUX MODE
GND
–
–
•
•
•
00000001
00000000
VIN
VREF
MSB-First/LSB-First (MSBF)
The output data of the LTC1098(L) is programmed for
MSB-first or LSB-first sequence using the MSBF bit.
When the MSBF bit is a logical one, data will appear on
the DOUT line in MSB-first format. Logical zeros will be
filled in indefinitely following the last data bit. When the
MSBF bit is a logical zero, LSB-first data will follow the
normal MSB-first data on the DOUT line. (see Operating
Sequence)
VREF–1LSB
VREF–2LSB
10968 AI03
1LSB
CHANNEL #
1
0
+
+
–
+
+
–
11111110
0V
DIFFERENTIAL MUX MODE
MUX ADDRESS
SGL/DIFF ODD/SIGN
1
0
1
1
0
0
0
1
Unipolar Transfer Curve
10968 AI04
Unipolar Output Code
OUTPUT CODE
INPUT VOLTAGE
INPUT VOLTAGE
(VREF = 5.000V)
11111111
11111110
•
•
•
00000001
00000000
VREF – 1LSB
VREF – 2LSB
•
•
•
1LSB
0V
4.9805V
4.9609V
•
•
•
0.0195V
0V
10968 AI05
Operation with DIN and DOUT Tied Together
The LTC1098(L) can be operated with DIN and DOUT tied
together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin
connected to this data line should be configurable as either
an input or an output. The LTC1098(L) will take control of
10968fc
18
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
MSBF BIT LATCHED
BY LTC1098(L)
CS
1
2
3
4
START
SGL/DIFF
ODD/SIGN
MSBF
CLK
DATA (DIN/DOUT)
B7
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1098(L)
• • •
B6
LTC1098(L) CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1098(L) TAKES CONTROL OF
DATA LINE ON 4TH FALLING CLK
10968 F03
Figure 3. LTC1098(L) Operation with DIN and DOUT Tied Together
In the Typical Applications section, there is an example of
interfacing the LTC1098(L) with DIN and DOUT tied together
to the Intel 8051 MPU.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 40μA and automatic
shutdown between conversions, the LTC1096/LTC1098
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). In systems that
convert continuously, the LTC1096/LTC1098 will draw
its normal operating power continuously. Figure 5 shows
that the typical current varies from 40μA at clock rates
below 50kHz to 100μA at 500kHz. Several things must
be taken into account to achieve such a low power
consumption.
SUPPLY CURRENT vs CLOCK RATE FOR
ACTIVE AND SHUTDOWN MODES
140
120
SUPPLY CURRENT, ICC (μA)
the data line and drive it low on the 4th falling CLK edge
after the start bit is received (see Figure 3). Therefore the
processor port line must be switched to an input before
this happens, to avoid a conflict.
TA = 25°C
VCC = 5V
100
80
60
40
20
0.002
1000
0
100
SUPPLY CURRENT, ICC (μA)
TA = 25°C
VCC = 5V
ACTIVE (CS LOW)
SHUTDOWN (CS HIGH)
10k
100k
1k
CLOCK FREQUENCY (Hz)
1M
10968 F05
Figure 5. After a Conversion, When the Microprocessor
Drives CS High, the ADC Automatically Shuts Down Until the
Next Conversion. The Supply Current, Which Is Very Low
During cConversions, Drops to Zero in Shutdown
100
10
Shutdown
1
0.1
1
10
Sample Rate, fSAMPLE (kHz)
100
10968 F04
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
Figures 1 and 2 show the operating sequence of the
LTC1096/LTC1098. The converter draws power when the
CS pin is low and powers itself down when that pin is high.
If the CS pin is not taken to ground when it is low and not
taken to supply voltage when it is high, the input buffers
10968fc
19
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
of the converter will draw current. This current may be
larger than the typical supply current. It is worthwhile to
bring the CS pin all the way to ground when it is low and
all the way to supply voltage when it is high to obtain the
lowest supply current.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the DIN and CLK input have no effect on supply
current during this time. There is no need to stop DIN and
CLK with CS = high, except the MPU may benefit.
Minimize CS Low Time
In systems that have significant time between conversions,
lowest power drain will occur with the minimum CS low
time. Bringing CS low, waiting 10μs for the wake-up time,
transferring data as quickly as possible, and then bringing
it back high will result in the lowest current drain. This
minimizes the amount of time the device draws power.
Even though the device draws more power at high clock
rates, the net power is less because the device is on for
a shorter time.
Wake-Up Time
A 10μs wake-up time must be provided for the ADCs
to convert correctly on a 5V supply. The wake-up time
is typically less than 3μs over the supply voltage range
(see typical curve of Wake-Up Time vs Supply Voltage).
With 10μs wake-up time provided over the supply range,
the ADCs will have adequate time to wake up and acquire
input signals.
Input Logic Levels
The input logic levels of CS, CLK and DIN are made to meet
TTL on 5V supply. When the supply voltage varies, the
input logic levels also change. For the LTC1096/LTC1098
to sample and convert correctly, the digital inputs have
to meet logic low and high levels relative to the operating
supply voltage (see typical curve of Digital Input Logic
Threshold vs Supply Voltage). If achieving micropower
consumption is desirable, the digital inputs must go railto-rail between supply voltage and ground (see ACHIEVING
MICROPOWER PERFORMANCE section).
Clock Frequency
DOUT Loading
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the DOUT pin
can more than double the 100μA supply current drain at a
500kHz clock frequency. An extra 100μA or so of current
goes into charging and discharging the load capacitor. The
same goes for digital lines driven at a high frequency by
any logic. The CxVxf currents must be evaluated and the
troublesome ones minimized.
Lower Supply Voltage
For lower supply voltages, LTC offers the LTC1096L/
LTC1098L. These pin compatible devices offer specified
performance to 2.65VMIN supply.
OPERATING ON OTHER THAN 5V SUPPLIES
The LTC1096 operates from 3V to 9V supplies and the
LTC1098 operates from 3V to 6V supplies. To operate the
LTC1096/LTC1098 on other than 5V supplies, a few things
must be kept in mind.
The maximum recommended clock frequency is 500kHz
for the LTC1096/LTC1098 running off a 5V supply. With the
supply voltage changing, the maximum clock frequency
for the devices also changes (see the typical curve of
Maximum Clock Rate vs Supply Voltage). If the maximum
clock frequency is used, care must be taken to ensure that
the device converts correctly.
Mixed Supplies
It is possible to have a microprocessor running off a 5V
supply and communicate with the LTC1096/LTC1098 operating on 3V or 9V supplies. The requirement to achieve
this is that the outputs of CS, CLK and DIN from the MPU
have to be able to trip the equivalent inputs of the ADCs
and the output of DOUT from the ADCs must be able to
toggle the equivalent input of the MPU (see typical curve
of Digital Input Logic Threshold vs Supply Voltage). With
the LTC1096 operating on a 9V supply, the output of DOUT
may go between 0V and 9V. The 9V output may damage
the MPU running off a 5V supply. The way to get around
this possibility is to have a resistor divider on DOUT
10968fc
20
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
(Figure 6) and connect the center point to the MPU input.
It should be noted that to get full shutdown, the CS input
of the LTC1096/LTC1098 must be driven to the VCC voltage. This would require adding a level shift circuit to the
CS signal in Figure 6.
9V
OPTIONAL
LEVEL SHIFT
9V 4.7μF
SAMPLE-AND-HOLD
MPU
(e.g. 8051)
DIFFERENTIAL INPUTS
COMMON MODE RANGE
0V TO 6V
CS
VCC
+IN
CLK
–IN
DOUT
GND
VREF
5V
P1.4
P1.3
50k
P1.2
6V
The VCC pin should be bypassed to the ground plane with
a 1μF tantalum with leads as short as possible. If power
supply is clean, the LTC1096(L)/LTC1098(L) can also operate with smaller 0.1μF surface mount or ceramic bypass
capacitors. All analog inputs should be referenced directly
to the single point ground. Digital inputs and outputs should
be shielded from and/or routed away from the reference
and analog circuitry.
50k
LTC1096
10968 F06
Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System
Both the LTC1096(L) and the LTC1098(L) provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1096(L) acquires input signals from “+”
input relative to “–” input during the tWAKEUP time (see
Figure 1). However, the S&H of the LTC1098(L) can sample
input signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).
Single-Ended Inputs
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1096(L)/LTC1098(L) should be used with an analog
ground plane and single point grounding techniques. The
GND pin should be tied directly to the ground plane.
The sample-and-hold of the LTC1098(L) allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
CS
tSMPL
tCONV
CLK
DIN
START
SGL/DIFF
MSBF
DOUT
DON'T CARE
B7
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
"+" INPUT
"–" INPUT
10968 F07
Figure 7. LTC1098(L) “+” and “–” Input Settling Windows
10968fc
21
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
Differential Inputs
With differential inputs, the ADC no longer converts just a
single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input
is still sampled and held and therefore may be rapidly
time varying just as in single-ended mode. However, the
voltage on the selected “–” input must remain constant
and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not
be performed accurately. The conversion time is 8 CLK
cycles. Therefore, a change in the “–” input voltage during
this interval can cause conversion errors. For a sinusoidal
voltage on the “–” input this error would be:
VERROR (MAX) = VPEAK • 2 • π • f(“–”) • 8/fCLK
Where f(“–”) is the frequency of the “–” input voltage,
VPEAK is its peak amplitude and fCLK is the frequency of
the CLK. In most cases VERROR will not be significant. For
a 60Hz signal on the “–” input to generate a 1/4LSB error
(5mV) with the converter running at CLK = 500kHz, its
peak value would have to be 750mV.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1096(L)/
LTC1098(L )have capacitive switching input current spikes.
These current spikes settle quickly and do not cause a
problem. However, if large source resistances are used
or if slow settling op amps drive the inputs, care must be
taken to ensure that the transients caused by the current
spikes settle completely before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1096(L) is switched onto
“+” input during the wake-up time (see Figure 1) and
samples the input signal within that time. However, the
input capacitor of the LTC1098(L) is switched onto “+”
input during the sample phase (tSMPL, see Figure 7). The
sample phase is 1.5 CLK cycles before conversion starts.
The voltage on the “+” input must settle completely within
t WAKEUP or tSMPL for the LTC1096(L) or the LTC1098(L)
respectively. Minimizing RSOURCE+ and C1 will improve the
input settling time. If a large “+” input source resistance
must be used, the sample time can be increased by using
a slower CLK frequency.
“–” Input Settling
At the end of the tWAKEUP or tSMPL, the input capacitor
switches to the “–” input and conversion starts (see
Figures 1 and 7). During the conversion the “+” input
voltage is effectively “held” by the sample-and-hold and
will not affect the conversion result. However, it is critical that the “–” input voltage settles completely during
the first CLK cycle of the conversion time and be free of
noise. Minimizing RSOURCE– and C2 will improve settling
time. If a large “–” input source resistance must be used,
the time allowed for settling can be extended by using a
slower CLK frequency.
Input Op Amps
When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see
Figure 7). Again, the “+” and “–” input sampling times can
be extended as described above to accommodate slower
op amps. Most op amps, including the LT1006 and LT1413
single supply op amps, can be made to settle well even
with the minimum settling windows of 3μs (“+” input)
which occur at the maximum clock rate of 500kHz.
Source Resistance
The analog inputs of the LTC1096/LTC1098 look like a 25pF
capacitor (CIN) in series with a 500Ω resistor (RON) as
shown in Figure 8. CIN gets switched between the selected
“+” and “–” inputs once during each conversion cycle.
RSOURCE +
“+”
INPUT
LTC1096
LTC1098
VIN +
C1
RSOURCE –
“–”
INPUT
RON = 500Ω
CIN = 25pF
VIN –
C2
10968 F08
Figure 8. Analog Input Equivalent Circuit
10968fc
22
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Large external source resistors and capacitances will slow
the settling of the inputs. It is important that the overall
RC time constants be short enough to allow the analog
inputs to completely settle within the allowed time.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 9. For large values of CF (e.g., 1μF), the
capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with
a small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 25pF(VIN /tCYC) and is roughly proportional to VIN. When running at the minimum cycle time
of 29μs, the input current equals 4.3μA at VIN = 5V. In this
case, a filter resistor of 390Ω will cause 0.1LSB of fullscale error. If a larger filter resistor must be used, errors
can be eliminated by increasing the cycle time.
RFILTER
IDC
“+”
VIN
CFILTER
LTC1098
capacitive current spike will be generated on the reference
pin by the ADC. These current spikes settle quickly and do
not cause a problem.
Using a slower CLK will allow more time for the reference
to settle. Even at the maximum CLK rate of 500kHz most
references and op amps can be made to settle within the
REF+
5
ROUT
VREF
LTC1096
EVERY CLK CYCLE
RON
GND
4
5pF TO 30pF
10968 F10
Figure 10. Reference Input Equivalent Circuit
2μs bit time.
Reduced Reference Operation
The minimum reference voltage of the LTC1098 is limited
to 3V because the VCC supply and reference are internally
tied together. However, the LTC1096 can operate with
reference voltages below 1V.
“–”
10968 F09
Figure 9. RC Input Filtering
Input Leakage Current
The effective resolution of the LTC1096 can be increased
by reducing the input span of the converter. The LTC1096
exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Linearity and Full
Scale Error vs Reference Voltage). However, care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. The following factors
must be considered when operating at low VREF values.
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1μA (at 125°C) flowing through a
source resistance of 3.9k will cause a voltage drop of 3.9mV
or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve
of Input Channel Leakage Current vs Temperature).
1. Offset
2. Noise
3. Conversion speed (CLK frequency)
REFERENCE INPUTS
Offset with Reduced VREF
The voltage on the reference input of the LTC1096 defines
the voltage span of the A/D converter. The reference
input transient capacitive switching currents due to the
switched-capacitor conversion technique (see Figure 10).
During each bit test of the conversion (every CLK cycle), a
The offset of the LTC1096 has a larger effect on the output
code when the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the
LSB is reduced. The typical curve of Unadjusted Offset
Error vs Reference Voltage shows how offset in LSBs is
10968fc
23
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Noise with Reduced VREF
The total input referred noise of the LTC1096 can be reduced
to approximately 1mV peak-to-peak using a ground plane,
good bypassing, good layout techniques and minimizing
noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of
an LSB as the size of the LSB is reduced.
For operation with a 5V reference, the 1mV noise is only
0.05LSB peak-to-peak. In this case, the LTC1096 noise
will contribute virtually no uncertainty to the output code.
However, for reduced references, the noise may become
a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1V reference,
this same 1mV noise is 0.25LSB peak-to-peak. This will
reduce the range of input voltages over which a stable
output code can be achieved by 1LSB. If the reference is
further reduced to 200mV, the 1mV noise becomes equal
to 1.25LSBs and a stable code may be difficult to achieve.
In this case averaging readings may be necessary.
This noise data was taken in a very clean setup. Any setupinduced noise (noise or ripple on VCC, VREF or VIN) will
add to the internal noise. The lower the reference voltage
to be used, the more critical it becomes to have a clean,
noise free setup.
Conversion Speed with Reduced VREF
With reduced reference voltages the LSB step size is
reduced and the LTC1096 internal comparator overdrive
is reduced. Therefore, it may be necessary to reduce
the maximum CLK frequency when low values of VREF
are used.
Input Divider
It is OK to use an input divider on the reference input of
the LTC1096 as long as the reference input can be made
to settle within the bit time at which the clock is running.
When using a larger value resistor divider on the reference
input the “–” input should be matched with an equivalent
resistance.
Bypassing Reference Input with Divider
Bypassing the reference input with a divider is also possible. However, care must be taken to make sure that the
DC voltage on the reference input will not drop too much
below the intended reference voltage.
AC PERFORMANCE
Two commonly used figures of merit for specifying the
dynamic performance of the ADCs in digital signal processing applications are the signal-to-noise ratio (SNR)
and the effective number of bits (ENOBs).
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency to
the RMS amplitude of all other frequency components at
the A/D output. This includes distortion as well as noise
products and for this reason it is sometimes referred to as
signal-to-noise + distortion [S/(N + D)]. The output is band
limited to frequencies from DC to one half the sampling
frequency. Figure 11 shows spectral content from DC to
15.625kHz which is 1/2 the 31.25kHz sampling rate.
0
–10
fSAMPLE = 31.25kHz
fIN = 11.8kHz
–20
AMPLITUDE (dB)
related to reference voltage for a typical value of VOS. For
example, a VOS of 2mV which is 0.1LSB with a 5V reference
becomes 0.5LSB with a 1V reference and 2.5LSBs with
a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the “–” input of the LTC1096.
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
2
4
10 12
8
6
FREQUENCY (kHz)
14
16
10968 F11
Figure 11. This Clean FFT of an 11.8kHz Input Shows
Remarkable Performance for an ADC That Draws Only 100μA
When Sampling at the 31.25kHz Rate
10968fc
24
LTC1096/LTC1096L
LTC1098/LTC1098L
APPLICATIONS INFORMATION
Effective Number of Bits
EFFECTIVE NUMBER OF BITS (ENOBs)
8
The effective number of bits (ENOBs) is a measurement
of the resolution of an A/D and is directly related to the
S/(N + D) by the equation:
ENOB = [S/(N + D) –1.76]/6.02
where S/(N + D) is expressed in dB. At the maximum sampling rate of 33kHz the LTC1096 maintains 7.5 ENOBs or
better to 40kHz. Above 40kHz the ENOBs gradually decline,
as shown in Figure 12, due to increasing second harmonic
distortion. The noise floor remains approximately 70dB.
fSAMPLE = 31.25kHz
7
6
5
4
3
2
1
0
20
0
40
INPUT FREQUENCY (kHz)
10968 F12
Figure 12. Dynamic Accuracy Is Maintained Up to an Input
Frequency of 40kHz
TYPICAL APPLICATIONS
MICROPROCESSOR INTERFACES
The LTC1096(L)/LTC1098(L) can interface directly (without
external hardware to most popular microprocessor (MPU)
synchronous serial formats (see Table 1). If an MPU without
a dedicated serial port is used, then three or four of the
MPU’s parallel port lines can be programmed to form the
serial link to the LTC1096(L)/LTC1098(L). Included here
is one serial interface example and one example showing
a parallel port programmed to form the serial interface.
Motorola SPI (MC68HC05C4,CM68HC11)
The MC68HC05C4 has been chosen as an example of
an MPU with a dedicated serial port. This MPU transfer
data MSB-first and in 8-bit increments. With two 8-bit
transfers, the A/D result is read into the MPU. The first
8-bit transfer sends the DIN word to the LTC1098(L) and
clocks into the processor. The second 8-bit transfer clocks
the A/D conversion result, B7 through B0, into the MPU.
ANDing the first MUP received byte with 00Hex clears the
first byte. Notice how the position of the start bit in the
first MPU transmit word is used to position the A/D result
right-justified in two memory locations.
Table 1. Microprocessor with Hardware Serial Interfaces
Compatible with the LTC1096(L)/LTC1098(L)
PART NUMBER
TYPE OF INTERFACE
Motorola
MC6805S2,S3
MC68HC11
MC68HC05
SPI
SPI
SPI
RCA
CDP68HC05
SPI
Hitachi
HD6305
HD63705
HD6301
HD63701
HD6303
HD64180
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
SCI Synchronous
CSI/O
National Semiconductor
COP400 Family
COP800 Family
NS8050U
HPC16000 Family
MICROWIRE™
MICROWIRE/PLUS™
MICROWIRE/PLUS
MICROWIRE/PLUS
Texas Instruments
TMS7002
TMS7042
TMS70C02
TMS70C42
TMS32011*
TMS32020
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
Serial Port
* Requires external hardware
MICROWIRE and MICROWIRE/PLUS are trademarks of
National Semiconductor Corp.
10968fc
25
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATIONS
Data Exchange Between LTC1098(L) and MC68HC05C4
START
BIT
MPU TRANSMIT
WORD
0
0
0
BYTE 1
SGL/ ODD/
MSBF X
DIFF SIGN
1
BYTE 2 (DUMMY)
X
X
X
X
X
X
X
X
X = DON'T CARE
CS
START
SGL/ ODD/
DIFF SIGN MSBF
DIN
DON'T CARE
CLK
DOUT
MPU RECEIVED
WORD
?
?
?
?
?
?
?
0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
1ST TRANSFER
Hardware and Software Interface to Motorola MC68HC05C4
CS
C0
SCK
MC68HC05C4
MISO
CLK
ANALOG
INPUTS
LTC1098
DIN
DOUT
MOSI
2ND TRANSFER
LABEL
MNEMONIC
START
BCLRn
LDA
STA
TST
BPL
LDA
10968 TA04
STA
AND
STA
TST
BPL
DOUT from LTC1098(L) Stored in MC68HC05C4
LOCATION A
0
0
0
0
0
0
0
0
BYTE 1
BSETn
LDA
LSB
LOCATION A + 1
B7
B6
B5
B4
B3
B2
B1
B0
10968 TA05
BYTE 2
STA
10968 TA03
COMMENTS
Bit 0 Port C goes low (CS goes low)
Load LTC1098(L) DIN word into Acc.
Load LTC1098(L) DIN word into SPI from Acc.
Transfer begins.
Test status of SPIF
Loop to previous instruction if not done
with transfer
Load contents of SPI data register
into Acc. (DOUT MSBs)
Start next SPI cycle
Clear the first DOUT word
Store in memory location A (MSBs)
Test status of SPIF
Loop to previous instruction if not done
with transfer
Set B0 of Port C (CS goes high)
Load contents of SPI data register into
Acc. (DOUT LSBs)
Store in memory location A + 1 (LSBs)
10968fc
26
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATIONS
Interfacing to the Parallel Port of the
Intel 8051 Family
LABEL
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1098(L) and parallel port microprocessors. Normally the CS, CLK and DIN signals
would be generated on three port lines and the DOUT signal
read on a fourth port line. This works very well. However,
we will demonstrate here an interface with the DIN and
DOUT of the LTC1098(L) tied together as described in the
SERIAL INTERFACE section. This saves one wire.
LOOP 1
LOOP
The 8051 first sends the start bit and MUX address to the
LTC1098(L) over the data line connected to P1.2. Then
P1.2 is reconfigured as an input (by writing to it a one) and
the 8051 reads back the 8-bit A/D result over the same
data line.
ANALOG
INPUTS
CS
LTC1098(L) CLK
DOUT
DIN
P1.4
P1.3
P1.2
MNEMONIC
OPERAND
COMMENTS
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
SETB
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
P1.4
DIN word for LTC1098(L)
Make sure CS is high
CS goes low
Load counter
Rotate DIN bit into Carry
CLK goes low
Output DIN bit to LTC1098(L)
CLK goes high
Next bit
Bit 2 becomes an input
CLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
CLK goes high
CLK goes low
Next bit
Store MSBs in R2
CS goes high
DOUT from LTC1098(L) Stored in 8051 RAM
8051
MSB
MUX ADDRESS
R2
A/D RESULT
B7
LSB
B6
B5
B4
B3
B2
B1
10968 TA06
B0
10968 TA07
MSBF BIT LATCHED
BY LTC1098(L)
CS
1
2
START
SGL/
DIFF
3
4
CLK
DATA (DIN/DOUT)
ODD/
SIGN
MSBF
8051 P1.2 OUTPUTS DATA
TO LTC1098(L)
8051 P1.2 RECONFIGURED
AS AN INPUT AFTER THE 4TH RISING
CLK AND BEFORE THE 4TH FALLING CLK
B7
B6
B5
B4
B3
B2
LTC1098(L) SENDS A/D RESULT
BACK TO 8051 P1.2
B1
B0
10968 TA08
LTC1098(L) TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
10968fc
27
LTC1096/LTC1096L
LTC1098/LTC1098L
A “Quick Look” Circuit for the LTC1096
Users can get a quick look at the function and timing of
the LT1096 by using the following simple circuit (Figure
13). VREF is tied to VCC. VIN is applied to the +IN input and
the – IN input is tied to the ground. CS is driven at 1/16
the clock rate by the 74C161 and DOUT outputs the data.
The output data from the DOUT pin can be viewed on an
oscilloscope that is set up to trigger on the falling edge
of CS (Figure 14). Note the LSB data is partially clocked
out before CS goes high.
CS
CLK
DOUT
10968 F14
4.7μF
MSB
(B7)
NULL
BIT
5V
VIN
CLR
VCC
RC
CLK
QA
A
QB
B
74C161
QC
C
QD
D
T
P
LOAD
GND
VCC
CH0
CLK
LTC1096
CH1
DOUT
GND
LSB DATA
(B1)
VERTICAL: 5V/DIV
HORIZONTAL: 10μs/DIV
+
CS
LSB
(B0)
VREF
5V
Figure 14. Scope Trace the LTC1096 “Quick Look” Circuit
Showing A/D Output 10101010 (AAHEX)
3V
0.1μF
LM134
75k
678Ω
VCC
CLOCK IN 150kHz MAX
TO OSCILLOSCOPE
CS
+IN
10968 F13
13.5k
Figure 13. “Quick Look” Circuit for the LTC1096
Figure 15 shows a temperature measurement system.
The LTC1096 is connected directly to the low cost silicon
temperature sensor. The voltage applied to the VREF pin
adjusts the full scale of the A/D to the output range of the
sensor. The zero point of the converter is matched to the
zero output voltage of the sensor by the voltage on the
LTC1096’s negative input.
–IN LTC1096 CLK
TO μP
182k
VREF
LT1004-1.2
0.01μF
DOUT
GND
0.01μF
63.4k
10968 F15
Figure 15. The LTC1096’s High Impedance Input Connects
Directly to This Temperature Sensor, Eliminating Signal
Conditioning Circuitry in This 0°C to 70°C Thermometer
10968fc
28
LTC1096/LTC1096L
LTC1098/LTC1098L
Remote or Isolated Systems
Figure 16 shows a floating system that sends data to a
grounded host system. The floating circuitry is isolated by
two optoisolators and powered by a simple capacitor diode
charge pump. The system has very low power requirements
because the LTC1096 shuts down between conversions
and the optoisolators draw power only when data is being
transferred. The system consumes only 50μA at a sample
rate of 10Hz (1ms on-time and 99ms off-time). This is
easily within the current supplied by the charge pump
running at 5MHz. If a truly isolated system is required,
the system’s low power simplifies generating an isolated
supply or powering the system from a battery.
FLOATING SYSTEM
1N5817
+
0.001μF
2kV
2N3904
47μF
0.1μF
75k
1N5817
0.022μF
VCC
100k
CS
5MHz
LT1004-2.5
LTC1096
1N5817
300Ω
CLK
100k
CLK
VREF
20k
+IN
–IN
ANALOG
INPUT
DOUT
GND
1k
10k
DATA
500k
10968 F16
Figure 16. Power for This Floating A/D System Is Provided by a Simple Capacitor Diode Charge Pump. The Two Optoisolators
Draw No Current Between Samples, Turning On Only to Send the Clock and Receive Data
10968fc
29
LTC1096/LTC1096L
LTC1098/LTC1098L
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.065
(1.651)
TYP
.100
(2.54)
BSC
.120
(3.048) .020
MIN
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
N8 1002
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
10968fc
30
LTC1096/LTC1096L
LTC1098/LTC1098L
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
NOTE 3
.045 ±.005
.050 BSC
8
.245
MIN
7
6
5
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
× 45°
(0.254 – 0.508)
.008 – .010
(0.203 – 0.254)
3
4
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
2
.014 – .019
(0.355 – 0.483)
TYP
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.050
(1.270)
BSC
SO8 0303
10968fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC1096/LTC1096L
LTC1098/LTC1098L
TYPICAL APPLICATION
A/D Conversion for 3V Systems
The LTC1096/LTC1098 are ideal for 3V systems. Figure
17 shows a 3V to 6V battery current monitor that draws
only 70μA from the battery it monitors. The battery current is sensed with the 0.02Ω resistor and amplified by
the LT1178. The LTC1096 digitizes the amplifier output
and sends it to the microprocessor in serial format. The
LT1004 provides the full-scale reference for the ADC. The
other half of the LTC1178 is used to provide low battery
detection. The circuit’s 70μA supply current is dominated
by the op amps and the reference. The circuit can be
located near the battery and data transmitted serially to
the microprocessor.
0.1μF
0.1μF
3V TO 6V
73.2k
470k
750k
L
O
A
D
24.9k
0.02Ω FOR 2A FULL SCALE
0.2Ω FOR 0.2A FULL SCALE
+
CS
1/2 LT1178
–
VCC
CLK
LTC1096 D
OUT
GND
VREF
+
–
TO μP
20M
+
LO BATTERY
1/2 LT1178
LT1004-1.2
470k
–
10968 F17
Figure 17. This 0A to 2A Battery Current Monitor Draws Only 70μA from a 3V Battery
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1196/LTC1198
8-Pin SO, 1Msps, 8-Bit ADCs
Low Power, Small Size, Low Cost
LTC1286/LTC1298
8-Pin SO, 5V Micropower, 12-Bit ADCs
1- or 2-Channel, Auto Shutdown
LTC1285/LTC1298
8-Pin SO, 3V Micropower, 12-Bit ADCs
1- or 2-Channel, Auto Shutdown
LTC1400
5V High Speed,Serial 12-Bit ADC
400ksps, Complete with VREF, CLK, Sample-and-Hold
LTC1594/LTC1598
4- and 8-Channel, 5V Micropower, 12-Bit ADCs
Low Power, Small Size, Low Cost
LTC1594L/LTC1598L
4- and 8-Channel, 3V Micropower, 12-Bit ADCs
Low Power, Small Size, Low Cost
10968fc
32 Linear Technology Corporation
LT 0708 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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