LTC1235CN#PBF

LTC1235 Microprocessor Supervisory Circuit FEATURES DESCRIPTION n The LTC®1235 provides complete power supply monitoring and battery control functions for microprocessor reset, battery backup, RAM write protection, power failure warning and watchdog timing. The LTC1235 has all the LTC695 features plus conditional battery backup and external reset control. When an out-of-tolerance power supply condition occurs, the reset outputs are forced to active states and the Chip Enable output write-protects external memory. The RESET output is guaranteed to remain logic low with VCC as low as 1V. External reset control is provided by a debounced pushbutton reset input. n n n n n n n n n n n n Guaranteed Reset Assertion at VCC = 1V 1.5mA Maximum Supply Current Fast (35ns Max.) Onboard Gating of RAM Chip Enable Signals Conditional Battery Backup Extends Battery Life 4.65V Precision Voltage Monitor Power OK/Reset Time Delay: 200ms External Reset Control Minimum External Component Count 1μA Maximum Standby Current Voltage Monitor for Power Fail or Low Battery Warning Thermal Limiting Performance Specified Over Temperature All the LTC695 Features Plus Conditional Battery Backup and External Reset Control The LTC1235 powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, provides backup power to the RAMs. The LTC1235 can be programmed by a P signal to either back up the RAMs or not. This extends the battery life in situations where RAM data need not always be saved when power goes down. APPLICATIONS n n n n Critical μP Power Monitoring Intelligent Instruments Battery-Powered Computers and Controllers Automotive Systems For an early warning of impending power failure, the LTC1235 provides an internal comparator with a userdefined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to the time-out period. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION + 10μF 10 LT1086-5 VIN VOUT ADJ +5V VCC + 100μF VOUT 0.1μF VBATT 51k 0.1μF LTC1235 +3V BACKUP RESET PFI PB RST POWER TO μP CMOS RAM POWER I/O LINE μP RESET PFO μP NMI WDI I/O LINE μP SYSTEM 10k 1235 TA1 THE LTC1235 EXTENDS BATTERY LIFE BY PROVIDING BATTERY POWER ONLY WHEN REQUIRED TO BACK UP RAM DATA. IT SAVES THE BATTERY WHEN NO DATA BACKUP IS NEEDED. THE μP REQUESTS BACKUP WITH THE BACKUP PIN. 9 BATTERY LIFE (NORMALIZED) VIN ≥ 7.5V Battery Life vs Backup Duty Cycle LTC1235 8 7 6 5 LTC695 (WITHOUT CONDITIONAL BATTERY BACKUP) 4 3 2 1 0 0 20 60 80 40 BACKUP DUTY CYCLE (%) 100 1235 TA02 1235fa 1 LTC1235 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Terminal Voltage VCC ....................................................... –0.3V to 6.0V VBATT .................................................... –0.3V to 6.0V All Other Inputs ........................–0.3V to (VCC + 0.3V) Input Current VCC ..................................................................200mA VBATT .................................................................50mA VOUT Output Current ................... Short Circuit Protected Power Dissipation ...............................................500mW Operating Temperature Range LTC1235C ................................................ 0°C to 70°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec.) ................. 300°C PIN CONFIGURATION TOP VIEW TOP VIEW VBATT 1 16 RESET VBATT 1 16 PRESET VOUT 2 15 RESET VOUT 2 15 PRESET WDO VCC 3 14 WDO VCC 3 14 GND 4 13 CE IN GND 4 13 CE IN BATT ON 5 12 CE OUT BATT ON 5 12 CE OUT LOW LINE 6 11 WDI LOW LINE 6 11 WDI PB RST 7 10 PFO PB RST 7 10 PFO BACKUP 8 9 PFI BACKUP 8 9 PFI LTC1235 N PACKAGE 16-LEAD PLASTIC DIP LTC1235 SW PACKAGE 16-LEAD PLASTIC SOL TJMAX = 110°C, θJA = 130°C/W TJMAX = 110°C, θJA = 130°C/W CONDITIONS:PCB MOUNT ON FR4 MATERIAL, STILL AIR AT 25°C COPPER TRACE ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1235CN#PBF LTC1235CN#TRPBF LTC1235CN 16-Lead Plastic DIP 0°C to 70°C LTC1235CSW#PBF LTC1235CSW#TRPBF LTC1235CSW 16-Lead Plastic SOL 0°C to 70°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ PRODUCT SELECTION GUIDE PINS RESET WATCHDOG TIMER BATTERY BACKUP POWER FAIL WARNING RAM WRITE PROTECT PUSH-BUTTON RESET CONDITIONAL BATTERY BACKUP X X X LTC1235 16 X X X X LTC690 8 X X X X LTC691 16 X X X X LTC694 8 X X X X LTC695 16 X X X X LTC699 8 X X LTC1232 8 X X X X X 1235fa 2 LTC1235 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS 5.50 4.25 V V Battery Backup Switching Operating Voltage Range VCC VBATT 4.75 2.00 VOUT Output Voltage IOUT = 1mA BACKUP Input Threshold VCC > Reset Voltage Threshold Logic Low Logic High l IOUT = 50mA VCC – 0.05 VCC – 0.1 VCC – 0.5 VCC – 0.005 VCC – 0.005 VCC – 0.25 V V V 0.8 2.0 BACKUP Pullup Current (Note 4) 3 VOUT in Battery Backup Mode (Note 5) IOUT = 250μA, VCC < VBATT VOUT in Battery Saving Mode (Note 5) VCC < VBATT 1MΩ Pulldown on VOUT VCC Supply Current (excluding IOUT ) IOUT ≤ 50mA Battery Supply Current in Battery Backup Mode and Battery Saving Mode (Note 5) VCC = 0V, VBATT = 2.8V Battery Standby Current (+ = Discharge, – = Charge) 5.5 > VCC > VBATT + 0.2V Battery Switchover Threshold VCC – VBATT Power-Up Power-Down V V μA VBATT – 0.1 VBATT – 0.02 V 0 V V l 0.6 0.6 1.5 2.5 mA mA l 0.04 0.04 1 5 μA μA +0.02 +0.10 μA μA l –0.1 –1.0 Battery Switchover Hysteresis 70 50 mV mV 20 mV BATT ON Output Voltage (Note 6) ISINK = 3.2mA BATT ON Output Short Circuit Current (Note 6) BATT ON = VOUT Sink Current BATT ON = 0V Source Current 0.5 Logic Low Logic High 2.0 V V l 40 ms l 4.5 35 1 0.4 V 25 mA μA Push-Button Reset PB RST Input Threshold PB RST Input Low Time (Notes 4, 7) 0.8 Reset and Watchdog Timer Reset Voltage Threshold Reset Threshold Hysteresis 4.65 4.75 40 Reset Active Time VCC = 5V Watchdog Time-out Period VCC = 5V V mV l 60 140 200 200 240 280 ms ms l 1.2 1.0 1.6 1.6 2.00 2.25 sec sec Reset Active Time PSRR 1 ms/V Watchdog Time-out Period PSRR 8 ms/V l Minimum WDI Input Pulse Width VIL = 0.4V, VIH = 3.5V 200 RESET Output Voltage At VCC = 1V ISINK = 10μA, VCC = 1V RESET and LOW LINE Output Voltage (Note 6) ISINK = 1.6mA, VCC = 4.25V ISOURCE = 1μA, VCC = 5V 3.5 RESET and WDO Output Voltage (Note 6) ISINK = 1.6mA, VCC = 5V ISOURCE = 1μA, VCC = 4.25V 3.5 ns 4 200 mV 0.4 V V 0.4 V V 1235fa 3 LTC1235 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = Full Operating Range, VBATT = 2.8V, Backup = No Connection, TA = 25°C, unless otherwise noted. PARAMETER CONDITIONS RESET, RESET, WDO, LOW LINE Output Short Circuit Current (Note 6) Output Source Current Output Sink Current WDI Input Threshold Logic Low Logic High WDI Input Current MIN TYP MAX 1 3 25 25 μA mA 0.8 V V 2.0 UNITS WDI = VOUT WDI = 0V l l 4 –8 50 –50 μA μA VCC = 5V l 1.25 1.3 1.35 V Power Fail Detector PFI Input Threshold PFI Input Threshold PSRR 0.3 PFI Input Current PFO Output Voltage (Note 6) PFO Short Circuit Source Current (Note 6) ±0.01 ISINK = 3.2mA ISOURCE = 1A mV/V ±25 nA 0.4 V V 25 μA mA 3.5 PFI = HIGH, PFO = 0V PFI = LOW, PFO = VOUT 1 3 30 PFI Comparator Response Time (falling) ΔVIN = –20mV, VOD = 15mV 2 μs PFI Comparator Response Time (rising) (Note 6) ΔVIN = 20mV, VOD = 15mV with 10kΩ Pullup 40 8 μs μs Chip Enable Gating CE IN Threshold 0.8 VIL VIH 2.0 CE IN Pullup Current (Note 4) CE OUT Output Voltage 3 ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1μA, VCC = 0V CE Propagation Delay VCC = 5V, CL = 20pF CE OUT Output Short Circuit Current Output Source Current Output Sink Current Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts, consult the factory. Note 4: The input pins of PB RST, BACKUP and CE IN, have weak internal pullups which pull to the supply when the input pins are floating. Note 5: The LTC1235 can be programmed either to provide or not to provide battery backup power to the VOUT pin during power failure. The power down condition of VOUT is selected by the logic level of the BACKUP pin which is latched internally when VCC falls through the reset voltage threshold. If the latched logic level of the BACKUP pin is high, μA 0.4 V V V 35 45 ns ns VOUT – 1.50 VOUT – 0.05 l 20 20 30 35 V V mA mA VOUT will be in Battery Backup Mode and will be switched to VBATT when VCC falls below VBATT. If the latched logic level of the BACKUP pin is low, VOUT will be in Battery Saving Mode when VCC falls below VBATT. Note 6: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and RESET have weak internal pullups of typically 3A. However, external pullup resistors may be used when higher speed is required. Note 7: The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset outputs go to the active states. The reset outputs will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level. 1235fa 4 LTC1235 TYPICAL PERFORMANCE CHARACTERISTICS VOUT vs IOUT 2.80 VCC = 5V VBATT = 2.8V TA = 25°C OUTPUT VOLTAGE (V) 4.95 4.90 SLOPE = 5Ω 4.85 1.308 VCC = 0V VBATT = 2.8V TA = 25°C 2.78 VCC = 5V 1.306 PFI INPUT THRESHOLD (V) 5.00 OUTPUT VOLTAGE (V) Power Failure Input Threshold vs Temperature VOUT vs IOUT BACKUP MODE SELECTED SLOPE = 125Ω 2.76 2.74 4.80 1.304 1.302 1.300 1.298 1.296 10 0 30 40 20 LOAD CURRENT (mA) 2.72 50 100 0 300 400 200 LOAD CURRENT (μA) 1235 G01 RESET VOLTAGE THRESHOLD (V) RESET ACTIVE TIME (ms) RESET OUTPUT VOLTAGE (V) 4.66 224 2 1 216 208 200 192 1 3 4 2 SUPPLY VOLTAGE (V) 5 184 –50 –25 50 25 75 0 TEMPERATURE (°C) 1235 G04 4 2 + – PFO 30pF 1 0 PFO OUTPUT VOLTAGE (V) VCC = 5V TA = 25°C 5 1.3V 125 6 5 VCC = 5V TA = 25°C 4 3 2 VPFI + 1 1.3V – 1.315V VPFI = 20mV STEP 1.285V 0 1 2 3 4 5 TIME (μs) 4.63 4.62 4.61 4.60 –50 –25 PFO 30pF 7 8 1235 G07 100 0 20 40 125 1235 G06 6 5 VCC = 5V TA = 25°C 4 3 2 +5V 1 0 1.315V VPFI = 20mV STEP 1.295V 6 50 25 75 0 TEMPERATURE (°C) Power Fail Comparator Response Time with Pullup Resistor 0 1.305V 4.64 Power Fail Comparator Response Time 6 VPFI 100 4.65 1235 G05 Power Fail Comparator Response Time 3 125 VCC = 5V 3 0 100 Reset Voltage Threshold vs Temperature 232 TA = 25°C EXTERNAL PULLUP = 10μA VBATT = 0V 4 50 25 75 0 TEMPERATURE (˚C) 1235 G03 Reset Active Time vs Temperature 5 PFO OUTPUT VOLTAGE (V) 1.294 –50 –25 1235 G02 RESET Output Voltage vs SupplyVoltage 0 500 PFO OUTPUT VOLTAGE (V) 4.75 1235 G08 + 1.3V – 10k PFO 30pF VPFI = 20mV STEP 1.295V 60 80 100 120 140 160 180 TIME (μs) VPFI 0 2 4 8 10 12 14 16 18 TIME (μs) 6 1235 G09 1235fa 5 LTC1235 PIN FUNCTIONS VBATT (Pin 1): Backup battery input. When VCC falls below VBATT, the status of the BACKUP pin stored in the Memory Logic controls M2. If the status is high, auxiliary power, connected to VBATT is delivered to VOUT through M2. If the status is low, the Memory Logic keeps M2 off and VOUT is in Battery Saving Mode. If backup battery or auxiliary power is not used, VBATT should be connected to GND. VOUT (Pin 2): Voltage output for backed up memory. Bypass with a capacitor of 0.1μF or greater. During normal operation, VOUT obtains power from VCC through an NMOS power switch, M1, which can deliver up to 50mA and has a typical on resistance of 5Ω. When VCC is lower than VBATT, the status of the BACKUP pin stored in Memory Logic controls M2. If the status is high, the Memory Logic turns on M2 and VOUT is internally switched to VBATT through M2. If the status is low, the Memory Logic keeps M2 off and VOUT is in Battery Saving Mode. If VOUT and VBATT are not used, connect VOUT to VCC. VCC (Pin 3): +5V supply input. The VCC pin should be bypassed with a 0.1μF capacitor. GND (Pin 4): Ground pin. BATT ON (Pin 5): Battery on logic output from comparator C2. BATT ON goes low when VOUT is internally connected to VCC. The output typically sinks 35mA and can provide base drive for an external PNP transistor to increase the output current above the 50mA rating of VOUT. BATT ON goes high when VCC falls below VBATT, if the status of the BACKUP pin stored in Memory Logic is high and VOUT is switched to VBATT. LOW LINE (Pin 6): Logic output from comparator C1. LOW LINE indicates a low line condition at the VCC input. When VCC falls below the reset voltage threshold (4.65V typically), LOW LINE goes low. As soon as VCC rises above the reset voltage threshold, LOW LINE returns high (see Figure 1). LOW LINE goes low when VCC drops below VBATT (see Table 1). PB RST (Pin 7): Logic input for direct connection to a pushbutton. The push-button reset input requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces RESET to active low. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level. Pulled to VCC with 60k. Backup (Pin 8): Logic input to control the PMOS switch, M2, when VCC is lower than VBATT. While VCC is falling through the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is latched in Memory Logic and used to turn on or off M2 when VCC is below VBATT. If the latched status of the BACKUP pin is high, the Memory Logic turns on M2 when VCC falls to 50mV greater than VBATT. If the latched status of the BACKUP pin is low, the Memory Logic keeps M2 off even after VCC falls below VBATT. If the BACKUP pin is left floating it will be pulled high by an internal pullup and the LTC1235 will provide battery backup when VCC falls. PFI (Pin 9): Power Failure Input. PFI is the noninverting input to the Power Fail Comparator, C3. The inverting input is internally connected to a 1.3V reference. The Power Failure Output remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. Connect PFI to GND or VOUT when C3 is not used. PFO (Pin 10): Power Failure Output from C3. PFO remains high when PFI is above 1.3V and goes low when PFI is below 1.3V. When VCC is lower than VBATT, C3 is shut down and PFO is forced low. WDI (Pin 11): Watchdog Input, WDI, is a three level input. Driving WDI either high or low for longer than the watchdog time-out period, forces both RESET and WDO low. Floating WDI disables the Watchdog Timer. The timer resets itself with each transition of the Watchdog Input (see Figure 11). CE OUT (Pin 12): Logic output from the Chip Enable gating circuit. When VCC is above the reset voltage threshold, CE OUT is a buffered replica of CE IN. When VCC is below the reset voltage threshold CE OUT is forced high (see Figure 6). CE IN (Pin 13): Logic input to the Chip Enable gating circuit. CE IN can be derived from microprocessor’s address line and/or decoder output. See Applications Information Section and Figure 6 for additional information. WDO (Pin 14): Watchdog logic output. When the watchdog input remains either high or low for longer than the watchdog time-out period, WDO goes low. WDO is set 1235fa 6 LTC1235 PIN FUNCTIONS high when ever there is a transition on the WDI pin, or LOW LINE goes low. The watchdog timer can be disabled by floating WDI (see Figure 11). RESET (Pin 15): Logic output for μP reset control. The LTC1235 provides three ways to generate μP reset. First, whenever VCC falls below either the reset voltage threshold (4.65V, typically) or VBATT, RESET goes active low. After VCC returns to 5V, the reset pulse generator forces RESET to remain active low for a minimum of 140ms. Second, when the watchdog timer is enabled but not serviced prior to the time-out period, the reset pulse generator also forces RESET to active low for a minimum of 140ms for every time-out period (see Figure 11). Third, when the PB RST pin stays active low for a minimum of 40ms, RESET is forced low by reset pulse generator. The RESET signal will remain active low for a minimum of 140ms from the moment the push-button reset input is released from logic low level. RESET (Pin 16): RESET is an active high logic output. It is the inverse of RESET. BLOCK DIAGRAM M2 VBATT VOUT M1 VCC BACKUP MEMORY LOGIC CHARGE PUMP – C2 + BATT ON LOW LINE + C1 – CE OUT 1.3V GND CE IN – PFO + PFI VCC OSC 60k PB RST WDI RESET LEVEL SENSE AND DEBOUNCE RESET PULSE GENERATOR TRANSITION DETECTOR WATCHDOG TIMER RESET WDO 1235 BD 1235fa 7 LTC1235 APPLICATIONS INFORMATION Power Monitoring The LTC1235 uses a bandgap voltage reference and a precision voltage comparator C1 to monitor the 5V supply input on VCC (see Block Diagram). When VCC falls below the reset voltage threshold, the reset outputs are forced to active states. The reset voltage threshold accounts for a 5% variation on VCC, so the reset outputs become active when VCC falls below 4.75V (4.65V typical). On power-up, the reset signals are held active states for a minimum of 140ms after the reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. On power-down, the RESET signal remains active low even with VCC as low as 1V. This capability helps hold the microprocessor in stable shutdown condition. Figure 1 shows the timing diagram of the RESET signal. The precision voltage comparator, C1, typically has 40mV of hysteresis which ensures that glitches at VCC pin do not activate the reset outputs. Response time is typically 10μs. V2 V1 VCC RESET To help prevent mistriggering due to transient loads, VCC pin should be bypassed with a 0.1μF capacitor with the leads trimmed as short as possible. LOW LINE is the output of the precision voltage comparator C1. When VCC falls below the reset voltage threshold, LOW LINE goes low. LOW LINE returns high as soon as VCC rises above the reset voltage threshold. Push-Button Reset The LTC1235 provides an logic input pin for direct connection to a push-button. The push-button reset input, PB RST, requires an active low signal. Internally, this input signal is debounced and timed for a minimum of 40ms. When this condition is satisfied, the reset pulse generator forces the reset outputs to active states. The reset signals will remain in active states for a minimum of 140ms from the moment the push-button reset input is released from logic low level (Figure 2). V2 V1 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS t1 t1 t1 = RESET ACTIVE TIME LOW LINE 1235 F01 Figure 1. Reset Active Time VCC = 5V PB RST t1 LOGIC LOW LOGIC HIGH t2 RESET LOGIC HIGH LOGIC LOW RESET 1235 F02 t1 = PUSH-BUTTON RESET LOW TIME t2 = RESET ACTIVE TIME Figure 2. Push-Button Reset 1235fa 8 LTC1235 APPLICATIONS INFORMATION Voltage Output During normal operation, the LTC1235 uses a charge pumped NMOS power switch to achieve low dropout and low supply current. This power switch can deliver up to 50mA to VOUT from VCC and has a typical on resistance of 5. The VOUT pin should be bypassed with a capacitor of 0.1μF or greater to ensure stability. Use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. When operating currents larger than 50mA are required from VOUT, or a lower dropout (VCC - VOUT voltage differential) is desired, the LTC1235 provides BATT ON output to drive the base of external PNP transistor (Figure 3). Another alternative to provide higher current is to connect a high current Schottky diode from the VCC pin to the VOUT pin to supply the extra current. ANY PNP POWER TRANSISTOR R1 BATT ON VOUT VCC +5V 0.1μF LTC1235 +3V 0.1μF VBATT GND 1235 F03 Figure 3. Using BATT ON to Drive External PNP Transistor The LTC1235 is protected for safe area operation with short circuit limit. Output current is limited to approximately 200mA. If the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. The threshold temperature for thermal shutdown is approximately 155°C with about 10°C of hysteresis which prevents the device from oscillating in and out of shutdown. The PNP switch was not chosen for the internal power switch because it injects unwanted current into the substrate. This current is collected by the VBATT pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. LTC1235 uses a charge pumped NMOS power switch to eliminate unwanted charging current while achieving low dropout and low supply current. Since no current goes to the substrate, the current collected by VBATT pin is strictly junction leakage. Conditional Battery Backup LTC1235 provides an unique feature to either allow VOUT to be switched to VBATT or to disable the CMOS RAM battery backup function when primary power is lost. Disabling the battery backup function is useful in conserving the backup battery’s life when the SRAM doesn’t need battery backup during long term storage of a computer system, or delivery of the computer system to the end user. The BACKUP pin (Pin 8) is used to serve this feature on power-down. When VCC is falling through the reset voltage threshold, the status of the BACKUP pin (logic low or logic high) is stored in the Memory Logic (see Block Diagram). If the stored status is logic high and VCC fall to 50mV greater than VBATT, a 125Ω PMOS switch, M2, connects the VBATT input to VOUT and the battery switchover comparator, C2, shuts off the NMOS power switch, M1. M2 is designed for very low dropout voltage (input-to-output differential). This feature is advantageous for low current applications such as battery backup in CMOS RAM and other low power CMOS circuitry. If the stored status is logic low and VCC falls to 50mV greater than VBATT, the Memory Logic keeps M2 off and C2 shuts off M1. VOUT is in Battery Saving Mode (see Figure 4). The supply current in both mode is 1μA maximum. On power-ups, C2 keeps M1 off before VCC reaches 70mV higher than VBATT. On the first power-up after the battery is replaced (with power off), the status stored in the Memory Logic is undetermined. VOUT could be either in Battery Backup Mode or in Battery Saving Mode. When VCC is 70mV greater than VBATT, M1 connects VOUT to VCC. C2 has typically 20mV of hysteresis to prevent spurious switching when VCC remains nearly equal to VBATT and the status stored in the Memory Logic is high. The response time of C2 is approximately 20μs. 1235fa 9 LTC1235 APPLICATIONS INFORMATION Replacing the Backup Battery with Power On VOUT IN BATTERY SAVING MODE BACKUP When changing the backup battery with system power on, spurious resets can occur while battery is removed due to battery standby current. Although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the VBATT pin. The oscillation cycle is as follows: When VBATT reaches within 50mV of VCC, the LTC1235 switches to battery backup or battery saving mode. In either case, the battery supply current pulls VBATT low and the device goes back to normal operation. The leakage current then charges up the VBATT pin again and the cycle repeats. LOGIC LOW RESET VOLTAGE THRESHOLD VCC VBATT VOUT Hi-Z VOUT IN BATTERY BACKUP MODE LOGIC HIGH BACKUP RESET VOLTAGE THRESHOLD VCC VBATT VOUT VOUT = VBATT 1235 F04 Figure 4. Conditional Battery Backup Operation The operating voltage at the VBATT pin ranges from 2.0V to 4.25V. High value capacitors, such as electrolytic or faradsize double layer capacitors, can be used for short term memory backup instead of a battery. For capacitor backup, see Typical Applications. The charging resistor for recharging rechargeable batteries should be connected to VOUT through a diode since this eliminates the discharge path that exists when VCC collapses and RAM is not backed up (Figure 5). V – VBATT – VD I = OUT R VCC VOUT 0.1μF 0.1μF RAM LTC1235 +3V BACKUP VBATT GND 4 where TREQ’D is the maximum time required to replace the backup battery. With VCC = 4.5V, VBATT = 3V and TREQ’D = 3 sec, the value for external capacitor is 2μF. Second, a resistor from VBATT to GND will hold the pin low while changing the battery. For example, the battery standby current is 1μA maximum over temperature and the external resistor required to hold VBATT below VCC is: R≤ VCC ± 50mV 1μA With VCC = 4.5V, a 4.3M resistor will work. With a 3V battery, this resistor will draw only 0.7μA from the battery, which is negligible in most cases. 1N4148 R +5V If spurious resets during battery replacement pose no problems, then no action is required. Otherwise, two methods can be used to eliminate this problem. First, a capacitor from VBATT to GND will allow time for battery replacement by slowing the charge rate. For example, the battery standby current is 1μA maximum over temperature and the external capacitor required to slow the charge rate is:   1μA CEXT
TREQ'D    VCC ± VBATT  I/O LINE μP 1235 F05 Figure 5. Charging External Battery Through VOUT If the battery connections are made with long wires or PC traces, inductive spikes can be generated during battery replacement. Even if a resistor is used to prevent spurious resets as described above, these spikes can take the VBATT pin below GND violating the LTC1235 absolute maximum ratings. A 0.1μF capacitor from VBATT to GND is recommended to eliminate these potential spikes when battery replacement is made through long wires. 1235fa 10 LTC1235 IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is +5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 6 shows the timing diagram of CE IN and CE OUT. Table 1 shows the state of each pin during battery backup. If the backup battery is not used, connect VBATT to GND and VOUT to VCC. Table 1. Input and Output Status in Battery Backup Mode SIGNAL STATUS VCC C2 monitors VCC for active switchover. BACKUP BACKUP is ignored. VOUT VOUT is connected to VBATT through an internal PMOS switch. VBATT The supply current is 1μA maximum. BATT ON Logic high. The open circuit output voltage is equal to VOUT. PFI Power Failure Input is ignored. PFO Logic low PB RST PB RST is ignored. RESET Logic low RESET Logic high. The open circuit output voltage is equal to VOUT. CE IN can be derived from the microprocessor’s address decoder output. Figure 7 shows a typical nonvolatile CMOS RAM application. +5V 0.1μF LOW LINE Logic low Watchdog Input is ignored. WDO Logic high. The open circuit output voltage is equal to VOUT. CE OUT VCC + 0.1μF 10μF LTC1235 WDI CE IN VOUT VCC CE OUT VBATT Chip Enable Input is ignored. +3V Logic high. The open circuit output voltage is equal to VOUT. GND CE IN BACKUP CS 20ns PROPAGATION DELAY FROM DECODER GND RESET TO μP Memory Protection The LTC1235 includes memory protection circuitry which ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two pins, CE 62512 RAM 1235 F07 Figure 7. A Typical Nonvolatile CMOS RAM Application BACKUP = VCC V2 VCC V1 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS CE IN VOUT = VBATT CE OUT VOUT = VBATT 1235 F06 Figure 6. Timing Diagram for CE IN and CE OUT 1235fa 11 LTC1235 APPLICATIONS INFORMATION Power Fail Warning The LTC1235 generates a Power Failure Output (PFO) for early warning of failure in the microprocessor’s power supply. This is accomplished by comparing the Power Failure Input (PFI) with an internal 1.3V reference. PFO goes low when the voltage at PFI pin is less than 1.3V. Typically PFI is driven by an external voltage divider (R1 and R2 in Figures 8 and 9) which senses either an unregulated DC input or a regulated 5V output. The voltage divider ratio can be chosen such that the voltage at PFI pin falls below 1.3V several milliseconds before the +5V supply falls below the maximum reset voltage threshold 4.75V. PFO is normally used to interrupt the microprocessor to execute shutdown procedure between PFO and RESET or RESET. VHYST = 5V R3 ≈ 5.88 R1 Choose R3 = 300k and R1 = 51k. Also select R4 = 10k which is much smaller than R3.
51k (5V ± 1.3V)51k  ± 7.5V = 1.3V 1+  1.3V(310k)   R2 R2 = 9.7k, Choose nearest 5% resistor 10k and recalculate VL,
51k (5V ± 1.3V)51k  ± VL =1.3V 1+  = 7.32V 1.3V(310k)   10k The power fail comparator, C3, does not have hysteresis. Hysteresis can be added however, by connecting a resistor between the PFO output and the noninverting PFI input pin as shown in Figures 8 and 9. The upper and lower trip points in the comparator are established as follows: When PFO output is low, R3 sinks current from the summing junction at the PFI pin.
R1 R1  VH = 1.3V 1+ +   R2 R3 
51k 51k  + VH =1.3V 1+  = 8.151V  10k 300k  (7.32V – 6.25V) = 10.7ms 100mV/ms VHYST = 8.151V – 7.32V = 831mV VIN ≥ 7.5V 10μF When PFO output is high, the series combination of R3 and R4 source current into the PFI summing junction.
R1 (5V ± 1.3V)R1  VL =1.3V 1+ ±   R2 1.3V(R3+R4)  Assuming R4«R3,VHYST = 5V + LT1086-5 VIN VOUT +5V + ADJ VCC 0.1μF R4 10k 100μF R3 300k R1 51k LTC1235 PFO BACKUP PFI GND TO μP R2 10k 1235 F08 R1 R3 Example 1: The circuit in Figure 8 demonstrates the use of the power fail comparator to monitor the unregulated power supply input. Assuming the rate of decay of the supply input VIN is 100mV/ms and the total time to execute a shut-down procedure is 8ms. Also the noise of VIN is 200mV. With these assumptions in mind, we can reasonably set VL = 7.5V which 1.25V greater than the sum of maximum reset voltage threshold and the dropout voltage of LT1086-5 (4.75V + 1.5V) and VHYST = 850mV. R1 = 850mV R3 Figure 8. Monitoring Unregulated DC Supply with the LTC1235 Power Fail Comparator VIN ≥ 6.5V + 10μF LT1086-5 VIN VOUT ADJ 10μF + +5V R1 27k R4 10k R3 2.7M 0.1μF VCC LTC1235 PFO BACKUP PFI GND TO μP R2 8.2k R5 3.3k 1235 F09 Figure 9. Monitoring Regulated DC Supply with the LTC1235 Power Fail Comparator 1235fa 12 LTC1235 APPLICATIONS INFORMATION The 10.7ms allows enough time to execute shut-down procedure for microprocessor and 831mV of hysteresis would prevent PFO from going low due to the noise of VIN. time-out period and reset active time. The watchdog timeout period is restarted as soon as the reset outputs are inactive. When either a high-to-low or low-to-high transition occurs at the WDI pin prior to time-out, the watchdog time is reset and begins to time out again. To ensure the watchdog time does not time out, either a high-to-low or low-to-high transition on the WDI pin must occur at or less than the minimum time-out period. If the input to the WDI pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. The watchdog timer can be deactivated by floating the WDI pin. The timer is also disabled when VCC falls below the reset voltage threshold or VBATT. Example 2: The circuit in Figure 9 can be used to measure the regulated 5V supply to provide early warning of power failure. Because of variations in the PFI threshold, this circuit requires adjustment to ensure that the PFI comparator trips before the reset threshold is reached. Adjust R5 such that the PFO output goes low when the VCC supply reaches the desired level (e.g., 4.85V). Monitoring the Status of the Battery C3 can also monitor the status of the memory backup battery (Figure 10). If desired, the CE OUT can be used to apply a test load to the battery. Since CE OUT is forced high in battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. The Watchdog Output, WDO, goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the WDI pin. WDO is also set high when VCC falls below the reset voltage threshold or VBATT. +5V Watchdog Timer VBATT PFO R1 1M The LTC1235 provides a watchdog timer function to monitor the activity of the microprocessor. If the microprocessor does not toggle the Watchdog Input (WDI) within the time-out period, the reset outputs are forced to active states for a minimum of 140ms. The watchdog time-out period is fixed at 1.0 second minimum on the LTC1235. This time-out period provides adequate time for many systems to service the watchdog timer immediately after a reset. Figure 11 shows the timing diagram of watchdog VCC LOW BATTERY SIGNAL TO μP I/O PIN LTC1235 PFI BACKUP R2 1M +3V CE IN CE OUT TO μP I/O PIN GND RL 20k OPTIONAL TEST LOAD 1235 F10 Figure 10. Backup Battery Monitor with Optional Test Load VCC = 5V WDI t1 = RESET ACTIVE TIME t2 = WATCHDOG TIME-OUT PERIOD WDO t2 t2 RESET t1 t1 t1 1235 F11 Figure 11. Watchdog Time-out Period and Reset Active Time 1235fa 13 LTC1235 TYPICAL APPLICATIONS Capacitor Backup with 74HC4016 Switch +5V VCC VOUT 0.1μF 0.1μF R1 10k 10 11 12 14 1 2 74HC4016 R2 30k LTC1235 13 7 VBATT LOW LINE + GND 100μF 1235 TA3 Write Protect for Additional RAMs 0.1μF +5V VOUT VCC 0.1μF + LTC1235 CE OUT CE IN BACKUP 62512 RAMA CS 20ns PROPAGATION DELAY VBATT +3V VCC 10μF LOW LINE GND 0.1μF CSA VCC 62128 RAMB CS1 CSB CS2 CSC 0.1μF VCC μP SYSTEM 62128 RAMC CS1 CS2 OPTIONAL CONNECTION FOR ADDITIONAL RAMs LTC1235 TA4 1235fa 14 LTC1235 PACKAGE DESCRIPTION N Package 16-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .770* (19.558) MAX 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .130 ± .005 (3.302 ± 0.127) .020 (0.508) MIN .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 +0.889 8.255 –0.381 .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .120 (3.048) MIN ) .018 ± .003 (0.457 ± 0.076) .100 (2.54) BSC NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) N16 1002 SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .398 – .413 (10.109 – 10.490) NOTE 4 16 N 15 14 13 12 11 10 9 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) .005 (0.127) RAD MIN 2 3 4 5 6 .093 – .104 (2.362 – 2.642) 7 8 .037 – .045 (0.940 – 1.143) 0° – 8° TYP .009 – .013 (0.229 – 0.330) NOTE 3 .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN .050 (1.270) BSC .004 – .012 (0.102 – 0.305) .014 – .019 (0.356 – 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S16 (WIDE) 0502 1235fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1235 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC690 Single Channel Supervisor UL recognized battery backup LTC691 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect LTC692 Single Channel Supervisor UL recognized battery backup LTC693 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect LTC694 Single Channel Supervisor UL recognized battery backup LTC695 Single Channel Supervisor UL recognized and conditional battery backup, RAM protect LTC699 Single Channel Supervisor Microprocessor Supervisory Circuit 1235fa 16 Linear Technology Corporation LT 0708 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1992