LTC2290IUP

LTC2290 Dual 12-Bit, 10Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2290 is a 12-bit 10Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2290 is perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated Dual 12-Bit ADCs Sample Rate: 10Msps Single 3V Supply (2.7V to 3.4V) Low Power: 120mW 71.3dB SNR 90dB SFDR 110dB Channel Isolation Multiplexed or Separate Data Bus Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit) 80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit) 65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit) 40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit) 25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit) 10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit) 64-Pin (9mm × 9mm) QFN Package DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. An optional multiplexer allows both channels to share a digital output bus. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation U TYPICAL APPLICATIO Typical INL, 2V Range ANALOG INPUT A INPUT S/H – 12-BIT PIPELINED ADC CORE OUTPUT DRIVERS OVDD 1.0 D11A 0.8 •• • 0.6 D0A OGND CLK A CLOCK/DUTY CYCLE CONTROL CLK B CLOCK/DUTY CYCLE CONTROL MUX INL ERROR (LSB) + 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 OVDD + ANALOG INPUT B INPUT S/H – 12-BIT PIPELINED ADC CORE OUTPUT DRIVERS D11B •• • D0B –1.0 0 1024 2048 CODE 3072 4096 2290 TA01 OGND 2295 TA01 2290fa 1 LTC2290 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2290C ............................................... 0°C to 70°C LTC2290I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA11 55 DA10 54 DA9 53 DA8 52 DA7 51 DA6 50 OGND 49 OVDD TOP VIEW AINA+ 1 AINA– 2 REFHA 3 REFHA 4 REFLA 5 REFLA 6 VDD 7 CLKA 8 CLKB 9 VDD 10 REFLB 11 REFLB 12 REFHB 13 REFHB 14 AINB– 15 AINB+ 16 48 DA5 47 DA4 46 DA3 45 DA2 44 DA1 43 DA0 42 NC 41 NC 40 OFB 39 DB11 38 DB10 37 DB9 36 DB8 35 DB7 34 DB6 33 DB5 GND 17 VDD 18 SENSEB 19 VCMB 20 MUX 21 SHDNB 22 OEB 23 NC 24 NC 25 DB0 26 DB1 27 DB2 28 DB3 29 DB4 30 OGND 31 OVDD 32 65 UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 125°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB ORDER PART NUMBER QFN PART* MARKING LTC2290CUP LTC2290IUP LTC2290UP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise CONDITIONS MIN ● Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference Internal Reference External Reference External Reference SENSE = 1V ● ● ● ● 12 –1.3 –0.7 –12 –2.5 TYP ±0.3 ±0.15 ±2 ±0.5 ±10 ±30 ±5 ±0.3 ±2 0.25 MAX 1.3 0.7 12 2.5 UNITS Bits LSB LSB mV %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS 2290fa 2 LTC2290 U U SYMBOL PARAMETER VIN Analog Input Range (AIN+ –AIN–) VIN,CM Analog Input Common Mode (AIN+ A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS +AIN –)/2 MIN 2.7V < VDD < 3.4V (Note 7) ● TYP MAX UNITS ±0.5 to ±1 V Differential Input (Note 7) ● 1 1.5 1.9 V Single Ended Input (Note 7) ● 0.5 1.5 2 V 0V < AIN+, AIN– ● –1 1 µA IIN Analog Input Leakage Current ISENSE SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA IMODE MODE Input Leakage Current 0V < MODE < VDD ● –3 3 µA tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB 575 MHz Full Power Bandwidth < VDD 0 Figure 8 Test Circuit ns W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 70MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher 70MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input IMD Intermodulation Distortion fIN = 4.3MHz, 4.6MHz Crosstalk fIN = 5MHz MIN TYP ● 69.6 71.3 ● 74 70MHz Input SFDR 5MHz Input 5MHz Input 70MHz Input ● ● 80 69 MAX UNITS dB 70.7 dB 90 dB 85 dB 90 dB 90 dB 71.3 dB 70.4 dB 90 dB –110 dB 2290fa 3 LTC2290 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN, MUX) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 0.8 V 10 µA 3 pF LOGIC OUTPUTS OVDD = 3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V 0.4 V V OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V 2290fa 4 LTC2290 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V OVDD Output Supply Voltage IVDD Supply Current (Note 9) ● 0.5 3 3.6 V Both ADCs at fS(MAX) ● 40 46 mA PDISS Power Dissipation Both ADCs at fS(MAX) ● 120 138 mW PSHDN Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW PNAP Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS fs Sampling Frequency (Note 9) ● MIN 1 TYP MAX tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 40 5 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 40 5 tAP Sample-and-Hold Aperture Delay tD CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns tMD MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns BUS Relinquish Time (Note 7) ● 3.3 8.5 MHz 50 50 500 500 ns ns 50 50 500 500 ns ns 0 Pipeline Latency Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential drive, unless otherwise noted. UNITS 10 5 nS ns Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with differential drive. The supply current and power dissipation are the sum total for both channels with both channels active. Note 9: Recommended operating conditions. 2290fa 5 LTC2290 U W TYPICAL PERFOR A CE CHARACTERISTICS Crosstalk vs Input Frequency Typical INL, 2V Range INL ERROR (LSB) CROSSTALK (dB) –105 –110 –115 –120 Typical DNL, 2V Range 1.0 1.0 0.8 0.8 0.6 0.6 0.4 DNL ERROR (LSB) –100 0.2 0 –0.2 –0.4 –0.6 –125 –130 0 20 –0.2 –0.4 –0.6 –0.8 –0.8 –1.0 1024 0 2048 CODE 4096 3072 8192 Point FFT, fIN = 5.1MHz, –1dB, 2V Range 0 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –80 AMPLITUDE (dB) –40 AMPLITUDE (dB) –60 –70 –50 –60 –70 –80 –90 –90 –40 –50 –60 –70 –80 –90 –100 –100 –100 –110 –110 –110 –120 0 1 3 2 FREQUENCY (MHz) 4 5 –120 4096 3072 8192 Point 2-Tone FFT, fIN = 4.3MHz and 4.6MHz, –1dB, 2V Range –10 –40 2048 CODE 2290 G03 8192 Point FFT, fIN = 70.1MHz, –1dB, 2V Range –50 1024 0 2290 G02 2290 G01 AMPLITUDE (dB) 0 –1.0 100 40 60 80 INPUT FREQUENCY (MHz) 0.4 0.2 1 0 2290 G04 3 2 FREQUENCY (MHz) 4 –120 5 1 0 3 2 FREQUENCY (MHz) 4 5 2290 G05 2290 G06 SNR vs Input Frequency, –1dB, 2V Range Grounded Input Histogram 70000 SFDR vs Input Frequency, –1dB, 2V Range 75 61758 100 74 60000 95 73 90 40000 30000 SFDR (dBFS) 72 SNR (dBFS) COUNT 50000 71 70 69 68 20000 85 80 75 67 10000 2155 1607 0 2048 2049 CODE 2050 2290 G07 70 66 65 65 0 10 40 30 20 50 60 INPUT FREQUENCY (MHz) 70 2290 G08 0 10 40 60 30 50 20 INPUT FREQUENCY (MHz) 70 2290 G09 2290fa 6 LTC2290 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Level, fIN = 5MHz, 2V Range SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB SFDR vs Input Level, fIN = 5MHz, 2V Range 120 80 100 dBFS 100 60 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 80 50 40 dBc 30 20 70 –0 –70 –60 60 10 12 4 6 8 SAMPLE RATE (Msps) 2 14 80 dBc 70 60 50 90dBc SFDR REFERENCE LINE 40 30 10 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 –70 0 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) 2290 G11 2290 G10 IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB –10 0 2290 G12 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V 2.0 50 1.8 2V RANGE 1.6 1.4 40 IOVDD (mA) 0 90 20 10 IVDD (mA) SNR AND SFDR (dBFS) 90 dBFS 110 70 1V RANGE 30 1.2 1.0 0.8 0.6 0.4 0.2 20 0 2 10 4 6 8 SAMPLE RATE (Msps) 12 14 2290 G13 0 0 2 8 6 4 10 SAMPLE RATE (Msps) 12 14 2290 G14 2290fa 7 LTC2290 U U U PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge. CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge. REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEB selects an input range of ±VSENSEB. ±1V is the largest valid input range. VCMB (Pin 20): Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMA. MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA11, OFA; Channel B comes out on DB0-DB11, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB11, OFB; Channel B comes out on DA0-DA11, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to VDD results in normal operation with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs at high impedance. OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function. NC (Pins 24, 25, 41, 42): Do Not Connect These Pins. DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital Outputs. DB11 is the MSB. REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. OVDD (Pins 32, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. AINB– (Pin 15): Channel B Negative Differential Analog Input. OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred. AINB+ (Pin 16): Channel B Positive Differential Analog Input. DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital Outputs. DA11 is the MSB. GND (Pins 17, 64): ADC Power Ground. OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred. SENSEB (Pin 19): Channel B Reference Programming Pin. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference OGND (Pins 31, 50): Output Driver Ground. OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA Pin Function. 2290fa 8 LTC2290 U U U PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance. MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. VCMA (Pin 61): Channel A 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to VCMB. SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to VCMA selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSEA selects an input range of ±VSENSEA. ±1V is the largest valid input range. GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground. W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 2290 F01 REFL OGND CLK MODE SHDN OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram (Only One Channel is Shown) 2290fa 9 LTC2290 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP N+4 N+2 N ANALOG INPUT N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D11, OF N–3 N–2 N–1 N 2290 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D11A, OFA A–4 tD D0B-D11B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 2290 TD02 2290fa 10 LTC2290 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Aperture Delay Time The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) Intermodulation Distortion Crosstalk If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal). If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, CONVERTER OPERATION As shown in Figure 1, the LTC2290 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive 2290fa 11 LTC2290 U U W U APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2290 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2290 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from LTC2290 VDD AIN+ CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD AIN– CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD CLK 2290 F02 Figure 2. Equivalent Input Circuit 2290fa 12 LTC2290 U W U U APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to VCM or a quiet reference voltage between 0.5V and 1.5V. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2290 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2290 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω AIN+ LTC2290 0.1µF 12pF 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2290 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer 2290fa 13 LTC2290 U W U U APPLICATIO S I FOR ATIO Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ LTC2290 + CM – 2.2µF 12pF – 25Ω AIN– 2290 F04 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. Reference Operation Figure 6 shows the LTC2290 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. LTC2290 1.5V VCM 4Ω 1.5V BANDGAP REFERENCE 2.2µF 1k 0.1µF ANALOG INPUT 1k 25Ω LTC2290 12pF 25Ω RANGE DETECT AND CONTROL 2.2µF AIN+ 0.5V 1V VCM AIN– TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V SENSE BUFFER INTERNAL ADC HIGH REFERENCE 1µF REFH 0.1µF 2290 F05 2.2µF 0.1µF Figure 5. Single-Ended Drive DIFF AMP 1µF The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. REFL INTERNAL ADC LOW REFERENCE 2290 F06 Figure 6. Equivalent Reference Circuit 2290fa 14 LTC2290 U W U U APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges. Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB. 1.5V VCM 2.2µF 12k 0.75V 12k LTC2290 SENSE 1µF 2290 F07 Figure 7. 1.5V Range ADC Input Range Driving the Clock Input The CLK inputs can be driven directly with a CMOS or TTL level signal. A differential clock can also be used along with a low jitter CMOS converter before the CLK pin (Figure 8). CLEAN SUPPLY 4.7µF FERRITE BEAD 0.1µF CLK 100Ω LTC2290 2290 F08 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter The noise performance of the LTC2290 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. 2290fa 15 LTC2290 U W U U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates Digital Output Buffers The maximum conversion rate for the LTC2290 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (±10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation. Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2290 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2290 is 1Msps. LTC2290 OVDD VDD 0.5V TO 3.6V VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OE OGND 2290 F09 Figure 9. Digital Output Buffer AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2290 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 Lower OVDD voltages will also help reduce interference from the digital outputs. +0.000488V 0.000000V –0.000488V –0.000976V 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.999512V –1.000000V