LTC2412
2-Channel Differential Input
24-Bit No Latency ∆Σ ADC
FEATURES
DESCRIPTION
2-Channel Differential Input with Automatic Channel Selection (Ping-Pong)
nn Low Supply Current: 200µA, 4µA in Autosleep
nn Differential Input and Differential Reference with
GND to VCC Common Mode Range
nn 2ppm INL, No Missing Codes
nn 2.5ppm Full-Scale Error and 0.1ppm Offset
nn 0.16ppm Noise, 22.5 Effective Number of Bits
nn No Latency: Digital Filter Settles in a Single Cycle and
Each Channel Conversion is Accurate
nn Internal Oscillator—No External Components Required
nn 110dB Min, 50Hz or 60Hz Notch Filter
nn Narrow SSOP-16 Package
nn Single Supply 2.7V to 5.5V Operation
The LTC®2412 is a 2-channel differential input micropower
24-bit No Latency ∆Σ™ analog-to-digital converter with an
integrated oscillator. It provides 2ppm INL and 0.16ppm
RMS noise over the entire supply range. The two differential channels are converted alternately with channel ID
included in the conversion results. It uses delta-sigma
technology and provides single conversion settling of the
digital filter. Through a single pin, the LTC2412 can be
configured for better than 110dB input differential mode
rejection at 50Hz or 60Hz ±2%, or it can be driven by an
external oscillator for a user defined rejection frequency.
The internal oscillator requires no external frequency setting components.
nn
APPLICATIONS
Direct Sensor Digitizer
Weight Scales
nn Direct Temperature Measurement
nn Gas Analyzers
nn Strain-Gage Transducers
nn Instrumentation
nn Data Acquisition
nn Industrial Process Control
nn 6-Digit DVMs
nn
nn
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The full-scale
differential input range is from –0.5VREF to 0.5VREF. The
reference common mode voltage, VREFCM, and the input
common mode voltage, VINCM, may be independently set
anywhere within the GND to VCC. The DC common mode
input rejection is better than 140dB.
The LTC2412 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRE
protocols.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Total Unadjusted Error vs Input
2.7V TO 5.5V
VCC
FO
14
+
REF
4
CH0+
LTC2412
5
13
SCK
CH0–
3
REF –
SDO
6
CH1+
CS
7
8, 9, 10, 15, 16
12
11
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
0.5
0
–0.5
–1.0
CH1–
GND
1.0
TUE (ppm OF VREF)
1
2
THERMOCOUPLE
1.5
VCC
1µF
VCC = 5V
REF+ = 5V
REF– = GND
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 90°C
TA = 25°C
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
2412 TA01
TA = –45°C
1 1.5
2
2.5
2412 TA02
2412fa
For more information www.linear.com/LTC2412
1
LTC2412
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) to GND........................ –0.3V to 7V
Analog Input Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Reference Input Voltage
to GND.......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND........–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2412C ................................................. 0°C to 70°C
LTC2412I ..............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
TOP VIEW
VCC
1
16 GND
REF +
2
15 GND
REF –
3
14 FO
CH0+
4
13 SCK
CH0–
5
12 SDO
CH1+
6
11 CS
CH1–
7
10 GND
GND
8
9
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2412CGN#PBF
LTC2412CGN#TRPBF
2412
16-Lead Plastic SSOP
0°C to 70°C
LTC2412IGN#PBF
LTC2412IGN#TRPBF
2412I
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
Offset Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Note 14)
Offset Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Positive Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Negative Full-Scale Error
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
Output Noise
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 13)
l
TYP
MAX
24
UNITS
Bits
l
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
l
0.5
2.5
µV
10
l
2.5
nV/°C
12
0.03
l
2.5
0.03
3
3
4
0.8
ppm of VREF
ppm of VREF/°C
12
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF
ppm of VREF
µVRMS
2412fa
2
For more information www.linear.com/LTC2412
LTC2412
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC (Note 5)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Notes 5, 7)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC, (Notes 5, 8)
Input Common Mode Rejection
60Hz ±2%
Input Common Mode Rejection
50Hz ±2%
MIN
TYP
MAX
UNITS
l
130
140
l
140
dB
l
140
dB
dB
Input Normal Mode Rejection
60Hz ±2%
(Notes 5, 7)
l
110
140
dB
Input Normal Mode Rejection
50Hz ±2%
(Note 5, 8)
l
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
l
130
140
dB
Power Supply Rejection, DC
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
120
dB
Power Supply Rejection, 60Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2%
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8)
120
dB
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
l
MIN
TYP
MAX
UNITS
GND – 0.3
VCC + 0.3
V
IN–
Absolute/Common Mode IN– Voltage
l
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range
(IN+ – IN–)
l
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
l
0.1
VCC
V
CS (IN+)
IN+ Sampling Capacitance
18
pF
CS
(IN–)
IN– Sampling Capacitance
18
pF
CS
(REF+)
REF+ Sampling Capacitance
18
pF
CS (REF–)
REF– Sampling Capacitance
18
pF
(IN+)
IN+ DC Leakage Current
CS = VCC
= 5.5V, IN+ = GND
l
–10
1
10
nA
IDC_LEAK (IN–)
IN– DC Leakage Current
CS = VCC = 5.5V, IN– = 5.5V
l
–10
1
10
nA
CS = VCC
= 5.5V, REF+ = 5.5V
l
–10
1
10
nA
CS = VCC
= 5.5V, REF– = GND
l
–10
1
10
nA
IDC_LEAK
IDC_LEAK
(REF+)
REF+ DC Leakage Current
IDC_LEAK
(REF–)
REF– DC Leakage Current
2412fa
For more information www.linear.com/LTC2412
3
LTC2412
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
l
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
l
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
l
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
l
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
l
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = –800µA
l
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
l
VOH
High Level Output Voltage
SCK
IO = –800µA (Note 10)
l
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
l
IOZ
Hi-Z Output Leakage
SDO
l
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
l
CS = 0V
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V
(Note 12)
l
l
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
13
µA
µA
µA
2412fa
4
For more information www.linear.com/LTC2412
LTC2412
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
l
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
MAX
UNITS
2.56
500
kHz
l
0.25
390
µs
l
0.25
390
µs
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
l
l
l
TYP
130.86 133.53 136.20
157.03 160.23 163.44
20510/fEOSC (in kHz)
ms
ms
ms
19.2
fEOSC/8
kHz
kHz
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 9)
l
45
55
%
2000
kHz
tLESCK
External SCK Low Period
(Note 9)
l
tHESCK
External SCK High Period
(Note 9)
l
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
1.64
1.67
1.70
256/fEOSC (in kHz)
ms
ms
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
l
32/fESCK (in kHz)
ms
t1
CS ↓ to SDO Low Z
t2
CS ↑ to SDO High Z
250
ns
l
0
200
ns
l
0
200
ns
CS ↓ to SCK ↓
(Note 10)
l
0
200
ns
t4
CS ↓ to SCK ↑
(Note 9)
l
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
t5
t6
t3
ns
220
l
ns
l
15
ns
SCK Set-Up Before CS ↓
l
50
ns
SCK Hold After CS ↓
l
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive
(CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external
oscillator).
50
ns
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external
oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
2412fa
For more information www.linear.com/LTC2412
5
LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 2.5V)
1.5
1.0
1.0
0.5
0
TA = –45°C
TA = 90°C
TA = 25°C
–0.5
TA = 25°C
TA = –45°C
1
1.5
2
2.5
–1.5
–1
–0.5
0
VIN (V)
0.5
1
1.5
2
2.5
TA = 25°C
TA = 90°C
0
–1.0
–1.0
TA = –45°C
0.5
–0.5
–0.5
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
10
1.0
TA = 90°C
–1.5
VCC = 5V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
–1
–0.5
8
6
4
2
0
VIN (V)
0.5
0.8
2412 G07
0.5
12
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = 460800Hz
TA = 25°C
1
4
2
0
–2
TA = 90°C
–4
TA = 25°C
–6
TA = –45°C
–10
1
–1
–0.5
0
VIN (V)
0.5
1
2412 G06
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 2.5V)
GAUSSIAN
DISTRIBUTION
m = 0.067ppm
σ = 0.151ppm
2
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
6
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 5V)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
10
0
VIN (V)
2412 G05
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
GAUSSIAN
DISTRIBUTION
m = 0.105ppm
σ = 0.153ppm
–0.5
VCC = 2.7V VREF = 2.5V
REF + = 2.5V VINCM = 1.25V
REF – = GND FO = GND
–8
2412 G04
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
–1
TA = –45°C
2412 G03
8
TA = –45°C
TA = 25°C
VCC = 2.7V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
Integral Nonlinearity vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
1.5
0
12
–4
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 2.5V)
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0.5
–2
2412 G02
2412 G01
1.0
TA = 25°C
0
–10
1
TA = 90°C
2
–6
–1.0
Integral Nonlinearity vs
Temperature (VCC = 5V,
VREF = 5V)
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
VINCM = 2.5V
FO = GND
4
–8
–1.5
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
1.5
6
INL ERROR (ppm OF VREF)
–1.0
TA = 90°C
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
VINCM = 2.5V
FO = GND
8
12
NUMBER OF READINGS (%)
–0.5
10
VCC = 5V
REF + = 2.5V
REF – = GND
VREF = 2.5V
VINCM = 1.25V
FO = GND
0.5
0
Total Unadjusted Error vs
Temperature (VCC = 2.7V,
VREF = 2.5V)
TUE (ppm OF VREF)
1.5
TUE (ppm OF VREF)
TUE (ppm OF VREF)
Total Unadjusted Error vs
Temperature (VCC = 5V,
VREF = 5V)
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.033ppm
σ = 0.293ppm
2
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
0.8
2412 G08
0
–1.6
–0.8
0
0.8
OUTPUT CODE (ppm OF VREF)
1.6
2412 G10
2412fa
6
For more information www.linear.com/LTC2412
LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
10
8
6
4
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 460800Hz
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = 0.014ppm
σ = 0.292ppm
12
NUMBER OF READINGS (%)
2
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = GND
TA = 25°C
10
8
6
4
GAUSSIAN
DISTRIBUTION
m = 0.079ppm
σ = 0.298ppm
2410 G11
4
2
4
RMS Noise
vs Input Differential Voltage
1.0
GAUSSIAN DISTRIBUTION
m = 0.101837ppm
σ = 0.154515ppm
0.5
0.6
0.4
0.2
0
–0.2
–0.4
IN + = 2.5V
VCC = 5V TA = 25°C
VREF = 5V REF + = 5V IN – = 2.5V
VIN = 0V REF – = GND
FO = GND
–0.6
–0.8
–1.0
0.8
0
0.4
0.3
0.2
0.1
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
5 10 15 20 25 30 35 40 45 50 55 60
TIME (HOURS)
2412 G16
2412 G17
RMS Noise vs VINCM
RMS Noise vs Temperature (TA)
RMS Noise vs VCC
850
825
825
825
800
800
800
RMS NOISE (nV)
850
775
725
700
675
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
IN + = VINCM
IN – = VINCM
VIN = 0V
FO = GND
TA = 25°C
775
750
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
VIN = 0V
FO = GND
725
700
675
650
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
2412 G19
650
–50
–25
0
25
50
TEMPERATURE (°C)
75
2.5
2412 G18
850
750
VCC = 5V
VREF = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
0.8
ADC CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
FO = GND
TA = 25°C
1.6
2412 G14
Consecutive ADC Readings
vs Time
0
–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6
OUTPUT CODE (ppm OF VREF)
RMS NOISE (nV)
6
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
1.6
RMS NOISE (ppm OF VREF)
6
8
GAUSSIAN
DISTRIBUTION
m = 0.177ppm
σ = 0.297ppm
2412 G13
ADC READING (ppm OF VREF)
NUMBER OF READINGS (%)
8
10
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = 1.25V
FO = 460800Hz
TA = 25°C
2
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
1.6
Long-Term Noise Histogram
(Time = 60 Hrs, VCC = 5V,
VREF = 5V)
10
12
2
0
–1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2
OUTPUT CODE (ppm OF VREF)
12
Noise Histogram (Output Rate =
22.5Hz, VCC = 2.7V, VREF = 2.5V)
100
2412 G20
RMS NOISE (nV)
NUMBER OF READINGS (%)
12
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
NUMBER OF READINGS (%)
Noise Histogram (Output Rate =
22.5Hz, VCC = 5V, VREF = 2.5V)
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = GND
IN – = GND
FO = GND
TA = 25°C
775
750
725
700
675
650
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2412 G21
2412fa
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7
LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VINCM
RMS Noise vs VREF
775
750
725
700
675
650
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
4.5
0.3
0.2
0.2
0.1
VCC = 5V
REF + = 5V
REF – = GND
VREF = 5V
IN + = VINCM
IN – = VINCM
VIN = 0V
FO = GND
TA = 25°C
0
–0.1
–0.2
–0.3
–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
VINCM (V)
5
2412 G22
0.2
–0.2
–0.3
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = GND
IN – = GND
FO = GND
TA = 25°C
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
0
VCC = 5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–0.1
–0.2
–0.3
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
4
+FULL-SCALE ERROR (ppm OF VREF)
+FULL-SCALE ERROR (ppm OF VREF)
–2
–3
4.5
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
0
–1
–2
2412 G28
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = GND
FO = GND
0 15 30 45 60
TEMPERATURE (°C)
1
0
VCC = 5V
REF + = VREF
REF – = GND
IN + = 0.5 • REF +
IN – = GND
FO = GND
TA = 25°C
–2
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
90
2412 G27
3
–1
75
–Full-Scale Error
vs Temperature (TA)
2
–3
100
1
–3
–45 –30 –15
5
3
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = 1.25V
IN – = GND
FO = GND
TA = 25°C
75
2
2412 G26
3
1
0
25
50
TEMPERATURE (°C)
2412 G24
+Full-Scale Error vs VREF
2
–25
3
0.1
+Full-Scale Error vs VCC
–1
–0.3
–50
+Full-Scale Error
vs Temperature (TA)
2412 G25
0
–0.2
+FULL-SCALE ERROR (ppm OF VREF)
0.2
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.3
0.1
VCC = 5V
REF + = 5V
REF – = GND
IN + = 2.5V
IN – = 2.5V
VIN = 0V
FO = GND
–0.1
Offset Error vs VREF
0.3
–0.1
0
2412 G23
Offset Error vs VCC
0
0.1
–FULL-SCALE ERROR (ppm OF VREF)
RMS NOISE (nV)
800
OFFSET ERROR (ppm OF VREF)
VCC = 5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
825
Offset Error vs Temperature (TA)
0.3
OFFSET ERROR (ppm OF VREF)
850
4
4.5
5
2412 G29
2
1
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
0
–1
–2
–3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2412 G30
2412fa
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LTC2412
TYPICAL PERFORMANCE CHARACTERISTICS
–Full-Scale Error vs VREF
REF + = 2.5V
REF – = GND
VREF = 2.5V
IN + = GND
IN – = 1.25V
FO = GND
TA = 25°C
2
1
–FULL-SCALE ERROR (ppm OF VREF)
–FULL-SCALE ERROR (ppm OF VREF)
3
0
–1
–2
–3
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
VCC = 5V
REF + = VREF
REF – = GND
IN + = GND
IN – = 0.5 • REF +
FO = GND
TA = 25°C
2
1
–120
0
0.5
1
1.5
2 2.5 3
VREF (V)
3.5
–80
4.5
5
–140
0.01
0
VCC = 4.1VDC ±1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–40
–60
–20
–40
–80
–60
–100
–100
–120
–120
–120
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
–140
0
30
60 90 120 150 180 210 240
FREQUENCY AT VCC (Hz)
Conversion Current
vs Temperature
1000
220
VCC = 5.5V
VCC = 5V
210
FO = GND
CS = GND
200 SCK = NC
SDO = NC
190
180
VCC = 3V
170
160
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
800
700
600
75
90
2412 G37
6
5
500
VCC = 5V
400
300
200
VCC = 2.7V
15350
15400
FREQUENCY AT VCC (Hz)
Sleep Mode Current
vs Temperature
VREF = VCC
IN + = GND
IN – = GND
SCK = NC
SDO = NC
CS = GND
FO = EXT OSC
TA = 25°C
900
100
15450
15300
2412 G36
Conversion Current
vs Output Data Rate
SUPPLY CURRENT (µA)
CONVERSION CURRENT (µA)
230
VCC = 4.1VDC ±0.7VP-P
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
2412 G35
2412 G34
240
PSRR vs Frequency at VCC
–140
15250
SLEEP MODE CURRENT (µA)
1
100
–80
–100
–140
0.1
1
10
FREQUENCY AT VCC (Hz)
2412 G33
REJECTION (dB)
–60
4
PSRR vs Frequency at VCC
–20
REJECTION (dB)
REJECTION (dB)
–40
–80
–100
–2
0
VCC = 4.1VDC
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–60
VCC = 4.1VDC 1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
2412 G32
PSRR vs Frequency at VCC
–20
–40
–1
2412 G31
0
–20
0
–3
5.5
PSRR vs Frequency at VCC
0
REJECTION (dB)
–Full-Scale Error vs VCC
3
4
VCC = 5.5V
3
VCC = 5V
2
VCC = 3V
1
FO = GND
CS = VCC
SCK = NC
SDO = NC
VCC = 2.7V
VCC = 3V
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
2412 G38
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2412 G39
2412fa
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9
LTC2412
PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF–, by at least 0.1V.
CH0+ (Pin 4): Positive Input for Differential Channel 0.
CH0– (Pin 5): Negative Input for Differential Channel 0.
CH1+ (Pin 6): Positive Input for Differential Channel 1.
CH1– (Pin 7): Negative Input for Differential Channel 1.
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and VCC. Within these limits
the converter bipolar input range (VIN = IN+ – IN–) extends
from –0.5 • (VREF) to 0.5 • (VREF). Outside this input range
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and VCC decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All five
pins must be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface clock
during the Data Output period. A weak internal pull-up is
automatically activated in Internal Serial Clock Operation
mode. The Serial Clock Operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO is
driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
2412fa
10
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LTC2412
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
OSCILLATOR
VCC
GND
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
CH0+
CH0–
IN +
MUX
CH1+
SCK
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
IN –
+
CH1–
–
SERIAL
INTERFACE
SDO
CS
DECIMATING FIR
CH0/CH1
PING-PONG
REF +
REF –
2412 FD
Figure 1. Functional Block Diagram
TEST CIRCUIT
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2412 TA03
2412 TA04
2412fa
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11
LTC2412
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2412 is a low power, ∆Σ ADC with automatic
alternate channel selection between the two differential
channels and an easy-to-use 3-wire serial interface (see
Figure 1). Channel 0 is selected automatically at power up
and the two channels are selected alternately afterwards
(ping-pong). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2412 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the first rising edge of SCK, the device begins
POWER UP
IN+ = CH0 +, IN – = CH0 –
CONVERT
SLEEP
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK).
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2412 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require programming
configuration registers; moreover, they do not disturb the
cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing
Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus
their harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock. The
LTC2412 incorporates a highly accurate on-chip oscillator.
This eliminates the need for external frequency setting
components such as crystals or oscillators. Clocked by
the on-chip oscillator, the LTC2412 achieves a minimum of
110dB rejection at the line frequency (50Hz or 60Hz ±2%).
Ease of Use
FALSE
The LTC2412 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
SWITCH CHANNEL
2412 F02
Figure 2. LTC2412 State Transition Diagram
2412fa
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LTC2412
APPLICATIONS INFORMATION
The LTC2412 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2412 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selection.
(See the 2-wire I/O sections in the Serial Interface Timing
Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers and selects channel 0. Following the
POR signal, the LTC2412 starts a normal conversion cycle
and follows the succession of states described above. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage specification
for the REF+ and REF– pins covers the entire range from
GND to VCC. For correct converter operation, the REF+ pin
must always be more positive than the REF– pin.
The LTC2412 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in nanovolts is nearly constant with reference
voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance. A reduced reference
voltage will also improve the converter performance when
operated with an external conversion clock (external FO
signal) at substantially higher output data rates (see the
Output Data Rate section).
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the CH0+/CH0– or CH1+/CH1–
input pins extending from GND – 0.3V to VCC + 0.3V.
Outside these limits, the ESD protection devices begin
to turn on and the errors due to input leakage current
increase rapidly. Within these limits, the LTC2412 converts the bipolar differential input signal, VIN = IN+ – IN–,
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF–, with the selected channel referred as IN+
and IN–. Outside this range, the converter indicates the
overrange or the underrange condition using distinct
output codes.
Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between these
series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as
practical to the pins. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
Output Data Format
The LTC2412 serial output data stream is 32 bits long.
The first 3 bits represent status information indicating the
conversion state, selected channel and sign. The next 24
bits are the conversion result, MSB first. The remaining
5 bits are sub LSBs beyond the 24-bit level that may be
included in averaging or discarded without loss of resolution. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the differential input voltage is above +FS).
2412fa
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13
LTC2412
APPLICATIONS INFORMATION
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is the selected channel indicator. The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be
required in certain configurations for anti-aliasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm at fullscale for each ohm of source resistance driving IN+ or
IN. When FO = HIGH (internal oscillator and 50Hz notch),
the typical differential input resistance is 2.16MΩ which
will generate a gain error of approximately 0.23ppm at
full-scale for each ohm of source resistance driving IN+
or IN. When FO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.28 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN– will
result in 1.78 • 10–6 • fEOSCppm gain error at full-scale.
The effect of the source resistance on the two input pins
is additive with respect to this gain error. The typical +FS
and –FS errors as a function of the sum of the source
resistance seen by IN+ and IN– for large values of CIN are
shown in Figures 15 and 16.
In addition to this gain error, an offset error term may
also appear. The offset error is proportional with the
mismatch between the source impedance driving the two
input pins IN+ and IN– and with the difference between the
input and reference common mode voltages. While the
input drive circuit nonzero source impedance combined
with the converter average input current will not degrade
the INL performance, indirect distortion may result from
the modulation of the offset error by the common mode
component of the input signal. Thus, when using large
+FS ERROR (ppm OF VREF)
300
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
240
180
CIN = 1µF, 10µF
CIN = 0.1µF
120
CIN = 0.01µF
60
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F15
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
CIN = 0.01µF
–FS ERROR (ppm OF VREF)
multiplexers, wires, connectors or sensors, the LTC2412
can maintain its exceptional accuracy while operating
with relative large values of source resistance as shown in
Figures 13 and 14. These measured results may be slightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small CIN values, the
settling on IN+ and IN– occurs almost independently and
there is little benefit in trying to match the source impedance for the two pins.
–60
–120
CIN = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
–180
–240
–300
CIN = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F16
Figure 16. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
CIN capacitor values, it is advisable to carefully match the
source impedance seen by the IN+ and IN– pins. When
FO = LOW (internal oscillator and 60Hz notch), every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.28ppm. When FO = HIGH (internal oscillator
and 50Hz notch), every 1Ω mismatch in source impedance
transforms a full-scale common mode input signal into
a differential mode input signal of 0.23ppm. When FO is
driven by an external oscillator with a frequency fEOSC, every
1Ω mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10–6 • fEOSCppm. Figure 17 shows the
typical offset error due to input common mode voltage for
For more information www.linear.com/LTC2412
2412fa
25
LTC2412
APPLICATIONS INFORMATION
120
OFFSET ERROR (ppm OF VREF)
100
80
60
B
40
Reference Current
C
20
D
0
E
–20
F
–40
–60
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
–80
–100
–120
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
0
0.5
1
1.5
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
2 2.5 3
VINCM (V)
3.5
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
2412 F17
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
various values of source resistance imbalance between the
IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are used
for the external source impedance seen by IN+ and IN–,
the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
values over the entire temperature and voltage range). Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
In a similar fashion, the LTC2412 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configurations. Such capacitors will average the reference sampling
charge and the external source resistance will see a quasi
constant reference differential impedance. When FO =
LOW (internal oscillator and 60Hz notch), the typical differential reference resistance is 1.3MΩ which will generate a gain error of approximately 0.38ppm at full-scale
for each ohm of source resistance driving REF+ or REF–.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential reference resistance is 1.56MΩ which
will generate a gain error of approximately 0.32ppm at
full-scale for each ohm of source resistance driving REF+
or REF–. When FO is driven by an external oscillator with
a frequency fEOSC (external conversion clock operation),
the typical differential reference resistance is 0.20 • 1012/
fEOSCΩ and each ohm of source resistance driving REF+
or REF– will result in 2.47 • 10–6 • fEOSCppm gain error at
full-scale. The effect of the source resistance on the two
reference pins is additive with respect to this gain error.
The typical +FS and –FS errors for various combinations
of source resistance seen by the REF+ and REF– pins and
external capacitance CREF connected to these pins are
shown in Figures 18, 19, 20 and 21.
2412fa
26
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LTC2412
APPLICATIONS INFORMATION
–10
–20
–30
CREF = 0.01µF
CREF = 0.001µF
–40
–50
50
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 100pF
CREF = 0pF
1
10
100
1k
RSOURCE (Ω)
10k
40
CREF = 100pF
CREF = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V
FO = GND
TA = 25°C
20
10
0
100k
CREF = 0.01µF
CREF = 0.001µF
1
10
100
1k
RSOURCE (Ω)
10k
2412 F18
Figure 18. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
–180
–360
–450
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
450
CREF = 0.01µF
–90
–270
2412 F19
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
100k
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
360
270
CREF = 0.1µF
180
CREF = 0.01µF
90
0
CREF = 1µF, 10µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2412 F20
2412 F21
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– translates into about 1.34ppm additional INL error. When FO
= HIGH (internal oscillator and 50Hz notch), every 100Ω
of source resistance driving REF+ or REF– translates into
about 1.1ppm additional INL error. When FO is driven by
an external oscillator with a frequency fEOSC, every 100Ω
of source resistance driving REF+ or REF– translates
into about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on
the two reference pins is additive with respect to this INL
error. In general, matching of source impedance for the
REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined
source impedance driving the REF+ and REF– pins rather
than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
2412fa
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27
LTC2412
APPLICATIONS INFORMATION
60Hz. There is no significant difference in the LTC2412
performance between these two operation modes.
15
RSOURCE = 1000Ω
12
INL (ppm OF VREF)
9
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
RSOURCE = 500Ω
6
3
0
–3
RSOURCE = 100Ω
–6
–9
–12
–15
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
TA = 25°C
REF– = GND
2412 F22
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2412 can produce
up to 7.5 readings per second with a notch frequency of
60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH). The actual output
data rate will depend upon the length of the sleep and
data output phases which are controlled by the user and
which can be made insignificantly short. When operated
with an external conversion clock (FO connected to an
external oscillator), the LTC2412 output data rate can be
increased as desired. The duration of the conversion phase
is 20510/fEOSC. If fEOSC = 153600Hz, the converter behaves
as if the internal oscillator is used and the notch is set at
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by
relying upon the LTC2412’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used,
the previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2412 typical
performance can be inferred from Figures 13, 14, 18 and
19 in which the horizontal axis is scaled by 153600/fEOSC.
Third, an increase in the frequency of the external oscillator
above 460800Hz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
auto-calibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
25 readings per second are shown in Figures 23, 24, 25,
26, 27, 28, 29 and 30. In order to obtain the highest possible level of accuracy from this converter at output data
rates above 7.5 readings per second, the user is advised
to maximize the power supply voltage used and to limit
the maximum ambient operating temperature. In certain
circumstances, a reduction of the differential reference
voltage may be beneficial.
2412fa
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LTC2412
APPLICATIONS INFORMATION
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
OFFSET ERROR (ppm OF VREF)
450
400
350
300
250
200
150
100
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = EXTERNAL OSCILLATOR
6000
5000
TA = 25°C
TA = 85°C
4000
3000
2000
1000
50
0
7000
TA = 25°C
TA = 85°C
+FS ERROR (ppm OF VREF)
500
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
0
25
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
2412 F23
Figure 23. Offset Error vs Output Data Rate and Temperature
2412 F24
Figure 24. +FS Error vs Output Data Rate and Temperature
0
24
–2000
–3000
–4000
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = EXTERNAL OSCILLATOR
–5000
–6000
0
TA = 25°C
22
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
23
TA = 25°C
TA = 85°C
–1000
–7000
TA = 85°C
21
20
19
18
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
12
25
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
2412 F25
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
22
250
TA = 25°C
TA = 85°C
18
16
14
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/INLMAX)
12
10
0
VCC = 5V
REF + = GND
VINCM = 2.5V
VIN = 0V
TA = 25°C
FO = EXTERNAL OSCILLATOR
225
OFFSET ERROR (ppm OF VREF)
RESOLUTION (BITS)
20
25
2412 F26
Figure 25. –FS Error vs Output Data Rate and Temperature
8
25
200
175
150
VREF = 2.5V
VREF = 5V
125
100
75
50
25
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
0
0
2412 F27
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
2412 F28
Figure 28. Offset Error vs Output
Data Rate and Reference Voltage
2412fa
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LTC2412
APPLICATIONS INFORMATION
Input Bandwidth
24
VREF = 5V
23
RESOLUTION (BITS)
22
21
VREF = 2.5V
20
19
18
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
12
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
2412 F29
Figure 29. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
22
VREF = 2.5V
RESOLUTION (BITS)
20
VREF = 5V
18
16
RESOLUTION =
LOG2(VREF/INLMAX)
TA = 25°C
VCC = 5V
REF – = GND
VINCM = 0.5 • REF +
–0.5V • VREF < VIN < 0.5 • VREF
FO = EXTERNAL OSCILLATOR
14
12
10
8
0
5
10
15
20
OUTPUT DATA RATE (READINGS/SEC)
25
2412 F30
Figure 30. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
0.0
INPUT SIGNAL ATTENUATION (dB)
–0.5
–1.0
–1.5
–2.0
FO = HIGH
FO = LOW
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F31
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
The combined effect of the internal Sinc4 digital filter and of
the analog and digital auto-calibration circuits determines
the LTC2412 input bandwidth. When the internal oscillator
is used with the notch set at 60Hz (FO = LOW), the 3dB
input bandwidth is 3.63Hz. When the internal oscillator
is used with the notch set at 50Hz (FO = HIGH), the 3dB
input bandwidth is 3.02Hz. If an external conversion clock
generator of frequency fEOSC is connected to the FO pin,
the 3dB input bandwidth is 0.236 • 10–6 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2412 input bandwidth is shown in
Figure 31 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2412 input bandwidth can be derived from Figure 31,
FO = LOW curve in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (800nVRMS typical for VREF = 5V) can
be modeled by a white noise source connected to a noise
free converter. The noise spectral density is 62.75nV/√Hz
for an infinite bandwidth source and 86.1nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2412, the
ADC input referred system noise calculation can be
simplified by Figure 32. The noise of an amplifier driving
the LTC2412 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency fi. The amplifier noise spectral density
is ni. From Figure 32, using fi as the x-axis selector, we
can find on the y-axis the noise equivalent bandwidth freqi
2412fa
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LTC2412
APPLICATIONS INFORMATION
Normal Mode Rejection and Anti-Aliasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2412 significantly
simplifies anti-aliasing filter requirements.
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2412’s auto-calibration circuits further simplify the
anti-aliasing requirements by additional normal mode
signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure 34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for
the external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
FO = LOW
10
FO = HIGH
1
0.1
0.1
1
10 100 1k
10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2412 F32
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
0
INPUT NORMAL MODE REJECTION (dB)
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if
the x-axis is scaled by fEOSC/153600. For large values of
the ratio fEOSC/153600, the Figure 32 plot accuracy begins
to decrease, but in the same time the LTC2412 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
100
FO = HIGH
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F33
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
0
INPUT NORMAL MODE REJECTION (dB)
of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
be calculated as N = ni • √freqi. The total system noise
(referred to the LTC2412 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2412 internal noise
(800nV), the noise of the IN+ driving amplifier and the
noise of the IN– driving amplifier.
FO = LOW OR
FO = EXTERNAL
OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2412 F34
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
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LTC2412
APPLICATIONS INFORMATION
Figure 36 (rejection at fS = 256fN) where fN represents
the notch frequency. These curves have been derived for
the external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary
architecture used for the LTC2412 third order modulator
resolves this problem and guarantees a predictable stable
behavior at input signal levels of up to 150% of full-scale.
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 37 and 38. Typical measured values of
the normal mode rejection of the LTC2412 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 37 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2412 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure
38 superimposed over the theoretical calculated curve.
As a result of these remarkable normal mode specifications, minimal (if any) anti-alias filtering is required in front
of the LTC2412. If passive RC components are placed in
front of the LTC2412, the input dynamic current should
be considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects
of dynamic input current.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2412 F35
2412 F36
Figure 35. Input Normal Mode Rejection
Figure 36. Input Normal Mode Rejection
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2412 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
2412fa
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LTC2412
APPLICATIONS INFORMATION
In many industrial applications, it is not uncommon to have
to measure microvolt level signals superimposed over
volt level perturbations and LTC2412 is eminently suited
for such tasks. When the perturbation is differential, the
specification of interest is the normal mode rejection for
large input signal levels. With a reference voltage VREF = 5V,
the LTC2412 has a full-scale differential input range of
5V peak-to-peak. Figures 39 and 40 show measurement
results for the LTC2412 normal mode rejection ratio with a
7.5V peak-to-peak (150% of full-scale) input signal superimposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full-scale)
input signal. In Figure 39, the LTC2412 uses the internal
oscillator with the notch set at 60Hz (FO = LOW) and in
Figure 40 it uses the internal oscillator with the notch set
at 50Hz (FO = HIGH). It is clear that the LTC2412 rejection
performance is maintained with no compromises in this
extreme situation. When operating with large input signal
levels, the user must observe that such signals do not
violate the device absolute maximum ratings.
NORMAL MODE REJECTION (dB)
0
Measuring Barometric Pressure and Temperature with
a Single Sensor
Figure 41 shows the LTC2412 measuring both temperature and pressure from an Intersema model MS5401-BM
absolute pressure sensor. The bridge has a nominal impedance of 3.4kΩ, a temperature coefficient of resistance
of 2900ppm/°C and a temperature coefficient of span of
–1900ppm/°C. R1 provides first order temperature compensation of the output span by causing the bridge voltage
to increase by 1900ppm/°C, offsetting the –1900ppm/°C
TC of span. R1 should have a much smaller TC than that
of the bridge resistance; 50ppm/°C or less is satisfactory.
In addition to compensating the bridge output span, this
circuit also provides a convenient way to measure ambient temperature. Channel 1 of the LTC2412 measures the
bridge excitation voltage, which has a slope of approximately 3.2mV/°C. Channel 0 measures the bridge output,
which has a slope of 50mV/bar. The temperature reading
can also be used for second order compensation of the
pressure reading.
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2412 F38
Figure 38. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full-Scale (50Hz Notch)
2412fa
For more information www.linear.com/LTC2412
33
LTC2412
APPLICATIONS INFORMATION
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL-SCALE)
–20
–40
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2412 F39
Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (60Hz Notch)
2412fa
34
For more information www.linear.com/LTC2412
LTC2412
APPLICATIONS INFORMATION
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL-SCALE)
–20
–40
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = 5V
TA = 25°C
– 60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2412 F40
Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full-Scale (50Hz Notch)
2412fa
For more information www.linear.com/LTC2412
35
LTC2412
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.0250
(0.635)
BSC
GN16 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2412fa
36
For more information www.linear.com/LTC2412
LTC2412
REVISION HISTORY
REV
DATE
DESCRIPTION
A
08/15
Updated fEOSC maximum to 500kHz and all associated information
PAGE NUMBER
5, 6, 7, 9, 28,
29, 30
2412fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2412
37
LTC2412
TYPICAL APPLICATION
5V
4.7µF
R1
6.8k
50ppm/°C
0.1µF
1
2
4
5
1
6
INTERSEMA
MSS401-BM
1 BAR FS
FO
7
2
3
8, 9, 10, 15, 16
14
REF+
FO SELECTED
FOR 60Hz
REJECTION
LTC2412
3
4
VCC
CH0+
CH0–
SCK
CH1+
SDO
CH1¯
CS
13
12
11
REF–
GND
2412 TA05
Figure 41. Measure Barometric Pressure and Temperature with a Single Sensor
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Precision LDO Reference
High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, No Latency ∆Σ ADC in MSOP
1.45µVRMS Noise, 2ppm INL
LTC2411-1
24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC
0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
LTC2413
24-Bit, No Latency ∆Σ ADC
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2414/LTC2418
8-/16-Channel, 24-Bit No Latency ∆Σ ADC
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2415
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
LTC2440
High Speed, Low Noise 24-Bit ADC
4kHz Output Rate, 200nV Noise, 24.6 ENOBs
2412fa
38 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2412
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2412
LT 0815 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2002
工商网监
湘ICP备2023018690号
